xref: /freebsd/sys/dev/xl/if_xl.c (revision 38a52bd3b5cac3da6f7f6eef3dd050e6aa08ebb3)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 1997, 1998, 1999
5  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *	This product includes software developed by Bill Paul.
18  * 4. Neither the name of the author nor the names of any co-contributors
19  *    may be used to endorse or promote products derived from this software
20  *    without specific prior written permission.
21  *
22  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32  * THE POSSIBILITY OF SUCH DAMAGE.
33  */
34 
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37 
38 /*
39  * 3Com 3c90x Etherlink XL PCI NIC driver
40  *
41  * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI
42  * bus-master chips (3c90x cards and embedded controllers) including
43  * the following:
44  *
45  * 3Com 3c900-TPO	10Mbps/RJ-45
46  * 3Com 3c900-COMBO	10Mbps/RJ-45,AUI,BNC
47  * 3Com 3c905-TX	10/100Mbps/RJ-45
48  * 3Com 3c905-T4	10/100Mbps/RJ-45
49  * 3Com 3c900B-TPO	10Mbps/RJ-45
50  * 3Com 3c900B-COMBO	10Mbps/RJ-45,AUI,BNC
51  * 3Com 3c900B-TPC	10Mbps/RJ-45,BNC
52  * 3Com 3c900B-FL	10Mbps/Fiber-optic
53  * 3Com 3c905B-COMBO	10/100Mbps/RJ-45,AUI,BNC
54  * 3Com 3c905B-TX	10/100Mbps/RJ-45
55  * 3Com 3c905B-FL/FX	10/100Mbps/Fiber-optic
56  * 3Com 3c905C-TX	10/100Mbps/RJ-45 (Tornado ASIC)
57  * 3Com 3c980-TX	10/100Mbps server adapter (Hurricane ASIC)
58  * 3Com 3c980C-TX	10/100Mbps server adapter (Tornado ASIC)
59  * 3Com 3cSOHO100-TX	10/100Mbps/RJ-45 (Hurricane ASIC)
60  * 3Com 3c450-TX	10/100Mbps/RJ-45 (Tornado ASIC)
61  * 3Com 3c555		10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane)
62  * 3Com 3c556		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
63  * 3Com 3c556B		10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC)
64  * 3Com 3c575TX		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
65  * 3Com 3c575B		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
66  * 3Com 3c575C		10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
67  * 3Com 3cxfem656	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
68  * 3Com 3cxfem656b	10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC)
69  * 3Com 3cxfem656c	10/100Mbps/RJ-45 (Cardbus, Tornado ASIC)
70  * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45
71  * Dell on-board 3c920 10/100Mbps/RJ-45
72  * Dell Precision on-board 3c905B 10/100Mbps/RJ-45
73  * Dell Latitude laptop docking station embedded 3c905-TX
74  *
75  * Written by Bill Paul <wpaul@ctr.columbia.edu>
76  * Electrical Engineering Department
77  * Columbia University, New York City
78  */
79 /*
80  * The 3c90x series chips use a bus-master DMA interface for transferring
81  * packets to and from the controller chip. Some of the "vortex" cards
82  * (3c59x) also supported a bus master mode, however for those chips
83  * you could only DMA packets to/from a contiguous memory buffer. For
84  * transmission this would mean copying the contents of the queued mbuf
85  * chain into an mbuf cluster and then DMAing the cluster. This extra
86  * copy would sort of defeat the purpose of the bus master support for
87  * any packet that doesn't fit into a single mbuf.
88  *
89  * By contrast, the 3c90x cards support a fragment-based bus master
90  * mode where mbuf chains can be encapsulated using TX descriptors.
91  * This is similar to other PCI chips such as the Texas Instruments
92  * ThunderLAN and the Intel 82557/82558.
93  *
94  * The "vortex" driver (if_vx.c) happens to work for the "boomerang"
95  * bus master chips because they maintain the old PIO interface for
96  * backwards compatibility, but starting with the 3c905B and the
97  * "cyclone" chips, the compatibility interface has been dropped.
98  * Since using bus master DMA is a big win, we use this driver to
99  * support the PCI "boomerang" chips even though they work with the
100  * "vortex" driver in order to obtain better performance.
101  */
102 
103 #ifdef HAVE_KERNEL_OPTION_HEADERS
104 #include "opt_device_polling.h"
105 #endif
106 
107 #include <sys/param.h>
108 #include <sys/systm.h>
109 #include <sys/sockio.h>
110 #include <sys/endian.h>
111 #include <sys/kernel.h>
112 #include <sys/malloc.h>
113 #include <sys/mbuf.h>
114 #include <sys/module.h>
115 #include <sys/socket.h>
116 #include <sys/taskqueue.h>
117 
118 #include <net/if.h>
119 #include <net/if_var.h>
120 #include <net/if_arp.h>
121 #include <net/ethernet.h>
122 #include <net/if_dl.h>
123 #include <net/if_media.h>
124 #include <net/if_types.h>
125 
126 #include <net/bpf.h>
127 
128 #include <machine/bus.h>
129 #include <machine/resource.h>
130 #include <sys/bus.h>
131 #include <sys/rman.h>
132 
133 #include <dev/mii/mii.h>
134 #include <dev/mii/mii_bitbang.h>
135 #include <dev/mii/miivar.h>
136 
137 #include <dev/pci/pcireg.h>
138 #include <dev/pci/pcivar.h>
139 
140 MODULE_DEPEND(xl, pci, 1, 1, 1);
141 MODULE_DEPEND(xl, ether, 1, 1, 1);
142 MODULE_DEPEND(xl, miibus, 1, 1, 1);
143 
144 /* "device miibus" required.  See GENERIC if you get errors here. */
145 #include "miibus_if.h"
146 
147 #include <dev/xl/if_xlreg.h>
148 
149 /*
150  * TX Checksumming is disabled by default for two reasons:
151  * - TX Checksumming will occasionally produce corrupt packets
152  * - TX Checksumming seems to reduce performance
153  *
154  * Only 905B/C cards were reported to have this problem, it is possible
155  * that later chips _may_ be immune.
156  */
157 #define	XL905B_TXCSUM_BROKEN	1
158 
159 #ifdef XL905B_TXCSUM_BROKEN
160 #define XL905B_CSUM_FEATURES	0
161 #else
162 #define XL905B_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
163 #endif
164 
165 /*
166  * Various supported device vendors/types and their names.
167  */
168 static const struct xl_type xl_devs[] = {
169 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT,
170 		"3Com 3c900-TPO Etherlink XL" },
171 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO,
172 		"3Com 3c900-COMBO Etherlink XL" },
173 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT,
174 		"3Com 3c905-TX Fast Etherlink XL" },
175 	{ TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4,
176 		"3Com 3c905-T4 Fast Etherlink XL" },
177 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT,
178 		"3Com 3c900B-TPO Etherlink XL" },
179 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO,
180 		"3Com 3c900B-COMBO Etherlink XL" },
181 	{ TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC,
182 		"3Com 3c900B-TPC Etherlink XL" },
183 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10FL,
184 		"3Com 3c900B-FL Etherlink XL" },
185 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT,
186 		"3Com 3c905B-TX Fast Etherlink XL" },
187 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4,
188 		"3Com 3c905B-T4 Fast Etherlink XL" },
189 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX,
190 		"3Com 3c905B-FX/SC Fast Etherlink XL" },
191 	{ TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO,
192 		"3Com 3c905B-COMBO Fast Etherlink XL" },
193 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT,
194 		"3Com 3c905C-TX Fast Etherlink XL" },
195 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B,
196 		"3Com 3c920B-EMB Integrated Fast Etherlink XL" },
197 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM,
198 		"3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" },
199 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV,
200 		"3Com 3c980 Fast Etherlink XL" },
201 	{ TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV,
202 		"3Com 3c980C Fast Etherlink XL" },
203 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX,
204 		"3Com 3cSOHO100-TX OfficeConnect" },
205 	{ TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT,
206 		"3Com 3c450-TX HomeConnect" },
207 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_555,
208 		"3Com 3c555 Fast Etherlink XL" },
209 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556,
210 		"3Com 3c556 Fast Etherlink XL" },
211 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_556B,
212 		"3Com 3c556B Fast Etherlink XL" },
213 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575A,
214 		"3Com 3c575TX Fast Etherlink XL" },
215 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575B,
216 		"3Com 3c575B Fast Etherlink XL" },
217 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_575C,
218 		"3Com 3c575C Fast Etherlink XL" },
219 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656,
220 		"3Com 3c656 Fast Etherlink XL" },
221 	{ TC_VENDORID, TC_DEVICEID_HURRICANE_656B,
222 		"3Com 3c656B Fast Etherlink XL" },
223 	{ TC_VENDORID, TC_DEVICEID_TORNADO_656C,
224 		"3Com 3c656C Fast Etherlink XL" },
225 	{ 0, 0, NULL }
226 };
227 
228 static int xl_probe(device_t);
229 static int xl_attach(device_t);
230 static int xl_detach(device_t);
231 
232 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *);
233 static void xl_tick(void *);
234 static void xl_stats_update(struct xl_softc *);
235 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **);
236 static int xl_rxeof(struct xl_softc *);
237 static void xl_rxeof_task(void *, int);
238 static int xl_rx_resync(struct xl_softc *);
239 static void xl_txeof(struct xl_softc *);
240 static void xl_txeof_90xB(struct xl_softc *);
241 static void xl_txeoc(struct xl_softc *);
242 static void xl_intr(void *);
243 static void xl_start(struct ifnet *);
244 static void xl_start_locked(struct ifnet *);
245 static void xl_start_90xB_locked(struct ifnet *);
246 static int xl_ioctl(struct ifnet *, u_long, caddr_t);
247 static void xl_init(void *);
248 static void xl_init_locked(struct xl_softc *);
249 static void xl_stop(struct xl_softc *);
250 static int xl_watchdog(struct xl_softc *);
251 static int xl_shutdown(device_t);
252 static int xl_suspend(device_t);
253 static int xl_resume(device_t);
254 static void xl_setwol(struct xl_softc *);
255 
256 #ifdef DEVICE_POLLING
257 static int xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
258 static int xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count);
259 #endif
260 
261 static int xl_ifmedia_upd(struct ifnet *);
262 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *);
263 
264 static int xl_eeprom_wait(struct xl_softc *);
265 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int);
266 
267 static void xl_rxfilter(struct xl_softc *);
268 static void xl_rxfilter_90x(struct xl_softc *);
269 static void xl_rxfilter_90xB(struct xl_softc *);
270 static void xl_setcfg(struct xl_softc *);
271 static void xl_setmode(struct xl_softc *, int);
272 static void xl_reset(struct xl_softc *);
273 static int xl_list_rx_init(struct xl_softc *);
274 static int xl_list_tx_init(struct xl_softc *);
275 static int xl_list_tx_init_90xB(struct xl_softc *);
276 static void xl_wait(struct xl_softc *);
277 static void xl_mediacheck(struct xl_softc *);
278 static void xl_choose_media(struct xl_softc *sc, int *media);
279 static void xl_choose_xcvr(struct xl_softc *, int);
280 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int);
281 #ifdef notdef
282 static void xl_testpacket(struct xl_softc *);
283 #endif
284 
285 static int xl_miibus_readreg(device_t, int, int);
286 static int xl_miibus_writereg(device_t, int, int, int);
287 static void xl_miibus_statchg(device_t);
288 static void xl_miibus_mediainit(device_t);
289 
290 /*
291  * MII bit-bang glue
292  */
293 static uint32_t xl_mii_bitbang_read(device_t);
294 static void xl_mii_bitbang_write(device_t, uint32_t);
295 
296 static const struct mii_bitbang_ops xl_mii_bitbang_ops = {
297 	xl_mii_bitbang_read,
298 	xl_mii_bitbang_write,
299 	{
300 		XL_MII_DATA,		/* MII_BIT_MDO */
301 		XL_MII_DATA,		/* MII_BIT_MDI */
302 		XL_MII_CLK,		/* MII_BIT_MDC */
303 		XL_MII_DIR,		/* MII_BIT_DIR_HOST_PHY */
304 		0,			/* MII_BIT_DIR_PHY_HOST */
305 	}
306 };
307 
308 static device_method_t xl_methods[] = {
309 	/* Device interface */
310 	DEVMETHOD(device_probe,		xl_probe),
311 	DEVMETHOD(device_attach,	xl_attach),
312 	DEVMETHOD(device_detach,	xl_detach),
313 	DEVMETHOD(device_shutdown,	xl_shutdown),
314 	DEVMETHOD(device_suspend,	xl_suspend),
315 	DEVMETHOD(device_resume,	xl_resume),
316 
317 	/* MII interface */
318 	DEVMETHOD(miibus_readreg,	xl_miibus_readreg),
319 	DEVMETHOD(miibus_writereg,	xl_miibus_writereg),
320 	DEVMETHOD(miibus_statchg,	xl_miibus_statchg),
321 	DEVMETHOD(miibus_mediainit,	xl_miibus_mediainit),
322 
323 	DEVMETHOD_END
324 };
325 
326 static driver_t xl_driver = {
327 	"xl",
328 	xl_methods,
329 	sizeof(struct xl_softc)
330 };
331 
332 DRIVER_MODULE_ORDERED(xl, pci, xl_driver, NULL, NULL, SI_ORDER_ANY);
333 DRIVER_MODULE(miibus, xl, miibus_driver, NULL, NULL);
334 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, xl, xl_devs,
335     nitems(xl_devs) - 1);
336 
337 static void
338 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
339 {
340 	u_int32_t *paddr;
341 
342 	paddr = arg;
343 	*paddr = segs->ds_addr;
344 }
345 
346 /*
347  * Murphy's law says that it's possible the chip can wedge and
348  * the 'command in progress' bit may never clear. Hence, we wait
349  * only a finite amount of time to avoid getting caught in an
350  * infinite loop. Normally this delay routine would be a macro,
351  * but it isn't called during normal operation so we can afford
352  * to make it a function.  Suppress warning when card gone.
353  */
354 static void
355 xl_wait(struct xl_softc *sc)
356 {
357 	int			i;
358 
359 	for (i = 0; i < XL_TIMEOUT; i++) {
360 		if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0)
361 			break;
362 	}
363 
364 	if (i == XL_TIMEOUT && bus_child_present(sc->xl_dev))
365 		device_printf(sc->xl_dev, "command never completed!\n");
366 }
367 
368 /*
369  * MII access routines are provided for adapters with external
370  * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in
371  * autoneg logic that's faked up to look like a PHY (3c905B-TX).
372  * Note: if you don't perform the MDIO operations just right,
373  * it's possible to end up with code that works correctly with
374  * some chips/CPUs/processor speeds/bus speeds/etc but not
375  * with others.
376  */
377 
378 /*
379  * Read the MII serial port for the MII bit-bang module.
380  */
381 static uint32_t
382 xl_mii_bitbang_read(device_t dev)
383 {
384 	struct xl_softc		*sc;
385 	uint32_t		val;
386 
387 	sc = device_get_softc(dev);
388 
389 	/* We're already in window 4. */
390 	val = CSR_READ_2(sc, XL_W4_PHY_MGMT);
391 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
392 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
393 
394 	return (val);
395 }
396 
397 /*
398  * Write the MII serial port for the MII bit-bang module.
399  */
400 static void
401 xl_mii_bitbang_write(device_t dev, uint32_t val)
402 {
403 	struct xl_softc		*sc;
404 
405 	sc = device_get_softc(dev);
406 
407 	/* We're already in window 4. */
408 	CSR_WRITE_2(sc, XL_W4_PHY_MGMT,	val);
409 	CSR_BARRIER(sc, XL_W4_PHY_MGMT, 2,
410 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
411 }
412 
413 static int
414 xl_miibus_readreg(device_t dev, int phy, int reg)
415 {
416 	struct xl_softc		*sc;
417 
418 	sc = device_get_softc(dev);
419 
420 	/* Select the window 4. */
421 	XL_SEL_WIN(4);
422 
423 	return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
424 }
425 
426 static int
427 xl_miibus_writereg(device_t dev, int phy, int reg, int data)
428 {
429 	struct xl_softc		*sc;
430 
431 	sc = device_get_softc(dev);
432 
433 	/* Select the window 4. */
434 	XL_SEL_WIN(4);
435 
436 	mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
437 
438 	return (0);
439 }
440 
441 static void
442 xl_miibus_statchg(device_t dev)
443 {
444 	struct xl_softc		*sc;
445 	struct mii_data		*mii;
446 	uint8_t			macctl;
447 
448 	sc = device_get_softc(dev);
449 	mii = device_get_softc(sc->xl_miibus);
450 
451 	xl_setcfg(sc);
452 
453 	/* Set ASIC's duplex mode to match the PHY. */
454 	XL_SEL_WIN(3);
455 	macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
456 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
457 		macctl |= XL_MACCTRL_DUPLEX;
458 		if (sc->xl_type == XL_TYPE_905B) {
459 			if ((IFM_OPTIONS(mii->mii_media_active) &
460 			    IFM_ETH_RXPAUSE) != 0)
461 				macctl |= XL_MACCTRL_FLOW_CONTROL_ENB;
462 			else
463 				macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
464 		}
465 	} else {
466 		macctl &= ~XL_MACCTRL_DUPLEX;
467 		if (sc->xl_type == XL_TYPE_905B)
468 			macctl &= ~XL_MACCTRL_FLOW_CONTROL_ENB;
469 	}
470 	CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
471 }
472 
473 /*
474  * Special support for the 3c905B-COMBO. This card has 10/100 support
475  * plus BNC and AUI ports. This means we will have both an miibus attached
476  * plus some non-MII media settings. In order to allow this, we have to
477  * add the extra media to the miibus's ifmedia struct, but we can't do
478  * that during xl_attach() because the miibus hasn't been attached yet.
479  * So instead, we wait until the miibus probe/attach is done, at which
480  * point we will get a callback telling is that it's safe to add our
481  * extra media.
482  */
483 static void
484 xl_miibus_mediainit(device_t dev)
485 {
486 	struct xl_softc		*sc;
487 	struct mii_data		*mii;
488 	struct ifmedia		*ifm;
489 
490 	sc = device_get_softc(dev);
491 	mii = device_get_softc(sc->xl_miibus);
492 	ifm = &mii->mii_media;
493 
494 	if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) {
495 		/*
496 		 * Check for a 10baseFL board in disguise.
497 		 */
498 		if (sc->xl_type == XL_TYPE_905B &&
499 		    sc->xl_media == XL_MEDIAOPT_10FL) {
500 			if (bootverbose)
501 				device_printf(sc->xl_dev, "found 10baseFL\n");
502 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL);
503 			ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0,
504 			    NULL);
505 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
506 				ifmedia_add(ifm,
507 				    IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL);
508 		} else {
509 			if (bootverbose)
510 				device_printf(sc->xl_dev, "found AUI\n");
511 			ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL);
512 		}
513 	}
514 
515 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
516 		if (bootverbose)
517 			device_printf(sc->xl_dev, "found BNC\n");
518 		ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL);
519 	}
520 }
521 
522 /*
523  * The EEPROM is slow: give it time to come ready after issuing
524  * it a command.
525  */
526 static int
527 xl_eeprom_wait(struct xl_softc *sc)
528 {
529 	int			i;
530 
531 	for (i = 0; i < 100; i++) {
532 		if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY)
533 			DELAY(162);
534 		else
535 			break;
536 	}
537 
538 	if (i == 100) {
539 		device_printf(sc->xl_dev, "eeprom failed to come ready\n");
540 		return (1);
541 	}
542 
543 	return (0);
544 }
545 
546 /*
547  * Read a sequence of words from the EEPROM. Note that ethernet address
548  * data is stored in the EEPROM in network byte order.
549  */
550 static int
551 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap)
552 {
553 	int			err = 0, i;
554 	u_int16_t		word = 0, *ptr;
555 
556 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F))
557 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F)
558 	/*
559 	 * XXX: WARNING! DANGER!
560 	 * It's easy to accidentally overwrite the rom content!
561 	 * Note: the 3c575 uses 8bit EEPROM offsets.
562 	 */
563 	XL_SEL_WIN(0);
564 
565 	if (xl_eeprom_wait(sc))
566 		return (1);
567 
568 	if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30)
569 		off += 0x30;
570 
571 	for (i = 0; i < cnt; i++) {
572 		if (sc->xl_flags & XL_FLAG_8BITROM)
573 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
574 			    XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i));
575 		else
576 			CSR_WRITE_2(sc, XL_W0_EE_CMD,
577 			    XL_EE_READ | EEPROM_5BIT_OFFSET(off + i));
578 		err = xl_eeprom_wait(sc);
579 		if (err)
580 			break;
581 		word = CSR_READ_2(sc, XL_W0_EE_DATA);
582 		ptr = (u_int16_t *)(dest + (i * 2));
583 		if (swap)
584 			*ptr = ntohs(word);
585 		else
586 			*ptr = word;
587 	}
588 
589 	return (err ? 1 : 0);
590 }
591 
592 static void
593 xl_rxfilter(struct xl_softc *sc)
594 {
595 
596 	if (sc->xl_type == XL_TYPE_905B)
597 		xl_rxfilter_90xB(sc);
598 	else
599 		xl_rxfilter_90x(sc);
600 }
601 
602 /*
603  * NICs older than the 3c905B have only one multicast option, which
604  * is to enable reception of all multicast frames.
605  */
606 static u_int
607 xl_check_maddr_90x(void *arg, struct sockaddr_dl *sdl, u_int cnt)
608 {
609 	uint8_t *rxfilt = arg;
610 
611 	*rxfilt |= XL_RXFILTER_ALLMULTI;
612 
613 	return (1);
614 }
615 
616 static void
617 xl_rxfilter_90x(struct xl_softc *sc)
618 {
619 	struct ifnet		*ifp;
620 	u_int8_t		rxfilt;
621 
622 	XL_LOCK_ASSERT(sc);
623 
624 	ifp = sc->xl_ifp;
625 
626 	XL_SEL_WIN(5);
627 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
628 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
629 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL);
630 
631 	/* Set the individual bit to receive frames for this host only. */
632 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
633 	/* Set capture broadcast bit to capture broadcast frames. */
634 	if (ifp->if_flags & IFF_BROADCAST)
635 		rxfilt |= XL_RXFILTER_BROADCAST;
636 
637 	/* If we want promiscuous mode, set the allframes bit. */
638 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
639 		if (ifp->if_flags & IFF_PROMISC)
640 			rxfilt |= XL_RXFILTER_ALLFRAMES;
641 		if (ifp->if_flags & IFF_ALLMULTI)
642 			rxfilt |= XL_RXFILTER_ALLMULTI;
643 	} else
644 		if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90x, &rxfilt);
645 
646 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
647 	XL_SEL_WIN(7);
648 }
649 
650 /*
651  * 3c905B adapters have a hash filter that we can program.
652  * Note: the 3c905B currently only supports a 64-bit
653  * hash table, which means we really only need 6 bits,
654  * but the manual indicates that future chip revisions
655  * will have a 256-bit hash table, hence the routine
656  * is set up to calculate 8 bits of position info in
657  * case we need it some day.
658  * Note II, The Sequel: _CURRENT_ versions of the
659  * 3c905B have a 256 bit hash table. This means we have
660  * to use all 8 bits regardless.  On older cards, the
661  * upper 2 bits will be ignored. Grrrr....
662  */
663 static u_int
664 xl_check_maddr_90xB(void *arg, struct sockaddr_dl *sdl, u_int count)
665 {
666 	struct xl_softc *sc = arg;
667 	uint16_t h;
668 
669 	h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) & 0xFF;
670 	CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET);
671 
672 	return (1);
673 }
674 
675 static void
676 xl_rxfilter_90xB(struct xl_softc *sc)
677 {
678 	struct ifnet		*ifp;
679 	int			i;
680 	u_int8_t		rxfilt;
681 
682 	XL_LOCK_ASSERT(sc);
683 
684 	ifp = sc->xl_ifp;
685 
686 	XL_SEL_WIN(5);
687 	rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER);
688 	rxfilt &= ~(XL_RXFILTER_ALLFRAMES | XL_RXFILTER_ALLMULTI |
689 	    XL_RXFILTER_BROADCAST | XL_RXFILTER_INDIVIDUAL |
690 	    XL_RXFILTER_MULTIHASH);
691 
692 	/* Set the individual bit to receive frames for this host only. */
693 	rxfilt |= XL_RXFILTER_INDIVIDUAL;
694 	/* Set capture broadcast bit to capture broadcast frames. */
695 	if (ifp->if_flags & IFF_BROADCAST)
696 		rxfilt |= XL_RXFILTER_BROADCAST;
697 
698 	/* If we want promiscuous mode, set the allframes bit. */
699 	if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
700 		if (ifp->if_flags & IFF_PROMISC)
701 			rxfilt |= XL_RXFILTER_ALLFRAMES;
702 		if (ifp->if_flags & IFF_ALLMULTI)
703 			rxfilt |= XL_RXFILTER_ALLMULTI;
704 	} else {
705 		/* First, zot all the existing hash bits. */
706 		for (i = 0; i < XL_HASHFILT_SIZE; i++)
707 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i);
708 
709 		/* Now program new ones. */
710 		if (if_foreach_llmaddr(sc->xl_ifp, xl_check_maddr_90xB, sc) > 0)
711 			rxfilt |= XL_RXFILTER_MULTIHASH;
712 	}
713 
714 	CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT);
715 	XL_SEL_WIN(7);
716 }
717 
718 static void
719 xl_setcfg(struct xl_softc *sc)
720 {
721 	u_int32_t		icfg;
722 
723 	/*XL_LOCK_ASSERT(sc);*/
724 
725 	XL_SEL_WIN(3);
726 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
727 	icfg &= ~XL_ICFG_CONNECTOR_MASK;
728 	if (sc->xl_media & XL_MEDIAOPT_MII ||
729 		sc->xl_media & XL_MEDIAOPT_BT4)
730 		icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS);
731 	if (sc->xl_media & XL_MEDIAOPT_BTX)
732 		icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS);
733 
734 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
735 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
736 }
737 
738 static void
739 xl_setmode(struct xl_softc *sc, int media)
740 {
741 	u_int32_t		icfg;
742 	u_int16_t		mediastat;
743 	char			*pmsg = "", *dmsg = "";
744 
745 	XL_LOCK_ASSERT(sc);
746 
747 	XL_SEL_WIN(4);
748 	mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
749 	XL_SEL_WIN(3);
750 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG);
751 
752 	if (sc->xl_media & XL_MEDIAOPT_BT) {
753 		if (IFM_SUBTYPE(media) == IFM_10_T) {
754 			pmsg = "10baseT transceiver";
755 			sc->xl_xcvr = XL_XCVR_10BT;
756 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
757 			icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS);
758 			mediastat |= XL_MEDIASTAT_LINKBEAT |
759 			    XL_MEDIASTAT_JABGUARD;
760 			mediastat &= ~XL_MEDIASTAT_SQEENB;
761 		}
762 	}
763 
764 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
765 		if (IFM_SUBTYPE(media) == IFM_100_FX) {
766 			pmsg = "100baseFX port";
767 			sc->xl_xcvr = XL_XCVR_100BFX;
768 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
769 			icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS);
770 			mediastat |= XL_MEDIASTAT_LINKBEAT;
771 			mediastat &= ~XL_MEDIASTAT_SQEENB;
772 		}
773 	}
774 
775 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
776 		if (IFM_SUBTYPE(media) == IFM_10_5) {
777 			pmsg = "AUI port";
778 			sc->xl_xcvr = XL_XCVR_AUI;
779 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
780 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
781 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
782 			    XL_MEDIASTAT_JABGUARD);
783 			mediastat |= ~XL_MEDIASTAT_SQEENB;
784 		}
785 		if (IFM_SUBTYPE(media) == IFM_10_FL) {
786 			pmsg = "10baseFL transceiver";
787 			sc->xl_xcvr = XL_XCVR_AUI;
788 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
789 			icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS);
790 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
791 			    XL_MEDIASTAT_JABGUARD);
792 			mediastat |= ~XL_MEDIASTAT_SQEENB;
793 		}
794 	}
795 
796 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
797 		if (IFM_SUBTYPE(media) == IFM_10_2) {
798 			pmsg = "AUI port";
799 			sc->xl_xcvr = XL_XCVR_COAX;
800 			icfg &= ~XL_ICFG_CONNECTOR_MASK;
801 			icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS);
802 			mediastat &= ~(XL_MEDIASTAT_LINKBEAT |
803 			    XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB);
804 		}
805 	}
806 
807 	if ((media & IFM_GMASK) == IFM_FDX ||
808 			IFM_SUBTYPE(media) == IFM_100_FX) {
809 		dmsg = "full";
810 		XL_SEL_WIN(3);
811 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
812 	} else {
813 		dmsg = "half";
814 		XL_SEL_WIN(3);
815 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
816 			(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
817 	}
818 
819 	if (IFM_SUBTYPE(media) == IFM_10_2)
820 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
821 	else
822 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
823 
824 	CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg);
825 	XL_SEL_WIN(4);
826 	CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat);
827 
828 	DELAY(800);
829 	XL_SEL_WIN(7);
830 
831 	device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg);
832 }
833 
834 static void
835 xl_reset(struct xl_softc *sc)
836 {
837 	int			i;
838 
839 	XL_LOCK_ASSERT(sc);
840 
841 	XL_SEL_WIN(0);
842 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET |
843 	    ((sc->xl_flags & XL_FLAG_WEIRDRESET) ?
844 	     XL_RESETOPT_DISADVFD:0));
845 
846 	/*
847 	 * If we're using memory mapped register mode, pause briefly
848 	 * after issuing the reset command before trying to access any
849 	 * other registers. With my 3c575C CardBus card, failing to do
850 	 * this results in the system locking up while trying to poll
851 	 * the command busy bit in the status register.
852 	 */
853 	if (sc->xl_flags & XL_FLAG_USE_MMIO)
854 		DELAY(100000);
855 
856 	for (i = 0; i < XL_TIMEOUT; i++) {
857 		DELAY(10);
858 		if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY))
859 			break;
860 	}
861 
862 	if (i == XL_TIMEOUT)
863 		device_printf(sc->xl_dev, "reset didn't complete\n");
864 
865 	/* Reset TX and RX. */
866 	/* Note: the RX reset takes an absurd amount of time
867 	 * on newer versions of the Tornado chips such as those
868 	 * on the 3c905CX and newer 3c908C cards. We wait an
869 	 * extra amount of time so that xl_wait() doesn't complain
870 	 * and annoy the users.
871 	 */
872 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
873 	DELAY(100000);
874 	xl_wait(sc);
875 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
876 	xl_wait(sc);
877 
878 	if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR ||
879 	    sc->xl_flags & XL_FLAG_INVERT_MII_PWR) {
880 		XL_SEL_WIN(2);
881 		CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS,
882 		    CSR_READ_2(sc, XL_W2_RESET_OPTIONS) |
883 		    ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ?
884 		    XL_RESETOPT_INVERT_LED : 0) |
885 		    ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ?
886 		    XL_RESETOPT_INVERT_MII : 0));
887 	}
888 
889 	/* Wait a little while for the chip to get its brains in order. */
890 	DELAY(100000);
891 }
892 
893 /*
894  * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device
895  * IDs against our list and return a device name if we find a match.
896  */
897 static int
898 xl_probe(device_t dev)
899 {
900 	const struct xl_type	*t;
901 
902 	t = xl_devs;
903 
904 	while (t->xl_name != NULL) {
905 		if ((pci_get_vendor(dev) == t->xl_vid) &&
906 		    (pci_get_device(dev) == t->xl_did)) {
907 			device_set_desc(dev, t->xl_name);
908 			return (BUS_PROBE_DEFAULT);
909 		}
910 		t++;
911 	}
912 
913 	return (ENXIO);
914 }
915 
916 /*
917  * This routine is a kludge to work around possible hardware faults
918  * or manufacturing defects that can cause the media options register
919  * (or reset options register, as it's called for the first generation
920  * 3c90x adapters) to return an incorrect result. I have encountered
921  * one Dell Latitude laptop docking station with an integrated 3c905-TX
922  * which doesn't have any of the 'mediaopt' bits set. This screws up
923  * the attach routine pretty badly because it doesn't know what media
924  * to look for. If we find ourselves in this predicament, this routine
925  * will try to guess the media options values and warn the user of a
926  * possible manufacturing defect with his adapter/system/whatever.
927  */
928 static void
929 xl_mediacheck(struct xl_softc *sc)
930 {
931 
932 	/*
933 	 * If some of the media options bits are set, assume they are
934 	 * correct. If not, try to figure it out down below.
935 	 * XXX I should check for 10baseFL, but I don't have an adapter
936 	 * to test with.
937 	 */
938 	if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) {
939 		/*
940 		 * Check the XCVR value. If it's not in the normal range
941 		 * of values, we need to fake it up here.
942 		 */
943 		if (sc->xl_xcvr <= XL_XCVR_AUTO)
944 			return;
945 		else {
946 			device_printf(sc->xl_dev,
947 			    "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr);
948 			device_printf(sc->xl_dev,
949 			    "choosing new default based on card type\n");
950 		}
951 	} else {
952 		if (sc->xl_type == XL_TYPE_905B &&
953 		    sc->xl_media & XL_MEDIAOPT_10FL)
954 			return;
955 		device_printf(sc->xl_dev,
956 "WARNING: no media options bits set in the media options register!!\n");
957 		device_printf(sc->xl_dev,
958 "this could be a manufacturing defect in your adapter or system\n");
959 		device_printf(sc->xl_dev,
960 "attempting to guess media type; you should probably consult your vendor\n");
961 	}
962 
963 	xl_choose_xcvr(sc, 1);
964 }
965 
966 static void
967 xl_choose_xcvr(struct xl_softc *sc, int verbose)
968 {
969 	u_int16_t		devid;
970 
971 	/*
972 	 * Read the device ID from the EEPROM.
973 	 * This is what's loaded into the PCI device ID register, so it has
974 	 * to be correct otherwise we wouldn't have gotten this far.
975 	 */
976 	xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0);
977 
978 	switch (devid) {
979 	case TC_DEVICEID_BOOMERANG_10BT:	/* 3c900-TPO */
980 	case TC_DEVICEID_KRAKATOA_10BT:		/* 3c900B-TPO */
981 		sc->xl_media = XL_MEDIAOPT_BT;
982 		sc->xl_xcvr = XL_XCVR_10BT;
983 		if (verbose)
984 			device_printf(sc->xl_dev,
985 			    "guessing 10BaseT transceiver\n");
986 		break;
987 	case TC_DEVICEID_BOOMERANG_10BT_COMBO:	/* 3c900-COMBO */
988 	case TC_DEVICEID_KRAKATOA_10BT_COMBO:	/* 3c900B-COMBO */
989 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
990 		sc->xl_xcvr = XL_XCVR_10BT;
991 		if (verbose)
992 			device_printf(sc->xl_dev,
993 			    "guessing COMBO (AUI/BNC/TP)\n");
994 		break;
995 	case TC_DEVICEID_KRAKATOA_10BT_TPC:	/* 3c900B-TPC */
996 		sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC;
997 		sc->xl_xcvr = XL_XCVR_10BT;
998 		if (verbose)
999 			device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n");
1000 		break;
1001 	case TC_DEVICEID_CYCLONE_10FL:		/* 3c900B-FL */
1002 		sc->xl_media = XL_MEDIAOPT_10FL;
1003 		sc->xl_xcvr = XL_XCVR_AUI;
1004 		if (verbose)
1005 			device_printf(sc->xl_dev, "guessing 10baseFL\n");
1006 		break;
1007 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1008 	case TC_DEVICEID_HURRICANE_555:		/* 3c555 */
1009 	case TC_DEVICEID_HURRICANE_556:		/* 3c556 */
1010 	case TC_DEVICEID_HURRICANE_556B:	/* 3c556B */
1011 	case TC_DEVICEID_HURRICANE_575A:	/* 3c575TX */
1012 	case TC_DEVICEID_HURRICANE_575B:	/* 3c575B */
1013 	case TC_DEVICEID_HURRICANE_575C:	/* 3c575C */
1014 	case TC_DEVICEID_HURRICANE_656:		/* 3c656 */
1015 	case TC_DEVICEID_HURRICANE_656B:	/* 3c656B */
1016 	case TC_DEVICEID_TORNADO_656C:		/* 3c656C */
1017 	case TC_DEVICEID_TORNADO_10_100BT_920B:	/* 3c920B-EMB */
1018 	case TC_DEVICEID_TORNADO_10_100BT_920B_WNM:	/* 3c920B-EMB-WNM */
1019 		sc->xl_media = XL_MEDIAOPT_MII;
1020 		sc->xl_xcvr = XL_XCVR_MII;
1021 		if (verbose)
1022 			device_printf(sc->xl_dev, "guessing MII\n");
1023 		break;
1024 	case TC_DEVICEID_BOOMERANG_100BT4:	/* 3c905-T4 */
1025 	case TC_DEVICEID_CYCLONE_10_100BT4:	/* 3c905B-T4 */
1026 		sc->xl_media = XL_MEDIAOPT_BT4;
1027 		sc->xl_xcvr = XL_XCVR_MII;
1028 		if (verbose)
1029 			device_printf(sc->xl_dev, "guessing 100baseT4/MII\n");
1030 		break;
1031 	case TC_DEVICEID_HURRICANE_10_100BT:	/* 3c905B-TX */
1032 	case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */
1033 	case TC_DEVICEID_TORNADO_10_100BT_SERV:	/* 3c980C-TX */
1034 	case TC_DEVICEID_HURRICANE_SOHO100TX:	/* 3cSOHO100-TX */
1035 	case TC_DEVICEID_TORNADO_10_100BT:	/* 3c905C-TX */
1036 	case TC_DEVICEID_TORNADO_HOMECONNECT:	/* 3c450-TX */
1037 		sc->xl_media = XL_MEDIAOPT_BTX;
1038 		sc->xl_xcvr = XL_XCVR_AUTO;
1039 		if (verbose)
1040 			device_printf(sc->xl_dev, "guessing 10/100 internal\n");
1041 		break;
1042 	case TC_DEVICEID_CYCLONE_10_100_COMBO:	/* 3c905B-COMBO */
1043 		sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI;
1044 		sc->xl_xcvr = XL_XCVR_AUTO;
1045 		if (verbose)
1046 			device_printf(sc->xl_dev,
1047 			    "guessing 10/100 plus BNC/AUI\n");
1048 		break;
1049 	default:
1050 		device_printf(sc->xl_dev,
1051 		    "unknown device ID: %x -- defaulting to 10baseT\n", devid);
1052 		sc->xl_media = XL_MEDIAOPT_BT;
1053 		break;
1054 	}
1055 }
1056 
1057 /*
1058  * Attach the interface. Allocate softc structures, do ifmedia
1059  * setup and ethernet/BPF attach.
1060  */
1061 static int
1062 xl_attach(device_t dev)
1063 {
1064 	u_char			eaddr[ETHER_ADDR_LEN];
1065 	u_int16_t		sinfo2, xcvr[2];
1066 	struct xl_softc		*sc;
1067 	struct ifnet		*ifp;
1068 	int			media, pmcap;
1069 	int			error = 0, phy, rid, res;
1070 	uint16_t		did;
1071 
1072 	sc = device_get_softc(dev);
1073 	sc->xl_dev = dev;
1074 
1075 	mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1076 	    MTX_DEF);
1077 	ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts);
1078 
1079 	did = pci_get_device(dev);
1080 
1081 	sc->xl_flags = 0;
1082 	if (did == TC_DEVICEID_HURRICANE_555)
1083 		sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK;
1084 	if (did == TC_DEVICEID_HURRICANE_556 ||
1085 	    did == TC_DEVICEID_HURRICANE_556B)
1086 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK |
1087 		    XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET |
1088 		    XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR;
1089 	if (did == TC_DEVICEID_HURRICANE_555 ||
1090 	    did == TC_DEVICEID_HURRICANE_556)
1091 		sc->xl_flags |= XL_FLAG_8BITROM;
1092 	if (did == TC_DEVICEID_HURRICANE_556B)
1093 		sc->xl_flags |= XL_FLAG_NO_XCVR_PWR;
1094 
1095 	if (did == TC_DEVICEID_HURRICANE_575B ||
1096 	    did == TC_DEVICEID_HURRICANE_575C ||
1097 	    did == TC_DEVICEID_HURRICANE_656B ||
1098 	    did == TC_DEVICEID_TORNADO_656C)
1099 		sc->xl_flags |= XL_FLAG_FUNCREG;
1100 	if (did == TC_DEVICEID_HURRICANE_575A ||
1101 	    did == TC_DEVICEID_HURRICANE_575B ||
1102 	    did == TC_DEVICEID_HURRICANE_575C ||
1103 	    did == TC_DEVICEID_HURRICANE_656B ||
1104 	    did == TC_DEVICEID_TORNADO_656C)
1105 		sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 |
1106 		  XL_FLAG_8BITROM;
1107 	if (did == TC_DEVICEID_HURRICANE_656)
1108 		sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK;
1109 	if (did == TC_DEVICEID_HURRICANE_575B)
1110 		sc->xl_flags |= XL_FLAG_INVERT_LED_PWR;
1111 	if (did == TC_DEVICEID_HURRICANE_575C)
1112 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1113 	if (did == TC_DEVICEID_TORNADO_656C)
1114 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR;
1115 	if (did == TC_DEVICEID_HURRICANE_656 ||
1116 	    did == TC_DEVICEID_HURRICANE_656B)
1117 		sc->xl_flags |= XL_FLAG_INVERT_MII_PWR |
1118 		    XL_FLAG_INVERT_LED_PWR;
1119 	if (did == TC_DEVICEID_TORNADO_10_100BT_920B ||
1120 	    did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM)
1121 		sc->xl_flags |= XL_FLAG_PHYOK;
1122 
1123 	switch (did) {
1124 	case TC_DEVICEID_BOOMERANG_10_100BT:	/* 3c905-TX */
1125 	case TC_DEVICEID_HURRICANE_575A:
1126 	case TC_DEVICEID_HURRICANE_575B:
1127 	case TC_DEVICEID_HURRICANE_575C:
1128 		sc->xl_flags |= XL_FLAG_NO_MMIO;
1129 		break;
1130 	default:
1131 		break;
1132 	}
1133 
1134 	/*
1135 	 * Map control/status registers.
1136 	 */
1137 	pci_enable_busmaster(dev);
1138 
1139 	if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) {
1140 		rid = XL_PCI_LOMEM;
1141 		res = SYS_RES_MEMORY;
1142 
1143 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1144 	}
1145 
1146 	if (sc->xl_res != NULL) {
1147 		sc->xl_flags |= XL_FLAG_USE_MMIO;
1148 		if (bootverbose)
1149 			device_printf(dev, "using memory mapped I/O\n");
1150 	} else {
1151 		rid = XL_PCI_LOIO;
1152 		res = SYS_RES_IOPORT;
1153 		sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE);
1154 		if (sc->xl_res == NULL) {
1155 			device_printf(dev, "couldn't map ports/memory\n");
1156 			error = ENXIO;
1157 			goto fail;
1158 		}
1159 		if (bootverbose)
1160 			device_printf(dev, "using port I/O\n");
1161 	}
1162 
1163 	sc->xl_btag = rman_get_bustag(sc->xl_res);
1164 	sc->xl_bhandle = rman_get_bushandle(sc->xl_res);
1165 
1166 	if (sc->xl_flags & XL_FLAG_FUNCREG) {
1167 		rid = XL_PCI_FUNCMEM;
1168 		sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1169 		    RF_ACTIVE);
1170 
1171 		if (sc->xl_fres == NULL) {
1172 			device_printf(dev, "couldn't map funcreg memory\n");
1173 			error = ENXIO;
1174 			goto fail;
1175 		}
1176 
1177 		sc->xl_ftag = rman_get_bustag(sc->xl_fres);
1178 		sc->xl_fhandle = rman_get_bushandle(sc->xl_fres);
1179 	}
1180 
1181 	/* Allocate interrupt */
1182 	rid = 0;
1183 	sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1184 	    RF_SHAREABLE | RF_ACTIVE);
1185 	if (sc->xl_irq == NULL) {
1186 		device_printf(dev, "couldn't map interrupt\n");
1187 		error = ENXIO;
1188 		goto fail;
1189 	}
1190 
1191 	/* Initialize interface name. */
1192 	ifp = sc->xl_ifp = if_alloc(IFT_ETHER);
1193 	if (ifp == NULL) {
1194 		device_printf(dev, "can not if_alloc()\n");
1195 		error = ENOSPC;
1196 		goto fail;
1197 	}
1198 	ifp->if_softc = sc;
1199 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1200 
1201 	/* Reset the adapter. */
1202 	XL_LOCK(sc);
1203 	xl_reset(sc);
1204 	XL_UNLOCK(sc);
1205 
1206 	/*
1207 	 * Get station address from the EEPROM.
1208 	 */
1209 	if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) {
1210 		device_printf(dev, "failed to read station address\n");
1211 		error = ENXIO;
1212 		goto fail;
1213 	}
1214 
1215 	callout_init_mtx(&sc->xl_tick_callout, &sc->xl_mtx, 0);
1216 	NET_TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc);
1217 
1218 	/*
1219 	 * Now allocate a tag for the DMA descriptor lists and a chunk
1220 	 * of DMA-able memory based on the tag.  Also obtain the DMA
1221 	 * addresses of the RX and TX ring, which we'll need later.
1222 	 * All of our lists are allocated as a contiguous block
1223 	 * of memory.
1224 	 */
1225 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1226 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1227 	    XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL,
1228 	    &sc->xl_ldata.xl_rx_tag);
1229 	if (error) {
1230 		device_printf(dev, "failed to allocate rx dma tag\n");
1231 		goto fail;
1232 	}
1233 
1234 	error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag,
1235 	    (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT |
1236 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_rx_dmamap);
1237 	if (error) {
1238 		device_printf(dev, "no memory for rx list buffers!\n");
1239 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1240 		sc->xl_ldata.xl_rx_tag = NULL;
1241 		goto fail;
1242 	}
1243 
1244 	error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag,
1245 	    sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list,
1246 	    XL_RX_LIST_SZ, xl_dma_map_addr,
1247 	    &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT);
1248 	if (error) {
1249 		device_printf(dev, "cannot get dma address of the rx ring!\n");
1250 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1251 		    sc->xl_ldata.xl_rx_dmamap);
1252 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1253 		sc->xl_ldata.xl_rx_tag = NULL;
1254 		goto fail;
1255 	}
1256 
1257 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
1258 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1259 	    XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL,
1260 	    &sc->xl_ldata.xl_tx_tag);
1261 	if (error) {
1262 		device_printf(dev, "failed to allocate tx dma tag\n");
1263 		goto fail;
1264 	}
1265 
1266 	error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag,
1267 	    (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT |
1268 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->xl_ldata.xl_tx_dmamap);
1269 	if (error) {
1270 		device_printf(dev, "no memory for list buffers!\n");
1271 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1272 		sc->xl_ldata.xl_tx_tag = NULL;
1273 		goto fail;
1274 	}
1275 
1276 	error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag,
1277 	    sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list,
1278 	    XL_TX_LIST_SZ, xl_dma_map_addr,
1279 	    &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT);
1280 	if (error) {
1281 		device_printf(dev, "cannot get dma address of the tx ring!\n");
1282 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1283 		    sc->xl_ldata.xl_tx_dmamap);
1284 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1285 		sc->xl_ldata.xl_tx_tag = NULL;
1286 		goto fail;
1287 	}
1288 
1289 	/*
1290 	 * Allocate a DMA tag for the mapping of mbufs.
1291 	 */
1292 	error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
1293 	    BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
1294 	    MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL,
1295 	    NULL, &sc->xl_mtag);
1296 	if (error) {
1297 		device_printf(dev, "failed to allocate mbuf dma tag\n");
1298 		goto fail;
1299 	}
1300 
1301 	/* We need a spare DMA map for the RX ring. */
1302 	error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap);
1303 	if (error)
1304 		goto fail;
1305 
1306 	/*
1307 	 * Figure out the card type. 3c905B adapters have the
1308 	 * 'supportsNoTxLength' bit set in the capabilities
1309 	 * word in the EEPROM.
1310 	 * Note: my 3c575C CardBus card lies. It returns a value
1311 	 * of 0x1578 for its capabilities word, which is somewhat
1312 	 * nonsensical. Another way to distinguish a 3c90x chip
1313 	 * from a 3c90xB/C chip is to check for the 'supportsLargePackets'
1314 	 * bit. This will only be set for 3c90x boomerage chips.
1315 	 */
1316 	xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0);
1317 	if (sc->xl_caps & XL_CAPS_NO_TXLENGTH ||
1318 	    !(sc->xl_caps & XL_CAPS_LARGE_PKTS))
1319 		sc->xl_type = XL_TYPE_905B;
1320 	else
1321 		sc->xl_type = XL_TYPE_90X;
1322 
1323 	/* Check availability of WOL. */
1324 	if ((sc->xl_caps & XL_CAPS_PWRMGMT) != 0 &&
1325 	    pci_find_cap(dev, PCIY_PMG, &pmcap) == 0) {
1326 		sc->xl_pmcap = pmcap;
1327 		sc->xl_flags |= XL_FLAG_WOL;
1328 		sinfo2 = 0;
1329 		xl_read_eeprom(sc, (caddr_t)&sinfo2, XL_EE_SOFTINFO2, 1, 0);
1330 		if ((sinfo2 & XL_SINFO2_AUX_WOL_CON) == 0 && bootverbose)
1331 			device_printf(dev,
1332 			    "No auxiliary remote wakeup connector!\n");
1333 	}
1334 
1335 	/* Set the TX start threshold for best performance. */
1336 	sc->xl_tx_thresh = XL_MIN_FRAMELEN;
1337 
1338 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1339 	ifp->if_ioctl = xl_ioctl;
1340 	ifp->if_capabilities = IFCAP_VLAN_MTU;
1341 	if (sc->xl_type == XL_TYPE_905B) {
1342 		ifp->if_hwassist = XL905B_CSUM_FEATURES;
1343 #ifdef XL905B_TXCSUM_BROKEN
1344 		ifp->if_capabilities |= IFCAP_RXCSUM;
1345 #else
1346 		ifp->if_capabilities |= IFCAP_HWCSUM;
1347 #endif
1348 	}
1349 	if ((sc->xl_flags & XL_FLAG_WOL) != 0)
1350 		ifp->if_capabilities |= IFCAP_WOL_MAGIC;
1351 	ifp->if_capenable = ifp->if_capabilities;
1352 #ifdef DEVICE_POLLING
1353 	ifp->if_capabilities |= IFCAP_POLLING;
1354 #endif
1355 	ifp->if_start = xl_start;
1356 	ifp->if_init = xl_init;
1357 	IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1);
1358 	ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1;
1359 	IFQ_SET_READY(&ifp->if_snd);
1360 
1361 	/*
1362 	 * Now we have to see what sort of media we have.
1363 	 * This includes probing for an MII interace and a
1364 	 * possible PHY.
1365 	 */
1366 	XL_SEL_WIN(3);
1367 	sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT);
1368 	if (bootverbose)
1369 		device_printf(dev, "media options word: %x\n", sc->xl_media);
1370 
1371 	xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0);
1372 	sc->xl_xcvr = xcvr[0] | xcvr[1] << 16;
1373 	sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK;
1374 	sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS;
1375 
1376 	xl_mediacheck(sc);
1377 
1378 	if (sc->xl_media & XL_MEDIAOPT_MII ||
1379 	    sc->xl_media & XL_MEDIAOPT_BTX ||
1380 	    sc->xl_media & XL_MEDIAOPT_BT4) {
1381 		if (bootverbose)
1382 			device_printf(dev, "found MII/AUTO\n");
1383 		xl_setcfg(sc);
1384 		/*
1385 		 * Attach PHYs only at MII address 24 if !XL_FLAG_PHYOK.
1386 		 * This is to guard against problems with certain 3Com ASIC
1387 		 * revisions that incorrectly map the internal transceiver
1388 		 * control registers at all MII addresses.
1389 		 */
1390 		phy = MII_PHY_ANY;
1391 		if ((sc->xl_flags & XL_FLAG_PHYOK) == 0)
1392 			phy = 24;
1393 		error = mii_attach(dev, &sc->xl_miibus, ifp, xl_ifmedia_upd,
1394 		    xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
1395 		    sc->xl_type == XL_TYPE_905B ? MIIF_DOPAUSE : 0);
1396 		if (error != 0) {
1397 			device_printf(dev, "attaching PHYs failed\n");
1398 			goto fail;
1399 		}
1400 		goto done;
1401 	}
1402 
1403 	/*
1404 	 * Sanity check. If the user has selected "auto" and this isn't
1405 	 * a 10/100 card of some kind, we need to force the transceiver
1406 	 * type to something sane.
1407 	 */
1408 	if (sc->xl_xcvr == XL_XCVR_AUTO)
1409 		xl_choose_xcvr(sc, bootverbose);
1410 
1411 	/*
1412 	 * Do ifmedia setup.
1413 	 */
1414 	if (sc->xl_media & XL_MEDIAOPT_BT) {
1415 		if (bootverbose)
1416 			device_printf(dev, "found 10baseT\n");
1417 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL);
1418 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL);
1419 		if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1420 			ifmedia_add(&sc->ifmedia,
1421 			    IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL);
1422 	}
1423 
1424 	if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) {
1425 		/*
1426 		 * Check for a 10baseFL board in disguise.
1427 		 */
1428 		if (sc->xl_type == XL_TYPE_905B &&
1429 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1430 			if (bootverbose)
1431 				device_printf(dev, "found 10baseFL\n");
1432 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL);
1433 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX,
1434 			    0, NULL);
1435 			if (sc->xl_caps & XL_CAPS_FULL_DUPLEX)
1436 				ifmedia_add(&sc->ifmedia,
1437 				    IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL);
1438 		} else {
1439 			if (bootverbose)
1440 				device_printf(dev, "found AUI\n");
1441 			ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL);
1442 		}
1443 	}
1444 
1445 	if (sc->xl_media & XL_MEDIAOPT_BNC) {
1446 		if (bootverbose)
1447 			device_printf(dev, "found BNC\n");
1448 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL);
1449 	}
1450 
1451 	if (sc->xl_media & XL_MEDIAOPT_BFX) {
1452 		if (bootverbose)
1453 			device_printf(dev, "found 100baseFX\n");
1454 		ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL);
1455 	}
1456 
1457 	media = IFM_ETHER|IFM_100_TX|IFM_FDX;
1458 	xl_choose_media(sc, &media);
1459 
1460 	if (sc->xl_miibus == NULL)
1461 		ifmedia_set(&sc->ifmedia, media);
1462 
1463 done:
1464 	if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) {
1465 		XL_SEL_WIN(0);
1466 		CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS);
1467 	}
1468 
1469 	/*
1470 	 * Call MI attach routine.
1471 	 */
1472 	ether_ifattach(ifp, eaddr);
1473 
1474 	error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1475 	    NULL, xl_intr, sc, &sc->xl_intrhand);
1476 	if (error) {
1477 		device_printf(dev, "couldn't set up irq\n");
1478 		ether_ifdetach(ifp);
1479 		goto fail;
1480 	}
1481 
1482 fail:
1483 	if (error)
1484 		xl_detach(dev);
1485 
1486 	return (error);
1487 }
1488 
1489 /*
1490  * Choose a default media.
1491  * XXX This is a leaf function only called by xl_attach() and
1492  *     acquires/releases the non-recursible driver mutex to
1493  *     satisfy lock assertions.
1494  */
1495 static void
1496 xl_choose_media(struct xl_softc *sc, int *media)
1497 {
1498 
1499 	XL_LOCK(sc);
1500 
1501 	switch (sc->xl_xcvr) {
1502 	case XL_XCVR_10BT:
1503 		*media = IFM_ETHER|IFM_10_T;
1504 		xl_setmode(sc, *media);
1505 		break;
1506 	case XL_XCVR_AUI:
1507 		if (sc->xl_type == XL_TYPE_905B &&
1508 		    sc->xl_media == XL_MEDIAOPT_10FL) {
1509 			*media = IFM_ETHER|IFM_10_FL;
1510 			xl_setmode(sc, *media);
1511 		} else {
1512 			*media = IFM_ETHER|IFM_10_5;
1513 			xl_setmode(sc, *media);
1514 		}
1515 		break;
1516 	case XL_XCVR_COAX:
1517 		*media = IFM_ETHER|IFM_10_2;
1518 		xl_setmode(sc, *media);
1519 		break;
1520 	case XL_XCVR_AUTO:
1521 	case XL_XCVR_100BTX:
1522 	case XL_XCVR_MII:
1523 		/* Chosen by miibus */
1524 		break;
1525 	case XL_XCVR_100BFX:
1526 		*media = IFM_ETHER|IFM_100_FX;
1527 		break;
1528 	default:
1529 		device_printf(sc->xl_dev, "unknown XCVR type: %d\n",
1530 		    sc->xl_xcvr);
1531 		/*
1532 		 * This will probably be wrong, but it prevents
1533 		 * the ifmedia code from panicking.
1534 		 */
1535 		*media = IFM_ETHER|IFM_10_T;
1536 		break;
1537 	}
1538 
1539 	XL_UNLOCK(sc);
1540 }
1541 
1542 /*
1543  * Shutdown hardware and free up resources. This can be called any
1544  * time after the mutex has been initialized. It is called in both
1545  * the error case in attach and the normal detach case so it needs
1546  * to be careful about only freeing resources that have actually been
1547  * allocated.
1548  */
1549 static int
1550 xl_detach(device_t dev)
1551 {
1552 	struct xl_softc		*sc;
1553 	struct ifnet		*ifp;
1554 	int			rid, res;
1555 
1556 	sc = device_get_softc(dev);
1557 	ifp = sc->xl_ifp;
1558 
1559 	KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized"));
1560 
1561 #ifdef DEVICE_POLLING
1562 	if (ifp && ifp->if_capenable & IFCAP_POLLING)
1563 		ether_poll_deregister(ifp);
1564 #endif
1565 
1566 	if (sc->xl_flags & XL_FLAG_USE_MMIO) {
1567 		rid = XL_PCI_LOMEM;
1568 		res = SYS_RES_MEMORY;
1569 	} else {
1570 		rid = XL_PCI_LOIO;
1571 		res = SYS_RES_IOPORT;
1572 	}
1573 
1574 	/* These should only be active if attach succeeded */
1575 	if (device_is_attached(dev)) {
1576 		XL_LOCK(sc);
1577 		xl_stop(sc);
1578 		XL_UNLOCK(sc);
1579 		taskqueue_drain(taskqueue_swi, &sc->xl_task);
1580 		callout_drain(&sc->xl_tick_callout);
1581 		ether_ifdetach(ifp);
1582 	}
1583 	if (sc->xl_miibus)
1584 		device_delete_child(dev, sc->xl_miibus);
1585 	bus_generic_detach(dev);
1586 	ifmedia_removeall(&sc->ifmedia);
1587 
1588 	if (sc->xl_intrhand)
1589 		bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand);
1590 	if (sc->xl_irq)
1591 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq);
1592 	if (sc->xl_fres != NULL)
1593 		bus_release_resource(dev, SYS_RES_MEMORY,
1594 		    XL_PCI_FUNCMEM, sc->xl_fres);
1595 	if (sc->xl_res)
1596 		bus_release_resource(dev, res, rid, sc->xl_res);
1597 
1598 	if (ifp)
1599 		if_free(ifp);
1600 
1601 	if (sc->xl_mtag) {
1602 		bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap);
1603 		bus_dma_tag_destroy(sc->xl_mtag);
1604 	}
1605 	if (sc->xl_ldata.xl_rx_tag) {
1606 		bus_dmamap_unload(sc->xl_ldata.xl_rx_tag,
1607 		    sc->xl_ldata.xl_rx_dmamap);
1608 		bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list,
1609 		    sc->xl_ldata.xl_rx_dmamap);
1610 		bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag);
1611 	}
1612 	if (sc->xl_ldata.xl_tx_tag) {
1613 		bus_dmamap_unload(sc->xl_ldata.xl_tx_tag,
1614 		    sc->xl_ldata.xl_tx_dmamap);
1615 		bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list,
1616 		    sc->xl_ldata.xl_tx_dmamap);
1617 		bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag);
1618 	}
1619 
1620 	mtx_destroy(&sc->xl_mtx);
1621 
1622 	return (0);
1623 }
1624 
1625 /*
1626  * Initialize the transmit descriptors.
1627  */
1628 static int
1629 xl_list_tx_init(struct xl_softc *sc)
1630 {
1631 	struct xl_chain_data	*cd;
1632 	struct xl_list_data	*ld;
1633 	int			error, i;
1634 
1635 	XL_LOCK_ASSERT(sc);
1636 
1637 	cd = &sc->xl_cdata;
1638 	ld = &sc->xl_ldata;
1639 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1640 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1641 		error = bus_dmamap_create(sc->xl_mtag, 0,
1642 		    &cd->xl_tx_chain[i].xl_map);
1643 		if (error)
1644 			return (error);
1645 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1646 		    i * sizeof(struct xl_list);
1647 		if (i == (XL_TX_LIST_CNT - 1))
1648 			cd->xl_tx_chain[i].xl_next = NULL;
1649 		else
1650 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1651 	}
1652 
1653 	cd->xl_tx_free = &cd->xl_tx_chain[0];
1654 	cd->xl_tx_tail = cd->xl_tx_head = NULL;
1655 
1656 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1657 	return (0);
1658 }
1659 
1660 /*
1661  * Initialize the transmit descriptors.
1662  */
1663 static int
1664 xl_list_tx_init_90xB(struct xl_softc *sc)
1665 {
1666 	struct xl_chain_data	*cd;
1667 	struct xl_list_data	*ld;
1668 	int			error, i;
1669 
1670 	XL_LOCK_ASSERT(sc);
1671 
1672 	cd = &sc->xl_cdata;
1673 	ld = &sc->xl_ldata;
1674 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
1675 		cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i];
1676 		error = bus_dmamap_create(sc->xl_mtag, 0,
1677 		    &cd->xl_tx_chain[i].xl_map);
1678 		if (error)
1679 			return (error);
1680 		cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr +
1681 		    i * sizeof(struct xl_list);
1682 		if (i == (XL_TX_LIST_CNT - 1))
1683 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0];
1684 		else
1685 			cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1];
1686 		if (i == 0)
1687 			cd->xl_tx_chain[i].xl_prev =
1688 			    &cd->xl_tx_chain[XL_TX_LIST_CNT - 1];
1689 		else
1690 			cd->xl_tx_chain[i].xl_prev =
1691 			    &cd->xl_tx_chain[i - 1];
1692 	}
1693 
1694 	bzero(ld->xl_tx_list, XL_TX_LIST_SZ);
1695 	ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY);
1696 
1697 	cd->xl_tx_prod = 1;
1698 	cd->xl_tx_cons = 1;
1699 	cd->xl_tx_cnt = 0;
1700 
1701 	bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE);
1702 	return (0);
1703 }
1704 
1705 /*
1706  * Initialize the RX descriptors and allocate mbufs for them. Note that
1707  * we arrange the descriptors in a closed ring, so that the last descriptor
1708  * points back to the first.
1709  */
1710 static int
1711 xl_list_rx_init(struct xl_softc *sc)
1712 {
1713 	struct xl_chain_data	*cd;
1714 	struct xl_list_data	*ld;
1715 	int			error, i, next;
1716 	u_int32_t		nextptr;
1717 
1718 	XL_LOCK_ASSERT(sc);
1719 
1720 	cd = &sc->xl_cdata;
1721 	ld = &sc->xl_ldata;
1722 
1723 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1724 		cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i];
1725 		error = bus_dmamap_create(sc->xl_mtag, 0,
1726 		    &cd->xl_rx_chain[i].xl_map);
1727 		if (error)
1728 			return (error);
1729 		error = xl_newbuf(sc, &cd->xl_rx_chain[i]);
1730 		if (error)
1731 			return (error);
1732 		if (i == (XL_RX_LIST_CNT - 1))
1733 			next = 0;
1734 		else
1735 			next = i + 1;
1736 		nextptr = ld->xl_rx_dmaaddr +
1737 		    next * sizeof(struct xl_list_onefrag);
1738 		cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next];
1739 		ld->xl_rx_list[i].xl_next = htole32(nextptr);
1740 	}
1741 
1742 	bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1743 	cd->xl_rx_head = &cd->xl_rx_chain[0];
1744 
1745 	return (0);
1746 }
1747 
1748 /*
1749  * Initialize an RX descriptor and attach an MBUF cluster.
1750  * If we fail to do so, we need to leave the old mbuf and
1751  * the old DMA map untouched so that it can be reused.
1752  */
1753 static int
1754 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c)
1755 {
1756 	struct mbuf		*m_new = NULL;
1757 	bus_dmamap_t		map;
1758 	bus_dma_segment_t	segs[1];
1759 	int			error, nseg;
1760 
1761 	XL_LOCK_ASSERT(sc);
1762 
1763 	m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1764 	if (m_new == NULL)
1765 		return (ENOBUFS);
1766 
1767 	m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
1768 
1769 	/* Force longword alignment for packet payload. */
1770 	m_adj(m_new, ETHER_ALIGN);
1771 
1772 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new,
1773 	    segs, &nseg, BUS_DMA_NOWAIT);
1774 	if (error) {
1775 		m_freem(m_new);
1776 		device_printf(sc->xl_dev, "can't map mbuf (error %d)\n",
1777 		    error);
1778 		return (error);
1779 	}
1780 	KASSERT(nseg == 1,
1781 	    ("%s: too many DMA segments (%d)", __func__, nseg));
1782 
1783 	bus_dmamap_unload(sc->xl_mtag, c->xl_map);
1784 	map = c->xl_map;
1785 	c->xl_map = sc->xl_tmpmap;
1786 	sc->xl_tmpmap = map;
1787 	c->xl_mbuf = m_new;
1788 	c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG);
1789 	c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr);
1790 	c->xl_ptr->xl_status = 0;
1791 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD);
1792 	return (0);
1793 }
1794 
1795 static int
1796 xl_rx_resync(struct xl_softc *sc)
1797 {
1798 	struct xl_chain_onefrag	*pos;
1799 	int			i;
1800 
1801 	XL_LOCK_ASSERT(sc);
1802 
1803 	pos = sc->xl_cdata.xl_rx_head;
1804 
1805 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
1806 		if (pos->xl_ptr->xl_status)
1807 			break;
1808 		pos = pos->xl_next;
1809 	}
1810 
1811 	if (i == XL_RX_LIST_CNT)
1812 		return (0);
1813 
1814 	sc->xl_cdata.xl_rx_head = pos;
1815 
1816 	return (EAGAIN);
1817 }
1818 
1819 /*
1820  * A frame has been uploaded: pass the resulting mbuf chain up to
1821  * the higher level protocols.
1822  */
1823 static int
1824 xl_rxeof(struct xl_softc *sc)
1825 {
1826 	struct mbuf		*m;
1827 	struct ifnet		*ifp = sc->xl_ifp;
1828 	struct xl_chain_onefrag	*cur_rx;
1829 	int			total_len;
1830 	int			rx_npkts = 0;
1831 	u_int32_t		rxstat;
1832 
1833 	XL_LOCK_ASSERT(sc);
1834 again:
1835 	bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap,
1836 	    BUS_DMASYNC_POSTREAD);
1837 	while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) {
1838 #ifdef DEVICE_POLLING
1839 		if (ifp->if_capenable & IFCAP_POLLING) {
1840 			if (sc->rxcycles <= 0)
1841 				break;
1842 			sc->rxcycles--;
1843 		}
1844 #endif
1845 		cur_rx = sc->xl_cdata.xl_rx_head;
1846 		sc->xl_cdata.xl_rx_head = cur_rx->xl_next;
1847 		total_len = rxstat & XL_RXSTAT_LENMASK;
1848 		rx_npkts++;
1849 
1850 		/*
1851 		 * Since we have told the chip to allow large frames,
1852 		 * we need to trap giant frame errors in software. We allow
1853 		 * a little more than the normal frame size to account for
1854 		 * frames with VLAN tags.
1855 		 */
1856 		if (total_len > XL_MAX_FRAMELEN)
1857 			rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE);
1858 
1859 		/*
1860 		 * If an error occurs, update stats, clear the
1861 		 * status word and leave the mbuf cluster in place:
1862 		 * it should simply get re-used next time this descriptor
1863 		 * comes up in the ring.
1864 		 */
1865 		if (rxstat & XL_RXSTAT_UP_ERROR) {
1866 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1867 			cur_rx->xl_ptr->xl_status = 0;
1868 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1869 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1870 			continue;
1871 		}
1872 
1873 		/*
1874 		 * If the error bit was not set, the upload complete
1875 		 * bit should be set which means we have a valid packet.
1876 		 * If not, something truly strange has happened.
1877 		 */
1878 		if (!(rxstat & XL_RXSTAT_UP_CMPLT)) {
1879 			device_printf(sc->xl_dev,
1880 			    "bad receive status -- packet dropped\n");
1881 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1882 			cur_rx->xl_ptr->xl_status = 0;
1883 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1884 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1885 			continue;
1886 		}
1887 
1888 		/* No errors; receive the packet. */
1889 		bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map,
1890 		    BUS_DMASYNC_POSTREAD);
1891 		m = cur_rx->xl_mbuf;
1892 
1893 		/*
1894 		 * Try to conjure up a new mbuf cluster. If that
1895 		 * fails, it means we have an out of memory condition and
1896 		 * should leave the buffer in place and continue. This will
1897 		 * result in a lost packet, but there's little else we
1898 		 * can do in this situation.
1899 		 */
1900 		if (xl_newbuf(sc, cur_rx)) {
1901 			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1902 			cur_rx->xl_ptr->xl_status = 0;
1903 			bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1904 			    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1905 			continue;
1906 		}
1907 		bus_dmamap_sync(sc->xl_ldata.xl_rx_tag,
1908 		    sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE);
1909 
1910 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1911 		m->m_pkthdr.rcvif = ifp;
1912 		m->m_pkthdr.len = m->m_len = total_len;
1913 
1914 		if (ifp->if_capenable & IFCAP_RXCSUM) {
1915 			/* Do IP checksum checking. */
1916 			if (rxstat & XL_RXSTAT_IPCKOK)
1917 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1918 			if (!(rxstat & XL_RXSTAT_IPCKERR))
1919 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1920 			if ((rxstat & XL_RXSTAT_TCPCOK &&
1921 			     !(rxstat & XL_RXSTAT_TCPCKERR)) ||
1922 			    (rxstat & XL_RXSTAT_UDPCKOK &&
1923 			     !(rxstat & XL_RXSTAT_UDPCKERR))) {
1924 				m->m_pkthdr.csum_flags |=
1925 					CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1926 				m->m_pkthdr.csum_data = 0xffff;
1927 			}
1928 		}
1929 
1930 		XL_UNLOCK(sc);
1931 		(*ifp->if_input)(ifp, m);
1932 		XL_LOCK(sc);
1933 
1934 		/*
1935 		 * If we are running from the taskqueue, the interface
1936 		 * might have been stopped while we were passing the last
1937 		 * packet up the network stack.
1938 		 */
1939 		if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1940 			return (rx_npkts);
1941 	}
1942 
1943 	/*
1944 	 * Handle the 'end of channel' condition. When the upload
1945 	 * engine hits the end of the RX ring, it will stall. This
1946 	 * is our cue to flush the RX ring, reload the uplist pointer
1947 	 * register and unstall the engine.
1948 	 * XXX This is actually a little goofy. With the ThunderLAN
1949 	 * chip, you get an interrupt when the receiver hits the end
1950 	 * of the receive ring, which tells you exactly when you
1951 	 * you need to reload the ring pointer. Here we have to
1952 	 * fake it. I'm mad at myself for not being clever enough
1953 	 * to avoid the use of a goto here.
1954 	 */
1955 	if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 ||
1956 		CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) {
1957 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
1958 		xl_wait(sc);
1959 		CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
1960 		sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0];
1961 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
1962 		goto again;
1963 	}
1964 	return (rx_npkts);
1965 }
1966 
1967 /*
1968  * Taskqueue wrapper for xl_rxeof().
1969  */
1970 static void
1971 xl_rxeof_task(void *arg, int pending)
1972 {
1973 	struct xl_softc *sc = (struct xl_softc *)arg;
1974 
1975 	XL_LOCK(sc);
1976 	if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING)
1977 		xl_rxeof(sc);
1978 	XL_UNLOCK(sc);
1979 }
1980 
1981 /*
1982  * A frame was downloaded to the chip. It's safe for us to clean up
1983  * the list buffers.
1984  */
1985 static void
1986 xl_txeof(struct xl_softc *sc)
1987 {
1988 	struct xl_chain		*cur_tx;
1989 	struct ifnet		*ifp = sc->xl_ifp;
1990 
1991 	XL_LOCK_ASSERT(sc);
1992 
1993 	/*
1994 	 * Go through our tx list and free mbufs for those
1995 	 * frames that have been uploaded. Note: the 3c905B
1996 	 * sets a special bit in the status word to let us
1997 	 * know that a frame has been downloaded, but the
1998 	 * original 3c900/3c905 adapters don't do that.
1999 	 * Consequently, we have to use a different test if
2000 	 * xl_type != XL_TYPE_905B.
2001 	 */
2002 	while (sc->xl_cdata.xl_tx_head != NULL) {
2003 		cur_tx = sc->xl_cdata.xl_tx_head;
2004 
2005 		if (CSR_READ_4(sc, XL_DOWNLIST_PTR))
2006 			break;
2007 
2008 		sc->xl_cdata.xl_tx_head = cur_tx->xl_next;
2009 		bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2010 		    BUS_DMASYNC_POSTWRITE);
2011 		bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2012 		m_freem(cur_tx->xl_mbuf);
2013 		cur_tx->xl_mbuf = NULL;
2014 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2015 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2016 
2017 		cur_tx->xl_next = sc->xl_cdata.xl_tx_free;
2018 		sc->xl_cdata.xl_tx_free = cur_tx;
2019 	}
2020 
2021 	if (sc->xl_cdata.xl_tx_head == NULL) {
2022 		sc->xl_wdog_timer = 0;
2023 		sc->xl_cdata.xl_tx_tail = NULL;
2024 	} else {
2025 		if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED ||
2026 			!CSR_READ_4(sc, XL_DOWNLIST_PTR)) {
2027 			CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2028 				sc->xl_cdata.xl_tx_head->xl_phys);
2029 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2030 		}
2031 	}
2032 }
2033 
2034 static void
2035 xl_txeof_90xB(struct xl_softc *sc)
2036 {
2037 	struct xl_chain		*cur_tx = NULL;
2038 	struct ifnet		*ifp = sc->xl_ifp;
2039 	int			idx;
2040 
2041 	XL_LOCK_ASSERT(sc);
2042 
2043 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2044 	    BUS_DMASYNC_POSTREAD);
2045 	idx = sc->xl_cdata.xl_tx_cons;
2046 	while (idx != sc->xl_cdata.xl_tx_prod) {
2047 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2048 
2049 		if (!(le32toh(cur_tx->xl_ptr->xl_status) &
2050 		      XL_TXSTAT_DL_COMPLETE))
2051 			break;
2052 
2053 		if (cur_tx->xl_mbuf != NULL) {
2054 			bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map,
2055 			    BUS_DMASYNC_POSTWRITE);
2056 			bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map);
2057 			m_freem(cur_tx->xl_mbuf);
2058 			cur_tx->xl_mbuf = NULL;
2059 		}
2060 
2061 		if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
2062 
2063 		sc->xl_cdata.xl_tx_cnt--;
2064 		XL_INC(idx, XL_TX_LIST_CNT);
2065 	}
2066 
2067 	if (sc->xl_cdata.xl_tx_cnt == 0)
2068 		sc->xl_wdog_timer = 0;
2069 	sc->xl_cdata.xl_tx_cons = idx;
2070 
2071 	if (cur_tx != NULL)
2072 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2073 }
2074 
2075 /*
2076  * TX 'end of channel' interrupt handler. Actually, we should
2077  * only get a 'TX complete' interrupt if there's a transmit error,
2078  * so this is really TX error handler.
2079  */
2080 static void
2081 xl_txeoc(struct xl_softc *sc)
2082 {
2083 	u_int8_t		txstat;
2084 
2085 	XL_LOCK_ASSERT(sc);
2086 
2087 	while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) {
2088 		if (txstat & XL_TXSTATUS_UNDERRUN ||
2089 			txstat & XL_TXSTATUS_JABBER ||
2090 			txstat & XL_TXSTATUS_RECLAIM) {
2091 			device_printf(sc->xl_dev,
2092 			    "transmission error: 0x%02x\n", txstat);
2093 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2094 			xl_wait(sc);
2095 			if (sc->xl_type == XL_TYPE_905B) {
2096 				if (sc->xl_cdata.xl_tx_cnt) {
2097 					int			i;
2098 					struct xl_chain		*c;
2099 
2100 					i = sc->xl_cdata.xl_tx_cons;
2101 					c = &sc->xl_cdata.xl_tx_chain[i];
2102 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2103 					    c->xl_phys);
2104 					CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2105 					sc->xl_wdog_timer = 5;
2106 				}
2107 			} else {
2108 				if (sc->xl_cdata.xl_tx_head != NULL) {
2109 					CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2110 					    sc->xl_cdata.xl_tx_head->xl_phys);
2111 					sc->xl_wdog_timer = 5;
2112 				}
2113 			}
2114 			/*
2115 			 * Remember to set this for the
2116 			 * first generation 3c90X chips.
2117 			 */
2118 			CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2119 			if (txstat & XL_TXSTATUS_UNDERRUN &&
2120 			    sc->xl_tx_thresh < XL_PACKET_SIZE) {
2121 				sc->xl_tx_thresh += XL_MIN_FRAMELEN;
2122 				device_printf(sc->xl_dev,
2123 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh);
2124 			}
2125 			CSR_WRITE_2(sc, XL_COMMAND,
2126 			    XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2127 			if (sc->xl_type == XL_TYPE_905B) {
2128 				CSR_WRITE_2(sc, XL_COMMAND,
2129 				XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2130 			}
2131 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2132 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2133 		} else {
2134 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2135 			CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2136 		}
2137 		/*
2138 		 * Write an arbitrary byte to the TX_STATUS register
2139 		 * to clear this interrupt/error and advance to the next.
2140 		 */
2141 		CSR_WRITE_1(sc, XL_TX_STATUS, 0x01);
2142 	}
2143 }
2144 
2145 static void
2146 xl_intr(void *arg)
2147 {
2148 	struct xl_softc		*sc = arg;
2149 	struct ifnet		*ifp = sc->xl_ifp;
2150 	u_int16_t		status;
2151 
2152 	XL_LOCK(sc);
2153 
2154 #ifdef DEVICE_POLLING
2155 	if (ifp->if_capenable & IFCAP_POLLING) {
2156 		XL_UNLOCK(sc);
2157 		return;
2158 	}
2159 #endif
2160 
2161 	for (;;) {
2162 		status = CSR_READ_2(sc, XL_STATUS);
2163 		if ((status & XL_INTRS) == 0 || status == 0xFFFF)
2164 			break;
2165 		CSR_WRITE_2(sc, XL_COMMAND,
2166 		    XL_CMD_INTR_ACK|(status & XL_INTRS));
2167 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2168 			break;
2169 
2170 		if (status & XL_STAT_UP_COMPLETE) {
2171 			if (xl_rxeof(sc) == 0) {
2172 				while (xl_rx_resync(sc))
2173 					xl_rxeof(sc);
2174 			}
2175 		}
2176 
2177 		if (status & XL_STAT_DOWN_COMPLETE) {
2178 			if (sc->xl_type == XL_TYPE_905B)
2179 				xl_txeof_90xB(sc);
2180 			else
2181 				xl_txeof(sc);
2182 		}
2183 
2184 		if (status & XL_STAT_TX_COMPLETE) {
2185 			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2186 			xl_txeoc(sc);
2187 		}
2188 
2189 		if (status & XL_STAT_ADFAIL) {
2190 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2191 			xl_init_locked(sc);
2192 			break;
2193 		}
2194 
2195 		if (status & XL_STAT_STATSOFLOW)
2196 			xl_stats_update(sc);
2197 	}
2198 
2199 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2200 	    ifp->if_drv_flags & IFF_DRV_RUNNING) {
2201 		if (sc->xl_type == XL_TYPE_905B)
2202 			xl_start_90xB_locked(ifp);
2203 		else
2204 			xl_start_locked(ifp);
2205 	}
2206 
2207 	XL_UNLOCK(sc);
2208 }
2209 
2210 #ifdef DEVICE_POLLING
2211 static int
2212 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2213 {
2214 	struct xl_softc *sc = ifp->if_softc;
2215 	int rx_npkts = 0;
2216 
2217 	XL_LOCK(sc);
2218 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2219 		rx_npkts = xl_poll_locked(ifp, cmd, count);
2220 	XL_UNLOCK(sc);
2221 	return (rx_npkts);
2222 }
2223 
2224 static int
2225 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
2226 {
2227 	struct xl_softc *sc = ifp->if_softc;
2228 	int rx_npkts;
2229 
2230 	XL_LOCK_ASSERT(sc);
2231 
2232 	sc->rxcycles = count;
2233 	rx_npkts = xl_rxeof(sc);
2234 	if (sc->xl_type == XL_TYPE_905B)
2235 		xl_txeof_90xB(sc);
2236 	else
2237 		xl_txeof(sc);
2238 
2239 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
2240 		if (sc->xl_type == XL_TYPE_905B)
2241 			xl_start_90xB_locked(ifp);
2242 		else
2243 			xl_start_locked(ifp);
2244 	}
2245 
2246 	if (cmd == POLL_AND_CHECK_STATUS) {
2247 		u_int16_t status;
2248 
2249 		status = CSR_READ_2(sc, XL_STATUS);
2250 		if (status & XL_INTRS && status != 0xFFFF) {
2251 			CSR_WRITE_2(sc, XL_COMMAND,
2252 			    XL_CMD_INTR_ACK|(status & XL_INTRS));
2253 
2254 			if (status & XL_STAT_TX_COMPLETE) {
2255 				if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2256 				xl_txeoc(sc);
2257 			}
2258 
2259 			if (status & XL_STAT_ADFAIL) {
2260 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2261 				xl_init_locked(sc);
2262 			}
2263 
2264 			if (status & XL_STAT_STATSOFLOW)
2265 				xl_stats_update(sc);
2266 		}
2267 	}
2268 	return (rx_npkts);
2269 }
2270 #endif /* DEVICE_POLLING */
2271 
2272 static void
2273 xl_tick(void *xsc)
2274 {
2275 	struct xl_softc *sc = xsc;
2276 	struct mii_data *mii;
2277 
2278 	XL_LOCK_ASSERT(sc);
2279 
2280 	if (sc->xl_miibus != NULL) {
2281 		mii = device_get_softc(sc->xl_miibus);
2282 		mii_tick(mii);
2283 	}
2284 
2285 	xl_stats_update(sc);
2286 	if (xl_watchdog(sc) == EJUSTRETURN)
2287 		return;
2288 
2289 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2290 }
2291 
2292 static void
2293 xl_stats_update(struct xl_softc *sc)
2294 {
2295 	struct ifnet		*ifp = sc->xl_ifp;
2296 	struct xl_stats		xl_stats;
2297 	u_int8_t		*p;
2298 	int			i;
2299 
2300 	XL_LOCK_ASSERT(sc);
2301 
2302 	bzero((char *)&xl_stats, sizeof(struct xl_stats));
2303 
2304 	p = (u_int8_t *)&xl_stats;
2305 
2306 	/* Read all the stats registers. */
2307 	XL_SEL_WIN(6);
2308 
2309 	for (i = 0; i < 16; i++)
2310 		*p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i);
2311 
2312 	if_inc_counter(ifp, IFCOUNTER_IERRORS, xl_stats.xl_rx_overrun);
2313 
2314 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
2315 	    xl_stats.xl_tx_multi_collision +
2316 	    xl_stats.xl_tx_single_collision +
2317 	    xl_stats.xl_tx_late_collision);
2318 
2319 	/*
2320 	 * Boomerang and cyclone chips have an extra stats counter
2321 	 * in window 4 (BadSSD). We have to read this too in order
2322 	 * to clear out all the stats registers and avoid a statsoflow
2323 	 * interrupt.
2324 	 */
2325 	XL_SEL_WIN(4);
2326 	CSR_READ_1(sc, XL_W4_BADSSD);
2327 	XL_SEL_WIN(7);
2328 }
2329 
2330 /*
2331  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
2332  * pointers to the fragment pointers.
2333  */
2334 static int
2335 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head)
2336 {
2337 	struct mbuf		*m_new;
2338 	struct ifnet		*ifp = sc->xl_ifp;
2339 	int			error, i, nseg, total_len;
2340 	u_int32_t		status;
2341 
2342 	XL_LOCK_ASSERT(sc);
2343 
2344 	error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head,
2345 	    sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2346 
2347 	if (error && error != EFBIG) {
2348 		if_printf(ifp, "can't map mbuf (error %d)\n", error);
2349 		return (error);
2350 	}
2351 
2352 	/*
2353 	 * Handle special case: we used up all 63 fragments,
2354 	 * but we have more mbufs left in the chain. Copy the
2355 	 * data into an mbuf cluster. Note that we don't
2356 	 * bother clearing the values in the other fragment
2357 	 * pointers/counters; it wouldn't gain us anything,
2358 	 * and would waste cycles.
2359 	 */
2360 	if (error) {
2361 		m_new = m_collapse(*m_head, M_NOWAIT, XL_MAXFRAGS);
2362 		if (m_new == NULL) {
2363 			m_freem(*m_head);
2364 			*m_head = NULL;
2365 			return (ENOBUFS);
2366 		}
2367 		*m_head = m_new;
2368 
2369 		error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map,
2370 		    *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT);
2371 		if (error) {
2372 			m_freem(*m_head);
2373 			*m_head = NULL;
2374 			if_printf(ifp, "can't map mbuf (error %d)\n", error);
2375 			return (error);
2376 		}
2377 	}
2378 
2379 	KASSERT(nseg <= XL_MAXFRAGS,
2380 	    ("%s: too many DMA segments (%d)", __func__, nseg));
2381 	if (nseg == 0) {
2382 		m_freem(*m_head);
2383 		*m_head = NULL;
2384 		return (EIO);
2385 	}
2386 	bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE);
2387 
2388 	total_len = 0;
2389 	for (i = 0; i < nseg; i++) {
2390 		KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES,
2391 		    ("segment size too large"));
2392 		c->xl_ptr->xl_frag[i].xl_addr =
2393 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr);
2394 		c->xl_ptr->xl_frag[i].xl_len =
2395 		    htole32(sc->xl_cdata.xl_tx_segs[i].ds_len);
2396 		total_len += sc->xl_cdata.xl_tx_segs[i].ds_len;
2397 	}
2398 	c->xl_ptr->xl_frag[nseg - 1].xl_len |= htole32(XL_LAST_FRAG);
2399 
2400 	if (sc->xl_type == XL_TYPE_905B) {
2401 		status = XL_TXSTAT_RND_DEFEAT;
2402 
2403 #ifndef XL905B_TXCSUM_BROKEN
2404 		if ((*m_head)->m_pkthdr.csum_flags) {
2405 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP)
2406 				status |= XL_TXSTAT_IPCKSUM;
2407 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP)
2408 				status |= XL_TXSTAT_TCPCKSUM;
2409 			if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP)
2410 				status |= XL_TXSTAT_UDPCKSUM;
2411 		}
2412 #endif
2413 	} else
2414 		status = total_len;
2415 	c->xl_ptr->xl_status = htole32(status);
2416 	c->xl_ptr->xl_next = 0;
2417 
2418 	c->xl_mbuf = *m_head;
2419 	return (0);
2420 }
2421 
2422 /*
2423  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2424  * to the mbuf data regions directly in the transmit lists. We also save a
2425  * copy of the pointers since the transmit list fragment pointers are
2426  * physical addresses.
2427  */
2428 
2429 static void
2430 xl_start(struct ifnet *ifp)
2431 {
2432 	struct xl_softc		*sc = ifp->if_softc;
2433 
2434 	XL_LOCK(sc);
2435 
2436 	if (sc->xl_type == XL_TYPE_905B)
2437 		xl_start_90xB_locked(ifp);
2438 	else
2439 		xl_start_locked(ifp);
2440 
2441 	XL_UNLOCK(sc);
2442 }
2443 
2444 static void
2445 xl_start_locked(struct ifnet *ifp)
2446 {
2447 	struct xl_softc		*sc = ifp->if_softc;
2448 	struct mbuf		*m_head;
2449 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2450 	struct xl_chain		*prev_tx;
2451 	int			error;
2452 
2453 	XL_LOCK_ASSERT(sc);
2454 
2455 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2456 	    IFF_DRV_RUNNING)
2457 		return;
2458 	/*
2459 	 * Check for an available queue slot. If there are none,
2460 	 * punt.
2461 	 */
2462 	if (sc->xl_cdata.xl_tx_free == NULL) {
2463 		xl_txeoc(sc);
2464 		xl_txeof(sc);
2465 		if (sc->xl_cdata.xl_tx_free == NULL) {
2466 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2467 			return;
2468 		}
2469 	}
2470 
2471 	start_tx = sc->xl_cdata.xl_tx_free;
2472 
2473 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2474 	    sc->xl_cdata.xl_tx_free != NULL;) {
2475 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2476 		if (m_head == NULL)
2477 			break;
2478 
2479 		/* Pick a descriptor off the free list. */
2480 		prev_tx = cur_tx;
2481 		cur_tx = sc->xl_cdata.xl_tx_free;
2482 
2483 		/* Pack the data into the descriptor. */
2484 		error = xl_encap(sc, cur_tx, &m_head);
2485 		if (error) {
2486 			cur_tx = prev_tx;
2487 			if (m_head == NULL)
2488 				break;
2489 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2490 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2491 			break;
2492 		}
2493 
2494 		sc->xl_cdata.xl_tx_free = cur_tx->xl_next;
2495 		cur_tx->xl_next = NULL;
2496 
2497 		/* Chain it together. */
2498 		if (prev != NULL) {
2499 			prev->xl_next = cur_tx;
2500 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2501 		}
2502 		prev = cur_tx;
2503 
2504 		/*
2505 		 * If there's a BPF listener, bounce a copy of this frame
2506 		 * to him.
2507 		 */
2508 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2509 	}
2510 
2511 	/*
2512 	 * If there are no packets queued, bail.
2513 	 */
2514 	if (cur_tx == NULL)
2515 		return;
2516 
2517 	/*
2518 	 * Place the request for the upload interrupt
2519 	 * in the last descriptor in the chain. This way, if
2520 	 * we're chaining several packets at once, we'll only
2521 	 * get an interrupt once for the whole chain rather than
2522 	 * once for each packet.
2523 	 */
2524 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2525 
2526 	/*
2527 	 * Queue the packets. If the TX channel is clear, update
2528 	 * the downlist pointer register.
2529 	 */
2530 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2531 	xl_wait(sc);
2532 
2533 	if (sc->xl_cdata.xl_tx_head != NULL) {
2534 		sc->xl_cdata.xl_tx_tail->xl_next = start_tx;
2535 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next =
2536 		    htole32(start_tx->xl_phys);
2537 		sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status &=
2538 		    htole32(~XL_TXSTAT_DL_INTR);
2539 		sc->xl_cdata.xl_tx_tail = cur_tx;
2540 	} else {
2541 		sc->xl_cdata.xl_tx_head = start_tx;
2542 		sc->xl_cdata.xl_tx_tail = cur_tx;
2543 	}
2544 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2545 	    BUS_DMASYNC_PREWRITE);
2546 	if (!CSR_READ_4(sc, XL_DOWNLIST_PTR))
2547 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys);
2548 
2549 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2550 
2551 	XL_SEL_WIN(7);
2552 
2553 	/*
2554 	 * Set a timeout in case the chip goes out to lunch.
2555 	 */
2556 	sc->xl_wdog_timer = 5;
2557 
2558 	/*
2559 	 * XXX Under certain conditions, usually on slower machines
2560 	 * where interrupts may be dropped, it's possible for the
2561 	 * adapter to chew up all the buffers in the receive ring
2562 	 * and stall, without us being able to do anything about it.
2563 	 * To guard against this, we need to make a pass over the
2564 	 * RX queue to make sure there aren't any packets pending.
2565 	 * Doing it here means we can flush the receive ring at the
2566 	 * same time the chip is DMAing the transmit descriptors we
2567 	 * just gave it.
2568 	 *
2569 	 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm)
2570 	 * nature of their chips in all their marketing literature;
2571 	 * we may as well take advantage of it. :)
2572 	 */
2573 	taskqueue_enqueue(taskqueue_swi, &sc->xl_task);
2574 }
2575 
2576 static void
2577 xl_start_90xB_locked(struct ifnet *ifp)
2578 {
2579 	struct xl_softc		*sc = ifp->if_softc;
2580 	struct mbuf		*m_head;
2581 	struct xl_chain		*prev = NULL, *cur_tx = NULL, *start_tx;
2582 	struct xl_chain		*prev_tx;
2583 	int			error, idx;
2584 
2585 	XL_LOCK_ASSERT(sc);
2586 
2587 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2588 	    IFF_DRV_RUNNING)
2589 		return;
2590 
2591 	idx = sc->xl_cdata.xl_tx_prod;
2592 	start_tx = &sc->xl_cdata.xl_tx_chain[idx];
2593 
2594 	for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2595 	    sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) {
2596 		if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) {
2597 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2598 			break;
2599 		}
2600 
2601 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2602 		if (m_head == NULL)
2603 			break;
2604 
2605 		prev_tx = cur_tx;
2606 		cur_tx = &sc->xl_cdata.xl_tx_chain[idx];
2607 
2608 		/* Pack the data into the descriptor. */
2609 		error = xl_encap(sc, cur_tx, &m_head);
2610 		if (error) {
2611 			cur_tx = prev_tx;
2612 			if (m_head == NULL)
2613 				break;
2614 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2615 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2616 			break;
2617 		}
2618 
2619 		/* Chain it together. */
2620 		if (prev != NULL)
2621 			prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys);
2622 		prev = cur_tx;
2623 
2624 		/*
2625 		 * If there's a BPF listener, bounce a copy of this frame
2626 		 * to him.
2627 		 */
2628 		BPF_MTAP(ifp, cur_tx->xl_mbuf);
2629 
2630 		XL_INC(idx, XL_TX_LIST_CNT);
2631 		sc->xl_cdata.xl_tx_cnt++;
2632 	}
2633 
2634 	/*
2635 	 * If there are no packets queued, bail.
2636 	 */
2637 	if (cur_tx == NULL)
2638 		return;
2639 
2640 	/*
2641 	 * Place the request for the upload interrupt
2642 	 * in the last descriptor in the chain. This way, if
2643 	 * we're chaining several packets at once, we'll only
2644 	 * get an interrupt once for the whole chain rather than
2645 	 * once for each packet.
2646 	 */
2647 	cur_tx->xl_ptr->xl_status |= htole32(XL_TXSTAT_DL_INTR);
2648 
2649 	/* Start transmission */
2650 	sc->xl_cdata.xl_tx_prod = idx;
2651 	start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys);
2652 	bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap,
2653 	    BUS_DMASYNC_PREWRITE);
2654 
2655 	/*
2656 	 * Set a timeout in case the chip goes out to lunch.
2657 	 */
2658 	sc->xl_wdog_timer = 5;
2659 }
2660 
2661 static void
2662 xl_init(void *xsc)
2663 {
2664 	struct xl_softc		*sc = xsc;
2665 
2666 	XL_LOCK(sc);
2667 	xl_init_locked(sc);
2668 	XL_UNLOCK(sc);
2669 }
2670 
2671 static void
2672 xl_init_locked(struct xl_softc *sc)
2673 {
2674 	struct ifnet		*ifp = sc->xl_ifp;
2675 	int			error, i;
2676 	struct mii_data		*mii = NULL;
2677 
2678 	XL_LOCK_ASSERT(sc);
2679 
2680 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2681 		return;
2682 	/*
2683 	 * Cancel pending I/O and free all RX/TX buffers.
2684 	 */
2685 	xl_stop(sc);
2686 
2687 	/* Reset the chip to a known state. */
2688 	xl_reset(sc);
2689 
2690 	if (sc->xl_miibus == NULL) {
2691 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2692 		xl_wait(sc);
2693 	}
2694 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2695 	xl_wait(sc);
2696 	DELAY(10000);
2697 
2698 	if (sc->xl_miibus != NULL)
2699 		mii = device_get_softc(sc->xl_miibus);
2700 
2701 	/*
2702 	 * Clear WOL status and disable all WOL feature as WOL
2703 	 * would interfere Rx operation under normal environments.
2704 	 */
2705 	if ((sc->xl_flags & XL_FLAG_WOL) != 0) {
2706 		XL_SEL_WIN(7);
2707 		CSR_READ_2(sc, XL_W7_BM_PME);
2708 		CSR_WRITE_2(sc, XL_W7_BM_PME, 0);
2709 	}
2710 	/* Init our MAC address */
2711 	XL_SEL_WIN(2);
2712 	for (i = 0; i < ETHER_ADDR_LEN; i++) {
2713 		CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i,
2714 				IF_LLADDR(sc->xl_ifp)[i]);
2715 	}
2716 
2717 	/* Clear the station mask. */
2718 	for (i = 0; i < 3; i++)
2719 		CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0);
2720 #ifdef notdef
2721 	/* Reset TX and RX. */
2722 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
2723 	xl_wait(sc);
2724 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
2725 	xl_wait(sc);
2726 #endif
2727 	/* Init circular RX list. */
2728 	error = xl_list_rx_init(sc);
2729 	if (error) {
2730 		device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n",
2731 		    error);
2732 		xl_stop(sc);
2733 		return;
2734 	}
2735 
2736 	/* Init TX descriptors. */
2737 	if (sc->xl_type == XL_TYPE_905B)
2738 		error = xl_list_tx_init_90xB(sc);
2739 	else
2740 		error = xl_list_tx_init(sc);
2741 	if (error) {
2742 		device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n",
2743 		    error);
2744 		xl_stop(sc);
2745 		return;
2746 	}
2747 
2748 	/*
2749 	 * Set the TX freethresh value.
2750 	 * Note that this has no effect on 3c905B "cyclone"
2751 	 * cards but is required for 3c900/3c905 "boomerang"
2752 	 * cards in order to enable the download engine.
2753 	 */
2754 	CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8);
2755 
2756 	/* Set the TX start threshold for best performance. */
2757 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh);
2758 
2759 	/*
2760 	 * If this is a 3c905B, also set the tx reclaim threshold.
2761 	 * This helps cut down on the number of tx reclaim errors
2762 	 * that could happen on a busy network. The chip multiplies
2763 	 * the register value by 16 to obtain the actual threshold
2764 	 * in bytes, so we divide by 16 when setting the value here.
2765 	 * The existing threshold value can be examined by reading
2766 	 * the register at offset 9 in window 5.
2767 	 */
2768 	if (sc->xl_type == XL_TYPE_905B) {
2769 		CSR_WRITE_2(sc, XL_COMMAND,
2770 		    XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4));
2771 	}
2772 
2773 	/* Set RX filter bits. */
2774 	xl_rxfilter(sc);
2775 
2776 	/*
2777 	 * Load the address of the RX list. We have to
2778 	 * stall the upload engine before we can manipulate
2779 	 * the uplist pointer register, then unstall it when
2780 	 * we're finished. We also have to wait for the
2781 	 * stall command to complete before proceeding.
2782 	 * Note that we have to do this after any RX resets
2783 	 * have completed since the uplist register is cleared
2784 	 * by a reset.
2785 	 */
2786 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL);
2787 	xl_wait(sc);
2788 	CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr);
2789 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL);
2790 	xl_wait(sc);
2791 
2792 	if (sc->xl_type == XL_TYPE_905B) {
2793 		/* Set polling interval */
2794 		CSR_WRITE_1(sc, XL_DOWN_POLL, 64);
2795 		/* Load the address of the TX list */
2796 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL);
2797 		xl_wait(sc);
2798 		CSR_WRITE_4(sc, XL_DOWNLIST_PTR,
2799 		    sc->xl_cdata.xl_tx_chain[0].xl_phys);
2800 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL);
2801 		xl_wait(sc);
2802 	}
2803 
2804 	/*
2805 	 * If the coax transceiver is on, make sure to enable
2806 	 * the DC-DC converter.
2807 	 */
2808 	XL_SEL_WIN(3);
2809 	if (sc->xl_xcvr == XL_XCVR_COAX)
2810 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START);
2811 	else
2812 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
2813 
2814 	/*
2815 	 * increase packet size to allow reception of 802.1q or ISL packets.
2816 	 * For the 3c90x chip, set the 'allow large packets' bit in the MAC
2817 	 * control register. For 3c90xB/C chips, use the RX packet size
2818 	 * register.
2819 	 */
2820 
2821 	if (sc->xl_type == XL_TYPE_905B)
2822 		CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
2823 	else {
2824 		u_int8_t macctl;
2825 		macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL);
2826 		macctl |= XL_MACCTRL_ALLOW_LARGE_PACK;
2827 		CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl);
2828 	}
2829 
2830 	/* Clear out the stats counters. */
2831 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
2832 	xl_stats_update(sc);
2833 	XL_SEL_WIN(4);
2834 	CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE);
2835 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE);
2836 
2837 	/*
2838 	 * Enable interrupts.
2839 	 */
2840 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF);
2841 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS);
2842 #ifdef DEVICE_POLLING
2843 	/* Disable interrupts if we are polling. */
2844 	if (ifp->if_capenable & IFCAP_POLLING)
2845 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
2846 	else
2847 #endif
2848 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS);
2849 	if (sc->xl_flags & XL_FLAG_FUNCREG)
2850 	    bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
2851 
2852 	/* Set the RX early threshold */
2853 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2));
2854 	CSR_WRITE_4(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY);
2855 
2856 	/* Enable receiver and transmitter. */
2857 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE);
2858 	xl_wait(sc);
2859 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
2860 	xl_wait(sc);
2861 
2862 	/* XXX Downcall to miibus. */
2863 	if (mii != NULL)
2864 		mii_mediachg(mii);
2865 
2866 	/* Select window 7 for normal operations. */
2867 	XL_SEL_WIN(7);
2868 
2869 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2870 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2871 
2872 	sc->xl_wdog_timer = 0;
2873 	callout_reset(&sc->xl_tick_callout, hz, xl_tick, sc);
2874 }
2875 
2876 /*
2877  * Set media options.
2878  */
2879 static int
2880 xl_ifmedia_upd(struct ifnet *ifp)
2881 {
2882 	struct xl_softc		*sc = ifp->if_softc;
2883 	struct ifmedia		*ifm = NULL;
2884 	struct mii_data		*mii = NULL;
2885 
2886 	XL_LOCK(sc);
2887 
2888 	if (sc->xl_miibus != NULL)
2889 		mii = device_get_softc(sc->xl_miibus);
2890 	if (mii == NULL)
2891 		ifm = &sc->ifmedia;
2892 	else
2893 		ifm = &mii->mii_media;
2894 
2895 	switch (IFM_SUBTYPE(ifm->ifm_media)) {
2896 	case IFM_100_FX:
2897 	case IFM_10_FL:
2898 	case IFM_10_2:
2899 	case IFM_10_5:
2900 		xl_setmode(sc, ifm->ifm_media);
2901 		XL_UNLOCK(sc);
2902 		return (0);
2903 	}
2904 
2905 	if (sc->xl_media & XL_MEDIAOPT_MII ||
2906 	    sc->xl_media & XL_MEDIAOPT_BTX ||
2907 	    sc->xl_media & XL_MEDIAOPT_BT4) {
2908 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2909 		xl_init_locked(sc);
2910 	} else {
2911 		xl_setmode(sc, ifm->ifm_media);
2912 	}
2913 
2914 	XL_UNLOCK(sc);
2915 
2916 	return (0);
2917 }
2918 
2919 /*
2920  * Report current media status.
2921  */
2922 static void
2923 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2924 {
2925 	struct xl_softc		*sc = ifp->if_softc;
2926 	u_int32_t		icfg;
2927 	u_int16_t		status = 0;
2928 	struct mii_data		*mii = NULL;
2929 
2930 	XL_LOCK(sc);
2931 
2932 	if (sc->xl_miibus != NULL)
2933 		mii = device_get_softc(sc->xl_miibus);
2934 
2935 	XL_SEL_WIN(4);
2936 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
2937 
2938 	XL_SEL_WIN(3);
2939 	icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK;
2940 	icfg >>= XL_ICFG_CONNECTOR_BITS;
2941 
2942 	ifmr->ifm_active = IFM_ETHER;
2943 	ifmr->ifm_status = IFM_AVALID;
2944 
2945 	if ((status & XL_MEDIASTAT_CARRIER) == 0)
2946 		ifmr->ifm_status |= IFM_ACTIVE;
2947 
2948 	switch (icfg) {
2949 	case XL_XCVR_10BT:
2950 		ifmr->ifm_active = IFM_ETHER|IFM_10_T;
2951 		if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2952 			ifmr->ifm_active |= IFM_FDX;
2953 		else
2954 			ifmr->ifm_active |= IFM_HDX;
2955 		break;
2956 	case XL_XCVR_AUI:
2957 		if (sc->xl_type == XL_TYPE_905B &&
2958 		    sc->xl_media == XL_MEDIAOPT_10FL) {
2959 			ifmr->ifm_active = IFM_ETHER|IFM_10_FL;
2960 			if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX)
2961 				ifmr->ifm_active |= IFM_FDX;
2962 			else
2963 				ifmr->ifm_active |= IFM_HDX;
2964 		} else
2965 			ifmr->ifm_active = IFM_ETHER|IFM_10_5;
2966 		break;
2967 	case XL_XCVR_COAX:
2968 		ifmr->ifm_active = IFM_ETHER|IFM_10_2;
2969 		break;
2970 	/*
2971 	 * XXX MII and BTX/AUTO should be separate cases.
2972 	 */
2973 
2974 	case XL_XCVR_100BTX:
2975 	case XL_XCVR_AUTO:
2976 	case XL_XCVR_MII:
2977 		if (mii != NULL) {
2978 			mii_pollstat(mii);
2979 			ifmr->ifm_active = mii->mii_media_active;
2980 			ifmr->ifm_status = mii->mii_media_status;
2981 		}
2982 		break;
2983 	case XL_XCVR_100BFX:
2984 		ifmr->ifm_active = IFM_ETHER|IFM_100_FX;
2985 		break;
2986 	default:
2987 		if_printf(ifp, "unknown XCVR type: %d\n", icfg);
2988 		break;
2989 	}
2990 
2991 	XL_UNLOCK(sc);
2992 }
2993 
2994 static int
2995 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2996 {
2997 	struct xl_softc		*sc = ifp->if_softc;
2998 	struct ifreq		*ifr = (struct ifreq *) data;
2999 	int			error = 0, mask;
3000 	struct mii_data		*mii = NULL;
3001 
3002 	switch (command) {
3003 	case SIOCSIFFLAGS:
3004 		XL_LOCK(sc);
3005 		if (ifp->if_flags & IFF_UP) {
3006 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
3007 			    (ifp->if_flags ^ sc->xl_if_flags) &
3008 			    (IFF_PROMISC | IFF_ALLMULTI))
3009 				xl_rxfilter(sc);
3010 			else
3011 				xl_init_locked(sc);
3012 		} else {
3013 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3014 				xl_stop(sc);
3015 		}
3016 		sc->xl_if_flags = ifp->if_flags;
3017 		XL_UNLOCK(sc);
3018 		break;
3019 	case SIOCADDMULTI:
3020 	case SIOCDELMULTI:
3021 		/* XXX Downcall from if_addmulti() possibly with locks held. */
3022 		XL_LOCK(sc);
3023 		if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3024 			xl_rxfilter(sc);
3025 		XL_UNLOCK(sc);
3026 		break;
3027 	case SIOCGIFMEDIA:
3028 	case SIOCSIFMEDIA:
3029 		if (sc->xl_miibus != NULL)
3030 			mii = device_get_softc(sc->xl_miibus);
3031 		if (mii == NULL)
3032 			error = ifmedia_ioctl(ifp, ifr,
3033 			    &sc->ifmedia, command);
3034 		else
3035 			error = ifmedia_ioctl(ifp, ifr,
3036 			    &mii->mii_media, command);
3037 		break;
3038 	case SIOCSIFCAP:
3039 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3040 #ifdef DEVICE_POLLING
3041 		if ((mask & IFCAP_POLLING) != 0 &&
3042 		    (ifp->if_capabilities & IFCAP_POLLING) != 0) {
3043 			ifp->if_capenable ^= IFCAP_POLLING;
3044 			if ((ifp->if_capenable & IFCAP_POLLING) != 0) {
3045 				error = ether_poll_register(xl_poll, ifp);
3046 				if (error)
3047 					break;
3048 				XL_LOCK(sc);
3049 				/* Disable interrupts */
3050 				CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3051 				ifp->if_capenable |= IFCAP_POLLING;
3052 				XL_UNLOCK(sc);
3053 			} else {
3054 				error = ether_poll_deregister(ifp);
3055 				/* Enable interrupts. */
3056 				XL_LOCK(sc);
3057 				CSR_WRITE_2(sc, XL_COMMAND,
3058 				    XL_CMD_INTR_ACK | 0xFF);
3059 				CSR_WRITE_2(sc, XL_COMMAND,
3060 				    XL_CMD_INTR_ENB | XL_INTRS);
3061 				if (sc->xl_flags & XL_FLAG_FUNCREG)
3062 					bus_space_write_4(sc->xl_ftag,
3063 					    sc->xl_fhandle, 4, 0x8000);
3064 				XL_UNLOCK(sc);
3065 			}
3066 		}
3067 #endif /* DEVICE_POLLING */
3068 		XL_LOCK(sc);
3069 		if ((mask & IFCAP_TXCSUM) != 0 &&
3070 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
3071 			ifp->if_capenable ^= IFCAP_TXCSUM;
3072 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
3073 				ifp->if_hwassist |= XL905B_CSUM_FEATURES;
3074 			else
3075 				ifp->if_hwassist &= ~XL905B_CSUM_FEATURES;
3076 		}
3077 		if ((mask & IFCAP_RXCSUM) != 0 &&
3078 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
3079 			ifp->if_capenable ^= IFCAP_RXCSUM;
3080 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
3081 		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
3082 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3083 		XL_UNLOCK(sc);
3084 		break;
3085 	default:
3086 		error = ether_ioctl(ifp, command, data);
3087 		break;
3088 	}
3089 
3090 	return (error);
3091 }
3092 
3093 static int
3094 xl_watchdog(struct xl_softc *sc)
3095 {
3096 	struct ifnet		*ifp = sc->xl_ifp;
3097 	u_int16_t		status = 0;
3098 	int			misintr;
3099 
3100 	XL_LOCK_ASSERT(sc);
3101 
3102 	if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0)
3103 		return (0);
3104 
3105 	xl_rxeof(sc);
3106 	xl_txeoc(sc);
3107 	misintr = 0;
3108 	if (sc->xl_type == XL_TYPE_905B) {
3109 		xl_txeof_90xB(sc);
3110 		if (sc->xl_cdata.xl_tx_cnt == 0)
3111 			misintr++;
3112 	} else {
3113 		xl_txeof(sc);
3114 		if (sc->xl_cdata.xl_tx_head == NULL)
3115 			misintr++;
3116 	}
3117 	if (misintr != 0) {
3118 		device_printf(sc->xl_dev,
3119 		    "watchdog timeout (missed Tx interrupts) -- recovering\n");
3120 		return (0);
3121 	}
3122 
3123 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3124 	XL_SEL_WIN(4);
3125 	status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS);
3126 	device_printf(sc->xl_dev, "watchdog timeout\n");
3127 
3128 	if (status & XL_MEDIASTAT_CARRIER)
3129 		device_printf(sc->xl_dev,
3130 		    "no carrier - transceiver cable problem?\n");
3131 
3132 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3133 	xl_init_locked(sc);
3134 
3135 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
3136 		if (sc->xl_type == XL_TYPE_905B)
3137 			xl_start_90xB_locked(ifp);
3138 		else
3139 			xl_start_locked(ifp);
3140 	}
3141 
3142 	return (EJUSTRETURN);
3143 }
3144 
3145 /*
3146  * Stop the adapter and free any mbufs allocated to the
3147  * RX and TX lists.
3148  */
3149 static void
3150 xl_stop(struct xl_softc *sc)
3151 {
3152 	int			i;
3153 	struct ifnet		*ifp = sc->xl_ifp;
3154 
3155 	XL_LOCK_ASSERT(sc);
3156 
3157 	sc->xl_wdog_timer = 0;
3158 
3159 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE);
3160 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
3161 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB);
3162 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD);
3163 	xl_wait(sc);
3164 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE);
3165 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
3166 	DELAY(800);
3167 
3168 #ifdef foo
3169 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET);
3170 	xl_wait(sc);
3171 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET);
3172 	xl_wait(sc);
3173 #endif
3174 
3175 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH);
3176 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0);
3177 	CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0);
3178 	if (sc->xl_flags & XL_FLAG_FUNCREG)
3179 		bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000);
3180 
3181 	/* Stop the stats updater. */
3182 	callout_stop(&sc->xl_tick_callout);
3183 
3184 	/*
3185 	 * Free data in the RX lists.
3186 	 */
3187 	for (i = 0; i < XL_RX_LIST_CNT; i++) {
3188 		if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) {
3189 			bus_dmamap_unload(sc->xl_mtag,
3190 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3191 			bus_dmamap_destroy(sc->xl_mtag,
3192 			    sc->xl_cdata.xl_rx_chain[i].xl_map);
3193 			m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf);
3194 			sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL;
3195 		}
3196 	}
3197 	if (sc->xl_ldata.xl_rx_list != NULL)
3198 		bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ);
3199 	/*
3200 	 * Free the TX list buffers.
3201 	 */
3202 	for (i = 0; i < XL_TX_LIST_CNT; i++) {
3203 		if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) {
3204 			bus_dmamap_unload(sc->xl_mtag,
3205 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3206 			bus_dmamap_destroy(sc->xl_mtag,
3207 			    sc->xl_cdata.xl_tx_chain[i].xl_map);
3208 			m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf);
3209 			sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL;
3210 		}
3211 	}
3212 	if (sc->xl_ldata.xl_tx_list != NULL)
3213 		bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ);
3214 
3215 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3216 }
3217 
3218 /*
3219  * Stop all chip I/O so that the kernel's probe routines don't
3220  * get confused by errant DMAs when rebooting.
3221  */
3222 static int
3223 xl_shutdown(device_t dev)
3224 {
3225 
3226 	return (xl_suspend(dev));
3227 }
3228 
3229 static int
3230 xl_suspend(device_t dev)
3231 {
3232 	struct xl_softc		*sc;
3233 
3234 	sc = device_get_softc(dev);
3235 
3236 	XL_LOCK(sc);
3237 	xl_stop(sc);
3238 	xl_setwol(sc);
3239 	XL_UNLOCK(sc);
3240 
3241 	return (0);
3242 }
3243 
3244 static int
3245 xl_resume(device_t dev)
3246 {
3247 	struct xl_softc		*sc;
3248 	struct ifnet		*ifp;
3249 
3250 	sc = device_get_softc(dev);
3251 	ifp = sc->xl_ifp;
3252 
3253 	XL_LOCK(sc);
3254 
3255 	if (ifp->if_flags & IFF_UP) {
3256 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3257 		xl_init_locked(sc);
3258 	}
3259 
3260 	XL_UNLOCK(sc);
3261 
3262 	return (0);
3263 }
3264 
3265 static void
3266 xl_setwol(struct xl_softc *sc)
3267 {
3268 	struct ifnet		*ifp;
3269 	u_int16_t		cfg, pmstat;
3270 
3271 	if ((sc->xl_flags & XL_FLAG_WOL) == 0)
3272 		return;
3273 
3274 	ifp = sc->xl_ifp;
3275 	XL_SEL_WIN(7);
3276 	/* Clear any pending PME events. */
3277 	CSR_READ_2(sc, XL_W7_BM_PME);
3278 	cfg = 0;
3279 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3280 		cfg |= XL_BM_PME_MAGIC;
3281 	CSR_WRITE_2(sc, XL_W7_BM_PME, cfg);
3282 	/* Enable RX. */
3283 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3284 		CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE);
3285 	/* Request PME. */
3286 	pmstat = pci_read_config(sc->xl_dev,
3287 	    sc->xl_pmcap + PCIR_POWER_STATUS, 2);
3288 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
3289 		pmstat |= PCIM_PSTAT_PMEENABLE;
3290 	else
3291 		pmstat &= ~PCIM_PSTAT_PMEENABLE;
3292 	pci_write_config(sc->xl_dev,
3293 	    sc->xl_pmcap + PCIR_POWER_STATUS, pmstat, 2);
3294 }
3295