1 /*- 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * 3Com 3c90x Etherlink XL PCI NIC driver 38 * 39 * Supports the 3Com "boomerang", "cyclone" and "hurricane" PCI 40 * bus-master chips (3c90x cards and embedded controllers) including 41 * the following: 42 * 43 * 3Com 3c900-TPO 10Mbps/RJ-45 44 * 3Com 3c900-COMBO 10Mbps/RJ-45,AUI,BNC 45 * 3Com 3c905-TX 10/100Mbps/RJ-45 46 * 3Com 3c905-T4 10/100Mbps/RJ-45 47 * 3Com 3c900B-TPO 10Mbps/RJ-45 48 * 3Com 3c900B-COMBO 10Mbps/RJ-45,AUI,BNC 49 * 3Com 3c900B-TPC 10Mbps/RJ-45,BNC 50 * 3Com 3c900B-FL 10Mbps/Fiber-optic 51 * 3Com 3c905B-COMBO 10/100Mbps/RJ-45,AUI,BNC 52 * 3Com 3c905B-TX 10/100Mbps/RJ-45 53 * 3Com 3c905B-FL/FX 10/100Mbps/Fiber-optic 54 * 3Com 3c905C-TX 10/100Mbps/RJ-45 (Tornado ASIC) 55 * 3Com 3c980-TX 10/100Mbps server adapter (Hurricane ASIC) 56 * 3Com 3c980C-TX 10/100Mbps server adapter (Tornado ASIC) 57 * 3Com 3cSOHO100-TX 10/100Mbps/RJ-45 (Hurricane ASIC) 58 * 3Com 3c450-TX 10/100Mbps/RJ-45 (Tornado ASIC) 59 * 3Com 3c555 10/100Mbps/RJ-45 (MiniPCI, Laptop Hurricane) 60 * 3Com 3c556 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 61 * 3Com 3c556B 10/100Mbps/RJ-45 (MiniPCI, Hurricane ASIC) 62 * 3Com 3c575TX 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 63 * 3Com 3c575B 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 64 * 3Com 3c575C 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 65 * 3Com 3cxfem656 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 66 * 3Com 3cxfem656b 10/100Mbps/RJ-45 (Cardbus, Hurricane ASIC) 67 * 3Com 3cxfem656c 10/100Mbps/RJ-45 (Cardbus, Tornado ASIC) 68 * Dell Optiplex GX1 on-board 3c918 10/100Mbps/RJ-45 69 * Dell on-board 3c920 10/100Mbps/RJ-45 70 * Dell Precision on-board 3c905B 10/100Mbps/RJ-45 71 * Dell Latitude laptop docking station embedded 3c905-TX 72 * 73 * Written by Bill Paul <wpaul@ctr.columbia.edu> 74 * Electrical Engineering Department 75 * Columbia University, New York City 76 */ 77 /* 78 * The 3c90x series chips use a bus-master DMA interface for transfering 79 * packets to and from the controller chip. Some of the "vortex" cards 80 * (3c59x) also supported a bus master mode, however for those chips 81 * you could only DMA packets to/from a contiguous memory buffer. For 82 * transmission this would mean copying the contents of the queued mbuf 83 * chain into an mbuf cluster and then DMAing the cluster. This extra 84 * copy would sort of defeat the purpose of the bus master support for 85 * any packet that doesn't fit into a single mbuf. 86 * 87 * By contrast, the 3c90x cards support a fragment-based bus master 88 * mode where mbuf chains can be encapsulated using TX descriptors. 89 * This is similar to other PCI chips such as the Texas Instruments 90 * ThunderLAN and the Intel 82557/82558. 91 * 92 * The "vortex" driver (if_vx.c) happens to work for the "boomerang" 93 * bus master chips because they maintain the old PIO interface for 94 * backwards compatibility, but starting with the 3c905B and the 95 * "cyclone" chips, the compatibility interface has been dropped. 96 * Since using bus master DMA is a big win, we use this driver to 97 * support the PCI "boomerang" chips even though they work with the 98 * "vortex" driver in order to obtain better performance. 99 */ 100 101 #ifdef HAVE_KERNEL_OPTION_HEADERS 102 #include "opt_device_polling.h" 103 #endif 104 105 #include <sys/param.h> 106 #include <sys/systm.h> 107 #include <sys/sockio.h> 108 #include <sys/endian.h> 109 #include <sys/mbuf.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/taskqueue.h> 114 115 #include <net/if.h> 116 #include <net/if_arp.h> 117 #include <net/ethernet.h> 118 #include <net/if_dl.h> 119 #include <net/if_media.h> 120 #include <net/if_types.h> 121 122 #include <net/bpf.h> 123 124 #include <machine/bus.h> 125 #include <machine/resource.h> 126 #include <sys/bus.h> 127 #include <sys/rman.h> 128 129 #include <dev/mii/mii.h> 130 #include <dev/mii/miivar.h> 131 132 #include <dev/pci/pcireg.h> 133 #include <dev/pci/pcivar.h> 134 135 MODULE_DEPEND(xl, pci, 1, 1, 1); 136 MODULE_DEPEND(xl, ether, 1, 1, 1); 137 MODULE_DEPEND(xl, miibus, 1, 1, 1); 138 139 /* "device miibus" required. See GENERIC if you get errors here. */ 140 #include "miibus_if.h" 141 142 #include <dev/xl/if_xlreg.h> 143 144 /* 145 * TX Checksumming is disabled by default for two reasons: 146 * - TX Checksumming will occasionally produce corrupt packets 147 * - TX Checksumming seems to reduce performance 148 * 149 * Only 905B/C cards were reported to have this problem, it is possible 150 * that later chips _may_ be immune. 151 */ 152 #define XL905B_TXCSUM_BROKEN 1 153 154 #ifdef XL905B_TXCSUM_BROKEN 155 #define XL905B_CSUM_FEATURES 0 156 #else 157 #define XL905B_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 158 #endif 159 160 /* 161 * Various supported device vendors/types and their names. 162 */ 163 static const struct xl_type xl_devs[] = { 164 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT, 165 "3Com 3c900-TPO Etherlink XL" }, 166 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10BT_COMBO, 167 "3Com 3c900-COMBO Etherlink XL" }, 168 { TC_VENDORID, TC_DEVICEID_BOOMERANG_10_100BT, 169 "3Com 3c905-TX Fast Etherlink XL" }, 170 { TC_VENDORID, TC_DEVICEID_BOOMERANG_100BT4, 171 "3Com 3c905-T4 Fast Etherlink XL" }, 172 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT, 173 "3Com 3c900B-TPO Etherlink XL" }, 174 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_COMBO, 175 "3Com 3c900B-COMBO Etherlink XL" }, 176 { TC_VENDORID, TC_DEVICEID_KRAKATOA_10BT_TPC, 177 "3Com 3c900B-TPC Etherlink XL" }, 178 { TC_VENDORID, TC_DEVICEID_CYCLONE_10FL, 179 "3Com 3c900B-FL Etherlink XL" }, 180 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT, 181 "3Com 3c905B-TX Fast Etherlink XL" }, 182 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100BT4, 183 "3Com 3c905B-T4 Fast Etherlink XL" }, 184 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100FX, 185 "3Com 3c905B-FX/SC Fast Etherlink XL" }, 186 { TC_VENDORID, TC_DEVICEID_CYCLONE_10_100_COMBO, 187 "3Com 3c905B-COMBO Fast Etherlink XL" }, 188 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT, 189 "3Com 3c905C-TX Fast Etherlink XL" }, 190 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B, 191 "3Com 3c920B-EMB Integrated Fast Etherlink XL" }, 192 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_920B_WNM, 193 "3Com 3c920B-EMB-WNM Integrated Fast Etherlink XL" }, 194 { TC_VENDORID, TC_DEVICEID_HURRICANE_10_100BT_SERV, 195 "3Com 3c980 Fast Etherlink XL" }, 196 { TC_VENDORID, TC_DEVICEID_TORNADO_10_100BT_SERV, 197 "3Com 3c980C Fast Etherlink XL" }, 198 { TC_VENDORID, TC_DEVICEID_HURRICANE_SOHO100TX, 199 "3Com 3cSOHO100-TX OfficeConnect" }, 200 { TC_VENDORID, TC_DEVICEID_TORNADO_HOMECONNECT, 201 "3Com 3c450-TX HomeConnect" }, 202 { TC_VENDORID, TC_DEVICEID_HURRICANE_555, 203 "3Com 3c555 Fast Etherlink XL" }, 204 { TC_VENDORID, TC_DEVICEID_HURRICANE_556, 205 "3Com 3c556 Fast Etherlink XL" }, 206 { TC_VENDORID, TC_DEVICEID_HURRICANE_556B, 207 "3Com 3c556B Fast Etherlink XL" }, 208 { TC_VENDORID, TC_DEVICEID_HURRICANE_575A, 209 "3Com 3c575TX Fast Etherlink XL" }, 210 { TC_VENDORID, TC_DEVICEID_HURRICANE_575B, 211 "3Com 3c575B Fast Etherlink XL" }, 212 { TC_VENDORID, TC_DEVICEID_HURRICANE_575C, 213 "3Com 3c575C Fast Etherlink XL" }, 214 { TC_VENDORID, TC_DEVICEID_HURRICANE_656, 215 "3Com 3c656 Fast Etherlink XL" }, 216 { TC_VENDORID, TC_DEVICEID_HURRICANE_656B, 217 "3Com 3c656B Fast Etherlink XL" }, 218 { TC_VENDORID, TC_DEVICEID_TORNADO_656C, 219 "3Com 3c656C Fast Etherlink XL" }, 220 { 0, 0, NULL } 221 }; 222 223 static int xl_probe(device_t); 224 static int xl_attach(device_t); 225 static int xl_detach(device_t); 226 227 static int xl_newbuf(struct xl_softc *, struct xl_chain_onefrag *); 228 static void xl_stats_update(void *); 229 static void xl_stats_update_locked(struct xl_softc *); 230 static int xl_encap(struct xl_softc *, struct xl_chain *, struct mbuf **); 231 static void xl_rxeof(struct xl_softc *); 232 static void xl_rxeof_task(void *, int); 233 static int xl_rx_resync(struct xl_softc *); 234 static void xl_txeof(struct xl_softc *); 235 static void xl_txeof_90xB(struct xl_softc *); 236 static void xl_txeoc(struct xl_softc *); 237 static void xl_intr(void *); 238 static void xl_start(struct ifnet *); 239 static void xl_start_locked(struct ifnet *); 240 static void xl_start_90xB_locked(struct ifnet *); 241 static int xl_ioctl(struct ifnet *, u_long, caddr_t); 242 static void xl_init(void *); 243 static void xl_init_locked(struct xl_softc *); 244 static void xl_stop(struct xl_softc *); 245 static int xl_watchdog(struct xl_softc *); 246 static int xl_shutdown(device_t); 247 static int xl_suspend(device_t); 248 static int xl_resume(device_t); 249 250 #ifdef DEVICE_POLLING 251 static void xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 252 static void xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count); 253 #endif 254 255 static int xl_ifmedia_upd(struct ifnet *); 256 static void xl_ifmedia_sts(struct ifnet *, struct ifmediareq *); 257 258 static int xl_eeprom_wait(struct xl_softc *); 259 static int xl_read_eeprom(struct xl_softc *, caddr_t, int, int, int); 260 static void xl_mii_sync(struct xl_softc *); 261 static void xl_mii_send(struct xl_softc *, u_int32_t, int); 262 static int xl_mii_readreg(struct xl_softc *, struct xl_mii_frame *); 263 static int xl_mii_writereg(struct xl_softc *, struct xl_mii_frame *); 264 265 static void xl_setcfg(struct xl_softc *); 266 static void xl_setmode(struct xl_softc *, int); 267 static void xl_setmulti(struct xl_softc *); 268 static void xl_setmulti_hash(struct xl_softc *); 269 static void xl_reset(struct xl_softc *); 270 static int xl_list_rx_init(struct xl_softc *); 271 static int xl_list_tx_init(struct xl_softc *); 272 static int xl_list_tx_init_90xB(struct xl_softc *); 273 static void xl_wait(struct xl_softc *); 274 static void xl_mediacheck(struct xl_softc *); 275 static void xl_choose_media(struct xl_softc *sc, int *media); 276 static void xl_choose_xcvr(struct xl_softc *, int); 277 static void xl_dma_map_addr(void *, bus_dma_segment_t *, int, int); 278 #ifdef notdef 279 static void xl_testpacket(struct xl_softc *); 280 #endif 281 282 static int xl_miibus_readreg(device_t, int, int); 283 static int xl_miibus_writereg(device_t, int, int, int); 284 static void xl_miibus_statchg(device_t); 285 static void xl_miibus_mediainit(device_t); 286 287 static device_method_t xl_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, xl_probe), 290 DEVMETHOD(device_attach, xl_attach), 291 DEVMETHOD(device_detach, xl_detach), 292 DEVMETHOD(device_shutdown, xl_shutdown), 293 DEVMETHOD(device_suspend, xl_suspend), 294 DEVMETHOD(device_resume, xl_resume), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, xl_miibus_readreg), 302 DEVMETHOD(miibus_writereg, xl_miibus_writereg), 303 DEVMETHOD(miibus_statchg, xl_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, xl_miibus_mediainit), 305 306 { 0, 0 } 307 }; 308 309 static driver_t xl_driver = { 310 "xl", 311 xl_methods, 312 sizeof(struct xl_softc) 313 }; 314 315 static devclass_t xl_devclass; 316 317 DRIVER_MODULE(xl, pci, xl_driver, xl_devclass, 0, 0); 318 DRIVER_MODULE(miibus, xl, miibus_driver, miibus_devclass, 0, 0); 319 320 static void 321 xl_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 322 { 323 u_int32_t *paddr; 324 325 paddr = arg; 326 *paddr = segs->ds_addr; 327 } 328 329 /* 330 * Murphy's law says that it's possible the chip can wedge and 331 * the 'command in progress' bit may never clear. Hence, we wait 332 * only a finite amount of time to avoid getting caught in an 333 * infinite loop. Normally this delay routine would be a macro, 334 * but it isn't called during normal operation so we can afford 335 * to make it a function. 336 */ 337 static void 338 xl_wait(struct xl_softc *sc) 339 { 340 register int i; 341 342 for (i = 0; i < XL_TIMEOUT; i++) { 343 if ((CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY) == 0) 344 break; 345 } 346 347 if (i == XL_TIMEOUT) 348 device_printf(sc->xl_dev, "command never completed!\n"); 349 } 350 351 /* 352 * MII access routines are provided for adapters with external 353 * PHYs (3c905-TX, 3c905-T4, 3c905B-T4) and those with built-in 354 * autoneg logic that's faked up to look like a PHY (3c905B-TX). 355 * Note: if you don't perform the MDIO operations just right, 356 * it's possible to end up with code that works correctly with 357 * some chips/CPUs/processor speeds/bus speeds/etc but not 358 * with others. 359 */ 360 #define MII_SET(x) \ 361 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 362 CSR_READ_2(sc, XL_W4_PHY_MGMT) | (x)) 363 364 #define MII_CLR(x) \ 365 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, \ 366 CSR_READ_2(sc, XL_W4_PHY_MGMT) & ~(x)) 367 368 /* 369 * Sync the PHYs by setting data bit and strobing the clock 32 times. 370 */ 371 static void 372 xl_mii_sync(struct xl_softc *sc) 373 { 374 register int i; 375 376 XL_SEL_WIN(4); 377 MII_SET(XL_MII_DIR|XL_MII_DATA); 378 379 for (i = 0; i < 32; i++) { 380 MII_SET(XL_MII_CLK); 381 MII_SET(XL_MII_DATA); 382 MII_SET(XL_MII_DATA); 383 MII_CLR(XL_MII_CLK); 384 MII_SET(XL_MII_DATA); 385 MII_SET(XL_MII_DATA); 386 } 387 } 388 389 /* 390 * Clock a series of bits through the MII. 391 */ 392 static void 393 xl_mii_send(struct xl_softc *sc, u_int32_t bits, int cnt) 394 { 395 int i; 396 397 XL_SEL_WIN(4); 398 MII_CLR(XL_MII_CLK); 399 400 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 401 if (bits & i) { 402 MII_SET(XL_MII_DATA); 403 } else { 404 MII_CLR(XL_MII_DATA); 405 } 406 MII_CLR(XL_MII_CLK); 407 MII_SET(XL_MII_CLK); 408 } 409 } 410 411 /* 412 * Read an PHY register through the MII. 413 */ 414 static int 415 xl_mii_readreg(struct xl_softc *sc, struct xl_mii_frame *frame) 416 { 417 int i, ack; 418 419 /* Set up frame for RX. */ 420 frame->mii_stdelim = XL_MII_STARTDELIM; 421 frame->mii_opcode = XL_MII_READOP; 422 frame->mii_turnaround = 0; 423 frame->mii_data = 0; 424 425 /* Select register window 4. */ 426 XL_SEL_WIN(4); 427 428 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, 0); 429 /* Turn on data xmit. */ 430 MII_SET(XL_MII_DIR); 431 432 xl_mii_sync(sc); 433 434 /* Send command/address info. */ 435 xl_mii_send(sc, frame->mii_stdelim, 2); 436 xl_mii_send(sc, frame->mii_opcode, 2); 437 xl_mii_send(sc, frame->mii_phyaddr, 5); 438 xl_mii_send(sc, frame->mii_regaddr, 5); 439 440 /* Idle bit */ 441 MII_CLR((XL_MII_CLK|XL_MII_DATA)); 442 MII_SET(XL_MII_CLK); 443 444 /* Turn off xmit. */ 445 MII_CLR(XL_MII_DIR); 446 447 /* Check for ack */ 448 MII_CLR(XL_MII_CLK); 449 ack = CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA; 450 MII_SET(XL_MII_CLK); 451 452 /* 453 * Now try reading data bits. If the ack failed, we still 454 * need to clock through 16 cycles to keep the PHY(s) in sync. 455 */ 456 if (ack) { 457 for (i = 0; i < 16; i++) { 458 MII_CLR(XL_MII_CLK); 459 MII_SET(XL_MII_CLK); 460 } 461 goto fail; 462 } 463 464 for (i = 0x8000; i; i >>= 1) { 465 MII_CLR(XL_MII_CLK); 466 if (!ack) { 467 if (CSR_READ_2(sc, XL_W4_PHY_MGMT) & XL_MII_DATA) 468 frame->mii_data |= i; 469 } 470 MII_SET(XL_MII_CLK); 471 } 472 473 fail: 474 MII_CLR(XL_MII_CLK); 475 MII_SET(XL_MII_CLK); 476 477 return (ack ? 1 : 0); 478 } 479 480 /* 481 * Write to a PHY register through the MII. 482 */ 483 static int 484 xl_mii_writereg(struct xl_softc *sc, struct xl_mii_frame *frame) 485 { 486 487 /* Set up frame for TX. */ 488 frame->mii_stdelim = XL_MII_STARTDELIM; 489 frame->mii_opcode = XL_MII_WRITEOP; 490 frame->mii_turnaround = XL_MII_TURNAROUND; 491 492 /* Select the window 4. */ 493 XL_SEL_WIN(4); 494 495 /* Turn on data output. */ 496 MII_SET(XL_MII_DIR); 497 498 xl_mii_sync(sc); 499 500 xl_mii_send(sc, frame->mii_stdelim, 2); 501 xl_mii_send(sc, frame->mii_opcode, 2); 502 xl_mii_send(sc, frame->mii_phyaddr, 5); 503 xl_mii_send(sc, frame->mii_regaddr, 5); 504 xl_mii_send(sc, frame->mii_turnaround, 2); 505 xl_mii_send(sc, frame->mii_data, 16); 506 507 /* Idle bit. */ 508 MII_SET(XL_MII_CLK); 509 MII_CLR(XL_MII_CLK); 510 511 /* Turn off xmit. */ 512 MII_CLR(XL_MII_DIR); 513 514 return (0); 515 } 516 517 static int 518 xl_miibus_readreg(device_t dev, int phy, int reg) 519 { 520 struct xl_softc *sc; 521 struct xl_mii_frame frame; 522 523 sc = device_get_softc(dev); 524 525 /* 526 * Pretend that PHYs are only available at MII address 24. 527 * This is to guard against problems with certain 3Com ASIC 528 * revisions that incorrectly map the internal transceiver 529 * control registers at all MII addresses. This can cause 530 * the miibus code to attach the same PHY several times over. 531 */ 532 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 533 return (0); 534 535 bzero((char *)&frame, sizeof(frame)); 536 frame.mii_phyaddr = phy; 537 frame.mii_regaddr = reg; 538 539 xl_mii_readreg(sc, &frame); 540 541 return (frame.mii_data); 542 } 543 544 static int 545 xl_miibus_writereg(device_t dev, int phy, int reg, int data) 546 { 547 struct xl_softc *sc; 548 struct xl_mii_frame frame; 549 550 sc = device_get_softc(dev); 551 552 if ((sc->xl_flags & XL_FLAG_PHYOK) == 0 && phy != 24) 553 return (0); 554 555 bzero((char *)&frame, sizeof(frame)); 556 frame.mii_phyaddr = phy; 557 frame.mii_regaddr = reg; 558 frame.mii_data = data; 559 560 xl_mii_writereg(sc, &frame); 561 562 return (0); 563 } 564 565 static void 566 xl_miibus_statchg(device_t dev) 567 { 568 struct xl_softc *sc; 569 struct mii_data *mii; 570 571 sc = device_get_softc(dev); 572 mii = device_get_softc(sc->xl_miibus); 573 574 xl_setcfg(sc); 575 576 /* Set ASIC's duplex mode to match the PHY. */ 577 XL_SEL_WIN(3); 578 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 579 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 580 else 581 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 582 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 583 } 584 585 /* 586 * Special support for the 3c905B-COMBO. This card has 10/100 support 587 * plus BNC and AUI ports. This means we will have both an miibus attached 588 * plus some non-MII media settings. In order to allow this, we have to 589 * add the extra media to the miibus's ifmedia struct, but we can't do 590 * that during xl_attach() because the miibus hasn't been attached yet. 591 * So instead, we wait until the miibus probe/attach is done, at which 592 * point we will get a callback telling is that it's safe to add our 593 * extra media. 594 */ 595 static void 596 xl_miibus_mediainit(device_t dev) 597 { 598 struct xl_softc *sc; 599 struct mii_data *mii; 600 struct ifmedia *ifm; 601 602 sc = device_get_softc(dev); 603 mii = device_get_softc(sc->xl_miibus); 604 ifm = &mii->mii_media; 605 606 if (sc->xl_media & (XL_MEDIAOPT_AUI | XL_MEDIAOPT_10FL)) { 607 /* 608 * Check for a 10baseFL board in disguise. 609 */ 610 if (sc->xl_type == XL_TYPE_905B && 611 sc->xl_media == XL_MEDIAOPT_10FL) { 612 if (bootverbose) 613 device_printf(sc->xl_dev, "found 10baseFL\n"); 614 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL, 0, NULL); 615 ifmedia_add(ifm, IFM_ETHER | IFM_10_FL|IFM_HDX, 0, 616 NULL); 617 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 618 ifmedia_add(ifm, 619 IFM_ETHER | IFM_10_FL | IFM_FDX, 0, NULL); 620 } else { 621 if (bootverbose) 622 device_printf(sc->xl_dev, "found AUI\n"); 623 ifmedia_add(ifm, IFM_ETHER | IFM_10_5, 0, NULL); 624 } 625 } 626 627 if (sc->xl_media & XL_MEDIAOPT_BNC) { 628 if (bootverbose) 629 device_printf(sc->xl_dev, "found BNC\n"); 630 ifmedia_add(ifm, IFM_ETHER | IFM_10_2, 0, NULL); 631 } 632 } 633 634 /* 635 * The EEPROM is slow: give it time to come ready after issuing 636 * it a command. 637 */ 638 static int 639 xl_eeprom_wait(struct xl_softc *sc) 640 { 641 int i; 642 643 for (i = 0; i < 100; i++) { 644 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) 645 DELAY(162); 646 else 647 break; 648 } 649 650 if (i == 100) { 651 device_printf(sc->xl_dev, "eeprom failed to come ready\n"); 652 return (1); 653 } 654 655 return (0); 656 } 657 658 /* 659 * Read a sequence of words from the EEPROM. Note that ethernet address 660 * data is stored in the EEPROM in network byte order. 661 */ 662 static int 663 xl_read_eeprom(struct xl_softc *sc, caddr_t dest, int off, int cnt, int swap) 664 { 665 int err = 0, i; 666 u_int16_t word = 0, *ptr; 667 668 #define EEPROM_5BIT_OFFSET(A) ((((A) << 2) & 0x7F00) | ((A) & 0x003F)) 669 #define EEPROM_8BIT_OFFSET(A) ((A) & 0x003F) 670 /* 671 * XXX: WARNING! DANGER! 672 * It's easy to accidentally overwrite the rom content! 673 * Note: the 3c575 uses 8bit EEPROM offsets. 674 */ 675 XL_SEL_WIN(0); 676 677 if (xl_eeprom_wait(sc)) 678 return (1); 679 680 if (sc->xl_flags & XL_FLAG_EEPROM_OFFSET_30) 681 off += 0x30; 682 683 for (i = 0; i < cnt; i++) { 684 if (sc->xl_flags & XL_FLAG_8BITROM) 685 CSR_WRITE_2(sc, XL_W0_EE_CMD, 686 XL_EE_8BIT_READ | EEPROM_8BIT_OFFSET(off + i)); 687 else 688 CSR_WRITE_2(sc, XL_W0_EE_CMD, 689 XL_EE_READ | EEPROM_5BIT_OFFSET(off + i)); 690 err = xl_eeprom_wait(sc); 691 if (err) 692 break; 693 word = CSR_READ_2(sc, XL_W0_EE_DATA); 694 ptr = (u_int16_t *)(dest + (i * 2)); 695 if (swap) 696 *ptr = ntohs(word); 697 else 698 *ptr = word; 699 } 700 701 return (err ? 1 : 0); 702 } 703 704 /* 705 * NICs older than the 3c905B have only one multicast option, which 706 * is to enable reception of all multicast frames. 707 */ 708 static void 709 xl_setmulti(struct xl_softc *sc) 710 { 711 struct ifnet *ifp = sc->xl_ifp; 712 struct ifmultiaddr *ifma; 713 u_int8_t rxfilt; 714 int mcnt = 0; 715 716 XL_LOCK_ASSERT(sc); 717 718 XL_SEL_WIN(5); 719 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 720 721 if (ifp->if_flags & IFF_ALLMULTI) { 722 rxfilt |= XL_RXFILTER_ALLMULTI; 723 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 724 return; 725 } 726 727 IF_ADDR_LOCK(ifp); 728 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 729 mcnt++; 730 IF_ADDR_UNLOCK(ifp); 731 732 if (mcnt) 733 rxfilt |= XL_RXFILTER_ALLMULTI; 734 else 735 rxfilt &= ~XL_RXFILTER_ALLMULTI; 736 737 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 738 } 739 740 /* 741 * 3c905B adapters have a hash filter that we can program. 742 */ 743 static void 744 xl_setmulti_hash(struct xl_softc *sc) 745 { 746 struct ifnet *ifp = sc->xl_ifp; 747 int h = 0, i; 748 struct ifmultiaddr *ifma; 749 u_int8_t rxfilt; 750 int mcnt = 0; 751 752 XL_LOCK_ASSERT(sc); 753 754 XL_SEL_WIN(5); 755 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 756 757 if (ifp->if_flags & IFF_ALLMULTI) { 758 rxfilt |= XL_RXFILTER_ALLMULTI; 759 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 760 return; 761 } else 762 rxfilt &= ~XL_RXFILTER_ALLMULTI; 763 764 /* first, zot all the existing hash bits */ 765 for (i = 0; i < XL_HASHFILT_SIZE; i++) 766 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH|i); 767 768 /* now program new ones */ 769 IF_ADDR_LOCK(ifp); 770 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 771 if (ifma->ifma_addr->sa_family != AF_LINK) 772 continue; 773 /* 774 * Note: the 3c905B currently only supports a 64-bit hash 775 * table, which means we really only need 6 bits, but the 776 * manual indicates that future chip revisions will have a 777 * 256-bit hash table, hence the routine is set up to 778 * calculate 8 bits of position info in case we need it some 779 * day. 780 * Note II, The Sequel: _CURRENT_ versions of the 3c905B have 781 * a 256 bit hash table. This means we have to use all 8 bits 782 * regardless. On older cards, the upper 2 bits will be 783 * ignored. Grrrr.... 784 */ 785 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 786 ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF; 787 CSR_WRITE_2(sc, XL_COMMAND, 788 h | XL_CMD_RX_SET_HASH | XL_HASH_SET); 789 mcnt++; 790 } 791 IF_ADDR_UNLOCK(ifp); 792 793 if (mcnt) 794 rxfilt |= XL_RXFILTER_MULTIHASH; 795 else 796 rxfilt &= ~XL_RXFILTER_MULTIHASH; 797 798 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); 799 } 800 801 static void 802 xl_setcfg(struct xl_softc *sc) 803 { 804 u_int32_t icfg; 805 806 /*XL_LOCK_ASSERT(sc);*/ 807 808 XL_SEL_WIN(3); 809 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 810 icfg &= ~XL_ICFG_CONNECTOR_MASK; 811 if (sc->xl_media & XL_MEDIAOPT_MII || 812 sc->xl_media & XL_MEDIAOPT_BT4) 813 icfg |= (XL_XCVR_MII << XL_ICFG_CONNECTOR_BITS); 814 if (sc->xl_media & XL_MEDIAOPT_BTX) 815 icfg |= (XL_XCVR_AUTO << XL_ICFG_CONNECTOR_BITS); 816 817 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 819 } 820 821 static void 822 xl_setmode(struct xl_softc *sc, int media) 823 { 824 u_int32_t icfg; 825 u_int16_t mediastat; 826 char *pmsg = "", *dmsg = ""; 827 828 XL_LOCK_ASSERT(sc); 829 830 XL_SEL_WIN(4); 831 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 832 XL_SEL_WIN(3); 833 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG); 834 835 if (sc->xl_media & XL_MEDIAOPT_BT) { 836 if (IFM_SUBTYPE(media) == IFM_10_T) { 837 pmsg = "10baseT transceiver"; 838 sc->xl_xcvr = XL_XCVR_10BT; 839 icfg &= ~XL_ICFG_CONNECTOR_MASK; 840 icfg |= (XL_XCVR_10BT << XL_ICFG_CONNECTOR_BITS); 841 mediastat |= XL_MEDIASTAT_LINKBEAT | 842 XL_MEDIASTAT_JABGUARD; 843 mediastat &= ~XL_MEDIASTAT_SQEENB; 844 } 845 } 846 847 if (sc->xl_media & XL_MEDIAOPT_BFX) { 848 if (IFM_SUBTYPE(media) == IFM_100_FX) { 849 pmsg = "100baseFX port"; 850 sc->xl_xcvr = XL_XCVR_100BFX; 851 icfg &= ~XL_ICFG_CONNECTOR_MASK; 852 icfg |= (XL_XCVR_100BFX << XL_ICFG_CONNECTOR_BITS); 853 mediastat |= XL_MEDIASTAT_LINKBEAT; 854 mediastat &= ~XL_MEDIASTAT_SQEENB; 855 } 856 } 857 858 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 859 if (IFM_SUBTYPE(media) == IFM_10_5) { 860 pmsg = "AUI port"; 861 sc->xl_xcvr = XL_XCVR_AUI; 862 icfg &= ~XL_ICFG_CONNECTOR_MASK; 863 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 864 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 865 XL_MEDIASTAT_JABGUARD); 866 mediastat |= ~XL_MEDIASTAT_SQEENB; 867 } 868 if (IFM_SUBTYPE(media) == IFM_10_FL) { 869 pmsg = "10baseFL transceiver"; 870 sc->xl_xcvr = XL_XCVR_AUI; 871 icfg &= ~XL_ICFG_CONNECTOR_MASK; 872 icfg |= (XL_XCVR_AUI << XL_ICFG_CONNECTOR_BITS); 873 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 874 XL_MEDIASTAT_JABGUARD); 875 mediastat |= ~XL_MEDIASTAT_SQEENB; 876 } 877 } 878 879 if (sc->xl_media & XL_MEDIAOPT_BNC) { 880 if (IFM_SUBTYPE(media) == IFM_10_2) { 881 pmsg = "AUI port"; 882 sc->xl_xcvr = XL_XCVR_COAX; 883 icfg &= ~XL_ICFG_CONNECTOR_MASK; 884 icfg |= (XL_XCVR_COAX << XL_ICFG_CONNECTOR_BITS); 885 mediastat &= ~(XL_MEDIASTAT_LINKBEAT | 886 XL_MEDIASTAT_JABGUARD | XL_MEDIASTAT_SQEENB); 887 } 888 } 889 890 if ((media & IFM_GMASK) == IFM_FDX || 891 IFM_SUBTYPE(media) == IFM_100_FX) { 892 dmsg = "full"; 893 XL_SEL_WIN(3); 894 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); 895 } else { 896 dmsg = "half"; 897 XL_SEL_WIN(3); 898 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, 899 (CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX)); 900 } 901 902 if (IFM_SUBTYPE(media) == IFM_10_2) 903 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 904 else 905 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 906 907 CSR_WRITE_4(sc, XL_W3_INTERNAL_CFG, icfg); 908 XL_SEL_WIN(4); 909 CSR_WRITE_2(sc, XL_W4_MEDIA_STATUS, mediastat); 910 911 DELAY(800); 912 XL_SEL_WIN(7); 913 914 device_printf(sc->xl_dev, "selecting %s, %s duplex\n", pmsg, dmsg); 915 } 916 917 static void 918 xl_reset(struct xl_softc *sc) 919 { 920 register int i; 921 922 XL_LOCK_ASSERT(sc); 923 924 XL_SEL_WIN(0); 925 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RESET | 926 ((sc->xl_flags & XL_FLAG_WEIRDRESET) ? 927 XL_RESETOPT_DISADVFD:0)); 928 929 /* 930 * If we're using memory mapped register mode, pause briefly 931 * after issuing the reset command before trying to access any 932 * other registers. With my 3c575C cardbus card, failing to do 933 * this results in the system locking up while trying to poll 934 * the command busy bit in the status register. 935 */ 936 if (sc->xl_flags & XL_FLAG_USE_MMIO) 937 DELAY(100000); 938 939 for (i = 0; i < XL_TIMEOUT; i++) { 940 DELAY(10); 941 if (!(CSR_READ_2(sc, XL_STATUS) & XL_STAT_CMDBUSY)) 942 break; 943 } 944 945 if (i == XL_TIMEOUT) 946 device_printf(sc->xl_dev, "reset didn't complete\n"); 947 948 /* Reset TX and RX. */ 949 /* Note: the RX reset takes an absurd amount of time 950 * on newer versions of the Tornado chips such as those 951 * on the 3c905CX and newer 3c908C cards. We wait an 952 * extra amount of time so that xl_wait() doesn't complain 953 * and annoy the users. 954 */ 955 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 956 DELAY(100000); 957 xl_wait(sc); 958 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 959 xl_wait(sc); 960 961 if (sc->xl_flags & XL_FLAG_INVERT_LED_PWR || 962 sc->xl_flags & XL_FLAG_INVERT_MII_PWR) { 963 XL_SEL_WIN(2); 964 CSR_WRITE_2(sc, XL_W2_RESET_OPTIONS, 965 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | 966 ((sc->xl_flags & XL_FLAG_INVERT_LED_PWR) ? 967 XL_RESETOPT_INVERT_LED : 0) | 968 ((sc->xl_flags & XL_FLAG_INVERT_MII_PWR) ? 969 XL_RESETOPT_INVERT_MII : 0)); 970 } 971 972 /* Wait a little while for the chip to get its brains in order. */ 973 DELAY(100000); 974 } 975 976 /* 977 * Probe for a 3Com Etherlink XL chip. Check the PCI vendor and device 978 * IDs against our list and return a device name if we find a match. 979 */ 980 static int 981 xl_probe(device_t dev) 982 { 983 const struct xl_type *t; 984 985 t = xl_devs; 986 987 while (t->xl_name != NULL) { 988 if ((pci_get_vendor(dev) == t->xl_vid) && 989 (pci_get_device(dev) == t->xl_did)) { 990 device_set_desc(dev, t->xl_name); 991 return (BUS_PROBE_DEFAULT); 992 } 993 t++; 994 } 995 996 return (ENXIO); 997 } 998 999 /* 1000 * This routine is a kludge to work around possible hardware faults 1001 * or manufacturing defects that can cause the media options register 1002 * (or reset options register, as it's called for the first generation 1003 * 3c90x adapters) to return an incorrect result. I have encountered 1004 * one Dell Latitude laptop docking station with an integrated 3c905-TX 1005 * which doesn't have any of the 'mediaopt' bits set. This screws up 1006 * the attach routine pretty badly because it doesn't know what media 1007 * to look for. If we find ourselves in this predicament, this routine 1008 * will try to guess the media options values and warn the user of a 1009 * possible manufacturing defect with his adapter/system/whatever. 1010 */ 1011 static void 1012 xl_mediacheck(struct xl_softc *sc) 1013 { 1014 1015 /* 1016 * If some of the media options bits are set, assume they are 1017 * correct. If not, try to figure it out down below. 1018 * XXX I should check for 10baseFL, but I don't have an adapter 1019 * to test with. 1020 */ 1021 if (sc->xl_media & (XL_MEDIAOPT_MASK & ~XL_MEDIAOPT_VCO)) { 1022 /* 1023 * Check the XCVR value. If it's not in the normal range 1024 * of values, we need to fake it up here. 1025 */ 1026 if (sc->xl_xcvr <= XL_XCVR_AUTO) 1027 return; 1028 else { 1029 device_printf(sc->xl_dev, 1030 "bogus xcvr value in EEPROM (%x)\n", sc->xl_xcvr); 1031 device_printf(sc->xl_dev, 1032 "choosing new default based on card type\n"); 1033 } 1034 } else { 1035 if (sc->xl_type == XL_TYPE_905B && 1036 sc->xl_media & XL_MEDIAOPT_10FL) 1037 return; 1038 device_printf(sc->xl_dev, 1039 "WARNING: no media options bits set in the media options register!!\n"); 1040 device_printf(sc->xl_dev, 1041 "this could be a manufacturing defect in your adapter or system\n"); 1042 device_printf(sc->xl_dev, 1043 "attempting to guess media type; you should probably consult your vendor\n"); 1044 } 1045 1046 xl_choose_xcvr(sc, 1); 1047 } 1048 1049 static void 1050 xl_choose_xcvr(struct xl_softc *sc, int verbose) 1051 { 1052 u_int16_t devid; 1053 1054 /* 1055 * Read the device ID from the EEPROM. 1056 * This is what's loaded into the PCI device ID register, so it has 1057 * to be correct otherwise we wouldn't have gotten this far. 1058 */ 1059 xl_read_eeprom(sc, (caddr_t)&devid, XL_EE_PRODID, 1, 0); 1060 1061 switch (devid) { 1062 case TC_DEVICEID_BOOMERANG_10BT: /* 3c900-TPO */ 1063 case TC_DEVICEID_KRAKATOA_10BT: /* 3c900B-TPO */ 1064 sc->xl_media = XL_MEDIAOPT_BT; 1065 sc->xl_xcvr = XL_XCVR_10BT; 1066 if (verbose) 1067 device_printf(sc->xl_dev, 1068 "guessing 10BaseT transceiver\n"); 1069 break; 1070 case TC_DEVICEID_BOOMERANG_10BT_COMBO: /* 3c900-COMBO */ 1071 case TC_DEVICEID_KRAKATOA_10BT_COMBO: /* 3c900B-COMBO */ 1072 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1073 sc->xl_xcvr = XL_XCVR_10BT; 1074 if (verbose) 1075 device_printf(sc->xl_dev, 1076 "guessing COMBO (AUI/BNC/TP)\n"); 1077 break; 1078 case TC_DEVICEID_KRAKATOA_10BT_TPC: /* 3c900B-TPC */ 1079 sc->xl_media = XL_MEDIAOPT_BT|XL_MEDIAOPT_BNC; 1080 sc->xl_xcvr = XL_XCVR_10BT; 1081 if (verbose) 1082 device_printf(sc->xl_dev, "guessing TPC (BNC/TP)\n"); 1083 break; 1084 case TC_DEVICEID_CYCLONE_10FL: /* 3c900B-FL */ 1085 sc->xl_media = XL_MEDIAOPT_10FL; 1086 sc->xl_xcvr = XL_XCVR_AUI; 1087 if (verbose) 1088 device_printf(sc->xl_dev, "guessing 10baseFL\n"); 1089 break; 1090 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1091 case TC_DEVICEID_HURRICANE_555: /* 3c555 */ 1092 case TC_DEVICEID_HURRICANE_556: /* 3c556 */ 1093 case TC_DEVICEID_HURRICANE_556B: /* 3c556B */ 1094 case TC_DEVICEID_HURRICANE_575A: /* 3c575TX */ 1095 case TC_DEVICEID_HURRICANE_575B: /* 3c575B */ 1096 case TC_DEVICEID_HURRICANE_575C: /* 3c575C */ 1097 case TC_DEVICEID_HURRICANE_656: /* 3c656 */ 1098 case TC_DEVICEID_HURRICANE_656B: /* 3c656B */ 1099 case TC_DEVICEID_TORNADO_656C: /* 3c656C */ 1100 case TC_DEVICEID_TORNADO_10_100BT_920B: /* 3c920B-EMB */ 1101 case TC_DEVICEID_TORNADO_10_100BT_920B_WNM: /* 3c920B-EMB-WNM */ 1102 sc->xl_media = XL_MEDIAOPT_MII; 1103 sc->xl_xcvr = XL_XCVR_MII; 1104 if (verbose) 1105 device_printf(sc->xl_dev, "guessing MII\n"); 1106 break; 1107 case TC_DEVICEID_BOOMERANG_100BT4: /* 3c905-T4 */ 1108 case TC_DEVICEID_CYCLONE_10_100BT4: /* 3c905B-T4 */ 1109 sc->xl_media = XL_MEDIAOPT_BT4; 1110 sc->xl_xcvr = XL_XCVR_MII; 1111 if (verbose) 1112 device_printf(sc->xl_dev, "guessing 100baseT4/MII\n"); 1113 break; 1114 case TC_DEVICEID_HURRICANE_10_100BT: /* 3c905B-TX */ 1115 case TC_DEVICEID_HURRICANE_10_100BT_SERV:/*3c980-TX */ 1116 case TC_DEVICEID_TORNADO_10_100BT_SERV: /* 3c980C-TX */ 1117 case TC_DEVICEID_HURRICANE_SOHO100TX: /* 3cSOHO100-TX */ 1118 case TC_DEVICEID_TORNADO_10_100BT: /* 3c905C-TX */ 1119 case TC_DEVICEID_TORNADO_HOMECONNECT: /* 3c450-TX */ 1120 sc->xl_media = XL_MEDIAOPT_BTX; 1121 sc->xl_xcvr = XL_XCVR_AUTO; 1122 if (verbose) 1123 device_printf(sc->xl_dev, "guessing 10/100 internal\n"); 1124 break; 1125 case TC_DEVICEID_CYCLONE_10_100_COMBO: /* 3c905B-COMBO */ 1126 sc->xl_media = XL_MEDIAOPT_BTX|XL_MEDIAOPT_BNC|XL_MEDIAOPT_AUI; 1127 sc->xl_xcvr = XL_XCVR_AUTO; 1128 if (verbose) 1129 device_printf(sc->xl_dev, 1130 "guessing 10/100 plus BNC/AUI\n"); 1131 break; 1132 default: 1133 device_printf(sc->xl_dev, 1134 "unknown device ID: %x -- defaulting to 10baseT\n", devid); 1135 sc->xl_media = XL_MEDIAOPT_BT; 1136 break; 1137 } 1138 } 1139 1140 /* 1141 * Attach the interface. Allocate softc structures, do ifmedia 1142 * setup and ethernet/BPF attach. 1143 */ 1144 static int 1145 xl_attach(device_t dev) 1146 { 1147 u_char eaddr[ETHER_ADDR_LEN]; 1148 u_int16_t xcvr[2]; 1149 struct xl_softc *sc; 1150 struct ifnet *ifp; 1151 int media; 1152 int unit, error = 0, rid, res; 1153 uint16_t did; 1154 1155 sc = device_get_softc(dev); 1156 sc->xl_dev = dev; 1157 1158 unit = device_get_unit(dev); 1159 1160 mtx_init(&sc->xl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1161 MTX_DEF); 1162 ifmedia_init(&sc->ifmedia, 0, xl_ifmedia_upd, xl_ifmedia_sts); 1163 1164 did = pci_get_device(dev); 1165 1166 sc->xl_flags = 0; 1167 if (did == TC_DEVICEID_HURRICANE_555) 1168 sc->xl_flags |= XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_PHYOK; 1169 if (did == TC_DEVICEID_HURRICANE_556 || 1170 did == TC_DEVICEID_HURRICANE_556B) 1171 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK | 1172 XL_FLAG_EEPROM_OFFSET_30 | XL_FLAG_WEIRDRESET | 1173 XL_FLAG_INVERT_LED_PWR | XL_FLAG_INVERT_MII_PWR; 1174 if (did == TC_DEVICEID_HURRICANE_555 || 1175 did == TC_DEVICEID_HURRICANE_556) 1176 sc->xl_flags |= XL_FLAG_8BITROM; 1177 if (did == TC_DEVICEID_HURRICANE_556B) 1178 sc->xl_flags |= XL_FLAG_NO_XCVR_PWR; 1179 1180 if (did == TC_DEVICEID_HURRICANE_575B || 1181 did == TC_DEVICEID_HURRICANE_575C || 1182 did == TC_DEVICEID_HURRICANE_656B || 1183 did == TC_DEVICEID_TORNADO_656C) 1184 sc->xl_flags |= XL_FLAG_FUNCREG; 1185 if (did == TC_DEVICEID_HURRICANE_575A || 1186 did == TC_DEVICEID_HURRICANE_575B || 1187 did == TC_DEVICEID_HURRICANE_575C || 1188 did == TC_DEVICEID_HURRICANE_656B || 1189 did == TC_DEVICEID_TORNADO_656C) 1190 sc->xl_flags |= XL_FLAG_PHYOK | XL_FLAG_EEPROM_OFFSET_30 | 1191 XL_FLAG_8BITROM; 1192 if (did == TC_DEVICEID_HURRICANE_656) 1193 sc->xl_flags |= XL_FLAG_FUNCREG | XL_FLAG_PHYOK; 1194 if (did == TC_DEVICEID_HURRICANE_575B) 1195 sc->xl_flags |= XL_FLAG_INVERT_LED_PWR; 1196 if (did == TC_DEVICEID_HURRICANE_575C) 1197 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1198 if (did == TC_DEVICEID_TORNADO_656C) 1199 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR; 1200 if (did == TC_DEVICEID_HURRICANE_656 || 1201 did == TC_DEVICEID_HURRICANE_656B) 1202 sc->xl_flags |= XL_FLAG_INVERT_MII_PWR | 1203 XL_FLAG_INVERT_LED_PWR; 1204 if (did == TC_DEVICEID_TORNADO_10_100BT_920B || 1205 did == TC_DEVICEID_TORNADO_10_100BT_920B_WNM) 1206 sc->xl_flags |= XL_FLAG_PHYOK; 1207 1208 switch (did) { 1209 case TC_DEVICEID_BOOMERANG_10_100BT: /* 3c905-TX */ 1210 case TC_DEVICEID_HURRICANE_575A: 1211 case TC_DEVICEID_HURRICANE_575B: 1212 case TC_DEVICEID_HURRICANE_575C: 1213 sc->xl_flags |= XL_FLAG_NO_MMIO; 1214 break; 1215 default: 1216 break; 1217 } 1218 1219 /* 1220 * Map control/status registers. 1221 */ 1222 pci_enable_busmaster(dev); 1223 1224 if ((sc->xl_flags & XL_FLAG_NO_MMIO) == 0) { 1225 rid = XL_PCI_LOMEM; 1226 res = SYS_RES_MEMORY; 1227 1228 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1229 } 1230 1231 if (sc->xl_res != NULL) { 1232 sc->xl_flags |= XL_FLAG_USE_MMIO; 1233 if (bootverbose) 1234 device_printf(dev, "using memory mapped I/O\n"); 1235 } else { 1236 rid = XL_PCI_LOIO; 1237 res = SYS_RES_IOPORT; 1238 sc->xl_res = bus_alloc_resource_any(dev, res, &rid, RF_ACTIVE); 1239 if (sc->xl_res == NULL) { 1240 device_printf(dev, "couldn't map ports/memory\n"); 1241 error = ENXIO; 1242 goto fail; 1243 } 1244 if (bootverbose) 1245 device_printf(dev, "using port I/O\n"); 1246 } 1247 1248 sc->xl_btag = rman_get_bustag(sc->xl_res); 1249 sc->xl_bhandle = rman_get_bushandle(sc->xl_res); 1250 1251 if (sc->xl_flags & XL_FLAG_FUNCREG) { 1252 rid = XL_PCI_FUNCMEM; 1253 sc->xl_fres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1254 RF_ACTIVE); 1255 1256 if (sc->xl_fres == NULL) { 1257 device_printf(dev, "couldn't map funcreg memory\n"); 1258 error = ENXIO; 1259 goto fail; 1260 } 1261 1262 sc->xl_ftag = rman_get_bustag(sc->xl_fres); 1263 sc->xl_fhandle = rman_get_bushandle(sc->xl_fres); 1264 } 1265 1266 /* Allocate interrupt */ 1267 rid = 0; 1268 sc->xl_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1269 RF_SHAREABLE | RF_ACTIVE); 1270 if (sc->xl_irq == NULL) { 1271 device_printf(dev, "couldn't map interrupt\n"); 1272 error = ENXIO; 1273 goto fail; 1274 } 1275 1276 /* Initialize interface name. */ 1277 ifp = sc->xl_ifp = if_alloc(IFT_ETHER); 1278 if (ifp == NULL) { 1279 device_printf(dev, "can not if_alloc()\n"); 1280 error = ENOSPC; 1281 goto fail; 1282 } 1283 ifp->if_softc = sc; 1284 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1285 1286 /* Reset the adapter. */ 1287 XL_LOCK(sc); 1288 xl_reset(sc); 1289 XL_UNLOCK(sc); 1290 1291 /* 1292 * Get station address from the EEPROM. 1293 */ 1294 if (xl_read_eeprom(sc, (caddr_t)&eaddr, XL_EE_OEM_ADR0, 3, 1)) { 1295 device_printf(dev, "failed to read station address\n"); 1296 error = ENXIO; 1297 goto fail; 1298 } 1299 1300 callout_init_mtx(&sc->xl_stat_callout, &sc->xl_mtx, 0); 1301 TASK_INIT(&sc->xl_task, 0, xl_rxeof_task, sc); 1302 1303 /* 1304 * Now allocate a tag for the DMA descriptor lists and a chunk 1305 * of DMA-able memory based on the tag. Also obtain the DMA 1306 * addresses of the RX and TX ring, which we'll need later. 1307 * All of our lists are allocated as a contiguous block 1308 * of memory. 1309 */ 1310 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1311 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1312 XL_RX_LIST_SZ, 1, XL_RX_LIST_SZ, 0, NULL, NULL, 1313 &sc->xl_ldata.xl_rx_tag); 1314 if (error) { 1315 device_printf(dev, "failed to allocate rx dma tag\n"); 1316 goto fail; 1317 } 1318 1319 error = bus_dmamem_alloc(sc->xl_ldata.xl_rx_tag, 1320 (void **)&sc->xl_ldata.xl_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1321 &sc->xl_ldata.xl_rx_dmamap); 1322 if (error) { 1323 device_printf(dev, "no memory for rx list buffers!\n"); 1324 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1325 sc->xl_ldata.xl_rx_tag = NULL; 1326 goto fail; 1327 } 1328 1329 error = bus_dmamap_load(sc->xl_ldata.xl_rx_tag, 1330 sc->xl_ldata.xl_rx_dmamap, sc->xl_ldata.xl_rx_list, 1331 XL_RX_LIST_SZ, xl_dma_map_addr, 1332 &sc->xl_ldata.xl_rx_dmaaddr, BUS_DMA_NOWAIT); 1333 if (error) { 1334 device_printf(dev, "cannot get dma address of the rx ring!\n"); 1335 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1336 sc->xl_ldata.xl_rx_dmamap); 1337 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1338 sc->xl_ldata.xl_rx_tag = NULL; 1339 goto fail; 1340 } 1341 1342 error = bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0, 1343 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1344 XL_TX_LIST_SZ, 1, XL_TX_LIST_SZ, 0, NULL, NULL, 1345 &sc->xl_ldata.xl_tx_tag); 1346 if (error) { 1347 device_printf(dev, "failed to allocate tx dma tag\n"); 1348 goto fail; 1349 } 1350 1351 error = bus_dmamem_alloc(sc->xl_ldata.xl_tx_tag, 1352 (void **)&sc->xl_ldata.xl_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1353 &sc->xl_ldata.xl_tx_dmamap); 1354 if (error) { 1355 device_printf(dev, "no memory for list buffers!\n"); 1356 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1357 sc->xl_ldata.xl_tx_tag = NULL; 1358 goto fail; 1359 } 1360 1361 error = bus_dmamap_load(sc->xl_ldata.xl_tx_tag, 1362 sc->xl_ldata.xl_tx_dmamap, sc->xl_ldata.xl_tx_list, 1363 XL_TX_LIST_SZ, xl_dma_map_addr, 1364 &sc->xl_ldata.xl_tx_dmaaddr, BUS_DMA_NOWAIT); 1365 if (error) { 1366 device_printf(dev, "cannot get dma address of the tx ring!\n"); 1367 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1368 sc->xl_ldata.xl_tx_dmamap); 1369 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1370 sc->xl_ldata.xl_tx_tag = NULL; 1371 goto fail; 1372 } 1373 1374 /* 1375 * Allocate a DMA tag for the mapping of mbufs. 1376 */ 1377 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 1378 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 1379 MCLBYTES * XL_MAXFRAGS, XL_MAXFRAGS, MCLBYTES, 0, NULL, 1380 NULL, &sc->xl_mtag); 1381 if (error) { 1382 device_printf(dev, "failed to allocate mbuf dma tag\n"); 1383 goto fail; 1384 } 1385 1386 /* We need a spare DMA map for the RX ring. */ 1387 error = bus_dmamap_create(sc->xl_mtag, 0, &sc->xl_tmpmap); 1388 if (error) 1389 goto fail; 1390 1391 /* 1392 * Figure out the card type. 3c905B adapters have the 1393 * 'supportsNoTxLength' bit set in the capabilities 1394 * word in the EEPROM. 1395 * Note: my 3c575C cardbus card lies. It returns a value 1396 * of 0x1578 for its capabilities word, which is somewhat 1397 * nonsensical. Another way to distinguish a 3c90x chip 1398 * from a 3c90xB/C chip is to check for the 'supportsLargePackets' 1399 * bit. This will only be set for 3c90x boomerage chips. 1400 */ 1401 xl_read_eeprom(sc, (caddr_t)&sc->xl_caps, XL_EE_CAPS, 1, 0); 1402 if (sc->xl_caps & XL_CAPS_NO_TXLENGTH || 1403 !(sc->xl_caps & XL_CAPS_LARGE_PKTS)) 1404 sc->xl_type = XL_TYPE_905B; 1405 else 1406 sc->xl_type = XL_TYPE_90X; 1407 1408 /* Set the TX start threshold for best performance. */ 1409 sc->xl_tx_thresh = XL_MIN_FRAMELEN; 1410 1411 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1412 ifp->if_ioctl = xl_ioctl; 1413 ifp->if_capabilities = IFCAP_VLAN_MTU; 1414 if (sc->xl_type == XL_TYPE_905B) { 1415 ifp->if_hwassist = XL905B_CSUM_FEATURES; 1416 #ifdef XL905B_TXCSUM_BROKEN 1417 ifp->if_capabilities |= IFCAP_RXCSUM; 1418 #else 1419 ifp->if_capabilities |= IFCAP_HWCSUM; 1420 #endif 1421 } 1422 ifp->if_capenable = ifp->if_capabilities; 1423 #ifdef DEVICE_POLLING 1424 ifp->if_capabilities |= IFCAP_POLLING; 1425 #endif 1426 ifp->if_start = xl_start; 1427 ifp->if_init = xl_init; 1428 IFQ_SET_MAXLEN(&ifp->if_snd, XL_TX_LIST_CNT - 1); 1429 ifp->if_snd.ifq_drv_maxlen = XL_TX_LIST_CNT - 1; 1430 IFQ_SET_READY(&ifp->if_snd); 1431 1432 /* 1433 * Now we have to see what sort of media we have. 1434 * This includes probing for an MII interace and a 1435 * possible PHY. 1436 */ 1437 XL_SEL_WIN(3); 1438 sc->xl_media = CSR_READ_2(sc, XL_W3_MEDIA_OPT); 1439 if (bootverbose) 1440 device_printf(dev, "media options word: %x\n", sc->xl_media); 1441 1442 xl_read_eeprom(sc, (char *)&xcvr, XL_EE_ICFG_0, 2, 0); 1443 sc->xl_xcvr = xcvr[0] | xcvr[1] << 16; 1444 sc->xl_xcvr &= XL_ICFG_CONNECTOR_MASK; 1445 sc->xl_xcvr >>= XL_ICFG_CONNECTOR_BITS; 1446 1447 xl_mediacheck(sc); 1448 1449 if (sc->xl_media & XL_MEDIAOPT_MII || 1450 sc->xl_media & XL_MEDIAOPT_BTX || 1451 sc->xl_media & XL_MEDIAOPT_BT4) { 1452 if (bootverbose) 1453 device_printf(dev, "found MII/AUTO\n"); 1454 xl_setcfg(sc); 1455 if (mii_phy_probe(dev, &sc->xl_miibus, 1456 xl_ifmedia_upd, xl_ifmedia_sts)) { 1457 device_printf(dev, "no PHY found!\n"); 1458 error = ENXIO; 1459 goto fail; 1460 } 1461 goto done; 1462 } 1463 1464 /* 1465 * Sanity check. If the user has selected "auto" and this isn't 1466 * a 10/100 card of some kind, we need to force the transceiver 1467 * type to something sane. 1468 */ 1469 if (sc->xl_xcvr == XL_XCVR_AUTO) 1470 xl_choose_xcvr(sc, bootverbose); 1471 1472 /* 1473 * Do ifmedia setup. 1474 */ 1475 if (sc->xl_media & XL_MEDIAOPT_BT) { 1476 if (bootverbose) 1477 device_printf(dev, "found 10baseT\n"); 1478 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T, 0, NULL); 1479 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_T|IFM_HDX, 0, NULL); 1480 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1481 ifmedia_add(&sc->ifmedia, 1482 IFM_ETHER|IFM_10_T|IFM_FDX, 0, NULL); 1483 } 1484 1485 if (sc->xl_media & (XL_MEDIAOPT_AUI|XL_MEDIAOPT_10FL)) { 1486 /* 1487 * Check for a 10baseFL board in disguise. 1488 */ 1489 if (sc->xl_type == XL_TYPE_905B && 1490 sc->xl_media == XL_MEDIAOPT_10FL) { 1491 if (bootverbose) 1492 device_printf(dev, "found 10baseFL\n"); 1493 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL, 0, NULL); 1494 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_FL|IFM_HDX, 1495 0, NULL); 1496 if (sc->xl_caps & XL_CAPS_FULL_DUPLEX) 1497 ifmedia_add(&sc->ifmedia, 1498 IFM_ETHER|IFM_10_FL|IFM_FDX, 0, NULL); 1499 } else { 1500 if (bootverbose) 1501 device_printf(dev, "found AUI\n"); 1502 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_5, 0, NULL); 1503 } 1504 } 1505 1506 if (sc->xl_media & XL_MEDIAOPT_BNC) { 1507 if (bootverbose) 1508 device_printf(dev, "found BNC\n"); 1509 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_10_2, 0, NULL); 1510 } 1511 1512 if (sc->xl_media & XL_MEDIAOPT_BFX) { 1513 if (bootverbose) 1514 device_printf(dev, "found 100baseFX\n"); 1515 ifmedia_add(&sc->ifmedia, IFM_ETHER|IFM_100_FX, 0, NULL); 1516 } 1517 1518 media = IFM_ETHER|IFM_100_TX|IFM_FDX; 1519 xl_choose_media(sc, &media); 1520 1521 if (sc->xl_miibus == NULL) 1522 ifmedia_set(&sc->ifmedia, media); 1523 1524 done: 1525 if (sc->xl_flags & XL_FLAG_NO_XCVR_PWR) { 1526 XL_SEL_WIN(0); 1527 CSR_WRITE_2(sc, XL_W0_MFG_ID, XL_NO_XCVR_PWR_MAGICBITS); 1528 } 1529 1530 /* 1531 * Call MI attach routine. 1532 */ 1533 ether_ifattach(ifp, eaddr); 1534 1535 error = bus_setup_intr(dev, sc->xl_irq, INTR_TYPE_NET | INTR_MPSAFE, 1536 NULL, xl_intr, sc, &sc->xl_intrhand); 1537 if (error) { 1538 device_printf(dev, "couldn't set up irq\n"); 1539 ether_ifdetach(ifp); 1540 goto fail; 1541 } 1542 1543 fail: 1544 if (error) 1545 xl_detach(dev); 1546 1547 return (error); 1548 } 1549 1550 /* 1551 * Choose a default media. 1552 * XXX This is a leaf function only called by xl_attach() and 1553 * acquires/releases the non-recursible driver mutex to 1554 * satisfy lock assertions. 1555 */ 1556 static void 1557 xl_choose_media(struct xl_softc *sc, int *media) 1558 { 1559 1560 XL_LOCK(sc); 1561 1562 switch (sc->xl_xcvr) { 1563 case XL_XCVR_10BT: 1564 *media = IFM_ETHER|IFM_10_T; 1565 xl_setmode(sc, *media); 1566 break; 1567 case XL_XCVR_AUI: 1568 if (sc->xl_type == XL_TYPE_905B && 1569 sc->xl_media == XL_MEDIAOPT_10FL) { 1570 *media = IFM_ETHER|IFM_10_FL; 1571 xl_setmode(sc, *media); 1572 } else { 1573 *media = IFM_ETHER|IFM_10_5; 1574 xl_setmode(sc, *media); 1575 } 1576 break; 1577 case XL_XCVR_COAX: 1578 *media = IFM_ETHER|IFM_10_2; 1579 xl_setmode(sc, *media); 1580 break; 1581 case XL_XCVR_AUTO: 1582 case XL_XCVR_100BTX: 1583 case XL_XCVR_MII: 1584 /* Chosen by miibus */ 1585 break; 1586 case XL_XCVR_100BFX: 1587 *media = IFM_ETHER|IFM_100_FX; 1588 break; 1589 default: 1590 device_printf(sc->xl_dev, "unknown XCVR type: %d\n", 1591 sc->xl_xcvr); 1592 /* 1593 * This will probably be wrong, but it prevents 1594 * the ifmedia code from panicking. 1595 */ 1596 *media = IFM_ETHER|IFM_10_T; 1597 break; 1598 } 1599 1600 XL_UNLOCK(sc); 1601 } 1602 1603 /* 1604 * Shutdown hardware and free up resources. This can be called any 1605 * time after the mutex has been initialized. It is called in both 1606 * the error case in attach and the normal detach case so it needs 1607 * to be careful about only freeing resources that have actually been 1608 * allocated. 1609 */ 1610 static int 1611 xl_detach(device_t dev) 1612 { 1613 struct xl_softc *sc; 1614 struct ifnet *ifp; 1615 int rid, res; 1616 1617 sc = device_get_softc(dev); 1618 ifp = sc->xl_ifp; 1619 1620 KASSERT(mtx_initialized(&sc->xl_mtx), ("xl mutex not initialized")); 1621 1622 #ifdef DEVICE_POLLING 1623 if (ifp && ifp->if_capenable & IFCAP_POLLING) 1624 ether_poll_deregister(ifp); 1625 #endif 1626 1627 if (sc->xl_flags & XL_FLAG_USE_MMIO) { 1628 rid = XL_PCI_LOMEM; 1629 res = SYS_RES_MEMORY; 1630 } else { 1631 rid = XL_PCI_LOIO; 1632 res = SYS_RES_IOPORT; 1633 } 1634 1635 /* These should only be active if attach succeeded */ 1636 if (device_is_attached(dev)) { 1637 XL_LOCK(sc); 1638 xl_reset(sc); 1639 xl_stop(sc); 1640 XL_UNLOCK(sc); 1641 taskqueue_drain(taskqueue_swi, &sc->xl_task); 1642 callout_drain(&sc->xl_stat_callout); 1643 ether_ifdetach(ifp); 1644 } 1645 if (sc->xl_miibus) 1646 device_delete_child(dev, sc->xl_miibus); 1647 bus_generic_detach(dev); 1648 ifmedia_removeall(&sc->ifmedia); 1649 1650 if (sc->xl_intrhand) 1651 bus_teardown_intr(dev, sc->xl_irq, sc->xl_intrhand); 1652 if (sc->xl_irq) 1653 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->xl_irq); 1654 if (sc->xl_fres != NULL) 1655 bus_release_resource(dev, SYS_RES_MEMORY, 1656 XL_PCI_FUNCMEM, sc->xl_fres); 1657 if (sc->xl_res) 1658 bus_release_resource(dev, res, rid, sc->xl_res); 1659 1660 if (ifp) 1661 if_free(ifp); 1662 1663 if (sc->xl_mtag) { 1664 bus_dmamap_destroy(sc->xl_mtag, sc->xl_tmpmap); 1665 bus_dma_tag_destroy(sc->xl_mtag); 1666 } 1667 if (sc->xl_ldata.xl_rx_tag) { 1668 bus_dmamap_unload(sc->xl_ldata.xl_rx_tag, 1669 sc->xl_ldata.xl_rx_dmamap); 1670 bus_dmamem_free(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_list, 1671 sc->xl_ldata.xl_rx_dmamap); 1672 bus_dma_tag_destroy(sc->xl_ldata.xl_rx_tag); 1673 } 1674 if (sc->xl_ldata.xl_tx_tag) { 1675 bus_dmamap_unload(sc->xl_ldata.xl_tx_tag, 1676 sc->xl_ldata.xl_tx_dmamap); 1677 bus_dmamem_free(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_list, 1678 sc->xl_ldata.xl_tx_dmamap); 1679 bus_dma_tag_destroy(sc->xl_ldata.xl_tx_tag); 1680 } 1681 1682 mtx_destroy(&sc->xl_mtx); 1683 1684 return (0); 1685 } 1686 1687 /* 1688 * Initialize the transmit descriptors. 1689 */ 1690 static int 1691 xl_list_tx_init(struct xl_softc *sc) 1692 { 1693 struct xl_chain_data *cd; 1694 struct xl_list_data *ld; 1695 int error, i; 1696 1697 XL_LOCK_ASSERT(sc); 1698 1699 cd = &sc->xl_cdata; 1700 ld = &sc->xl_ldata; 1701 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1702 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1703 error = bus_dmamap_create(sc->xl_mtag, 0, 1704 &cd->xl_tx_chain[i].xl_map); 1705 if (error) 1706 return (error); 1707 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1708 i * sizeof(struct xl_list); 1709 if (i == (XL_TX_LIST_CNT - 1)) 1710 cd->xl_tx_chain[i].xl_next = NULL; 1711 else 1712 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1713 } 1714 1715 cd->xl_tx_free = &cd->xl_tx_chain[0]; 1716 cd->xl_tx_tail = cd->xl_tx_head = NULL; 1717 1718 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1719 return (0); 1720 } 1721 1722 /* 1723 * Initialize the transmit descriptors. 1724 */ 1725 static int 1726 xl_list_tx_init_90xB(struct xl_softc *sc) 1727 { 1728 struct xl_chain_data *cd; 1729 struct xl_list_data *ld; 1730 int error, i; 1731 1732 XL_LOCK_ASSERT(sc); 1733 1734 cd = &sc->xl_cdata; 1735 ld = &sc->xl_ldata; 1736 for (i = 0; i < XL_TX_LIST_CNT; i++) { 1737 cd->xl_tx_chain[i].xl_ptr = &ld->xl_tx_list[i]; 1738 error = bus_dmamap_create(sc->xl_mtag, 0, 1739 &cd->xl_tx_chain[i].xl_map); 1740 if (error) 1741 return (error); 1742 cd->xl_tx_chain[i].xl_phys = ld->xl_tx_dmaaddr + 1743 i * sizeof(struct xl_list); 1744 if (i == (XL_TX_LIST_CNT - 1)) 1745 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[0]; 1746 else 1747 cd->xl_tx_chain[i].xl_next = &cd->xl_tx_chain[i + 1]; 1748 if (i == 0) 1749 cd->xl_tx_chain[i].xl_prev = 1750 &cd->xl_tx_chain[XL_TX_LIST_CNT - 1]; 1751 else 1752 cd->xl_tx_chain[i].xl_prev = 1753 &cd->xl_tx_chain[i - 1]; 1754 } 1755 1756 bzero(ld->xl_tx_list, XL_TX_LIST_SZ); 1757 ld->xl_tx_list[0].xl_status = htole32(XL_TXSTAT_EMPTY); 1758 1759 cd->xl_tx_prod = 1; 1760 cd->xl_tx_cons = 1; 1761 cd->xl_tx_cnt = 0; 1762 1763 bus_dmamap_sync(ld->xl_tx_tag, ld->xl_tx_dmamap, BUS_DMASYNC_PREWRITE); 1764 return (0); 1765 } 1766 1767 /* 1768 * Initialize the RX descriptors and allocate mbufs for them. Note that 1769 * we arrange the descriptors in a closed ring, so that the last descriptor 1770 * points back to the first. 1771 */ 1772 static int 1773 xl_list_rx_init(struct xl_softc *sc) 1774 { 1775 struct xl_chain_data *cd; 1776 struct xl_list_data *ld; 1777 int error, i, next; 1778 u_int32_t nextptr; 1779 1780 XL_LOCK_ASSERT(sc); 1781 1782 cd = &sc->xl_cdata; 1783 ld = &sc->xl_ldata; 1784 1785 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1786 cd->xl_rx_chain[i].xl_ptr = &ld->xl_rx_list[i]; 1787 error = bus_dmamap_create(sc->xl_mtag, 0, 1788 &cd->xl_rx_chain[i].xl_map); 1789 if (error) 1790 return (error); 1791 error = xl_newbuf(sc, &cd->xl_rx_chain[i]); 1792 if (error) 1793 return (error); 1794 if (i == (XL_RX_LIST_CNT - 1)) 1795 next = 0; 1796 else 1797 next = i + 1; 1798 nextptr = ld->xl_rx_dmaaddr + 1799 next * sizeof(struct xl_list_onefrag); 1800 cd->xl_rx_chain[i].xl_next = &cd->xl_rx_chain[next]; 1801 ld->xl_rx_list[i].xl_next = htole32(nextptr); 1802 } 1803 1804 bus_dmamap_sync(ld->xl_rx_tag, ld->xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1805 cd->xl_rx_head = &cd->xl_rx_chain[0]; 1806 1807 return (0); 1808 } 1809 1810 /* 1811 * Initialize an RX descriptor and attach an MBUF cluster. 1812 * If we fail to do so, we need to leave the old mbuf and 1813 * the old DMA map untouched so that it can be reused. 1814 */ 1815 static int 1816 xl_newbuf(struct xl_softc *sc, struct xl_chain_onefrag *c) 1817 { 1818 struct mbuf *m_new = NULL; 1819 bus_dmamap_t map; 1820 bus_dma_segment_t segs[1]; 1821 int error, nseg; 1822 1823 XL_LOCK_ASSERT(sc); 1824 1825 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1826 if (m_new == NULL) 1827 return (ENOBUFS); 1828 1829 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1830 1831 /* Force longword alignment for packet payload. */ 1832 m_adj(m_new, ETHER_ALIGN); 1833 1834 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, sc->xl_tmpmap, m_new, 1835 segs, &nseg, BUS_DMA_NOWAIT); 1836 if (error) { 1837 m_freem(m_new); 1838 device_printf(sc->xl_dev, "can't map mbuf (error %d)\n", 1839 error); 1840 return (error); 1841 } 1842 KASSERT(nseg == 1, 1843 ("%s: too many DMA segments (%d)", __func__, nseg)); 1844 1845 bus_dmamap_unload(sc->xl_mtag, c->xl_map); 1846 map = c->xl_map; 1847 c->xl_map = sc->xl_tmpmap; 1848 sc->xl_tmpmap = map; 1849 c->xl_mbuf = m_new; 1850 c->xl_ptr->xl_frag.xl_len = htole32(m_new->m_len | XL_LAST_FRAG); 1851 c->xl_ptr->xl_status = 0; 1852 c->xl_ptr->xl_frag.xl_addr = htole32(segs->ds_addr); 1853 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREREAD); 1854 return (0); 1855 } 1856 1857 static int 1858 xl_rx_resync(struct xl_softc *sc) 1859 { 1860 struct xl_chain_onefrag *pos; 1861 int i; 1862 1863 XL_LOCK_ASSERT(sc); 1864 1865 pos = sc->xl_cdata.xl_rx_head; 1866 1867 for (i = 0; i < XL_RX_LIST_CNT; i++) { 1868 if (pos->xl_ptr->xl_status) 1869 break; 1870 pos = pos->xl_next; 1871 } 1872 1873 if (i == XL_RX_LIST_CNT) 1874 return (0); 1875 1876 sc->xl_cdata.xl_rx_head = pos; 1877 1878 return (EAGAIN); 1879 } 1880 1881 /* 1882 * A frame has been uploaded: pass the resulting mbuf chain up to 1883 * the higher level protocols. 1884 */ 1885 static void 1886 xl_rxeof(struct xl_softc *sc) 1887 { 1888 struct mbuf *m; 1889 struct ifnet *ifp = sc->xl_ifp; 1890 struct xl_chain_onefrag *cur_rx; 1891 int total_len = 0; 1892 u_int32_t rxstat; 1893 1894 XL_LOCK_ASSERT(sc); 1895 again: 1896 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, sc->xl_ldata.xl_rx_dmamap, 1897 BUS_DMASYNC_POSTREAD); 1898 while ((rxstat = le32toh(sc->xl_cdata.xl_rx_head->xl_ptr->xl_status))) { 1899 #ifdef DEVICE_POLLING 1900 if (ifp->if_capenable & IFCAP_POLLING) { 1901 if (sc->rxcycles <= 0) 1902 break; 1903 sc->rxcycles--; 1904 } 1905 #endif 1906 cur_rx = sc->xl_cdata.xl_rx_head; 1907 sc->xl_cdata.xl_rx_head = cur_rx->xl_next; 1908 total_len = rxstat & XL_RXSTAT_LENMASK; 1909 1910 /* 1911 * Since we have told the chip to allow large frames, 1912 * we need to trap giant frame errors in software. We allow 1913 * a little more than the normal frame size to account for 1914 * frames with VLAN tags. 1915 */ 1916 if (total_len > XL_MAX_FRAMELEN) 1917 rxstat |= (XL_RXSTAT_UP_ERROR|XL_RXSTAT_OVERSIZE); 1918 1919 /* 1920 * If an error occurs, update stats, clear the 1921 * status word and leave the mbuf cluster in place: 1922 * it should simply get re-used next time this descriptor 1923 * comes up in the ring. 1924 */ 1925 if (rxstat & XL_RXSTAT_UP_ERROR) { 1926 ifp->if_ierrors++; 1927 cur_rx->xl_ptr->xl_status = 0; 1928 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1929 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1930 continue; 1931 } 1932 1933 /* 1934 * If the error bit was not set, the upload complete 1935 * bit should be set which means we have a valid packet. 1936 * If not, something truly strange has happened. 1937 */ 1938 if (!(rxstat & XL_RXSTAT_UP_CMPLT)) { 1939 device_printf(sc->xl_dev, 1940 "bad receive status -- packet dropped\n"); 1941 ifp->if_ierrors++; 1942 cur_rx->xl_ptr->xl_status = 0; 1943 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1944 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1945 continue; 1946 } 1947 1948 /* No errors; receive the packet. */ 1949 bus_dmamap_sync(sc->xl_mtag, cur_rx->xl_map, 1950 BUS_DMASYNC_POSTREAD); 1951 m = cur_rx->xl_mbuf; 1952 1953 /* 1954 * Try to conjure up a new mbuf cluster. If that 1955 * fails, it means we have an out of memory condition and 1956 * should leave the buffer in place and continue. This will 1957 * result in a lost packet, but there's little else we 1958 * can do in this situation. 1959 */ 1960 if (xl_newbuf(sc, cur_rx)) { 1961 ifp->if_ierrors++; 1962 cur_rx->xl_ptr->xl_status = 0; 1963 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1964 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1965 continue; 1966 } 1967 bus_dmamap_sync(sc->xl_ldata.xl_rx_tag, 1968 sc->xl_ldata.xl_rx_dmamap, BUS_DMASYNC_PREWRITE); 1969 1970 ifp->if_ipackets++; 1971 m->m_pkthdr.rcvif = ifp; 1972 m->m_pkthdr.len = m->m_len = total_len; 1973 1974 if (ifp->if_capenable & IFCAP_RXCSUM) { 1975 /* Do IP checksum checking. */ 1976 if (rxstat & XL_RXSTAT_IPCKOK) 1977 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1978 if (!(rxstat & XL_RXSTAT_IPCKERR)) 1979 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1980 if ((rxstat & XL_RXSTAT_TCPCOK && 1981 !(rxstat & XL_RXSTAT_TCPCKERR)) || 1982 (rxstat & XL_RXSTAT_UDPCKOK && 1983 !(rxstat & XL_RXSTAT_UDPCKERR))) { 1984 m->m_pkthdr.csum_flags |= 1985 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1986 m->m_pkthdr.csum_data = 0xffff; 1987 } 1988 } 1989 1990 XL_UNLOCK(sc); 1991 (*ifp->if_input)(ifp, m); 1992 XL_LOCK(sc); 1993 1994 /* 1995 * If we are running from the taskqueue, the interface 1996 * might have been stopped while we were passing the last 1997 * packet up the network stack. 1998 */ 1999 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 2000 return; 2001 } 2002 2003 /* 2004 * Handle the 'end of channel' condition. When the upload 2005 * engine hits the end of the RX ring, it will stall. This 2006 * is our cue to flush the RX ring, reload the uplist pointer 2007 * register and unstall the engine. 2008 * XXX This is actually a little goofy. With the ThunderLAN 2009 * chip, you get an interrupt when the receiver hits the end 2010 * of the receive ring, which tells you exactly when you 2011 * you need to reload the ring pointer. Here we have to 2012 * fake it. I'm mad at myself for not being clever enough 2013 * to avoid the use of a goto here. 2014 */ 2015 if (CSR_READ_4(sc, XL_UPLIST_PTR) == 0 || 2016 CSR_READ_4(sc, XL_UPLIST_STATUS) & XL_PKTSTAT_UP_STALLED) { 2017 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2018 xl_wait(sc); 2019 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2020 sc->xl_cdata.xl_rx_head = &sc->xl_cdata.xl_rx_chain[0]; 2021 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2022 goto again; 2023 } 2024 } 2025 2026 /* 2027 * Taskqueue wrapper for xl_rxeof(). 2028 */ 2029 static void 2030 xl_rxeof_task(void *arg, int pending) 2031 { 2032 struct xl_softc *sc = (struct xl_softc *)arg; 2033 2034 XL_LOCK(sc); 2035 if (sc->xl_ifp->if_drv_flags & IFF_DRV_RUNNING) 2036 xl_rxeof(sc); 2037 XL_UNLOCK(sc); 2038 } 2039 2040 /* 2041 * A frame was downloaded to the chip. It's safe for us to clean up 2042 * the list buffers. 2043 */ 2044 static void 2045 xl_txeof(struct xl_softc *sc) 2046 { 2047 struct xl_chain *cur_tx; 2048 struct ifnet *ifp = sc->xl_ifp; 2049 2050 XL_LOCK_ASSERT(sc); 2051 2052 /* 2053 * Go through our tx list and free mbufs for those 2054 * frames that have been uploaded. Note: the 3c905B 2055 * sets a special bit in the status word to let us 2056 * know that a frame has been downloaded, but the 2057 * original 3c900/3c905 adapters don't do that. 2058 * Consequently, we have to use a different test if 2059 * xl_type != XL_TYPE_905B. 2060 */ 2061 while (sc->xl_cdata.xl_tx_head != NULL) { 2062 cur_tx = sc->xl_cdata.xl_tx_head; 2063 2064 if (CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2065 break; 2066 2067 sc->xl_cdata.xl_tx_head = cur_tx->xl_next; 2068 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2069 BUS_DMASYNC_POSTWRITE); 2070 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2071 m_freem(cur_tx->xl_mbuf); 2072 cur_tx->xl_mbuf = NULL; 2073 ifp->if_opackets++; 2074 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2075 2076 cur_tx->xl_next = sc->xl_cdata.xl_tx_free; 2077 sc->xl_cdata.xl_tx_free = cur_tx; 2078 } 2079 2080 if (sc->xl_cdata.xl_tx_head == NULL) { 2081 sc->xl_wdog_timer = 0; 2082 sc->xl_cdata.xl_tx_tail = NULL; 2083 } else { 2084 if (CSR_READ_4(sc, XL_DMACTL) & XL_DMACTL_DOWN_STALLED || 2085 !CSR_READ_4(sc, XL_DOWNLIST_PTR)) { 2086 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2087 sc->xl_cdata.xl_tx_head->xl_phys); 2088 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2089 } 2090 } 2091 } 2092 2093 static void 2094 xl_txeof_90xB(struct xl_softc *sc) 2095 { 2096 struct xl_chain *cur_tx = NULL; 2097 struct ifnet *ifp = sc->xl_ifp; 2098 int idx; 2099 2100 XL_LOCK_ASSERT(sc); 2101 2102 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2103 BUS_DMASYNC_POSTREAD); 2104 idx = sc->xl_cdata.xl_tx_cons; 2105 while (idx != sc->xl_cdata.xl_tx_prod) { 2106 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2107 2108 if (!(le32toh(cur_tx->xl_ptr->xl_status) & 2109 XL_TXSTAT_DL_COMPLETE)) 2110 break; 2111 2112 if (cur_tx->xl_mbuf != NULL) { 2113 bus_dmamap_sync(sc->xl_mtag, cur_tx->xl_map, 2114 BUS_DMASYNC_POSTWRITE); 2115 bus_dmamap_unload(sc->xl_mtag, cur_tx->xl_map); 2116 m_freem(cur_tx->xl_mbuf); 2117 cur_tx->xl_mbuf = NULL; 2118 } 2119 2120 ifp->if_opackets++; 2121 2122 sc->xl_cdata.xl_tx_cnt--; 2123 XL_INC(idx, XL_TX_LIST_CNT); 2124 } 2125 2126 if (sc->xl_cdata.xl_tx_cnt == 0) 2127 sc->xl_wdog_timer = 0; 2128 sc->xl_cdata.xl_tx_cons = idx; 2129 2130 if (cur_tx != NULL) 2131 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2132 } 2133 2134 /* 2135 * TX 'end of channel' interrupt handler. Actually, we should 2136 * only get a 'TX complete' interrupt if there's a transmit error, 2137 * so this is really TX error handler. 2138 */ 2139 static void 2140 xl_txeoc(struct xl_softc *sc) 2141 { 2142 u_int8_t txstat; 2143 2144 XL_LOCK_ASSERT(sc); 2145 2146 while ((txstat = CSR_READ_1(sc, XL_TX_STATUS))) { 2147 if (txstat & XL_TXSTATUS_UNDERRUN || 2148 txstat & XL_TXSTATUS_JABBER || 2149 txstat & XL_TXSTATUS_RECLAIM) { 2150 device_printf(sc->xl_dev, 2151 "transmission error: %x\n", txstat); 2152 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2153 xl_wait(sc); 2154 if (sc->xl_type == XL_TYPE_905B) { 2155 if (sc->xl_cdata.xl_tx_cnt) { 2156 int i; 2157 struct xl_chain *c; 2158 2159 i = sc->xl_cdata.xl_tx_cons; 2160 c = &sc->xl_cdata.xl_tx_chain[i]; 2161 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2162 c->xl_phys); 2163 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2164 } 2165 } else { 2166 if (sc->xl_cdata.xl_tx_head != NULL) 2167 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2168 sc->xl_cdata.xl_tx_head->xl_phys); 2169 } 2170 /* 2171 * Remember to set this for the 2172 * first generation 3c90X chips. 2173 */ 2174 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2175 if (txstat & XL_TXSTATUS_UNDERRUN && 2176 sc->xl_tx_thresh < XL_PACKET_SIZE) { 2177 sc->xl_tx_thresh += XL_MIN_FRAMELEN; 2178 device_printf(sc->xl_dev, 2179 "tx underrun, increasing tx start threshold to %d bytes\n", sc->xl_tx_thresh); 2180 } 2181 CSR_WRITE_2(sc, XL_COMMAND, 2182 XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2183 if (sc->xl_type == XL_TYPE_905B) { 2184 CSR_WRITE_2(sc, XL_COMMAND, 2185 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2186 } 2187 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2188 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2189 } else { 2190 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2191 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2192 } 2193 /* 2194 * Write an arbitrary byte to the TX_STATUS register 2195 * to clear this interrupt/error and advance to the next. 2196 */ 2197 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); 2198 } 2199 } 2200 2201 static void 2202 xl_intr(void *arg) 2203 { 2204 struct xl_softc *sc = arg; 2205 struct ifnet *ifp = sc->xl_ifp; 2206 u_int16_t status; 2207 2208 XL_LOCK(sc); 2209 2210 #ifdef DEVICE_POLLING 2211 if (ifp->if_capenable & IFCAP_POLLING) { 2212 XL_UNLOCK(sc); 2213 return; 2214 } 2215 #endif 2216 2217 while ((status = CSR_READ_2(sc, XL_STATUS)) & XL_INTRS && 2218 status != 0xFFFF) { 2219 CSR_WRITE_2(sc, XL_COMMAND, 2220 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2221 2222 if (status & XL_STAT_UP_COMPLETE) { 2223 int curpkts; 2224 2225 curpkts = ifp->if_ipackets; 2226 xl_rxeof(sc); 2227 if (curpkts == ifp->if_ipackets) { 2228 while (xl_rx_resync(sc)) 2229 xl_rxeof(sc); 2230 } 2231 } 2232 2233 if (status & XL_STAT_DOWN_COMPLETE) { 2234 if (sc->xl_type == XL_TYPE_905B) 2235 xl_txeof_90xB(sc); 2236 else 2237 xl_txeof(sc); 2238 } 2239 2240 if (status & XL_STAT_TX_COMPLETE) { 2241 ifp->if_oerrors++; 2242 xl_txeoc(sc); 2243 } 2244 2245 if (status & XL_STAT_ADFAIL) { 2246 xl_reset(sc); 2247 xl_init_locked(sc); 2248 } 2249 2250 if (status & XL_STAT_STATSOFLOW) { 2251 sc->xl_stats_no_timeout = 1; 2252 xl_stats_update_locked(sc); 2253 sc->xl_stats_no_timeout = 0; 2254 } 2255 } 2256 2257 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2258 if (sc->xl_type == XL_TYPE_905B) 2259 xl_start_90xB_locked(ifp); 2260 else 2261 xl_start_locked(ifp); 2262 } 2263 2264 XL_UNLOCK(sc); 2265 } 2266 2267 #ifdef DEVICE_POLLING 2268 static void 2269 xl_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2270 { 2271 struct xl_softc *sc = ifp->if_softc; 2272 2273 XL_LOCK(sc); 2274 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2275 xl_poll_locked(ifp, cmd, count); 2276 XL_UNLOCK(sc); 2277 } 2278 2279 static void 2280 xl_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2281 { 2282 struct xl_softc *sc = ifp->if_softc; 2283 2284 XL_LOCK_ASSERT(sc); 2285 2286 sc->rxcycles = count; 2287 xl_rxeof(sc); 2288 if (sc->xl_type == XL_TYPE_905B) 2289 xl_txeof_90xB(sc); 2290 else 2291 xl_txeof(sc); 2292 2293 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2294 if (sc->xl_type == XL_TYPE_905B) 2295 xl_start_90xB_locked(ifp); 2296 else 2297 xl_start_locked(ifp); 2298 } 2299 2300 if (cmd == POLL_AND_CHECK_STATUS) { 2301 u_int16_t status; 2302 2303 status = CSR_READ_2(sc, XL_STATUS); 2304 if (status & XL_INTRS && status != 0xFFFF) { 2305 CSR_WRITE_2(sc, XL_COMMAND, 2306 XL_CMD_INTR_ACK|(status & XL_INTRS)); 2307 2308 if (status & XL_STAT_TX_COMPLETE) { 2309 ifp->if_oerrors++; 2310 xl_txeoc(sc); 2311 } 2312 2313 if (status & XL_STAT_ADFAIL) { 2314 xl_reset(sc); 2315 xl_init_locked(sc); 2316 } 2317 2318 if (status & XL_STAT_STATSOFLOW) { 2319 sc->xl_stats_no_timeout = 1; 2320 xl_stats_update_locked(sc); 2321 sc->xl_stats_no_timeout = 0; 2322 } 2323 } 2324 } 2325 } 2326 #endif /* DEVICE_POLLING */ 2327 2328 /* 2329 * XXX: This is an entry point for callout which needs to take the lock. 2330 */ 2331 static void 2332 xl_stats_update(void *xsc) 2333 { 2334 struct xl_softc *sc = xsc; 2335 2336 XL_LOCK_ASSERT(sc); 2337 2338 if (xl_watchdog(sc) == EJUSTRETURN) 2339 return; 2340 2341 xl_stats_update_locked(sc); 2342 } 2343 2344 static void 2345 xl_stats_update_locked(struct xl_softc *sc) 2346 { 2347 struct ifnet *ifp = sc->xl_ifp; 2348 struct xl_stats xl_stats; 2349 u_int8_t *p; 2350 int i; 2351 struct mii_data *mii = NULL; 2352 2353 XL_LOCK_ASSERT(sc); 2354 2355 bzero((char *)&xl_stats, sizeof(struct xl_stats)); 2356 2357 if (sc->xl_miibus != NULL) 2358 mii = device_get_softc(sc->xl_miibus); 2359 2360 p = (u_int8_t *)&xl_stats; 2361 2362 /* Read all the stats registers. */ 2363 XL_SEL_WIN(6); 2364 2365 for (i = 0; i < 16; i++) 2366 *p++ = CSR_READ_1(sc, XL_W6_CARRIER_LOST + i); 2367 2368 ifp->if_ierrors += xl_stats.xl_rx_overrun; 2369 2370 ifp->if_collisions += xl_stats.xl_tx_multi_collision + 2371 xl_stats.xl_tx_single_collision + xl_stats.xl_tx_late_collision; 2372 2373 /* 2374 * Boomerang and cyclone chips have an extra stats counter 2375 * in window 4 (BadSSD). We have to read this too in order 2376 * to clear out all the stats registers and avoid a statsoflow 2377 * interrupt. 2378 */ 2379 XL_SEL_WIN(4); 2380 CSR_READ_1(sc, XL_W4_BADSSD); 2381 2382 if ((mii != NULL) && (!sc->xl_stats_no_timeout)) 2383 mii_tick(mii); 2384 2385 XL_SEL_WIN(7); 2386 2387 if (!sc->xl_stats_no_timeout) 2388 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2389 } 2390 2391 /* 2392 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 2393 * pointers to the fragment pointers. 2394 */ 2395 static int 2396 xl_encap(struct xl_softc *sc, struct xl_chain *c, struct mbuf **m_head) 2397 { 2398 struct mbuf *m_new; 2399 struct ifnet *ifp = sc->xl_ifp; 2400 int error, i, nseg, total_len; 2401 u_int32_t status; 2402 2403 XL_LOCK_ASSERT(sc); 2404 2405 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, *m_head, 2406 sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2407 2408 if (error && error != EFBIG) { 2409 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2410 return (error); 2411 } 2412 2413 /* 2414 * Handle special case: we used up all 63 fragments, 2415 * but we have more mbufs left in the chain. Copy the 2416 * data into an mbuf cluster. Note that we don't 2417 * bother clearing the values in the other fragment 2418 * pointers/counters; it wouldn't gain us anything, 2419 * and would waste cycles. 2420 */ 2421 if (error) { 2422 m_new = m_collapse(*m_head, M_DONTWAIT, XL_MAXFRAGS); 2423 if (m_new == NULL) { 2424 m_freem(*m_head); 2425 *m_head = NULL; 2426 return (ENOBUFS); 2427 } 2428 *m_head = m_new; 2429 2430 error = bus_dmamap_load_mbuf_sg(sc->xl_mtag, c->xl_map, 2431 *m_head, sc->xl_cdata.xl_tx_segs, &nseg, BUS_DMA_NOWAIT); 2432 if (error) { 2433 m_freem(*m_head); 2434 *m_head = NULL; 2435 if_printf(ifp, "can't map mbuf (error %d)\n", error); 2436 return (error); 2437 } 2438 } 2439 2440 KASSERT(nseg <= XL_MAXFRAGS, 2441 ("%s: too many DMA segments (%d)", __func__, nseg)); 2442 if (nseg == 0) { 2443 m_freem(*m_head); 2444 *m_head = NULL; 2445 return (EIO); 2446 } 2447 2448 total_len = 0; 2449 for (i = 0; i < nseg; i++) { 2450 KASSERT(sc->xl_cdata.xl_tx_segs[i].ds_len <= MCLBYTES, 2451 ("segment size too large")); 2452 c->xl_ptr->xl_frag[i].xl_addr = 2453 htole32(sc->xl_cdata.xl_tx_segs[i].ds_addr); 2454 c->xl_ptr->xl_frag[i].xl_len = 2455 htole32(sc->xl_cdata.xl_tx_segs[i].ds_len); 2456 total_len += sc->xl_cdata.xl_tx_segs[i].ds_len; 2457 } 2458 c->xl_ptr->xl_frag[nseg - 1].xl_len = 2459 htole32(sc->xl_cdata.xl_tx_segs[nseg - 1].ds_len | XL_LAST_FRAG); 2460 c->xl_ptr->xl_status = htole32(total_len); 2461 c->xl_ptr->xl_next = 0; 2462 2463 if (sc->xl_type == XL_TYPE_905B) { 2464 status = XL_TXSTAT_RND_DEFEAT; 2465 2466 #ifndef XL905B_TXCSUM_BROKEN 2467 if (m_head->m_pkthdr.csum_flags) { 2468 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2469 status |= XL_TXSTAT_IPCKSUM; 2470 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 2471 status |= XL_TXSTAT_TCPCKSUM; 2472 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 2473 status |= XL_TXSTAT_UDPCKSUM; 2474 } 2475 #endif 2476 c->xl_ptr->xl_status = htole32(status); 2477 } 2478 2479 c->xl_mbuf = *m_head; 2480 bus_dmamap_sync(sc->xl_mtag, c->xl_map, BUS_DMASYNC_PREWRITE); 2481 return (0); 2482 } 2483 2484 /* 2485 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2486 * to the mbuf data regions directly in the transmit lists. We also save a 2487 * copy of the pointers since the transmit list fragment pointers are 2488 * physical addresses. 2489 */ 2490 2491 static void 2492 xl_start(struct ifnet *ifp) 2493 { 2494 struct xl_softc *sc = ifp->if_softc; 2495 2496 XL_LOCK(sc); 2497 2498 if (sc->xl_type == XL_TYPE_905B) 2499 xl_start_90xB_locked(ifp); 2500 else 2501 xl_start_locked(ifp); 2502 2503 XL_UNLOCK(sc); 2504 } 2505 2506 static void 2507 xl_start_locked(struct ifnet *ifp) 2508 { 2509 struct xl_softc *sc = ifp->if_softc; 2510 struct mbuf *m_head = NULL; 2511 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2512 u_int32_t status; 2513 int error; 2514 2515 XL_LOCK_ASSERT(sc); 2516 2517 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2518 IFF_DRV_RUNNING) 2519 return; 2520 /* 2521 * Check for an available queue slot. If there are none, 2522 * punt. 2523 */ 2524 if (sc->xl_cdata.xl_tx_free == NULL) { 2525 xl_txeoc(sc); 2526 xl_txeof(sc); 2527 if (sc->xl_cdata.xl_tx_free == NULL) { 2528 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2529 return; 2530 } 2531 } 2532 2533 start_tx = sc->xl_cdata.xl_tx_free; 2534 2535 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2536 sc->xl_cdata.xl_tx_free != NULL;) { 2537 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2538 if (m_head == NULL) 2539 break; 2540 2541 /* Pick a descriptor off the free list. */ 2542 cur_tx = sc->xl_cdata.xl_tx_free; 2543 2544 /* Pack the data into the descriptor. */ 2545 error = xl_encap(sc, cur_tx, &m_head); 2546 if (error) { 2547 if (m_head == NULL) 2548 break; 2549 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2550 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2551 break; 2552 } 2553 2554 sc->xl_cdata.xl_tx_free = cur_tx->xl_next; 2555 cur_tx->xl_next = NULL; 2556 2557 /* Chain it together. */ 2558 if (prev != NULL) { 2559 prev->xl_next = cur_tx; 2560 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2561 } 2562 prev = cur_tx; 2563 2564 /* 2565 * If there's a BPF listener, bounce a copy of this frame 2566 * to him. 2567 */ 2568 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2569 } 2570 2571 /* 2572 * If there are no packets queued, bail. 2573 */ 2574 if (cur_tx == NULL) 2575 return; 2576 2577 /* 2578 * Place the request for the upload interrupt 2579 * in the last descriptor in the chain. This way, if 2580 * we're chaining several packets at once, we'll only 2581 * get an interrupt once for the whole chain rather than 2582 * once for each packet. 2583 */ 2584 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2585 XL_TXSTAT_DL_INTR); 2586 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2587 BUS_DMASYNC_PREWRITE); 2588 2589 /* 2590 * Queue the packets. If the TX channel is clear, update 2591 * the downlist pointer register. 2592 */ 2593 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2594 xl_wait(sc); 2595 2596 if (sc->xl_cdata.xl_tx_head != NULL) { 2597 sc->xl_cdata.xl_tx_tail->xl_next = start_tx; 2598 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_next = 2599 htole32(start_tx->xl_phys); 2600 status = sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status; 2601 sc->xl_cdata.xl_tx_tail->xl_ptr->xl_status = 2602 htole32(le32toh(status) & ~XL_TXSTAT_DL_INTR); 2603 sc->xl_cdata.xl_tx_tail = cur_tx; 2604 } else { 2605 sc->xl_cdata.xl_tx_head = start_tx; 2606 sc->xl_cdata.xl_tx_tail = cur_tx; 2607 } 2608 if (!CSR_READ_4(sc, XL_DOWNLIST_PTR)) 2609 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, start_tx->xl_phys); 2610 2611 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2612 2613 XL_SEL_WIN(7); 2614 2615 /* 2616 * Set a timeout in case the chip goes out to lunch. 2617 */ 2618 sc->xl_wdog_timer = 5; 2619 2620 /* 2621 * XXX Under certain conditions, usually on slower machines 2622 * where interrupts may be dropped, it's possible for the 2623 * adapter to chew up all the buffers in the receive ring 2624 * and stall, without us being able to do anything about it. 2625 * To guard against this, we need to make a pass over the 2626 * RX queue to make sure there aren't any packets pending. 2627 * Doing it here means we can flush the receive ring at the 2628 * same time the chip is DMAing the transmit descriptors we 2629 * just gave it. 2630 * 2631 * 3Com goes to some lengths to emphasize the Parallel Tasking (tm) 2632 * nature of their chips in all their marketing literature; 2633 * we may as well take advantage of it. :) 2634 */ 2635 taskqueue_enqueue(taskqueue_swi, &sc->xl_task); 2636 } 2637 2638 static void 2639 xl_start_90xB_locked(struct ifnet *ifp) 2640 { 2641 struct xl_softc *sc = ifp->if_softc; 2642 struct mbuf *m_head = NULL; 2643 struct xl_chain *prev = NULL, *cur_tx = NULL, *start_tx; 2644 int error, idx; 2645 2646 XL_LOCK_ASSERT(sc); 2647 2648 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2649 IFF_DRV_RUNNING) 2650 return; 2651 2652 idx = sc->xl_cdata.xl_tx_prod; 2653 start_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2654 2655 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2656 sc->xl_cdata.xl_tx_chain[idx].xl_mbuf == NULL;) { 2657 if ((XL_TX_LIST_CNT - sc->xl_cdata.xl_tx_cnt) < 3) { 2658 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2659 break; 2660 } 2661 2662 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2663 if (m_head == NULL) 2664 break; 2665 2666 cur_tx = &sc->xl_cdata.xl_tx_chain[idx]; 2667 2668 /* Pack the data into the descriptor. */ 2669 error = xl_encap(sc, cur_tx, &m_head); 2670 if (error) { 2671 if (m_head == NULL) 2672 break; 2673 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2674 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2675 break; 2676 } 2677 2678 /* Chain it together. */ 2679 if (prev != NULL) 2680 prev->xl_ptr->xl_next = htole32(cur_tx->xl_phys); 2681 prev = cur_tx; 2682 2683 /* 2684 * If there's a BPF listener, bounce a copy of this frame 2685 * to him. 2686 */ 2687 BPF_MTAP(ifp, cur_tx->xl_mbuf); 2688 2689 XL_INC(idx, XL_TX_LIST_CNT); 2690 sc->xl_cdata.xl_tx_cnt++; 2691 } 2692 2693 /* 2694 * If there are no packets queued, bail. 2695 */ 2696 if (cur_tx == NULL) 2697 return; 2698 2699 /* 2700 * Place the request for the upload interrupt 2701 * in the last descriptor in the chain. This way, if 2702 * we're chaining several packets at once, we'll only 2703 * get an interrupt once for the whole chain rather than 2704 * once for each packet. 2705 */ 2706 cur_tx->xl_ptr->xl_status = htole32(le32toh(cur_tx->xl_ptr->xl_status) | 2707 XL_TXSTAT_DL_INTR); 2708 bus_dmamap_sync(sc->xl_ldata.xl_tx_tag, sc->xl_ldata.xl_tx_dmamap, 2709 BUS_DMASYNC_PREWRITE); 2710 2711 /* Start transmission */ 2712 sc->xl_cdata.xl_tx_prod = idx; 2713 start_tx->xl_prev->xl_ptr->xl_next = htole32(start_tx->xl_phys); 2714 2715 /* 2716 * Set a timeout in case the chip goes out to lunch. 2717 */ 2718 sc->xl_wdog_timer = 5; 2719 } 2720 2721 static void 2722 xl_init(void *xsc) 2723 { 2724 struct xl_softc *sc = xsc; 2725 2726 XL_LOCK(sc); 2727 xl_init_locked(sc); 2728 XL_UNLOCK(sc); 2729 } 2730 2731 static void 2732 xl_init_locked(struct xl_softc *sc) 2733 { 2734 struct ifnet *ifp = sc->xl_ifp; 2735 int error, i; 2736 u_int16_t rxfilt = 0; 2737 struct mii_data *mii = NULL; 2738 2739 XL_LOCK_ASSERT(sc); 2740 2741 /* 2742 * Cancel pending I/O and free all RX/TX buffers. 2743 */ 2744 xl_stop(sc); 2745 2746 if (sc->xl_miibus == NULL) { 2747 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2748 xl_wait(sc); 2749 } 2750 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2751 xl_wait(sc); 2752 DELAY(10000); 2753 2754 if (sc->xl_miibus != NULL) 2755 mii = device_get_softc(sc->xl_miibus); 2756 2757 /* Init our MAC address */ 2758 XL_SEL_WIN(2); 2759 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2760 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, 2761 IF_LLADDR(sc->xl_ifp)[i]); 2762 } 2763 2764 /* Clear the station mask. */ 2765 for (i = 0; i < 3; i++) 2766 CSR_WRITE_2(sc, XL_W2_STATION_MASK_LO + (i * 2), 0); 2767 #ifdef notdef 2768 /* Reset TX and RX. */ 2769 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 2770 xl_wait(sc); 2771 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 2772 xl_wait(sc); 2773 #endif 2774 /* Init circular RX list. */ 2775 error = xl_list_rx_init(sc); 2776 if (error) { 2777 device_printf(sc->xl_dev, "initialization of the rx ring failed (%d)\n", 2778 error); 2779 xl_stop(sc); 2780 return; 2781 } 2782 2783 /* Init TX descriptors. */ 2784 if (sc->xl_type == XL_TYPE_905B) 2785 error = xl_list_tx_init_90xB(sc); 2786 else 2787 error = xl_list_tx_init(sc); 2788 if (error) { 2789 device_printf(sc->xl_dev, "initialization of the tx ring failed (%d)\n", 2790 error); 2791 xl_stop(sc); 2792 return; 2793 } 2794 2795 /* 2796 * Set the TX freethresh value. 2797 * Note that this has no effect on 3c905B "cyclone" 2798 * cards but is required for 3c900/3c905 "boomerang" 2799 * cards in order to enable the download engine. 2800 */ 2801 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); 2802 2803 /* Set the TX start threshold for best performance. */ 2804 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_SET_START|sc->xl_tx_thresh); 2805 2806 /* 2807 * If this is a 3c905B, also set the tx reclaim threshold. 2808 * This helps cut down on the number of tx reclaim errors 2809 * that could happen on a busy network. The chip multiplies 2810 * the register value by 16 to obtain the actual threshold 2811 * in bytes, so we divide by 16 when setting the value here. 2812 * The existing threshold value can be examined by reading 2813 * the register at offset 9 in window 5. 2814 */ 2815 if (sc->xl_type == XL_TYPE_905B) { 2816 CSR_WRITE_2(sc, XL_COMMAND, 2817 XL_CMD_SET_TX_RECLAIM|(XL_PACKET_SIZE >> 4)); 2818 } 2819 2820 /* Set RX filter bits. */ 2821 XL_SEL_WIN(5); 2822 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 2823 2824 /* Set the individual bit to receive frames for this host only. */ 2825 rxfilt |= XL_RXFILTER_INDIVIDUAL; 2826 2827 /* If we want promiscuous mode, set the allframes bit. */ 2828 if (ifp->if_flags & IFF_PROMISC) { 2829 rxfilt |= XL_RXFILTER_ALLFRAMES; 2830 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2831 } else { 2832 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 2833 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2834 } 2835 2836 /* 2837 * Set capture broadcast bit to capture broadcast frames. 2838 */ 2839 if (ifp->if_flags & IFF_BROADCAST) { 2840 rxfilt |= XL_RXFILTER_BROADCAST; 2841 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2842 } else { 2843 rxfilt &= ~XL_RXFILTER_BROADCAST; 2844 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_FILT|rxfilt); 2845 } 2846 2847 /* 2848 * Program the multicast filter, if necessary. 2849 */ 2850 if (sc->xl_type == XL_TYPE_905B) 2851 xl_setmulti_hash(sc); 2852 else 2853 xl_setmulti(sc); 2854 2855 /* 2856 * Load the address of the RX list. We have to 2857 * stall the upload engine before we can manipulate 2858 * the uplist pointer register, then unstall it when 2859 * we're finished. We also have to wait for the 2860 * stall command to complete before proceeding. 2861 * Note that we have to do this after any RX resets 2862 * have completed since the uplist register is cleared 2863 * by a reset. 2864 */ 2865 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_STALL); 2866 xl_wait(sc); 2867 CSR_WRITE_4(sc, XL_UPLIST_PTR, sc->xl_ldata.xl_rx_dmaaddr); 2868 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_UP_UNSTALL); 2869 xl_wait(sc); 2870 2871 if (sc->xl_type == XL_TYPE_905B) { 2872 /* Set polling interval */ 2873 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); 2874 /* Load the address of the TX list */ 2875 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_STALL); 2876 xl_wait(sc); 2877 CSR_WRITE_4(sc, XL_DOWNLIST_PTR, 2878 sc->xl_cdata.xl_tx_chain[0].xl_phys); 2879 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_DOWN_UNSTALL); 2880 xl_wait(sc); 2881 } 2882 2883 /* 2884 * If the coax transceiver is on, make sure to enable 2885 * the DC-DC converter. 2886 */ 2887 XL_SEL_WIN(3); 2888 if (sc->xl_xcvr == XL_XCVR_COAX) 2889 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); 2890 else 2891 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 2892 2893 /* 2894 * increase packet size to allow reception of 802.1q or ISL packets. 2895 * For the 3c90x chip, set the 'allow large packets' bit in the MAC 2896 * control register. For 3c90xB/C chips, use the RX packet size 2897 * register. 2898 */ 2899 2900 if (sc->xl_type == XL_TYPE_905B) 2901 CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE); 2902 else { 2903 u_int8_t macctl; 2904 macctl = CSR_READ_1(sc, XL_W3_MAC_CTRL); 2905 macctl |= XL_MACCTRL_ALLOW_LARGE_PACK; 2906 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); 2907 } 2908 2909 /* Clear out the stats counters. */ 2910 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 2911 sc->xl_stats_no_timeout = 1; 2912 xl_stats_update_locked(sc); 2913 sc->xl_stats_no_timeout = 0; 2914 XL_SEL_WIN(4); 2915 CSR_WRITE_2(sc, XL_W4_NET_DIAG, XL_NETDIAG_UPPER_BYTES_ENABLE); 2916 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_ENABLE); 2917 2918 /* 2919 * Enable interrupts. 2920 */ 2921 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 2922 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|XL_INTRS); 2923 #ifdef DEVICE_POLLING 2924 /* Disable interrupts if we are polling. */ 2925 if (ifp->if_capenable & IFCAP_POLLING) 2926 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 2927 else 2928 #endif 2929 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 2930 if (sc->xl_flags & XL_FLAG_FUNCREG) 2931 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 2932 2933 /* Set the RX early threshold */ 2934 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_THRESH|(XL_PACKET_SIZE >>2)); 2935 CSR_WRITE_2(sc, XL_DMACTL, XL_DMACTL_UP_RX_EARLY); 2936 2937 /* Enable receiver and transmitter. */ 2938 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_ENABLE); 2939 xl_wait(sc); 2940 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_ENABLE); 2941 xl_wait(sc); 2942 2943 /* XXX Downcall to miibus. */ 2944 if (mii != NULL) 2945 mii_mediachg(mii); 2946 2947 /* Select window 7 for normal operations. */ 2948 XL_SEL_WIN(7); 2949 2950 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2951 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2952 2953 sc->xl_wdog_timer = 0; 2954 callout_reset(&sc->xl_stat_callout, hz, xl_stats_update, sc); 2955 } 2956 2957 /* 2958 * Set media options. 2959 */ 2960 static int 2961 xl_ifmedia_upd(struct ifnet *ifp) 2962 { 2963 struct xl_softc *sc = ifp->if_softc; 2964 struct ifmedia *ifm = NULL; 2965 struct mii_data *mii = NULL; 2966 2967 XL_LOCK(sc); 2968 2969 if (sc->xl_miibus != NULL) 2970 mii = device_get_softc(sc->xl_miibus); 2971 if (mii == NULL) 2972 ifm = &sc->ifmedia; 2973 else 2974 ifm = &mii->mii_media; 2975 2976 switch (IFM_SUBTYPE(ifm->ifm_media)) { 2977 case IFM_100_FX: 2978 case IFM_10_FL: 2979 case IFM_10_2: 2980 case IFM_10_5: 2981 xl_setmode(sc, ifm->ifm_media); 2982 XL_UNLOCK(sc); 2983 return (0); 2984 } 2985 2986 if (sc->xl_media & XL_MEDIAOPT_MII || 2987 sc->xl_media & XL_MEDIAOPT_BTX || 2988 sc->xl_media & XL_MEDIAOPT_BT4) { 2989 xl_init_locked(sc); 2990 } else { 2991 xl_setmode(sc, ifm->ifm_media); 2992 } 2993 2994 XL_UNLOCK(sc); 2995 2996 return (0); 2997 } 2998 2999 /* 3000 * Report current media status. 3001 */ 3002 static void 3003 xl_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3004 { 3005 struct xl_softc *sc = ifp->if_softc; 3006 u_int32_t icfg; 3007 u_int16_t status = 0; 3008 struct mii_data *mii = NULL; 3009 3010 XL_LOCK(sc); 3011 3012 if (sc->xl_miibus != NULL) 3013 mii = device_get_softc(sc->xl_miibus); 3014 3015 XL_SEL_WIN(4); 3016 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3017 3018 XL_SEL_WIN(3); 3019 icfg = CSR_READ_4(sc, XL_W3_INTERNAL_CFG) & XL_ICFG_CONNECTOR_MASK; 3020 icfg >>= XL_ICFG_CONNECTOR_BITS; 3021 3022 ifmr->ifm_active = IFM_ETHER; 3023 ifmr->ifm_status = IFM_AVALID; 3024 3025 if ((status & XL_MEDIASTAT_CARRIER) == 0) 3026 ifmr->ifm_status |= IFM_ACTIVE; 3027 3028 switch (icfg) { 3029 case XL_XCVR_10BT: 3030 ifmr->ifm_active = IFM_ETHER|IFM_10_T; 3031 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3032 ifmr->ifm_active |= IFM_FDX; 3033 else 3034 ifmr->ifm_active |= IFM_HDX; 3035 break; 3036 case XL_XCVR_AUI: 3037 if (sc->xl_type == XL_TYPE_905B && 3038 sc->xl_media == XL_MEDIAOPT_10FL) { 3039 ifmr->ifm_active = IFM_ETHER|IFM_10_FL; 3040 if (CSR_READ_1(sc, XL_W3_MAC_CTRL) & XL_MACCTRL_DUPLEX) 3041 ifmr->ifm_active |= IFM_FDX; 3042 else 3043 ifmr->ifm_active |= IFM_HDX; 3044 } else 3045 ifmr->ifm_active = IFM_ETHER|IFM_10_5; 3046 break; 3047 case XL_XCVR_COAX: 3048 ifmr->ifm_active = IFM_ETHER|IFM_10_2; 3049 break; 3050 /* 3051 * XXX MII and BTX/AUTO should be separate cases. 3052 */ 3053 3054 case XL_XCVR_100BTX: 3055 case XL_XCVR_AUTO: 3056 case XL_XCVR_MII: 3057 if (mii != NULL) { 3058 mii_pollstat(mii); 3059 ifmr->ifm_active = mii->mii_media_active; 3060 ifmr->ifm_status = mii->mii_media_status; 3061 } 3062 break; 3063 case XL_XCVR_100BFX: 3064 ifmr->ifm_active = IFM_ETHER|IFM_100_FX; 3065 break; 3066 default: 3067 if_printf(ifp, "unknown XCVR type: %d\n", icfg); 3068 break; 3069 } 3070 3071 XL_UNLOCK(sc); 3072 } 3073 3074 static int 3075 xl_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3076 { 3077 struct xl_softc *sc = ifp->if_softc; 3078 struct ifreq *ifr = (struct ifreq *) data; 3079 int error = 0; 3080 struct mii_data *mii = NULL; 3081 u_int8_t rxfilt; 3082 3083 switch (command) { 3084 case SIOCSIFFLAGS: 3085 XL_LOCK(sc); 3086 3087 XL_SEL_WIN(5); 3088 rxfilt = CSR_READ_1(sc, XL_W5_RX_FILTER); 3089 if (ifp->if_flags & IFF_UP) { 3090 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3091 ifp->if_flags & IFF_PROMISC && 3092 !(sc->xl_if_flags & IFF_PROMISC)) { 3093 rxfilt |= XL_RXFILTER_ALLFRAMES; 3094 CSR_WRITE_2(sc, XL_COMMAND, 3095 XL_CMD_RX_SET_FILT|rxfilt); 3096 XL_SEL_WIN(7); 3097 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3098 !(ifp->if_flags & IFF_PROMISC) && 3099 sc->xl_if_flags & IFF_PROMISC) { 3100 rxfilt &= ~XL_RXFILTER_ALLFRAMES; 3101 CSR_WRITE_2(sc, XL_COMMAND, 3102 XL_CMD_RX_SET_FILT|rxfilt); 3103 XL_SEL_WIN(7); 3104 } else { 3105 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3106 xl_init_locked(sc); 3107 } 3108 } else { 3109 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3110 xl_stop(sc); 3111 } 3112 sc->xl_if_flags = ifp->if_flags; 3113 XL_UNLOCK(sc); 3114 error = 0; 3115 break; 3116 case SIOCADDMULTI: 3117 case SIOCDELMULTI: 3118 /* XXX Downcall from if_addmulti() possibly with locks held. */ 3119 XL_LOCK(sc); 3120 if (sc->xl_type == XL_TYPE_905B) 3121 xl_setmulti_hash(sc); 3122 else 3123 xl_setmulti(sc); 3124 XL_UNLOCK(sc); 3125 error = 0; 3126 break; 3127 case SIOCGIFMEDIA: 3128 case SIOCSIFMEDIA: 3129 if (sc->xl_miibus != NULL) 3130 mii = device_get_softc(sc->xl_miibus); 3131 if (mii == NULL) 3132 error = ifmedia_ioctl(ifp, ifr, 3133 &sc->ifmedia, command); 3134 else 3135 error = ifmedia_ioctl(ifp, ifr, 3136 &mii->mii_media, command); 3137 break; 3138 case SIOCSIFCAP: 3139 #ifdef DEVICE_POLLING 3140 if (ifr->ifr_reqcap & IFCAP_POLLING && 3141 !(ifp->if_capenable & IFCAP_POLLING)) { 3142 error = ether_poll_register(xl_poll, ifp); 3143 if (error) 3144 return(error); 3145 XL_LOCK(sc); 3146 /* Disable interrupts */ 3147 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3148 ifp->if_capenable |= IFCAP_POLLING; 3149 XL_UNLOCK(sc); 3150 return (error); 3151 } 3152 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 3153 ifp->if_capenable & IFCAP_POLLING) { 3154 error = ether_poll_deregister(ifp); 3155 /* Enable interrupts. */ 3156 XL_LOCK(sc); 3157 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|0xFF); 3158 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|XL_INTRS); 3159 if (sc->xl_flags & XL_FLAG_FUNCREG) 3160 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 3161 4, 0x8000); 3162 ifp->if_capenable &= ~IFCAP_POLLING; 3163 XL_UNLOCK(sc); 3164 return (error); 3165 } 3166 #endif /* DEVICE_POLLING */ 3167 XL_LOCK(sc); 3168 ifp->if_capenable = ifr->ifr_reqcap; 3169 if (ifp->if_capenable & IFCAP_TXCSUM) 3170 ifp->if_hwassist = XL905B_CSUM_FEATURES; 3171 else 3172 ifp->if_hwassist = 0; 3173 XL_UNLOCK(sc); 3174 break; 3175 default: 3176 error = ether_ioctl(ifp, command, data); 3177 break; 3178 } 3179 3180 return (error); 3181 } 3182 3183 static int 3184 xl_watchdog(struct xl_softc *sc) 3185 { 3186 struct ifnet *ifp = sc->xl_ifp; 3187 u_int16_t status = 0; 3188 int misintr; 3189 3190 XL_LOCK_ASSERT(sc); 3191 3192 if (sc->xl_wdog_timer == 0 || --sc->xl_wdog_timer != 0) 3193 return (0); 3194 3195 xl_rxeof(sc); 3196 xl_txeoc(sc); 3197 misintr = 0; 3198 if (sc->xl_type == XL_TYPE_905B) { 3199 xl_txeof_90xB(sc); 3200 if (sc->xl_cdata.xl_tx_cnt == 0) 3201 misintr++; 3202 } else { 3203 xl_txeof(sc); 3204 if (sc->xl_cdata.xl_tx_head == NULL) 3205 misintr++; 3206 } 3207 if (misintr != 0) { 3208 device_printf(sc->xl_dev, 3209 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 3210 return (0); 3211 } 3212 3213 ifp->if_oerrors++; 3214 XL_SEL_WIN(4); 3215 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); 3216 device_printf(sc->xl_dev, "watchdog timeout\n"); 3217 3218 if (status & XL_MEDIASTAT_CARRIER) 3219 device_printf(sc->xl_dev, 3220 "no carrier - transceiver cable problem?\n"); 3221 3222 xl_reset(sc); 3223 xl_init_locked(sc); 3224 3225 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 3226 if (sc->xl_type == XL_TYPE_905B) 3227 xl_start_90xB_locked(ifp); 3228 else 3229 xl_start_locked(ifp); 3230 } 3231 3232 return (EJUSTRETURN); 3233 } 3234 3235 /* 3236 * Stop the adapter and free any mbufs allocated to the 3237 * RX and TX lists. 3238 */ 3239 static void 3240 xl_stop(struct xl_softc *sc) 3241 { 3242 register int i; 3243 struct ifnet *ifp = sc->xl_ifp; 3244 3245 XL_LOCK_ASSERT(sc); 3246 3247 sc->xl_wdog_timer = 0; 3248 3249 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISABLE); 3250 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE); 3251 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB); 3252 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_DISCARD); 3253 xl_wait(sc); 3254 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_DISABLE); 3255 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); 3256 DELAY(800); 3257 3258 #ifdef foo 3259 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_RESET); 3260 xl_wait(sc); 3261 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_TX_RESET); 3262 xl_wait(sc); 3263 #endif 3264 3265 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ACK|XL_STAT_INTLATCH); 3266 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STAT_ENB|0); 3267 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_INTR_ENB|0); 3268 if (sc->xl_flags & XL_FLAG_FUNCREG) 3269 bus_space_write_4(sc->xl_ftag, sc->xl_fhandle, 4, 0x8000); 3270 3271 /* Stop the stats updater. */ 3272 callout_stop(&sc->xl_stat_callout); 3273 3274 /* 3275 * Free data in the RX lists. 3276 */ 3277 for (i = 0; i < XL_RX_LIST_CNT; i++) { 3278 if (sc->xl_cdata.xl_rx_chain[i].xl_mbuf != NULL) { 3279 bus_dmamap_unload(sc->xl_mtag, 3280 sc->xl_cdata.xl_rx_chain[i].xl_map); 3281 bus_dmamap_destroy(sc->xl_mtag, 3282 sc->xl_cdata.xl_rx_chain[i].xl_map); 3283 m_freem(sc->xl_cdata.xl_rx_chain[i].xl_mbuf); 3284 sc->xl_cdata.xl_rx_chain[i].xl_mbuf = NULL; 3285 } 3286 } 3287 if (sc->xl_ldata.xl_rx_list != NULL) 3288 bzero(sc->xl_ldata.xl_rx_list, XL_RX_LIST_SZ); 3289 /* 3290 * Free the TX list buffers. 3291 */ 3292 for (i = 0; i < XL_TX_LIST_CNT; i++) { 3293 if (sc->xl_cdata.xl_tx_chain[i].xl_mbuf != NULL) { 3294 bus_dmamap_unload(sc->xl_mtag, 3295 sc->xl_cdata.xl_tx_chain[i].xl_map); 3296 bus_dmamap_destroy(sc->xl_mtag, 3297 sc->xl_cdata.xl_tx_chain[i].xl_map); 3298 m_freem(sc->xl_cdata.xl_tx_chain[i].xl_mbuf); 3299 sc->xl_cdata.xl_tx_chain[i].xl_mbuf = NULL; 3300 } 3301 } 3302 if (sc->xl_ldata.xl_tx_list != NULL) 3303 bzero(sc->xl_ldata.xl_tx_list, XL_TX_LIST_SZ); 3304 3305 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3306 } 3307 3308 /* 3309 * Stop all chip I/O so that the kernel's probe routines don't 3310 * get confused by errant DMAs when rebooting. 3311 */ 3312 static int 3313 xl_shutdown(device_t dev) 3314 { 3315 struct xl_softc *sc; 3316 3317 sc = device_get_softc(dev); 3318 3319 XL_LOCK(sc); 3320 xl_reset(sc); 3321 xl_stop(sc); 3322 XL_UNLOCK(sc); 3323 3324 return (0); 3325 } 3326 3327 static int 3328 xl_suspend(device_t dev) 3329 { 3330 struct xl_softc *sc; 3331 3332 sc = device_get_softc(dev); 3333 3334 XL_LOCK(sc); 3335 xl_stop(sc); 3336 XL_UNLOCK(sc); 3337 3338 return (0); 3339 } 3340 3341 static int 3342 xl_resume(device_t dev) 3343 { 3344 struct xl_softc *sc; 3345 struct ifnet *ifp; 3346 3347 sc = device_get_softc(dev); 3348 ifp = sc->xl_ifp; 3349 3350 XL_LOCK(sc); 3351 3352 xl_reset(sc); 3353 if (ifp->if_flags & IFF_UP) 3354 xl_init_locked(sc); 3355 3356 XL_UNLOCK(sc); 3357 3358 return (0); 3359 } 3360