1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_XILINX_XLNX_PCIB_H_ 34 #define _DEV_XILINX_XLNX_PCIB_H_ 35 36 #define XLNX_PCIE_VSEC 0x12c 37 #define XLNX_PCIE_BIR 0x130 /* Bridge Info Register */ 38 #define XLNX_PCIE_BSCR 0x134 /* Bridge Status and Control */ 39 #define XLNX_PCIE_IDR 0x138 /* Interrupt Decode Register */ 40 #define XLNX_PCIE_IMR 0x13C /* Interrupt Mask Register */ 41 #define IMR_LINK_DOWN (1 << 0) 42 #define IMR_HOT_RESET (1 << 3) 43 #define IMR_CFG_COMPL_STATUS_S 5 44 #define IMR_CFG_COMPL_STATUS_M (0x7 << IMR_CFG_COMPL_STATUS_S) 45 #define IMR_CFG_TIMEOUT (1 << 8) 46 #define IMR_CORRECTABLE (1 << 9) 47 #define IMR_NON_FATAL (1 << 10) 48 #define IMR_FATAL (1 << 11) 49 #define IMR_INTX (1 << 16) /* INTx Interrupt Received */ 50 #define IMR_MSI (1 << 17) /* MSI Interrupt Received */ 51 #define IMR_SLAVE_UNSUPP_REQ (1 << 20) 52 #define IMR_SLAVE_UNEXP_COMPL (1 << 21) 53 #define IMR_SLAVE_COMPL_TIMOUT (1 << 22) 54 #define IMR_SLAVE_ERROR_POISON (1 << 23) 55 #define IMR_SLAVE_COMPL_ABORT (1 << 24) 56 #define IMR_SLAVE_ILLEG_BURST (1 << 25) 57 #define IMR_MASTER_DECERR (1 << 26) 58 #define IMR_MASTER_SLVERR (1 << 27) 59 #define XLNX_PCIE_BLR 0x140 /* Bus Location Register */ 60 #define XLNX_PCIE_PHYSCR 0x144 /* PHY Status/Control Register */ 61 #define PHYSCR_LINK_UP (1 << 11) /* Current PHY Link-up state */ 62 #define XLNX_PCIE_RPSCR 0x148 /* Root Port Status/Control Register */ 63 #define RPSCR_BE (1 << 0) /* Bridge Enable */ 64 #define XLNX_PCIE_RPMSIBR1 0x14C /* Root Port MSI Base Register 1 */ 65 #define XLNX_PCIE_RPMSIBR2 0x150 /* Root Port MSI Base Register 2 */ 66 #define XLNX_PCIE_RPERRFRR 0x154 /* Root Port Error FIFO Read */ 67 #define RPERRFRR_VALID (1 << 18) /* Indicates whether read succeeded.*/ 68 #define RPERRFRR_REQ_ID_S 0 /* Requester of the error message. */ 69 #define RPERRFRR_REQ_ID_M (0xffff << RPERRFRR_REQ_ID_S) 70 #define XLNX_PCIE_RPIFRR1 0x158 /* Root Port Interrupt FIFO Read 1 */ 71 #define XLNX_PCIE_RPIFRR2 0x15C /* Root Port Interrupt FIFO Read 2 */ 72 #define XLNX_PCIE_RPID2 0x160 /* Root Port Interrupt Decode 2 */ 73 #define XLNX_PCIE_RPID2_MASK 0x164 /* Root Port Interrupt Decode 2 Mask */ 74 #define XLNX_PCIE_RPMSIID1 0x170 /* Root Port MSI Interrupt Decode 1 */ 75 #define XLNX_PCIE_RPMSIID2 0x174 /* Root Port MSI Interrupt Decode 2 */ 76 #define XLNX_PCIE_RPMSIID1_MASK 0x178 /* Root Port MSI Int. Decode 1 Mask */ 77 #define XLNX_PCIE_RPMSIID2_MASK 0x17C /* Root Port MSI Int. Decode 2 Mask */ 78 #define XLNX_PCIE_CCR 0x168 /* Configuration Control Register */ 79 #define XLNX_PCIE_VSEC_CR 0x200 /* VSEC Capability Register 2 */ 80 #define XLNX_PCIE_VSEC_HR 0x204 /* VSEC Header Register 2 */ 81 82 #endif /* !_DEV_XILINX_XLNX_PCIB_H_ */ 83