1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _DEV_XILINX_IF_XAE_H_ 34 #define _DEV_XILINX_IF_XAE_H_ 35 36 #define XAE_RAF 0x00000 /* Reset and Address Filter RW */ 37 #define XAE_TPF 0x00004 /* Transmit Pause Frame RW */ 38 #define XAE_IFGP 0x00008 /* Transmit Inter Frame Gap Adjustment RW */ 39 #define XAE_IS 0x0000C /* Interrupt Status register RW */ 40 #define XAE_IP 0x00010 /* Interrupt Pending register RO */ 41 #define XAE_IE 0x00014 /* Interrupt Enable register RW */ 42 #define XAE_TTAG 0x00018 /* Transmit VLAN Tag RW */ 43 #define XAE_RTAG 0x0001C /* Receive VLAN Tag RW */ 44 #define XAE_UAWL 0x00020 /* Unicast Address Word Lower RW */ 45 #define XAE_UAWU 0x00024 /* Unicast Address Word Upper RW */ 46 #define XAE_TPID0 0x00028 /* VLAN TPID Word 0 RW */ 47 #define XAE_TPID1 0x0002C /* VLAN TPID Word 1 RW */ 48 #define XAE_PPST 0x00030 /* PCS PMA Status register RO */ 49 #define XAE_STATCNT(n) (0x00200 + 0x8 * (n)) /* Statistics Counters RO */ 50 #define XAE_RCW0 0x00400 /* Receive Configuration Word 0 Register RW */ 51 #define XAE_RCW1 0x00404 /* Receive Configuration Word 1 Register RW */ 52 #define RCW1_RX (1 << 28) /* Receive Enable */ 53 #define XAE_TC 0x00408 /* Transmitter Configuration register RW */ 54 #define TC_TX (1 << 28) /* Transmit Enable */ 55 #define XAE_FCC 0x0040C /* Flow Control Configuration register RW */ 56 #define FCC_FCRX (1 << 29) /* Flow Control Enable (RX) */ 57 #define XAE_SPEED 0x00410 /* MAC Speed Configuration Word RW */ 58 #define SPEED_CONF_S 30 59 #define SPEED_10 (0 << SPEED_CONF_S) 60 #define SPEED_100 (1 << SPEED_CONF_S) 61 #define SPEED_1000 (2 << SPEED_CONF_S) 62 #define XAE_RX_MAXFRAME 0x00414 /* RX Max Frame Configuration RW */ 63 #define XAE_TX_MAXFRAME 0x00418 /* TX Max Frame Configuration RW */ 64 #define XAE_TX_TIMESTMP 0x0041C /* TX timestamp adjust control register RW */ 65 #define XAE_IDENT 0x004F8 /* Identification register RO */ 66 #define XAE_ABILITY 0x004FC /* Ability register RO */ 67 #define XAE_MDIO_SETUP 0x00500 /* MDIO Setup register RW */ 68 #define MDIO_SETUP_ENABLE (1 << 6) /* MDIO Enable */ 69 #define MDIO_SETUP_CLK_DIV_S 0 /* Clock Divide */ 70 #define XAE_MDIO_CTRL 0x00504 /* MDIO Control RW */ 71 #define MDIO_TX_REGAD_S 16 /* This controls the register address being accessed. */ 72 #define MDIO_TX_REGAD_M (0x1f << MDIO_TX_REGAD_S) 73 #define MDIO_TX_PHYAD_S 24 /* This controls the PHY address being accessed. */ 74 #define MDIO_TX_PHYAD_M (0x1f << MDIO_TX_PHYAD_S) 75 #define MDIO_CTRL_TX_OP_S 14 /* Type of access performed. */ 76 #define MDIO_CTRL_TX_OP_M (0x3 << MDIO_CTRL_TX_OP_S) 77 #define MDIO_CTRL_TX_OP_READ (0x2 << MDIO_CTRL_TX_OP_S) 78 #define MDIO_CTRL_TX_OP_WRITE (0x1 << MDIO_CTRL_TX_OP_S) 79 #define MDIO_CTRL_INITIATE (1 << 11) /* Start an MDIO transfer. */ 80 #define MDIO_CTRL_READY (1 << 7) /* MDIO is ready for a new xfer */ 81 #define XAE_MDIO_WRITE 0x00508 /* MDIO Write Data RW */ 82 #define XAE_MDIO_READ 0x0050C /* MDIO Read Data RO */ 83 #define XAE_INT_STATUS 0x00600 /* Interrupt Status Register RW */ 84 #define XAE_INT_PEND 0x00610 /* Interrupt Pending Register RO */ 85 #define XAE_INT_ENABLE 0x00620 /* Interrupt Enable Register RW */ 86 #define XAE_INT_CLEAR 0x00630 /* Interrupt Clear Register RW */ 87 #define XAE_UAW0 0x00700 /* Unicast Address Word 0 register (UAW0) RW */ 88 #define XAE_UAW1 0x00704 /* Unicast Address Word 1 register (UAW1) RW */ 89 #define XAE_FFC 0x00708 /* Frame Filter Control RW */ 90 #define FFC_PM (1 << 31) /* Promiscuous Mode */ 91 #define XAE_FFV(n) (0x00710 + 0x4 * (n)) /* Frame Filter Value RW */ 92 #define XAE_FFMV(n) (0x00750 + 0x4 * (n)) /* Frame Filter Mask Value RW */ 93 #define XAE_TX_VLAN(n) (0x04000 + 0x4 * (n)) /* Transmit VLAN Data Table RW */ 94 #define XAE_RX_VLAN(n) (0x08000 + 0x4 * (n)) /* Receive VLAN Data Table RW */ 95 #define XAE_AVB(n) (0x10000 + 0x4 * (n)) /* Ethernet AVB RW */ 96 #define XAE_MAT(n) (0x20000 + 0x4 * (n)) /* Multicast Address Table RW */ 97 98 #define XAE_MULTICAST_TABLE_SIZE 4 99 100 /* RX statistical counters. */ 101 #define RX_BYTES 0 102 #define RX_GOOD_FRAMES 18 103 #define RX_FRAME_CHECK_SEQ_ERROR 19 104 #define RX_GOOD_MCASTS 21 105 #define RX_LEN_OUT_OF_RANGE 23 106 #define RX_ALIGNMENT_ERRORS 40 107 108 /* TX statistical counters. */ 109 #define TX_BYTES 1 110 #define TX_GOOD_FRAMES 27 111 #define TX_GOOD_MCASTS 29 112 #define TX_GOOD_UNDERRUN_ERRORS 30 113 #define TX_SINGLE_COLLISION_FRAMES 34 114 #define TX_MULTI_COLLISION_FRAMES 35 115 #define TX_LATE_COLLISIONS 37 116 #define TX_EXCESS_COLLISIONS 38 117 118 #define XAE_MAX_COUNTERS 43 119 120 #endif /* _DEV_XILINX_IF_XAE_H_ */ 121