1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2019 Ruslan Bukin <br@bsdpad.com> 5 * 6 * This software was developed by SRI International and the University of 7 * Cambridge Computer Laboratory (Department of Computer Science and 8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the 9 * DARPA SSITH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _DEV_XILINX_AXIDMA_H_ 36 #define _DEV_XILINX_AXIDMA_H_ 37 38 #define AXI_DMACR(n) (0x00 + 0x30 * (n)) /* DMA Control register */ 39 #define DMACR_RS (1 << 0) /* Run / Stop. */ 40 #define DMACR_RESET (1 << 2) /* Soft reset the AXI DMA core. */ 41 #define DMACR_IOC_IRQEN (1 << 12) /* Interrupt on Complete (IOC) Interrupt Enable. */ 42 #define DMACR_DLY_IRQEN (1 << 13) /* Interrupt on Delay Timer Interrupt Enable. */ 43 #define DMACR_ERR_IRQEN (1 << 14) /* Interrupt on Error Interrupt Enable. */ 44 #define AXI_DMASR(n) (0x04 + 0x30 * (n)) /* DMA Status register */ 45 #define DMASR_HALTED (1 << 0) 46 #define DMASR_IDLE (1 << 1) 47 #define DMASR_SGINCLD (1 << 3) /* Scatter Gather Enabled */ 48 #define DMASR_DMAINTERR (1 << 4) /* DMA Internal Error. */ 49 #define DMASR_DMASLVERR (1 << 5) /* DMA Slave Error. */ 50 #define DMASR_DMADECOREERR (1 << 6) /* Decode Error. */ 51 #define DMASR_SGINTERR (1 << 8) /* Scatter Gather Internal Error. */ 52 #define DMASR_SGSLVERR (1 << 9) /* Scatter Gather Slave Error. */ 53 #define DMASR_SGDECERR (1 << 10) /* Scatter Gather Decode Error. */ 54 #define DMASR_IOC_IRQ (1 << 12) /* Interrupt on Complete. */ 55 #define DMASR_DLY_IRQ (1 << 13) /* Interrupt on Delay. */ 56 #define DMASR_ERR_IRQ (1 << 14) /* Interrupt on Error. */ 57 #define AXI_CURDESC(n) (0x08 + 0x30 * (n)) /* Current Descriptor Pointer. Lower 32 bits of the address. */ 58 #define AXI_CURDESC_MSB(n) (0x0C + 0x30 * (n)) /* Current Descriptor Pointer. Upper 32 bits of address. */ 59 #define AXI_TAILDESC(n) (0x10 + 0x30 * (n)) /* Tail Descriptor Pointer. Lower 32 bits. */ 60 #define AXI_TAILDESC_MSB(n) (0x14 + 0x30 * (n)) /* Tail Descriptor Pointer. Upper 32 bits of address. */ 61 #define AXI_SG_CTL 0x2C /* Scatter/Gather User and Cache */ 62 63 #define READ4(_sc, _reg) \ 64 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 65 #define WRITE4(_sc, _reg, _val) \ 66 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 67 #define READ8(_sc, _reg) \ 68 bus_space_read_8(_sc->bst, _sc->bsh, _reg) 69 #define WRITE8(_sc, _reg, _val) \ 70 bus_space_write_8(_sc->bst, _sc->bsh, _reg, _val) 71 72 struct axidma_desc { 73 uint32_t next; 74 uint32_t reserved1; 75 uint32_t phys; 76 uint32_t reserved2; 77 uint32_t reserved3; 78 uint32_t reserved4; 79 uint32_t control; 80 #define BD_CONTROL_TXSOF (1 << 27) /* Start of Frame. */ 81 #define BD_CONTROL_TXEOF (1 << 26) /* End of Frame. */ 82 #define BD_CONTROL_LEN_S 0 /* Buffer Length. */ 83 #define BD_CONTROL_LEN_M (0x3ffffff << BD_CONTROL_LEN_S) 84 uint32_t status; 85 #define BD_STATUS_CMPLT (1 << 31) 86 #define BD_STATUS_TRANSFERRED_S 0 87 #define BD_STATUS_TRANSFERRED_M (0x7fffff << BD_STATUS_TRANSFERRED_S) 88 uint32_t app0; 89 uint32_t app1; 90 uint32_t app2; 91 uint32_t app3; 92 uint32_t app4; 93 uint32_t reserved[3]; 94 }; 95 96 #endif /* !_DEV_XILINX_AXIDMA_H_ */ 97