1 /*- 2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 */ 34 35 /* 36 * Xilinx AXI_QUAD_SPI 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/malloc.h> 45 #include <sys/rman.h> 46 #include <sys/timeet.h> 47 #include <sys/timetc.h> 48 #include <sys/watchdog.h> 49 50 #include <dev/spibus/spi.h> 51 #include <dev/spibus/spibusvar.h> 52 53 #include "spibus_if.h" 54 55 #include <dev/fdt/fdt_common.h> 56 #include <dev/ofw/openfirm.h> 57 #include <dev/ofw/ofw_bus.h> 58 #include <dev/ofw/ofw_bus_subr.h> 59 60 #include <machine/bus.h> 61 #include <machine/cpu.h> 62 #include <machine/intr.h> 63 64 #define READ4(_sc, _reg) \ 65 bus_space_read_4(_sc->bst, _sc->bsh, _reg) 66 #define WRITE4(_sc, _reg, _val) \ 67 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) 68 69 #define SPI_SRR 0x40 /* Software reset register */ 70 #define SRR_RESET 0x0A /* The only reset value */ 71 #define SPI_CR 0x60 /* Control register */ 72 #define CR_LSB_FIRST (1 << 9) /* LSB first */ 73 #define CR_MASTER_TI (1 << 8) /* Master Transaction Inhibit */ 74 #define CR_MSS (1 << 7) /* Manual Slave Select */ 75 #define CR_RST_RX (1 << 6) /* RX FIFO Reset */ 76 #define CR_RST_TX (1 << 5) /* TX FIFO Reset */ 77 #define CR_CPHA (1 << 4) /* Clock phase */ 78 #define CR_CPOL (1 << 3) /* Clock polarity */ 79 #define CR_MASTER (1 << 2) /* Master (SPI master mode) */ 80 #define CR_SPE (1 << 1) /* SPI system enable */ 81 #define CR_LOOP (1 << 0) /* Local loopback mode */ 82 #define SPI_SR 0x64 /* Status register */ 83 #define SR_TX_FULL (1 << 3) /* Transmit full */ 84 #define SR_TX_EMPTY (1 << 2) /* Transmit empty */ 85 #define SR_RX_FULL (1 << 1) /* Receive full */ 86 #define SR_RX_EMPTY (1 << 0) /* Receive empty */ 87 #define SPI_DTR 0x68 /* Data transmit register */ 88 #define SPI_DRR 0x6C /* Data receive register */ 89 #define SPI_SSR 0x70 /* Slave select register */ 90 #define SPI_TFOR 0x74 /* Transmit FIFO Occupancy Register */ 91 #define SPI_RFOR 0x78 /* Receive FIFO Occupancy Register */ 92 #define SPI_DGIER 0x1C /* Device global interrupt enable register */ 93 #define SPI_IPISR 0x20 /* IP interrupt status register */ 94 #define SPI_IPIER 0x28 /* IP interrupt enable register */ 95 96 struct spi_softc { 97 struct resource *res[1]; 98 bus_space_tag_t bst; 99 bus_space_handle_t bsh; 100 void *ih; 101 }; 102 103 static struct resource_spec spi_spec[] = { 104 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 105 { -1, 0 } 106 }; 107 108 static int 109 spi_probe(device_t dev) 110 { 111 112 if (!ofw_bus_status_okay(dev)) 113 return (ENXIO); 114 115 if (!ofw_bus_is_compatible(dev, "xlnx,xps-spi-3.2")) 116 return (ENXIO); 117 118 device_set_desc(dev, "Xilinx Quad SPI"); 119 return (BUS_PROBE_DEFAULT); 120 } 121 122 static int 123 spi_attach(device_t dev) 124 { 125 struct spi_softc *sc; 126 uint32_t reg; 127 128 sc = device_get_softc(dev); 129 130 if (bus_alloc_resources(dev, spi_spec, sc->res)) { 131 device_printf(dev, "could not allocate resources\n"); 132 return (ENXIO); 133 } 134 135 /* Memory interface */ 136 sc->bst = rman_get_bustag(sc->res[0]); 137 sc->bsh = rman_get_bushandle(sc->res[0]); 138 139 /* Reset */ 140 WRITE4(sc, SPI_SRR, SRR_RESET); 141 142 DELAY(1000); 143 144 reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX); 145 WRITE4(sc, SPI_CR, reg); 146 WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ 147 148 reg = (CR_MASTER | CR_MSS | CR_SPE); 149 WRITE4(sc, SPI_CR, reg); 150 151 device_add_child(dev, "spibus", 0); 152 return (bus_generic_attach(dev)); 153 } 154 155 static int 156 spi_txrx(struct spi_softc *sc, uint8_t *out_buf, 157 uint8_t *in_buf, int bufsz, int cs) 158 { 159 uint32_t data; 160 uint32_t i; 161 162 for (i = 0; i < bufsz; i++) { 163 WRITE4(sc, SPI_DTR, out_buf[i]); 164 165 while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY)) 166 continue; 167 168 data = READ4(sc, SPI_DRR); 169 if (in_buf) 170 in_buf[i] = (data & 0xff); 171 } 172 173 return (0); 174 } 175 176 static int 177 spi_transfer(device_t dev, device_t child, struct spi_command *cmd) 178 { 179 struct spi_softc *sc; 180 uint32_t reg; 181 uint32_t cs; 182 183 sc = device_get_softc(dev); 184 185 KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, 186 ("%s: TX/RX command sizes should be equal", __func__)); 187 KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, 188 ("%s: TX/RX data sizes should be equal", __func__)); 189 190 /* get the proper chip select */ 191 spibus_get_cs(child, &cs); 192 193 cs &= ~SPIBUS_CS_HIGH; 194 195 /* Assert CS */ 196 reg = READ4(sc, SPI_SSR); 197 reg &= ~(1 << cs); 198 WRITE4(sc, SPI_SSR, reg); 199 200 /* Command */ 201 spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); 202 203 /* Data */ 204 spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); 205 206 /* Deassert CS */ 207 reg = READ4(sc, SPI_SSR); 208 reg |= (1 << cs); 209 WRITE4(sc, SPI_SSR, reg); 210 211 return (0); 212 } 213 214 static device_method_t spi_methods[] = { 215 /* Device interface */ 216 DEVMETHOD(device_probe, spi_probe), 217 DEVMETHOD(device_attach, spi_attach), 218 219 /* SPI interface */ 220 DEVMETHOD(spibus_transfer, spi_transfer), 221 DEVMETHOD_END 222 }; 223 224 static driver_t spi_driver = { 225 "spi", 226 spi_methods, 227 sizeof(struct spi_softc), 228 }; 229 230 DRIVER_MODULE(spi, simplebus, spi_driver, 0, 0); 231