xref: /freebsd/sys/dev/wpi/if_wpireg.h (revision 39beb93c3f8bdbf72a61fda42300b5ebed7390c8)
1 /*	$FreeBSD$	*/
2 
3 /*-
4  * Copyright (c) 2006,2007
5  *	Damien Bergamini <damien.bergamini@free.fr>
6  *
7  * Permission to use, copy, modify, and distribute this software for any
8  * purpose with or without fee is hereby granted, provided that the above
9  * copyright notice and this permission notice appear in all copies.
10  *
11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18  */
19 
20 #define WPI_TX_RING_COUNT	256
21 #define WPI_CMD_RING_COUNT	256
22 #define WPI_RX_RING_COUNT	64
23 
24 /*
25  * Rings must be aligned on a 16K boundary.
26  */
27 #define WPI_RING_DMA_ALIGN	0x4000
28 
29 /* maximum scatter/gather */
30 #define WPI_MAX_SCATTER	4
31 
32 /* maximum Rx buffer size */
33 #define WPI_RBUF_SIZE ( 3 * 1024 ) /* XXX 3000 but must be aligned */
34 
35 /*
36  * Control and status registers.
37  */
38 #define WPI_HWCONFIG		0x000
39 #define WPI_INTR		0x008
40 #define WPI_MASK		0x00c
41 #define WPI_INTR_STATUS		0x010
42 #define WPI_GPIO_STATUS		0x018
43 #define WPI_RESET		0x020
44 #define WPI_GPIO_CTL		0x024
45 #define WPI_EEPROM_CTL		0x02c
46 #define WPI_EEPROM_STATUS	0x030
47 #define WPI_UCODE_SET		0x058
48 #define WPI_UCODE_CLR		0x05c
49 #define WPI_TEMPERATURE		0x060
50 #define WPI_CHICKEN		0x100
51 #define WPI_PLL_CTL		0x20c
52 #define WPI_WRITE_MEM_ADDR	0x444
53 #define WPI_READ_MEM_ADDR	0x448
54 #define WPI_WRITE_MEM_DATA	0x44c
55 #define WPI_READ_MEM_DATA	0x450
56 #define WPI_TX_WIDX		0x460
57 #define WPI_TX_CTL(qid)		(0x940 + (qid) * 8)
58 #define WPI_TX_BASE(qid)	(0x944 + (qid) * 8)
59 #define WPI_TX_DESC(qid)	(0x980 + (qid) * 80)
60 #define WPI_RX_CONFIG		0xc00
61 #define WPI_RX_BASE		0xc04
62 #define WPI_RX_WIDX		0xc20
63 #define WPI_RX_RIDX_PTR		0xc24
64 #define WPI_RX_CTL		0xcc0
65 #define WPI_RX_STATUS		0xcc4
66 #define WPI_TX_CONFIG(qid)	(0xd00 + (qid) * 32)
67 #define WPI_TX_CREDIT(qid)	(0xd04 + (qid) * 32)
68 #define WPI_TX_STATE(qid)	(0xd08 + (qid) * 32)
69 #define WPI_TX_BASE_PTR		0xe80
70 #define WPI_MSG_CONFIG		0xe88
71 #define WPI_TX_STATUS		0xe90
72 
73 
74 /*
75  * NIC internal memory offsets.
76  */
77 #define WPI_MEM_MODE		0x2e00
78 #define WPI_MEM_RA		0x2e04
79 #define WPI_MEM_TXCFG		0x2e10
80 #define WPI_MEM_MAGIC4		0x2e14
81 #define WPI_MEM_MAGIC5		0x2e20
82 #define WPI_MEM_BYPASS1		0x2e2c
83 #define WPI_MEM_BYPASS2		0x2e30
84 #define WPI_MEM_CLOCK1		0x3004
85 #define WPI_MEM_CLOCK2		0x3008
86 #define WPI_MEM_POWER		0x300c
87 #define WPI_MEM_PCIDEV		0x3010
88 #define WPI_MEM_HW_RADIO_OFF	0x3014
89 #define WPI_MEM_UCODE_CTL	0x3400
90 #define WPI_MEM_UCODE_SRC	0x3404
91 #define WPI_MEM_UCODE_DST	0x3408
92 #define WPI_MEM_UCODE_SIZE	0x340c
93 #define WPI_MEM_UCODE_BASE	0x3800
94 
95 #define WPI_MEM_TEXT_BASE	0x3490
96 #define WPI_MEM_TEXT_SIZE	0x3494
97 #define WPI_MEM_DATA_BASE	0x3498
98 #define WPI_MEM_DATA_SIZE	0x349c
99 
100 
101 /* possible flags for register WPI_HWCONFIG */
102 #define WPI_HW_ALM_MB	(1 << 8)
103 #define WPI_HW_ALM_MM	(1 << 9)
104 #define WPI_HW_SKU_MRC	(1 << 10)
105 #define WPI_HW_REV_D	(1 << 11)
106 #define WPI_HW_TYPE_B	(1 << 12)
107 
108 /* possible flags for registers WPI_READ_MEM_ADDR/WPI_WRITE_MEM_ADDR */
109 #define WPI_MEM_4	((sizeof (uint32_t) - 1) << 24)
110 
111 /* possible values for WPI_MEM_UCODE_DST */
112 #define WPI_FW_TEXT	0x00000000
113 
114 /* possible flags for WPI_GPIO_STATUS */
115 #define WPI_POWERED		(1 << 9)
116 
117 /* possible flags for register WPI_RESET */
118 #define WPI_NEVO_RESET		(1 << 0)
119 #define WPI_SW_RESET		(1 << 7)
120 #define WPI_MASTER_DISABLED	(1 << 8)
121 #define WPI_STOP_MASTER		(1 << 9)
122 
123 /* possible flags for register WPI_GPIO_CTL */
124 #define WPI_GPIO_CLOCK		(1 << 0)
125 #define WPI_GPIO_INIT		(1 << 2)
126 #define WPI_GPIO_MAC		(1 << 3)
127 #define WPI_GPIO_SLEEP		(1 << 4)
128 #define WPI_GPIO_PWR_STATUS	0x07000000
129 #define WPI_GPIO_PWR_SLEEP	(4 << 24)
130 
131 /* possible flags for register WPI_CHICKEN */
132 #define WPI_CHICKEN_RXNOLOS	(1 << 23)
133 
134 /* possible flags for register WPI_PLL_CTL */
135 #define WPI_PLL_INIT		(1 << 24)
136 
137 /* possible flags for register WPI_UCODE_CLR */
138 #define WPI_RADIO_OFF		(1 << 1)
139 #define WPI_DISABLE_CMD		(1 << 2)
140 
141 /* possible flags for WPI_RX_STATUS */
142 #define	WPI_RX_IDLE	(1 << 24)
143 
144 /* possible flags for register WPI_UC_CTL */
145 #define WPI_UC_ENABLE	(1 << 30)
146 #define WPI_UC_RUN	(1 << 31)
147 
148 /* possible flags for register WPI_INTR_CSR */
149 #define WPI_ALIVE_INTR	(1 << 0)
150 #define WPI_WAKEUP_INTR	(1 << 1)
151 #define WPI_SW_ERROR	(1 << 25)
152 #define WPI_TX_INTR	(1 << 27)
153 #define WPI_HW_ERROR	(1 << 29)
154 #define WPI_RX_INTR	(1 << 31)
155 
156 #define WPI_INTR_MASK							\
157 	(WPI_SW_ERROR | WPI_HW_ERROR | WPI_TX_INTR | WPI_RX_INTR |	\
158 	 WPI_ALIVE_INTR | WPI_WAKEUP_INTR)
159 
160 /* possible flags for register WPI_TX_STATUS */
161 #define WPI_TX_IDLE(qid)	(1 << ((qid) + 24) | 1 << ((qid) + 16))
162 
163 /* possible flags for register WPI_EEPROM_CTL */
164 #define WPI_EEPROM_READY	(1 << 0)
165 
166 /* possible flags for register WPI_EEPROM_STATUS */
167 #define WPI_EEPROM_VERSION	0x00000007
168 #define WPI_EEPROM_LOCKED	0x00000180
169 
170 
171 struct wpi_shared {
172 	uint32_t	txbase[8];
173 	uint32_t	next;
174 	uint32_t	reserved[2];
175 } __packed;
176 
177 #define WPI_MAX_SEG_LEN	65520
178 struct wpi_tx_desc {
179 	uint32_t	flags;
180 #define WPI_PAD32(x)	(roundup2(x, 4) - (x))
181 
182 	struct {
183 		uint32_t	addr;
184 		uint32_t	len;
185 	} __attribute__((__packed__))	segs[WPI_MAX_SCATTER];
186 	uint8_t		reserved[28];
187 } __packed;
188 
189 struct wpi_tx_stat {
190 	uint8_t		nrts;
191 	uint8_t		ntries;
192 	uint8_t		nkill;
193 	uint8_t		rate;
194 	uint32_t	duration;
195 	uint32_t	status;
196 } __packed;
197 
198 struct wpi_rx_desc {
199 	uint32_t	len;
200 	uint8_t		type;
201 #define WPI_UC_READY		  1
202 #define WPI_RX_DONE		 27
203 #define WPI_TX_DONE		 28
204 #define WPI_START_SCAN		130
205 #define WPI_SCAN_RESULTS	131
206 #define WPI_STOP_SCAN		132
207 #define WPI_STATE_CHANGED	161
208 #define WPI_MISSED_BEACON	162
209 
210 	uint8_t		flags;
211 	uint8_t		idx;
212 	uint8_t		qid;
213 } __packed;
214 
215 struct wpi_rx_stat {
216 	uint8_t		len;
217 #define WPI_STAT_MAXLEN	20
218 
219 	uint8_t		id;
220 	uint8_t		rssi;	/* received signal strength */
221 #define WPI_RSSI_OFFSET	95
222 
223 	uint8_t		agc;	/* access gain control */
224 	uint16_t	signal;
225 	uint16_t	noise;
226 } __packed;
227 
228 struct wpi_rx_head {
229 	uint16_t	chan;
230 	uint16_t	flags;
231 	uint8_t		reserved;
232 	uint8_t		rate;
233 	uint16_t	len;
234 } __packed;
235 
236 struct wpi_rx_tail {
237 	uint32_t	flags;
238 #if 0
239 #define WPI_RX_NO_CRC_ERR	(1 << 0)
240 #define WPI_RX_NO_OVFL_ERR	(1 << 1)
241 /* shortcut for the above */
242 #define WPI_RX_NOERROR		(WPI_RX_NO_CRC_ERR | WPI_RX_NO_OVFL_ERR)
243 #endif
244 	uint64_t	tstamp;
245 	uint32_t	tbeacon;
246 } __packed;
247 
248 struct wpi_tx_cmd {
249 	uint8_t	code;
250 #define WPI_CMD_CONFIGURE	 16
251 #define WPI_CMD_ASSOCIATE	 17
252 #define WPI_CMD_SET_WME          19
253 #define WPI_CMD_TSF		 20
254 #define WPI_CMD_ADD_NODE	 24
255 #define WPI_CMD_TX_DATA		 28
256 #define WPI_CMD_MRR_SETUP	 71
257 #define WPI_CMD_SET_LED		 72
258 #define WPI_CMD_SET_POWER_MODE	119
259 #define WPI_CMD_SCAN		128
260 #define WPI_CMD_SET_BEACON	145
261 #define WPI_CMD_TXPOWER		151
262 #define WPI_CMD_BLUETOOTH	155
263 
264 	uint8_t	flags;
265 	uint8_t	idx;
266 	uint8_t	qid;
267 	uint8_t	data[360];
268 } __packed;
269 
270 /* structure for WPI_CMD_CONFIGURE */
271 struct wpi_config {
272 	uint8_t		myaddr[IEEE80211_ADDR_LEN];
273 	uint16_t	reserved1;
274 	uint8_t		bssid[IEEE80211_ADDR_LEN];
275 	uint16_t	reserved2;
276 	uint8_t		wlap_bssid_addr[6];
277 	uint16_t	reserved3;
278 	uint8_t		mode;
279 #define WPI_MODE_HOSTAP		1
280 #define WPI_MODE_STA		3
281 #define WPI_MODE_IBSS		4
282 #define WPI_MODE_MONITOR	6
283 
284 	uint8_t		air_propogation;
285 	uint16_t	reserved4;
286 	uint8_t		ofdm_mask;
287 	uint8_t		cck_mask;
288 	uint16_t	associd;
289 	uint32_t	flags;
290 #define WPI_CONFIG_24GHZ	(1 << 0)
291 #define WPI_CONFIG_CCK		(1 << 1)
292 #define WPI_CONFIG_AUTO		(1 << 2)
293 #define WPI_CONFIG_SHSLOT	(1 << 4)
294 #define WPI_CONFIG_SHPREAMBLE	(1 << 5)
295 #define WPI_CONFIG_NODIVERSITY	(1 << 7)
296 #define WPI_CONFIG_ANTENNA_A	(1 << 8)
297 #define WPI_CONFIG_ANTENNA_B	(1 << 9)
298 #define WPI_CONFIG_TSF		(1 << 15)
299 
300 	uint32_t	filter;
301 #define WPI_FILTER_PROMISC	(1 << 0)
302 #define WPI_FILTER_CTL		(1 << 1)
303 #define WPI_FILTER_MULTICAST	(1 << 2)
304 #define WPI_FILTER_NODECRYPT	(1 << 3)
305 #define WPI_FILTER_BSS		(1 << 5)
306 #define WPI_FILTER_BEACON	(1 << 6)
307 
308 	uint8_t		chan;
309 	uint16_t	reserved6;
310 } __packed;
311 
312 /* structure for command WPI_CMD_ASSOCIATE */
313 struct wpi_assoc {
314 	uint32_t	flags;
315 	uint32_t	filter;
316 	uint8_t		ofdm_mask;
317 	uint8_t		cck_mask;
318 	uint16_t	reserved;
319 } __packed;
320 
321 /* structure for command WPI_CMD_SET_WME */
322 struct wpi_wme_setup {
323 	uint32_t	flags;
324 	struct {
325 		uint16_t	cwmin;
326 		uint16_t	cwmax;
327 		uint8_t		aifsn;
328 		uint8_t		reserved;
329 		uint16_t	txop;
330 	} __packed	ac[WME_NUM_AC];
331 } __packed;
332 
333 /* structure for command WPI_CMD_TSF */
334 struct wpi_cmd_tsf {
335 	uint64_t	tstamp;
336 	uint16_t	bintval;
337 	uint16_t	atim;
338 	uint32_t	binitval;
339 	uint16_t	lintval;
340 	uint16_t	reserved;
341 } __packed;
342 
343 /* structure for WPI_CMD_ADD_NODE */
344 struct wpi_node_info {
345 	uint8_t		control;
346 #define WPI_NODE_UPDATE	(1 << 0)
347 
348 	uint8_t		reserved1[3];
349 	uint8_t		bssid[IEEE80211_ADDR_LEN];
350 	uint16_t	reserved2;
351 	uint8_t		id;
352 #define WPI_ID_BSS		0
353 #define WPI_ID_BROADCAST	24
354 
355 	uint8_t		flags;
356 	uint16_t	reserved3;
357 	uint16_t	key_flags;
358 	uint8_t		tkip;
359 	uint8_t		reserved4;
360 	uint16_t	ttak[5];
361 	uint16_t	reserved5;
362 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
363 	uint32_t	action;
364 #define WPI_ACTION_SET_RATE	4
365 	uint32_t	mask;
366 	uint16_t	tid;
367 	uint8_t		rate;
368 	uint8_t		antenna;
369 #define WPI_ANTENNA_A	(1<<6)
370 #define WPI_ANTENNA_B	(1<<7)
371 #define WPI_ANTENNA_BOTH	(WPI_ANTENNA_A|WPI_ANTENNA_B)
372 	uint8_t		add_imm;
373 	uint8_t		del_imm;
374 	uint16_t	add_imm_start;
375 } __packed;
376 
377 /* structure for command WPI_CMD_TX_DATA */
378 struct wpi_cmd_data {
379 	uint16_t	len;
380 	uint16_t	lnext;
381 	uint32_t	flags;
382 #define WPI_TX_NEED_RTS		(1 <<  1)
383 #define WPI_TX_NEED_CTS         (1 <<  2)
384 #define WPI_TX_NEED_ACK		(1 <<  3)
385 #define WPI_TX_FULL_TXOP	(1 <<  7)
386 #define WPI_TX_BT_DISABLE	(1 << 12) /* bluetooth coexistence */
387 #define WPI_TX_AUTO_SEQ		(1 << 13)
388 #define WPI_TX_INSERT_TSTAMP	(1 << 16)
389 
390 	uint8_t		rate;
391 	uint8_t		id;
392 	uint8_t		tid;
393 	uint8_t		security;
394 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
395 	uint8_t		tkip[IEEE80211_WEP_MICLEN];
396 	uint32_t	fnext;
397 	uint32_t	lifetime;
398 #define WPI_LIFETIME_INFINITE	0xffffffff
399 	uint8_t		ofdm_mask;
400 	uint8_t		cck_mask;
401 	uint8_t		rts_ntries;
402 	uint8_t		data_ntries;
403 	uint16_t	timeout;
404 	uint16_t	txop;
405 	struct          ieee80211_frame wh;
406 } __packed;
407 
408 /* structure for command WPI_CMD_SET_BEACON */
409 struct wpi_cmd_beacon {
410 	uint16_t	len;
411 	uint16_t	reserved1;
412 	uint32_t	flags;	/* same as wpi_cmd_data */
413 	uint8_t		rate;
414 	uint8_t		id;
415 	uint8_t		reserved2[30];
416 	uint32_t	lifetime;
417 	uint8_t		ofdm_mask;
418 	uint8_t		cck_mask;
419 	uint16_t	reserved3[3];
420 	uint16_t	tim;
421 	uint8_t		timsz;
422 	uint8_t		reserved4;
423 	struct		ieee80211_frame wh;
424 } __packed;
425 
426 /* structure for notification WPI_MISSED_BEACON */
427 struct wpi_missed_beacon {
428     uint32_t consecutive;
429     uint32_t total;
430     uint32_t expected;
431     uint32_t received;
432 } __packed;
433 
434 
435 /* structure for WPI_CMD_MRR_SETUP */
436 struct wpi_mrr_setup {
437 	uint8_t	which;
438 #define WPI_MRR_CTL	0
439 #define WPI_MRR_DATA	1
440 
441 	uint8_t		reserved[3];
442 
443 	struct {
444 		uint8_t	signal;
445 		uint8_t	flags;
446 		uint8_t	ntries;
447 		uint8_t	next;
448 #define WPI_OFDM6	0
449 #define WPI_OFDM54	7
450 #define WPI_CCK1	8
451 #define WPI_CCK2	9
452 #define WPI_CCK11	11
453 
454 	} __attribute__((__packed__))	rates[WPI_CCK11 + 1];
455 } __packed;
456 
457 /* structure for WPI_CMD_SET_LED */
458 struct wpi_cmd_led {
459 	uint32_t	unit;	/* multiplier (in usecs) */
460 	uint8_t		which;
461 #define WPI_LED_ACTIVITY	1
462 #define WPI_LED_LINK		2
463 
464 	uint8_t		off;
465 	uint8_t		on;
466 	uint8_t		reserved;
467 } __packed;
468 
469 /* structure for WPI_CMD_SET_POWER_MODE */
470 struct wpi_power {
471 	uint32_t	flags;
472 #define WPI_POWER_CAM	0	/* constantly awake mode */
473 	uint32_t	rx_timeout;
474 	uint32_t	tx_timeout;
475 	uint32_t	sleep[5];
476 } __packed;
477 
478 /* structure for command WPI_CMD_SCAN */
479 struct wpi_scan_hdr {
480 	uint16_t	len;
481 	uint8_t		reserved1;
482 	uint8_t		nchan;
483 	uint16_t	quiet;
484 	uint16_t	threshold;
485 	uint16_t	promotion;
486 	uint16_t	reserved2;
487 	uint32_t	maxtimeout;
488 	uint32_t	suspend;
489 	uint32_t	flags;
490 	uint32_t	filter;
491 
492 struct {
493 	uint16_t	len;
494 	uint16_t	lnext;
495 	uint32_t	flags;
496 	uint8_t		rate;
497 	uint8_t		id;
498 	uint8_t		tid;
499 	uint8_t		security;
500 	uint8_t		key[IEEE80211_KEYBUF_SIZE];
501 	uint8_t		tkip[IEEE80211_WEP_MICLEN];
502 	uint32_t	fnext;
503 	uint32_t	lifetime;
504 	uint8_t		ofdm_mask;
505 	uint8_t		cck_mask;
506 	uint8_t		rts_ntries;
507 	uint8_t		data_ntries;
508 	uint16_t	timeout;
509 	uint16_t	txop;
510 }	tx __attribute__((__packed__));
511 
512 #define WPI_SCAN_MAX_ESSIDS	4
513 	struct {
514 	    uint8_t		id;
515 	    uint8_t		esslen;
516 	    uint8_t		essid[32];
517 	}scan_essids[WPI_SCAN_MAX_ESSIDS];
518 	/* followed by probe request body */
519 	/* followed by nchan x wpi_scan_chan */
520 } __packed;
521 
522 struct wpi_scan_chan {
523 	uint8_t		flags;
524 	uint8_t		chan;
525 #define WPI_CHAN_ACTIVE	(1 << 0)
526 #define WPI_CHAN_DIRECT (1 << 1)
527 	uint8_t		gain_radio;
528 	uint8_t		gain_dsp;
529 	uint16_t	active;		/* msecs */
530 	uint16_t	passive;	/* msecs */
531 } __packed;
532 
533 /* structure for WPI_CMD_BLUETOOTH */
534 struct wpi_bluetooth {
535 	uint8_t		flags;
536 	uint8_t		lead;
537 	uint8_t		kill;
538 	uint8_t		reserved;
539 	uint32_t	ack;
540 	uint32_t	cts;
541 } __packed;
542 
543 /* structure for command WPI_CMD_TXPOWER */
544 struct wpi_cmd_txpower {
545 
546 	uint8_t		band;
547 #define WPI_RATE_5GHZ	0
548 #define WPI_RATE_2GHZ	1
549 	uint8_t		reserved;
550 	uint16_t	channel;
551 
552 #define WPI_RATE_MAPPING_COUNT 12
553 	struct {
554 	    uint8_t	rate;
555 	    uint8_t	gain_radio;
556 	    uint8_t	gain_dsp;
557 	    uint8_t	reserved;
558 	} __packed rates [WPI_RATE_MAPPING_COUNT];
559 
560 } __packed;
561 
562 
563 
564 #define WPI_FW_MAIN_TEXT_MAXSZ (80 * 1024 )
565 #define WPI_FW_MAIN_DATA_MAXSZ (32 * 1024 )
566 #define WPI_FW_INIT_TEXT_MAXSZ (80 * 1024 )
567 #define WPI_FW_INIT_DATA_MAXSZ (32 * 1024 )
568 #define WPI_FW_BOOT_TEXT_MAXSZ 1024
569 
570 #define WPI_FW_UPDATED	(1 << 31 )
571 
572 /* firmware image header */
573 struct wpi_firmware_hdr {
574 
575 #define WPI_FW_MINVERSION 2144
576 
577 	uint32_t	version;
578 	uint32_t	rtextsz;
579 	uint32_t	rdatasz;
580 	uint32_t	itextsz;
581 	uint32_t	idatasz;
582 	uint32_t	btextsz;
583 } __packed;
584 
585 /* structure for WPI_UC_READY notification */
586 struct wpi_ucode_info {
587 	uint32_t	version;
588 	uint8_t		revision[8];
589 	uint8_t		type;
590 	uint8_t		subtype;
591 	uint16_t	reserved;
592 	uint32_t	logptr;
593 	uint32_t	errorptr;
594 	uint32_t	timestamp;
595 	uint32_t	valid;
596 } __packed;
597 
598 /* structure for WPI_START_SCAN notification */
599 struct wpi_start_scan {
600 	uint64_t	tstamp;
601 	uint32_t	tbeacon;
602 	uint8_t		chan;
603 	uint8_t		band;
604 	uint16_t	reserved;
605 	uint32_t	status;
606 } __packed;
607 
608 /* structure for WPI_STOP_SCAN notification */
609 struct wpi_stop_scan {
610 	uint8_t		nchan;
611 	uint8_t		status;
612 	uint8_t		reserved;
613 	uint8_t		chan;
614 	uint64_t	tsf;
615 } __packed;
616 
617 #define WPI_EEPROM_MAC		0x015
618 #define WPI_EEPROM_REVISION	0x035
619 #define WPI_EEPROM_CAPABILITIES	0x045
620 #define WPI_EEPROM_TYPE		0x04a
621 #define WPI_EEPROM_DOMAIN	0x060
622 #define WPI_EEPROM_BAND1	0x063
623 #define WPI_EEPROM_BAND2	0x072
624 #define WPI_EEPROM_BAND3	0x080
625 #define WPI_EEPROM_BAND4	0x08d
626 #define WPI_EEPROM_BAND5	0x099
627 #define WPI_EEPROM_POWER_GRP	0x100
628 
629 struct wpi_eeprom_chan {
630 	uint8_t	flags;
631 #define WPI_EEPROM_CHAN_VALID	(1<<0)
632 #define	WPI_EEPROM_CHAN_IBSS	(1<<1)
633 #define WPI_EEPROM_CHAN_ACTIVE	(1<<3)
634 #define WPI_EEPROM_CHAN_RADAR	(1<<4)
635 
636 	int8_t	maxpwr;
637 } __packed;
638 
639 struct wpi_eeprom_sample {
640     uint8_t	index;
641     int8_t	power;
642     uint16_t	volt;
643 };
644 
645 #define WPI_POWER_GROUPS_COUNT	5
646 
647 struct wpi_eeprom_group {
648     struct	wpi_eeprom_sample samples[5];
649     int32_t	coef[5];
650     int32_t	corr[5];
651     int8_t	maxpwr;
652     uint8_t	chan;
653     int16_t	temp;
654 } __packed;
655 
656 #define WPI_CHAN_BANDS_COUNT	5
657 #define WPI_MAX_CHAN_PER_BAND	14
658 
659 static const struct wpi_chan_band {
660     uint32_t	addr;	/* offset in EEPROM */
661     uint8_t	nchan;
662     uint8_t	chan[WPI_MAX_CHAN_PER_BAND];
663 } wpi_bands[5] = {
664     { WPI_EEPROM_BAND1, 14,
665 	{ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }},
666     { WPI_EEPROM_BAND2, 13,
667 	{ 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 }},
668     { WPI_EEPROM_BAND3, 12,
669 	{ 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 }},
670     { WPI_EEPROM_BAND4, 11,
671 	{ 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 }},
672     { WPI_EEPROM_BAND5, 6,
673 	{ 145, 149, 153, 157, 161, 165 }}
674 };
675 
676 #define WPI_MAX_PWR_INDEX	77
677 
678 /*
679  * RF Tx gain values from highest to lowest power (values obtained from
680  * the reference driver.)
681  */
682 static const uint8_t wpi_rf_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = {
683     0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xfb, 0xbb, 0xbb, 0xbb,
684     0xbb, 0xf3, 0xf3, 0xf3, 0xf3, 0xf3, 0xd3, 0xd3, 0xb3, 0xb3, 0xb3,
685     0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x93, 0x73, 0xeb, 0xeb, 0xeb,
686     0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xcb, 0xab, 0xab, 0xab, 0x8b,
687     0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xe3, 0xc3, 0xc3, 0xc3, 0xc3, 0xa3,
688     0xa3, 0xa3, 0xa3, 0x83, 0x83, 0x83, 0x83, 0x63, 0x63, 0x63, 0x63,
689     0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23, 0x03, 0x03, 0x03,
690     0x03
691 };
692 
693 static const uint8_t wpi_rf_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = {
694     0xfb, 0xfb, 0xfb, 0xdb, 0xdb, 0xbb, 0xbb, 0x9b, 0x9b, 0x7b, 0x7b,
695     0x7b, 0x7b, 0x5b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x3b, 0x1b, 0x1b,
696     0x1b, 0x73, 0x73, 0x73, 0x53, 0x53, 0x53, 0x53, 0x53, 0x33, 0x33,
697     0x33, 0x33, 0x13, 0x13, 0x13, 0x13, 0x13, 0xab, 0xab, 0xab, 0x8b,
698     0x8b, 0x8b, 0x8b, 0x6b, 0x6b, 0x6b, 0x6b, 0x4b, 0x4b, 0x4b, 0x4b,
699     0x2b, 0x2b, 0x2b, 0x2b, 0x0b, 0x0b, 0x0b, 0x0b, 0x83, 0x83, 0x63,
700     0x63, 0x63, 0x63, 0x43, 0x43, 0x43, 0x43, 0x23, 0x23, 0x23, 0x23,
701     0x03
702 };
703 
704 /*
705  * DSP pre-DAC gain values from highest to lowest power (values obtained
706  * from the reference driver.)
707  */
708 static const uint8_t wpi_dsp_gain_2ghz[WPI_MAX_PWR_INDEX + 1] = {
709     0x7f, 0x7f, 0x7f, 0x7f, 0x7d, 0x6e, 0x69, 0x62, 0x7d, 0x73, 0x6c,
710     0x63, 0x77, 0x6f, 0x69, 0x61, 0x5c, 0x6a, 0x64, 0x78, 0x71, 0x6b,
711     0x7d, 0x77, 0x70, 0x6a, 0x65, 0x61, 0x5b, 0x6b, 0x79, 0x73, 0x6d,
712     0x7f, 0x79, 0x73, 0x6c, 0x66, 0x60, 0x5c, 0x6e, 0x68, 0x62, 0x74,
713     0x7d, 0x77, 0x71, 0x6b, 0x65, 0x60, 0x71, 0x6a, 0x66, 0x5f, 0x71,
714     0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f,
715     0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66, 0x5f, 0x71, 0x6a, 0x66,
716     0x5f
717 };
718 
719 static const uint8_t wpi_dsp_gain_5ghz[WPI_MAX_PWR_INDEX + 1] = {
720     0x7f, 0x78, 0x72, 0x77, 0x65, 0x71, 0x66, 0x72, 0x67, 0x75, 0x6b,
721     0x63, 0x5c, 0x6c, 0x7d, 0x76, 0x6d, 0x66, 0x60, 0x5a, 0x68, 0x62,
722     0x5c, 0x76, 0x6f, 0x68, 0x7e, 0x79, 0x71, 0x69, 0x63, 0x76, 0x6f,
723     0x68, 0x62, 0x74, 0x6d, 0x66, 0x62, 0x5d, 0x71, 0x6b, 0x63, 0x78,
724     0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
725     0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x6b, 0x63, 0x78,
726     0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63, 0x78, 0x71, 0x6b, 0x63,
727     0x78
728 };
729 
730 
731 #define WPI_READ(sc, reg)						\
732     bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
733 
734 #define WPI_WRITE(sc, reg, val)						\
735     bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
736 
737 #define WPI_WRITE_REGION_4(sc, offset, datap, count)			\
738     bus_space_write_region_4((sc)->sc_st, (sc)->sc_sh, (offset),	\
739 			     (datap), (count))
740