1 /*- 2 * Copyright (c) 2011 Sandvine Incorporated ULC. 3 * Copyright (c) 2012 iXsystems, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 /* 28 * Support for Winbond watchdog. 29 * 30 * With minor abstractions it might be possible to add support for other 31 * different Winbond Super I/O chips as well. Winbond seems to have four 32 * different types of chips, four different ways to get into extended config 33 * mode. 34 * 35 * Note: there is no serialization between the debugging sysctl handlers and 36 * the watchdog functions and possibly others poking the registers at the same 37 * time. For that at least possibly interfering sysctls are hidden by default. 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <sys/param.h> 44 #include <sys/kernel.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/eventhandler.h> 48 #include <sys/lock.h> 49 #include <sys/module.h> 50 #include <sys/rman.h> 51 #include <sys/sbuf.h> 52 #include <sys/sysctl.h> 53 #include <sys/watchdog.h> 54 55 #include <isa/isavar.h> 56 57 #include <machine/bus.h> 58 #include <machine/resource.h> 59 60 /* 61 * Global registers. 62 */ 63 #define WB_DEVICE_ID_REG 0x20 /* Device ID */ 64 #define WB_DEVICE_REV_REG 0x21 /* Device revision */ 65 #define WB_CR26 0x26 /* Bit6: HEFRAS (base port selector) */ 66 67 /* LDN selection. */ 68 #define WB_LDN_REG 0x07 69 #define WB_LDN_REG_LDN8 0x08 /* GPIO 2, Watchdog */ 70 71 /* 72 * LDN8 (GPIO 2, Watchdog) specific registers and options. 73 */ 74 /* CR30: LDN8 activation control. */ 75 #define WB_LDN8_CR30 0x30 76 #define WB_LDN8_CR30_ACTIVE 0x01 /* 1: LD active */ 77 78 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */ 79 #define WB_LDN8_CRF5 0xF5 80 #define WB_LDN8_CRF5_SCALE 0x08 /* 0: 1s, 1: 60s */ 81 #define WB_LDN8_CRF5_KEYB_P20 0x04 /* 1: keyb P20 forces timeout */ 82 #define WB_LDN8_CRF5_KBRST 0x02 /* 1: timeout causes pin60 kbd reset */ 83 84 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */ 85 #define WB_LDN8_CRF6 0xF6 86 87 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */ 88 #define WB_LDN8_CRF7 0xF7 89 #define WB_LDN8_CRF7_MOUSE 0x80 /* 1: mouse irq resets wd timer */ 90 #define WB_LDN8_CRF7_KEYB 0x40 /* 1: keyb irq resets wd timer */ 91 #define WB_LDN8_CRF7_FORCE 0x20 /* 1: force timeout (self-clear) */ 92 #define WB_LDN8_CRF7_TS 0x10 /* 0: counting, 1: fired */ 93 #define WB_LDN8_CRF7_IRQS 0x0f /* irq source for watchdog, 2 == SMI */ 94 95 enum chips { w83627hf, w83627s, w83697hf, w83697ug, w83637hf, w83627thf, 96 w83687thf, w83627ehf, w83627dhg, w83627uhg, w83667hg, 97 w83627dhg_p, w83667hg_b, nct6775, nct6776, nct6779, nct6791, 98 nct6792, nct6102 }; 99 100 struct wb_softc { 101 device_t dev; 102 struct resource *portres; 103 bus_space_tag_t bst; 104 bus_space_handle_t bsh; 105 int rid; 106 eventhandler_tag ev_tag; 107 int (*ext_cfg_enter_f)(struct wb_softc *, u_short); 108 void (*ext_cfg_exit_f)(struct wb_softc *, u_short); 109 enum chips chip; 110 uint8_t ctl_reg; 111 uint8_t time_reg; 112 uint8_t csr_reg; 113 int debug_verbose; 114 115 /* 116 * Special feature to let the watchdog fire at a different 117 * timeout as set by watchdog(4) but still use that API to 118 * re-load it periodically. 119 */ 120 unsigned int timeout_override; 121 122 /* 123 * Space to save current state temporary and for sysctls. 124 * We want to know the timeout value and usually need two 125 * additional registers for options. Do not name them by 126 * register as these might be different by chip. 127 */ 128 uint8_t reg_timeout; 129 uint8_t reg_1; 130 uint8_t reg_2; 131 }; 132 133 static int ext_cfg_enter_0x87_0x87(struct wb_softc *, u_short); 134 static void ext_cfg_exit_0xaa(struct wb_softc *, u_short); 135 136 struct winbond_superio_cfg { 137 uint8_t efer; /* and efir */ 138 int (*ext_cfg_enter_f)(struct wb_softc *, u_short); 139 void (*ext_cfg_exit_f)(struct wb_softc *, u_short); 140 } probe_addrs[] = { 141 { 142 .efer = 0x2e, 143 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87, 144 .ext_cfg_exit_f = ext_cfg_exit_0xaa, 145 }, 146 { 147 .efer = 0x4e, 148 .ext_cfg_enter_f = ext_cfg_enter_0x87_0x87, 149 .ext_cfg_exit_f = ext_cfg_exit_0xaa, 150 }, 151 }; 152 153 struct winbond_vendor_device_id { 154 uint8_t device_id; 155 enum chips chip; 156 const char * descr; 157 } wb_devs[] = { 158 { 159 .device_id = 0x52, 160 .chip = w83627hf, 161 .descr = "Winbond 83627HF/F/HG/G", 162 }, 163 { 164 .device_id = 0x59, 165 .chip = w83627s, 166 .descr = "Winbond 83627S", 167 }, 168 { 169 .device_id = 0x60, 170 .chip = w83697hf, 171 .descr = "Winbond 83697HF", 172 }, 173 { 174 .device_id = 0x68, 175 .chip = w83697ug, 176 .descr = "Winbond 83697UG", 177 }, 178 { 179 .device_id = 0x70, 180 .chip = w83637hf, 181 .descr = "Winbond 83637HF", 182 }, 183 { 184 .device_id = 0x82, 185 .chip = w83627thf, 186 .descr = "Winbond 83627THF", 187 }, 188 { 189 .device_id = 0x85, 190 .chip = w83687thf, 191 .descr = "Winbond 83687THF", 192 }, 193 { 194 .device_id = 0x88, 195 .chip = w83627ehf, 196 .descr = "Winbond 83627EHF", 197 }, 198 { 199 .device_id = 0xa0, 200 .chip = w83627dhg, 201 .descr = "Winbond 83627DHG", 202 }, 203 { 204 .device_id = 0xa2, 205 .chip = w83627uhg, 206 .descr = "Winbond 83627UHG", 207 }, 208 { 209 .device_id = 0xa5, 210 .chip = w83667hg, 211 .descr = "Winbond 83667HG", 212 }, 213 { 214 .device_id = 0xb0, 215 .chip = w83627dhg_p, 216 .descr = "Winbond 83627DHG-P", 217 }, 218 { 219 .device_id = 0xb3, 220 .chip = w83667hg_b, 221 .descr = "Winbond 83667HG-B", 222 }, 223 { 224 .device_id = 0xb4, 225 .chip = nct6775, 226 .descr = "Nuvoton NCT6775", 227 }, 228 { 229 .device_id = 0xc3, 230 .chip = nct6776, 231 .descr = "Nuvoton NCT6776", 232 }, 233 { 234 .device_id = 0xc4, 235 .chip = nct6102, 236 .descr = "Nuvoton NCT6102", 237 }, 238 { 239 .device_id = 0xc5, 240 .chip = nct6779, 241 .descr = "Nuvoton NCT6779", 242 }, 243 { 244 .device_id = 0xc8, 245 .chip = nct6791, 246 .descr = "Nuvoton NCT6791", 247 }, 248 { 249 .device_id = 0xc9, 250 .chip = nct6792, 251 .descr = "Nuvoton NCT6792", 252 }, 253 }; 254 255 static void 256 write_efir_1(struct wb_softc *sc, u_short baseport, uint8_t value) 257 { 258 259 MPASS(sc != NULL || baseport != 0); 260 if (sc != NULL) 261 bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value)); 262 else 263 outb(baseport, value); 264 } 265 266 static uint8_t __unused 267 read_efir_1(struct wb_softc *sc, u_short baseport) 268 { 269 270 MPASS(sc != NULL || baseport != 0); 271 if (sc != NULL) 272 return (bus_space_read_1((sc)->bst, (sc)->bsh, 0)); 273 else 274 return (inb(baseport)); 275 } 276 277 static void 278 write_efdr_1(struct wb_softc *sc, u_short baseport, uint8_t value) 279 { 280 281 MPASS(sc != NULL || baseport != 0); 282 if (sc != NULL) 283 bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value)); 284 else 285 outb(baseport + 1, value); 286 } 287 288 static uint8_t 289 read_efdr_1(struct wb_softc *sc, u_short baseport) 290 { 291 292 MPASS(sc != NULL || baseport != 0); 293 if (sc != NULL) 294 return (bus_space_read_1((sc)->bst, (sc)->bsh, 1)); 295 else 296 return (inb(baseport + 1)); 297 } 298 299 static void 300 write_reg(struct wb_softc *sc, uint8_t reg, uint8_t value) 301 { 302 303 write_efir_1(sc, 0, reg); 304 write_efdr_1(sc, 0, value); 305 } 306 307 static uint8_t 308 read_reg(struct wb_softc *sc, uint8_t reg) 309 { 310 311 write_efir_1(sc, 0, reg); 312 return (read_efdr_1(sc, 0)); 313 } 314 315 /* 316 * Return the watchdog related registers as we last read them. This will 317 * usually not give the current timeout or state on whether the watchdog 318 * fired. 319 */ 320 static int 321 sysctl_wb_debug(SYSCTL_HANDLER_ARGS) 322 { 323 struct wb_softc *sc; 324 struct sbuf sb; 325 int error; 326 327 sc = arg1; 328 329 sbuf_new_for_sysctl(&sb, NULL, 64, req); 330 331 sbuf_printf(&sb, "LDN8 (GPIO2, Watchdog): "); 332 sbuf_printf(&sb, "CR%02X 0x%02x ", sc->ctl_reg, sc->reg_1); 333 sbuf_printf(&sb, "CR%02X 0x%02x ", sc->time_reg, sc->reg_timeout); 334 sbuf_printf(&sb, "CR%02X 0x%02x", sc->csr_reg, sc->reg_2); 335 336 error = sbuf_finish(&sb); 337 sbuf_delete(&sb); 338 return (error); 339 } 340 341 /* 342 * Read the current values before returning them. Given this might poke 343 * the registers the same time as the watchdog, this sysctl handler should 344 * be marked CTLFLAG_SKIP to not show up by default. 345 */ 346 static int 347 sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS) 348 { 349 struct wb_softc *sc; 350 351 sc = arg1; 352 353 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0) 354 return (ENXIO); 355 356 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */ 357 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8); 358 359 sc->reg_1 = read_reg(sc, sc->ctl_reg); 360 sc->reg_timeout = read_reg(sc, sc->time_reg); 361 sc->reg_2 = read_reg(sc, sc->csr_reg); 362 363 (*sc->ext_cfg_exit_f)(sc, 0); 364 365 return (sysctl_wb_debug(oidp, arg1, arg2, req)); 366 } 367 368 /* 369 * Sysctl handlers to force a watchdog timeout or to test the NMI functionality 370 * works as expetced. 371 * For testing we could set a test_nmi flag in the softc that, in case of NMI, a 372 * callback function from trap.c could check whether we fired and not report the 373 * timeout but clear the flag for the sysctl again. This is interesting given a 374 * lot of boards have jumpers to change the action on watchdog timeout or 375 * disable the watchdog completely. 376 * XXX-BZ notyet: currently no general infrastructure exists to do this. 377 */ 378 static int 379 sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS) 380 { 381 struct wb_softc *sc; 382 int error, test, val; 383 384 sc = arg1; 385 test = arg2; 386 387 #ifdef notyet 388 val = sc->test_nmi; 389 #else 390 val = 0; 391 #endif 392 error = sysctl_handle_int(oidp, &val, 0, req); 393 if (error || !req->newptr) 394 return (error); 395 396 #ifdef notyet 397 /* Manually clear the test for a value of 0 and do nothing else. */ 398 if (test && val == 0) { 399 sc->test_nmi = 0; 400 return (0); 401 } 402 #endif 403 404 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0) 405 return (ENXIO); 406 407 #ifdef notyet 408 /* 409 * If we are testing the NMI functionality, set the flag before 410 * forcing the timeout. 411 */ 412 if (test) 413 sc->test_nmi = 1; 414 #endif 415 416 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */ 417 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8); 418 419 /* Force watchdog to fire. */ 420 sc->reg_2 = read_reg(sc, sc->csr_reg); 421 sc->reg_2 |= WB_LDN8_CRF7_FORCE; 422 write_reg(sc, sc->csr_reg, sc->reg_2); 423 424 (*sc->ext_cfg_exit_f)(sc, 0); 425 426 return (0); 427 } 428 429 /* 430 * Print current watchdog state. 431 * 432 * Note: it is the responsibility of the caller to update the registers 433 * upfront. 434 */ 435 static void 436 wb_print_state(struct wb_softc *sc, const char *msg) 437 { 438 439 device_printf(sc->dev, "%s%sWatchdog %sabled. %s" 440 "Scaling by %ds, timer at %d (%s=%ds%s). " 441 "CRF5 0x%02x CRF7 0x%02x\n", 442 (msg != NULL) ? msg : "", (msg != NULL) ? ": " : "", 443 (sc->reg_timeout > 0x00) ? "en" : "dis", 444 (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "", 445 (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1, 446 sc->reg_timeout, 447 (sc->reg_timeout > 0x00) ? "<" : "", 448 sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1), 449 (sc->reg_timeout > 0x00) ? " left" : "", 450 sc->reg_1, sc->reg_2); 451 } 452 453 /* 454 * Functions to enter and exit extended function mode. Possibly shared 455 * between different chips. 456 */ 457 static int 458 ext_cfg_enter_0x87_0x87(struct wb_softc *sc, u_short baseport) 459 { 460 461 /* 462 * Enable extended function mode. 463 * Winbond does not allow us to validate so always return success. 464 */ 465 write_efir_1(sc, baseport, 0x87); 466 write_efir_1(sc, baseport, 0x87); 467 468 return (0); 469 } 470 471 static void 472 ext_cfg_exit_0xaa(struct wb_softc *sc, u_short baseport) 473 { 474 475 write_efir_1(sc, baseport, 0xaa); 476 } 477 478 /* 479 * (Re)load the watchdog counter depending on timeout. A timeout of 0 will 480 * disable the watchdog. 481 */ 482 static int 483 wb_set_watchdog(struct wb_softc *sc, unsigned int timeout) 484 { 485 486 if (timeout != 0) { 487 /* 488 * In case an override is set, let it override. It may lead 489 * to strange results as we do not check the input of the sysctl. 490 */ 491 if (sc->timeout_override > 0) 492 timeout = sc->timeout_override; 493 494 /* Make sure we support the requested timeout. */ 495 if (timeout > 255 * 60) 496 return (EINVAL); 497 } 498 499 if (sc->debug_verbose) 500 wb_print_state(sc, "Before watchdog counter (re)load"); 501 502 if ((*sc->ext_cfg_enter_f)(sc, 0) != 0) 503 return (ENXIO); 504 505 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */ 506 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8); 507 508 /* Disable and validate or arm/reset watchdog. */ 509 if (timeout == 0) { 510 /* Disable watchdog. */ 511 write_reg(sc, sc->time_reg, 0x00); 512 sc->reg_timeout = read_reg(sc, sc->time_reg); 513 (*sc->ext_cfg_exit_f)(sc, 0); 514 515 /* Re-check. */ 516 if (sc->reg_timeout != 0x00) { 517 device_printf(sc->dev, "Failed to disable watchdog: " 518 "0x%02x.\n", sc->reg_timeout); 519 return (EIO); 520 } 521 522 } else { 523 /* Read current scaling factor. */ 524 sc->reg_1 = read_reg(sc, sc->ctl_reg); 525 526 if (timeout > 255) { 527 /* Set scaling factor to 60s. */ 528 sc->reg_1 |= WB_LDN8_CRF5_SCALE; 529 sc->reg_timeout = (timeout / 60); 530 if (timeout % 60) 531 sc->reg_timeout++; 532 } else { 533 /* Set scaling factor to 1s. */ 534 sc->reg_1 &= ~WB_LDN8_CRF5_SCALE; 535 sc->reg_timeout = timeout; 536 } 537 538 /* In case we fired before we need to clear to fire again. */ 539 sc->reg_2 = read_reg(sc, sc->csr_reg); 540 if (sc->reg_2 & WB_LDN8_CRF7_TS) { 541 sc->reg_2 &= ~WB_LDN8_CRF7_TS; 542 write_reg(sc, sc->csr_reg, sc->reg_2); 543 } 544 545 /* Write back scaling factor. */ 546 write_reg(sc, sc->ctl_reg, sc->reg_1); 547 548 /* Set timer and arm/reset the watchdog. */ 549 write_reg(sc, sc->time_reg, sc->reg_timeout); 550 (*sc->ext_cfg_exit_f)(sc, 0); 551 } 552 553 if (sc->debug_verbose) 554 wb_print_state(sc, "After watchdog counter (re)load"); 555 556 return (0); 557 } 558 559 /* 560 * watchdog(9) EVENTHANDLER function implementation to (re)load the counter 561 * with the given timeout or disable the watchdog. 562 */ 563 static void 564 wb_watchdog_fn(void *private, u_int cmd, int *error) 565 { 566 struct wb_softc *sc; 567 unsigned int timeout; 568 int e; 569 570 sc = private; 571 KASSERT(sc != NULL, ("%s: watchdog handler function called without " 572 "softc.", __func__)); 573 574 cmd &= WD_INTERVAL; 575 if (cmd > 0 && cmd <= 63) { 576 /* Reset (and arm) watchdog. */ 577 timeout = ((uint64_t)1 << cmd) / 1000000000; 578 if (timeout == 0) 579 timeout = 1; 580 e = wb_set_watchdog(sc, timeout); 581 if (e == 0) { 582 if (error != NULL) 583 *error = 0; 584 } else { 585 /* On error, try to make sure the WD is disabled. */ 586 wb_set_watchdog(sc, 0); 587 } 588 589 } else { 590 /* Disable watchdog. */ 591 e = wb_set_watchdog(sc, 0); 592 if (e != 0 && cmd == 0 && error != NULL) { 593 /* Failed to disable watchdog. */ 594 *error = EOPNOTSUPP; 595 } 596 } 597 } 598 599 /* 600 * Probe/attach the Winbond Super I/O chip. 601 * 602 * Initial abstraction to possibly support more chips: 603 * - Iterate over the well known base ports, try to enable extended function 604 * mode and read and match the device ID and device revision. Unfortunately 605 * the Vendor ID is in the hardware monitoring section accessible by different 606 * base ports only. 607 * - Also HEFRAS, which would tell use the base port, is only accessible after 608 * entering extended function mode, for which the base port is needed. 609 * At least check HEFRAS to match the current base port we are probing. 610 * - On match set the description, remember functions to enter/exit extended 611 * function mode as well as the base port. 612 */ 613 static int 614 wb_probe_enable(device_t dev, int probe) 615 { 616 struct wb_softc *sc; 617 int error, found, i, j; 618 uint8_t dev_id, dev_rev, cr26; 619 char buf[128]; 620 621 if (dev == NULL) 622 sc = NULL; 623 else { 624 sc = device_get_softc(dev); 625 bzero(sc, sizeof(*sc)); 626 sc->dev = dev; 627 } 628 629 error = ENXIO; 630 found = 0; 631 for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) { 632 633 if (sc != NULL) { 634 /* Allocate bus resources for IO index/data register access. */ 635 sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid, 636 probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE); 637 if (sc->portres == NULL) 638 continue; 639 sc->bst = rman_get_bustag(sc->portres); 640 sc->bsh = rman_get_bushandle(sc->portres); 641 } 642 643 error = (*probe_addrs[i].ext_cfg_enter_f)(sc, probe_addrs[i].efer); 644 if (error != 0) 645 goto cleanup; 646 647 /* Identify the SuperIO chip. */ 648 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_ID_REG); 649 dev_id = read_efdr_1(sc, probe_addrs[i].efer); 650 write_efir_1(sc, probe_addrs[i].efer, WB_DEVICE_REV_REG); 651 dev_rev = read_efdr_1(sc, probe_addrs[i].efer); 652 write_efir_1(sc, probe_addrs[i].efer, WB_CR26); 653 cr26 = read_efdr_1(sc, probe_addrs[i].efer); 654 655 if (dev_id == 0xff && dev_rev == 0xff) 656 goto cleanup; 657 658 /* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */ 659 if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) || 660 ((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) { 661 if (dev != NULL) 662 device_printf(dev, "HEFRAS and EFER do not " 663 "align: EFER 0x%02x DevID 0x%02x DevRev " 664 "0x%02x CR26 0x%02x\n", 665 probe_addrs[i].efer, dev_id, dev_rev, cr26); 666 goto cleanup; 667 } 668 669 for (j = 0; j < sizeof(wb_devs) / sizeof(*wb_devs); j++) { 670 if (wb_devs[j].device_id == dev_id) { 671 found = 1; 672 break; 673 } 674 } 675 676 if (probe && dev != NULL) { 677 snprintf(buf, sizeof(buf), 678 "%s (0x%02x/0x%02x) Watchdog Timer", 679 found ? wb_devs[j].descr : 680 "Unknown Winbond/Nuvoton", dev_id, dev_rev); 681 device_set_desc_copy(dev, buf); 682 } 683 684 /* If this is hinted attach, try to guess the model. */ 685 if (dev != NULL && !found) { 686 found = 1; 687 j = 0; 688 } 689 690 cleanup: 691 if (probe || !found) { 692 (*probe_addrs[i].ext_cfg_exit_f)(sc, probe_addrs[i].efer); 693 if (sc != NULL) 694 (void) bus_release_resource(dev, SYS_RES_IOPORT, 695 sc->rid, sc->portres); 696 } 697 698 /* 699 * Stop probing if have successfully identified the SuperIO. 700 * Remember the extended function mode enter/exit functions 701 * for operations. 702 */ 703 if (found) { 704 if (sc != NULL) { 705 sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f; 706 sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f; 707 sc->chip = wb_devs[j].chip; 708 sc->ctl_reg = 0xf5; 709 sc->time_reg = 0xf6; 710 sc->csr_reg = 0xf7; 711 if (sc->chip == w83697hf || 712 sc->chip == w83697ug) { 713 sc->ctl_reg = 0xf3; 714 sc->time_reg = 0xf4; 715 } else if (sc->chip == nct6102) { 716 sc->ctl_reg = 0xf0; 717 sc->time_reg = 0xf1; 718 sc->csr_reg = 0xf2; 719 } 720 } 721 return (BUS_PROBE_SPECIFIC); 722 } else 723 error = ENXIO; 724 } 725 726 return (error); 727 } 728 729 static void 730 wb_identify(driver_t *driver, device_t parent) 731 { 732 733 if (device_find_child(parent, driver->name, 0) == NULL) { 734 if (wb_probe_enable(NULL, 1) <= 0) 735 BUS_ADD_CHILD(parent, 0, driver->name, 0); 736 } 737 } 738 739 static int 740 wb_probe(device_t dev) 741 { 742 743 /* Make sure we do not claim some ISA PNP device. */ 744 if (isa_get_logicalid(dev) != 0) 745 return (ENXIO); 746 747 return (wb_probe_enable(dev, 1)); 748 } 749 750 static int 751 wb_attach(device_t dev) 752 { 753 struct wb_softc *sc; 754 struct sysctl_ctx_list *sctx; 755 struct sysctl_oid *soid; 756 unsigned long timeout; 757 int error; 758 uint8_t t; 759 760 error = wb_probe_enable(dev, 0); 761 if (error > 0) 762 return (ENXIO); 763 764 sc = device_get_softc(dev); 765 KASSERT(sc->ext_cfg_enter_f != NULL && sc->ext_cfg_exit_f != NULL, 766 ("%s: successfull probe result but not setup correctly", __func__)); 767 768 /* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */ 769 write_reg(sc, WB_LDN_REG, WB_LDN_REG_LDN8); 770 771 /* Make sure WDT is enabled. */ 772 write_reg(sc, WB_LDN8_CR30, 773 read_reg(sc, WB_LDN8_CR30) | WB_LDN8_CR30_ACTIVE); 774 775 switch (sc->chip) { 776 case w83627hf: 777 case w83627s: 778 t = read_reg(sc, 0x2B) & ~0x10; 779 write_reg(sc, 0x2B, t); /* set GPIO24 to WDT0 */ 780 break; 781 case w83697hf: 782 /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ 783 t = read_reg(sc, 0x29) & ~0x60; 784 t |= 0x20; 785 write_reg(sc, 0x29, t); 786 break; 787 case w83697ug: 788 /* Set pin 118 to WDTO# mode */ 789 t = read_reg(sc, 0x2b) & ~0x04; 790 write_reg(sc, 0x2b, t); 791 break; 792 case w83627thf: 793 t = (read_reg(sc, 0x2B) & ~0x08) | 0x04; 794 write_reg(sc, 0x2B, t); /* set GPIO3 to WDT0 */ 795 break; 796 case w83627dhg: 797 case w83627dhg_p: 798 t = read_reg(sc, 0x2D) & ~0x01; /* PIN77 -> WDT0# */ 799 write_reg(sc, 0x2D, t); /* set GPIO5 to WDT0 */ 800 t = read_reg(sc, sc->ctl_reg); 801 t |= 0x02; /* enable the WDTO# output low pulse 802 * to the KBRST# pin */ 803 write_reg(sc, sc->ctl_reg, t); 804 break; 805 case w83637hf: 806 break; 807 case w83687thf: 808 t = read_reg(sc, 0x2C) & ~0x80; /* PIN47 -> WDT0# */ 809 write_reg(sc, 0x2C, t); 810 break; 811 case w83627ehf: 812 case w83627uhg: 813 case w83667hg: 814 case w83667hg_b: 815 case nct6775: 816 case nct6776: 817 case nct6779: 818 case nct6791: 819 case nct6792: 820 case nct6102: 821 /* 822 * These chips have a fixed WDTO# output pin (W83627UHG), 823 * or support more than one WDTO# output pin. 824 * Don't touch its configuration, and hope the BIOS 825 * does the right thing. 826 */ 827 t = read_reg(sc, sc->ctl_reg); 828 t |= 0x02; /* enable the WDTO# output low pulse 829 * to the KBRST# pin */ 830 write_reg(sc, sc->ctl_reg, t); 831 break; 832 default: 833 break; 834 } 835 836 /* Read the current watchdog configuration. */ 837 sc->reg_1 = read_reg(sc, sc->ctl_reg); 838 sc->reg_timeout = read_reg(sc, sc->time_reg); 839 sc->reg_2 = read_reg(sc, sc->csr_reg); 840 841 /* Print current state if bootverbose or watchdog already enabled. */ 842 if (bootverbose || (sc->reg_timeout > 0x00)) 843 wb_print_state(sc, "Before watchdog attach"); 844 845 sc->reg_1 &= ~WB_LDN8_CRF5_KEYB_P20; 846 sc->reg_1 |= WB_LDN8_CRF5_KBRST; 847 write_reg(sc, sc->ctl_reg, sc->reg_1); 848 849 /* 850 * Clear a previous watchdog timeout event (if still set). 851 * Disable timer reset on mouse interrupts. Leave reset on keyboard, 852 * since one of my boards is getting stuck in reboot without it. 853 */ 854 sc->reg_2 &= ~(WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_TS); 855 write_reg(sc, sc->csr_reg, sc->reg_2); 856 857 (*sc->ext_cfg_exit_f)(sc, 0); 858 859 /* Read global timeout override tunable, Add per device sysctls. */ 860 if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) { 861 if (timeout > 0) 862 sc->timeout_override = timeout; 863 } 864 sctx = device_get_sysctl_ctx(dev); 865 soid = device_get_sysctl_tree(dev); 866 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 867 "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0, 868 "Timeout in seconds overriding default watchdog timeout"); 869 SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 870 "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0, 871 "Enables extra debugging information"); 872 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug", 873 CTLTYPE_STRING|CTLFLAG_RD, sc, 0, sysctl_wb_debug, "A", 874 "Selected register information from last change by driver"); 875 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug_current", 876 CTLTYPE_STRING|CTLFLAG_RD|CTLFLAG_SKIP, sc, 0, 877 sysctl_wb_debug_current, "A", 878 "Selected register information (may interfere)"); 879 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "force_timeout", 880 CTLTYPE_INT|CTLFLAG_RW|CTLFLAG_SKIP, sc, 0, 881 sysctl_wb_force_test_nmi, "I", "Enable to force watchdog to fire."); 882 883 /* Register watchdog. */ 884 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc, 885 0); 886 887 if (bootverbose) 888 wb_print_state(sc, "After watchdog attach"); 889 890 return (0); 891 } 892 893 static int 894 wb_detach(device_t dev) 895 { 896 struct wb_softc *sc; 897 898 sc = device_get_softc(dev); 899 900 /* Unregister and stop the watchdog if running. */ 901 if (sc->ev_tag) 902 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 903 wb_set_watchdog(sc, 0); 904 905 /* Disable extended function mode. */ 906 (*sc->ext_cfg_exit_f)(sc, 0); 907 908 /* Cleanup resources. */ 909 (void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres); 910 911 /* Bus subroutines take care of sysctls already. */ 912 913 return (0); 914 } 915 916 static device_method_t wb_methods[] = { 917 /* Device interface */ 918 DEVMETHOD(device_identify, wb_identify), 919 DEVMETHOD(device_probe, wb_probe), 920 DEVMETHOD(device_attach, wb_attach), 921 DEVMETHOD(device_detach, wb_detach), 922 923 DEVMETHOD_END 924 }; 925 926 static driver_t wb_isa_driver = { 927 "wbwd", 928 wb_methods, 929 sizeof(struct wb_softc) 930 }; 931 932 static devclass_t wb_devclass; 933 934 DRIVER_MODULE(wb, isa, wb_isa_driver, wb_devclass, NULL, NULL); 935