xref: /freebsd/sys/dev/wbwd/wbwd.c (revision 56961fd7949de755f95a60fe8ac936f81e953f5b)
1 /*-
2  * Copyright (c) 2011 Sandvine Incorporated ULC.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 /*
27  * Support for Winbond watchdog.
28  *
29  * With minor abstractions it might be possible to add support for other
30  * different Winbond Super I/O chips as well.  Winbond seems to have four
31  * different types of chips, four different ways to get into extended config
32  * mode.
33  *
34  * Note: there is no serialization between the debugging sysctl handlers and
35  * the watchdog functions and possibly others poking the registers at the same
36  * time.  For that at least possibly interfering sysctls are hidden by default.
37  */
38 
39 #include <sys/cdefs.h>
40 __FBSDID("$FreeBSD$");
41 
42 #include <sys/param.h>
43 #include <sys/kernel.h>
44 #include <sys/systm.h>
45 #include <sys/bus.h>
46 #include <sys/eventhandler.h>
47 #include <sys/lock.h>
48 #include <sys/module.h>
49 #include <sys/rman.h>
50 #include <sys/sbuf.h>
51 #include <sys/sysctl.h>
52 #include <sys/watchdog.h>
53 
54 #include <isa/isavar.h>
55 
56 #include <machine/bus.h>
57 #include <machine/resource.h>
58 
59 /*
60  * Global registers.
61  */
62 #define	WB_DEVICE_ID_REG	0x20	/* Device ID */
63 #define	WB_DEVICE_REV_REG	0x21	/* Device revision */
64 #define	WB_CR26			0x26	/* Bit6: HEFRAS (base port selector) */
65 
66 /* LDN selection. */
67 #define	WB_LDN_REG		0x07
68 #define	WB_LDN_REG_LDN8		0x08	/* GPIO 2, Watchdog */
69 
70 /*
71  * LDN8 (GPIO 2, Watchdog) specific registers and options.
72  */
73 /* CR30: LDN8 activation control. */
74 #define	WB_LDN8_CR30		0x30
75 #define	WB_LDN8_CR30_ACTIVE	0x01	/* 1: LD active */
76 
77 /* CRF5: Watchdog scale, P20. Mapped to reg_1. */
78 #define	WB_LDN8_CRF5		0xF5
79 #define	WB_LDN8_CRF5_SCALE	0x08	/* 0: 1s, 1: 60s */
80 #define	WB_LDN8_CRF5_KEYB_P20	0x04	/* 1: keyb P20 forces timeout */
81 #define	WB_LDN8_CRF5_KBRST	0x02	/* 1: timeout causes pin60 kbd reset */
82 
83 /* CRF6: Watchdog Timeout (0 == off). Mapped to reg_timeout. */
84 #define	WB_LDN8_CRF6		0xF6
85 
86 /* CRF7: Watchdog mouse, keyb, force, .. Mapped to reg_2. */
87 #define	WB_LDN8_CRF7		0xF7
88 #define	WB_LDN8_CRF7_MOUSE	0x80	/* 1: mouse irq resets wd timer */
89 #define	WB_LDN8_CRF7_KEYB	0x40	/* 1: keyb irq resets wd timer */
90 #define	WB_LDN8_CRF7_FORCE	0x20	/* 1: force timeout (self-clear) */
91 #define	WB_LDN8_CRF7_TS		0x10	/* 0: counting, 1: fired */
92 #define	WB_LDN8_CRF7_IRQS	0x0f	/* irq source for watchdog, 2 == SMI */
93 #define	WB_LDN8_CRF7_CLEAR_MASK	\
94     (WB_LDN8_CRF7_MOUSE|WB_LDN8_CRF7_KEYB|WB_LDN8_CRF7_TS|WB_LDN8_CRF7_IRQS)
95 
96 #define	write_efir_1(sc, value)						\
97 	bus_space_write_1((sc)->bst, (sc)->bsh, 0, (value))
98 #define	read_efir_1(sc)							\
99 	bus_space_read_1((sc)->bst, (sc)->bsh, 0)
100 #define	write_efdr_1(sc, value)						\
101 	bus_space_write_1((sc)->bst, (sc)->bsh, 1, (value))
102 #define	read_efdr_1(sc)							\
103 	bus_space_read_1((sc)->bst, (sc)->bsh, 1)
104 
105 struct wb_softc {
106 	device_t		dev;
107 	struct resource		*portres;
108 	bus_space_tag_t		bst;
109 	bus_space_handle_t	bsh;
110 	int			rid;
111 	eventhandler_tag	ev_tag;
112 	int			(*ext_cfg_enter_f)(struct wb_softc *);
113 	void			(*ext_cfg_exit_f)(struct wb_softc *);
114 	int			debug_verbose;
115 
116 	/*
117 	 * Special feature to let the watchdog fire at a different
118 	 * timeout as set by watchdog(4) but still use that API to
119 	 * re-load it periodically.
120 	 */
121 	unsigned int		timeout_override;
122 
123 	/*
124 	 * Space to save current state temporary and for sysctls.
125 	 * We want to know the timeout value and usually need two
126 	 * additional registers for options. Do not name them by
127 	 * register as these might be different by chip.
128 	 */
129 	uint8_t			reg_timeout;
130 	uint8_t			reg_1;
131 	uint8_t			reg_2;
132 };
133 
134 static int	ext_cfg_enter_0x87_0x87(struct wb_softc *);
135 static void	ext_cfg_exit_0xaa(struct wb_softc *);
136 
137 struct winbond_superio_cfg {
138 	uint8_t			efer;	/* and efir */
139 	int			(*ext_cfg_enter_f)(struct wb_softc *);
140 	void			(*ext_cfg_exit_f)(struct wb_softc *);
141 } probe_addrs[] = {
142 	{
143 		.efer			= 0x2e,
144 		.ext_cfg_enter_f	= ext_cfg_enter_0x87_0x87,
145 		.ext_cfg_exit_f		= ext_cfg_exit_0xaa,
146 	},
147 	{
148 		.efer			= 0x4e,
149 		.ext_cfg_enter_f	= ext_cfg_enter_0x87_0x87,
150 		.ext_cfg_exit_f		= ext_cfg_exit_0xaa,
151 	},
152 };
153 
154 struct winbond_vendor_device_id {
155 	uint16_t		vendor_id;
156 	uint8_t			device_id;
157 	uint8_t			device_rev;
158 	const char *		descr;
159 } wb_devs[] = {
160 	{
161 		.vendor_id	= 0x5ca3,
162 		.device_id	= 0x52,
163 		.device_rev	= 0x17,
164 		.descr		= "Winbond 83627HF/F/HG/G Rev. G",
165 	},
166 	{
167 		.vendor_id	= 0x5ca3,
168 		.device_id	= 0x52,
169 		.device_rev	= 0x3a,
170 		.descr		= "Winbond 83627HF/F/HG/G Rev. J",
171 	},
172 	{
173 		.vendor_id	= 0x5ca3,
174 		.device_id	= 0x52,
175 		.device_rev	= 0x41,
176 		.descr		= "Winbond 83627HF/F/HG/G Rev. UD-A",
177 	},
178 	{
179 		.vendor_id	= 0x5ca3,
180 		.device_id	= 0xa0,
181 		.device_rev	= 0x25,
182 		.descr		= "Winbond 83627DHG IC ver. 5",
183 	},
184 	{
185 		.vendor_id	= 0x5ca3,
186 		.device_id	= 0xb0,
187 		.device_rev	= 0x73,
188 		.descr		= "Winbond 83627DHG-P",
189 	},
190 };
191 
192 /*
193  * Return the watchdog related registers as we last read them.  This will
194  * usually not give the current timeout or state on whether the watchdog
195  * fired.
196  */
197 static int
198 sysctl_wb_debug(SYSCTL_HANDLER_ARGS)
199 {
200 	struct wb_softc *sc;
201 	struct sbuf sb;
202 	int error;
203 
204 	sc = arg1;
205 
206 	sbuf_new_for_sysctl(&sb, NULL, 64, req);
207 
208 	sbuf_printf(&sb, "LDN8 (GPIO2, Watchdog): ");
209 	sbuf_printf(&sb, "CRF5 0x%02x ", sc->reg_1);
210 	sbuf_printf(&sb, "CRF6 0x%02x ", sc->reg_timeout);
211 	sbuf_printf(&sb, "CRF7 0x%02x", sc->reg_2);
212 
213 	error = sbuf_finish(&sb);
214 	sbuf_delete(&sb);
215 	return (error);
216 }
217 
218 /*
219  * Read the current values before returning them.  Given this might poke
220  * the registers the same time as the watchdog, this sysctl handler should
221  * be marked CTLFLAG_SKIP to not show up by default.
222  */
223 static int
224 sysctl_wb_debug_current(SYSCTL_HANDLER_ARGS)
225 {
226 	struct wb_softc *sc;
227 
228 	sc = arg1;
229 
230 	/*
231 	 * Enter extended function mode in case someone else has been
232 	 * poking on the registers.  We will not leave it though.
233 	 */
234 	if ((*sc->ext_cfg_enter_f)(sc) != 0)
235 		return (ENXIO);
236 
237 	/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
238 	write_efir_1(sc, WB_LDN_REG);
239 	write_efdr_1(sc, WB_LDN_REG_LDN8);
240 
241 	write_efir_1(sc, WB_LDN8_CRF5);
242 	sc->reg_1 = read_efdr_1(sc);
243 	write_efir_1(sc, WB_LDN8_CRF6);
244 	sc->reg_timeout = read_efdr_1(sc);
245 	write_efir_1(sc, WB_LDN8_CRF7);
246 	sc->reg_2 = read_efdr_1(sc);
247 
248 	return (sysctl_wb_debug(oidp, arg1, arg2, req));
249 }
250 
251 /*
252  * Sysctl handlers to force a watchdog timeout or to test the NMI functionality
253  * works as expetced.
254  * For testing we could set a test_nmi flag in the softc that, in case of NMI, a
255  * callback function from trap.c could check whether we fired and not report the
256  * timeout but clear the flag for the sysctl again.  This is interesting given a
257  * lot of boards have jumpers to change the action on watchdog timeout or
258  * disable the watchdog completely.
259  * XXX-BZ notyet: currently no general infrastructure exists to do this.
260  */
261 static int
262 sysctl_wb_force_test_nmi(SYSCTL_HANDLER_ARGS)
263 {
264 	struct wb_softc *sc;
265 	int error, test, val;
266 
267 	sc = arg1;
268 	test = arg2;
269 
270 #ifdef notyet
271 	val = sc->test_nmi;
272 #else
273 	val = 0;
274 #endif
275 	error = sysctl_handle_int(oidp, &val, 0, req);
276         if (error || !req->newptr)
277                 return (error);
278 
279 #ifdef notyet
280 	/* Manually clear the test for a value of 0 and do nothing else. */
281 	if (test && val == 0) {
282 		sc->test_nmi = 0;
283 		return (0);
284 	}
285 #endif
286 
287 	/*
288 	 * Enter extended function mode in case someone else has been
289 	 * poking on the registers.  We will not leave it though.
290 	 */
291 	if ((*sc->ext_cfg_enter_f)(sc) != 0)
292 		return (ENXIO);
293 
294 #ifdef notyet
295 	/*
296 	 * If we are testing the NMI functionality, set the flag before
297 	 * forcing the timeout.
298 	 */
299 	if (test)
300 		sc->test_nmi = 1;
301 #endif
302 
303 	/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
304 	write_efir_1(sc, WB_LDN_REG);
305 	write_efdr_1(sc, WB_LDN_REG_LDN8);
306 
307 	/* Force watchdog to fire. */
308 	write_efir_1(sc, WB_LDN8_CRF7);
309 	sc->reg_2 = read_efdr_1(sc);
310 	sc->reg_2 |= WB_LDN8_CRF7_FORCE;
311 
312 	write_efir_1(sc, WB_LDN8_CRF7);
313 	write_efdr_1(sc, sc->reg_2);
314 
315 	return (0);
316 }
317 
318 /*
319  * Print current watchdog state.
320  *
321  * Note: it is the responsibility of the caller to update the registers
322  * upfront.
323  */
324 static void
325 wb_print_state(struct wb_softc *sc, const char *msg)
326 {
327 
328 	device_printf(sc->dev, "%s%sWatchdog %sabled. %s"
329 	    "Scaling by %ds, timer at %d (%s=%ds%s). "
330 	    "CRF5 0x%02x CRF7 0x%02x\n",
331 	    (msg != NULL) ? msg : "", (msg != NULL) ? ": " : "",
332 	    (sc->reg_timeout > 0x00) ? "en" : "dis",
333 	    (sc->reg_2 & WB_LDN8_CRF7_TS) ? "Watchdog fired. " : "",
334 	    (sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1,
335 	    sc->reg_timeout,
336 	    (sc->reg_timeout > 0x00) ? "<" : "",
337 	    sc->reg_timeout * ((sc->reg_1 & WB_LDN8_CRF5_SCALE) ? 60 : 1),
338 	    (sc->reg_timeout > 0x00) ? " left" : "",
339 	    sc->reg_1, sc->reg_2);
340 }
341 
342 /*
343  * Functions to enter and exit extended function mode.  Possibly shared
344  * between different chips.
345  */
346 static int
347 ext_cfg_enter_0x87_0x87(struct wb_softc *sc)
348 {
349 
350 	/*
351 	 * Enable extended function mode.
352 	 * Winbond does not allow us to validate so always return success.
353 	 */
354 	write_efir_1(sc, 0x87);
355 	write_efir_1(sc, 0x87);
356 
357 	return (0);
358 }
359 
360 static void
361 ext_cfg_exit_0xaa(struct wb_softc *sc)
362 {
363 
364 	write_efir_1(sc, 0xaa);
365 }
366 
367 /*
368  * (Re)load the watchdog counter depending on timeout.  A timeout of 0 will
369  * disable the watchdog.
370  */
371 static int
372 wb_set_watchdog(struct wb_softc *sc, unsigned int timeout)
373 {
374 
375 	if (sc->debug_verbose)
376 		wb_print_state(sc, "Before watchdog counter (re)load");
377 
378 	/*
379 	 * Enter extended function mode in case someone else has been
380 	 * poking on the registers.  We will not leave it though.
381 	 */
382 	if ((*sc->ext_cfg_enter_f)(sc) != 0)
383 		return (ENXIO);
384 
385 	/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog) */
386 	write_efir_1(sc, WB_LDN_REG);
387 	write_efdr_1(sc, WB_LDN_REG_LDN8);
388 
389 	/* Disable and validate or arm/reset watchdog. */
390 	if (timeout == 0) {
391 		/* Disable watchdog. */
392 		write_efir_1(sc, WB_LDN8_CRF6);
393 		write_efdr_1(sc, 0x00);
394 
395 		/* Re-check. */
396 		write_efir_1(sc, WB_LDN8_CRF6);
397 		sc->reg_timeout = read_efdr_1(sc);
398 
399 		if (sc->reg_timeout != 0x00) {
400 			device_printf(sc->dev, "Failed to disable watchdog: "
401 			    "0x%02x.\n", sc->reg_timeout);
402 			return (EIO);
403 		}
404 
405 	} else {
406 		/*
407 		 * In case an override is set, let it override.  It may lead
408 		 * to strange results as we do not check the input of the sysctl.
409 		 */
410 		if (sc->timeout_override > 0)
411 			timeout = sc->timeout_override;
412 
413 		/* Make sure we support the requested timeout. */
414 		if (timeout > 255 * 60)
415 			return (EINVAL);
416 
417 		/* Read current scaling factor. */
418 		write_efir_1(sc, WB_LDN8_CRF5);
419 		sc->reg_1 = read_efdr_1(sc);
420 
421 		if (timeout > 255) {
422 			/* Set scaling factor to 60s. */
423 			sc->reg_1 |= WB_LDN8_CRF5_SCALE;
424 			sc->reg_timeout = (timeout / 60);
425 			if (timeout % 60)
426 				sc->reg_timeout++;
427 		} else {
428 			/* Set scaling factor to 1s. */
429 			sc->reg_1 &= ~WB_LDN8_CRF5_SCALE;
430 			sc->reg_timeout = timeout;
431 		}
432 
433 		/* In case we fired before we need to clear to fire again. */
434 		write_efir_1(sc, WB_LDN8_CRF7);
435 		sc->reg_2 = read_efdr_1(sc);
436 		if (sc->reg_2 & WB_LDN8_CRF7_TS) {
437 			sc->reg_2 &= ~WB_LDN8_CRF7_TS;
438 			write_efir_1(sc, WB_LDN8_CRF7);
439 			write_efdr_1(sc, sc->reg_2);
440 		}
441 
442 		/* Write back scaling factor. */
443 		write_efir_1(sc, WB_LDN8_CRF5);
444 		write_efdr_1(sc, sc->reg_1);
445 
446 		/* Set timer and arm/reset the watchdog. */
447 		write_efir_1(sc, WB_LDN8_CRF6);
448 		write_efdr_1(sc, sc->reg_timeout);
449 	}
450 
451 	if (sc->debug_verbose)
452 		wb_print_state(sc, "After watchdog counter (re)load");
453 
454 	return (0);
455 }
456 
457 /*
458  * watchdog(9) EVENTHANDLER function implementation to (re)load the counter
459  * with the given timeout or disable the watchdog.
460  */
461 static void
462 wb_watchdog_fn(void *private, u_int cmd, int *error)
463 {
464 	struct wb_softc *sc;
465 	unsigned int timeout;
466 	int e;
467 
468 	sc = private;
469 	KASSERT(sc != NULL, ("%s: watchdog handler function called without "
470 	    "softc.", __func__));
471 
472 	cmd &= WD_INTERVAL;
473 	if (cmd > 0 && cmd <= 63) {
474 		/* Reset (and arm) watchdog. */
475 		timeout = ((uint64_t)1 << cmd) / 1000000000;
476 		if (timeout == 0)
477 			timeout = 1;
478 		e = wb_set_watchdog(sc, timeout);
479 		if (e == 0) {
480 			if (error != NULL)
481 				*error = 0;
482 		} else {
483 			/* On error, try to make sure the WD is disabled. */
484 			wb_set_watchdog(sc, 0);
485 		}
486 
487 	} else {
488 		/* Disable watchdog. */
489 		e = wb_set_watchdog(sc, 0);
490 		if (e != 0 && cmd == 0 && error != NULL) {
491 			/* Failed to disable watchdog. */
492 			*error = EOPNOTSUPP;
493 		}
494 	}
495 }
496 
497 /*
498  * Probe/attach the Winbond Super I/O chip.
499  *
500  * Initial abstraction to possibly support more chips:
501  * - Iterate over the well known base ports, try to enable extended function
502  *   mode and read and match the device ID and device revision.  Unfortunately
503  *   the Vendor ID is in the hardware monitoring section accessible by different
504  *   base ports only.
505  * - Also HEFRAS, which would tell use the base port, is only accessible after
506  *   entering extended function mode, for which the base port is needed.
507  *   At least check HEFRAS to match the current base port we are probing.
508  * - On match set the description, remember functions to enter/exit extended
509  *   function mode as well as the base port.
510  */
511 static int
512 wb_probe_enable(device_t dev, int probe)
513 {
514 	struct wb_softc *sc;
515 	int error, found, i, j;
516 	uint8_t dev_id, dev_rev, cr26;
517 
518 	sc = device_get_softc(dev);
519 	bzero(sc, sizeof(*sc));
520 	sc->dev = dev;
521 
522 	error = ENXIO;
523 	for (i = 0; i < sizeof(probe_addrs) / sizeof(*probe_addrs); i++) {
524 
525 		/* Allocate bus resources for IO index/data register access. */
526 		sc->portres = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->rid,
527 		    probe_addrs[i].efer, probe_addrs[i].efer + 1, 2, RF_ACTIVE);
528 		if (sc->portres == NULL)
529 			continue;
530 		sc->bst = rman_get_bustag(sc->portres);
531 		sc->bsh = rman_get_bushandle(sc->portres);
532 
533 		found = 0;
534 		error = (*probe_addrs[i].ext_cfg_enter_f)(sc);
535 		if (error != 0)
536 			goto cleanup;
537 
538 		/* Identify the SuperIO chip. */
539 		write_efir_1(sc, WB_DEVICE_ID_REG);
540 		dev_id = read_efdr_1(sc);
541 		write_efir_1(sc, WB_DEVICE_REV_REG);
542 		dev_rev = read_efdr_1(sc);
543 		write_efir_1(sc, WB_CR26);
544 		cr26 = read_efdr_1(sc);
545 
546 		/* HEFRAS of 0 means EFER at 0x2e, 1 means EFER at 0x4e. */
547 		if (((cr26 & 0x40) == 0x00 && probe_addrs[i].efer != 0x2e) ||
548 		    ((cr26 & 0x40) == 0x40 && probe_addrs[i].efer != 0x4e)) {
549 			device_printf(dev, "HEFRAS and EFER do not align: EFER "
550 			    "0x%02x DevID 0x%02x DevRev 0x%02x CR26 0x%02x\n",
551 			     probe_addrs[i].efer, dev_id, dev_rev, cr26);
552 			goto cleanup;
553 		}
554 
555 		for (j = 0; j < sizeof(wb_devs) / sizeof(*wb_devs); j++) {
556 			if (wb_devs[j].device_id == dev_id &&
557 			    wb_devs[j].device_rev == dev_rev) {
558 				if (probe)
559 					device_set_desc(dev, wb_devs[j].descr);
560 				found++;
561 				break;
562 			}
563 		}
564 		if (probe && found && bootverbose)
565 			device_printf(dev, "%s EFER 0x%02x ID 0x%02x Rev 0x%02x"
566 			     " CR26 0x%02x (probing)\n", device_get_desc(dev),
567 			     probe_addrs[i].efer, dev_id, dev_rev, cr26);
568 cleanup:
569 		if (probe || !found) {
570 			(*probe_addrs[i].ext_cfg_exit_f)(sc);
571 
572 			(void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid,
573 			    sc->portres);
574 		}
575 
576 		/*
577 		 * Stop probing if have successfully identified the SuperIO.
578 		 * Remember the extended function mode enter/exit functions
579 		 * for operations.
580 		 */
581 		if (found) {
582 			sc->ext_cfg_enter_f = probe_addrs[i].ext_cfg_enter_f;
583 			sc->ext_cfg_exit_f = probe_addrs[i].ext_cfg_exit_f;
584 			error = BUS_PROBE_DEFAULT;
585 			break;
586 		} else
587 			error = ENXIO;
588 	}
589 
590 	return (error);
591 }
592 
593 static int
594 wb_probe(device_t dev)
595 {
596 
597 	/* Make sure we do not claim some ISA PNP device. */
598 	if (isa_get_logicalid(dev) != 0)
599 		return (ENXIO);
600 
601 	return (wb_probe_enable(dev, 1));
602 }
603 
604 static int
605 wb_attach(device_t dev)
606 {
607 	struct wb_softc *sc;
608 	struct sysctl_ctx_list *sctx;
609 	struct sysctl_oid *soid;
610 	unsigned long timeout;
611 	int error;
612 
613 	error = wb_probe_enable(dev, 0);
614 	if (error > 0)
615 		return (ENXIO);
616 
617 	sc = device_get_softc(dev);
618 	KASSERT(sc->ext_cfg_enter_f != NULL && sc->ext_cfg_exit_f != NULL,
619 	    ("%s: successfull probe result but not setup correctly", __func__));
620 
621 	/* Watchdog is configured as part of LDN 8 (GPIO Port2, Watchdog). */
622 	write_efir_1(sc, WB_LDN_REG);
623 	write_efdr_1(sc, WB_LDN_REG_LDN8);
624 
625 	/* Make sure LDN8 is enabled (Do we need to? Also affects GPIO). */
626 	write_efir_1(sc, WB_LDN8_CR30);
627 	write_efdr_1(sc, WB_LDN8_CR30_ACTIVE);
628 
629 	/* Read the current watchdog configuration. */
630 	write_efir_1(sc, WB_LDN8_CRF5);
631 	sc->reg_1 = read_efdr_1(sc);
632 	write_efir_1(sc, WB_LDN8_CRF6);
633 	sc->reg_timeout = read_efdr_1(sc);
634 	write_efir_1(sc, WB_LDN8_CRF7);
635 	sc->reg_2 = read_efdr_1(sc);
636 
637 	/* Print current state if bootverbose or watchdog already enabled. */
638 	if (bootverbose || (sc->reg_timeout > 0x00))
639 		wb_print_state(sc, "Before watchdog attach");
640 
641 	/*
642 	 * Clear a previous watchdog timeout event (if (still) set).
643 	 * Disable all all interrupt reset sources (defaults).
644 	 */
645 	sc->reg_1 &= ~(WB_LDN8_CRF5_KEYB_P20);
646 	sc->reg_1 |= WB_LDN8_CRF5_KBRST;
647 	write_efir_1(sc, WB_LDN8_CRF5);
648 	write_efdr_1(sc, sc->reg_1);
649 
650 	sc->reg_2 &= ~WB_LDN8_CRF7_CLEAR_MASK;
651 	write_efir_1(sc, WB_LDN8_CRF7);
652 	write_efdr_1(sc, sc->reg_2);
653 
654 	/* Read global timeout override tunable, Add per device sysctls. */
655 	if (TUNABLE_ULONG_FETCH("hw.wbwd.timeout_override", &timeout)) {
656 		if (timeout > 0)
657 			sc->timeout_override = timeout;
658 	}
659 	sctx = device_get_sysctl_ctx(dev);
660 	soid = device_get_sysctl_tree(dev);
661         SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
662 	    "timeout_override", CTLFLAG_RW, &sc->timeout_override, 0,
663             "Timeout in seconds overriding default watchdog timeout");
664         SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO,
665 	    "debug_verbose", CTLFLAG_RW, &sc->debug_verbose, 0,
666             "Enables extra debugging information");
667         SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug",
668 	    CTLTYPE_STRING|CTLFLAG_RD, sc, 0, sysctl_wb_debug, "A",
669             "Selected register information from last change by driver");
670         SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "debug_current",
671 	    CTLTYPE_STRING|CTLFLAG_RD|CTLFLAG_SKIP, sc, 0,
672 	     sysctl_wb_debug_current, "A",
673 	     "Selected register information (may interfere)");
674 	SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "force_timeout",
675 	    CTLTYPE_INT|CTLFLAG_RW|CTLFLAG_SKIP, sc, 0,
676 	    sysctl_wb_force_test_nmi, "I", "Enable to force watchdog to fire.");
677 
678 	/* Register watchdog. */
679 	sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, wb_watchdog_fn, sc,
680 	    0);
681 
682 	if (bootverbose)
683 		wb_print_state(sc, "After watchdog attach");
684 
685 	return (0);
686 }
687 
688 static int
689 wb_detach(device_t dev)
690 {
691 	struct wb_softc *sc;
692 
693 	sc = device_get_softc(dev);
694 
695 	/* Unregister and stop the watchdog if running. */
696 	if (sc->ev_tag)
697 		EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
698 	wb_set_watchdog(sc, 0);
699 
700 	/* Disable extended function mode. */
701 	(*sc->ext_cfg_exit_f)(sc);
702 
703 	/* Cleanup resources. */
704 	(void) bus_release_resource(dev, SYS_RES_IOPORT, sc->rid, sc->portres);
705 
706 	/* Bus subroutines take care of sysctls already. */
707 
708 	return (0);
709 }
710 
711 static device_method_t wb_methods[] = {
712 	/* Device interface */
713 	DEVMETHOD(device_probe,		wb_probe),
714 	DEVMETHOD(device_attach,	wb_attach),
715 	DEVMETHOD(device_detach,	wb_detach),
716 
717 	{ 0, 0 }
718 };
719 
720 static driver_t wb_isa_driver = {
721 	"wbwd",
722 	wb_methods,
723 	sizeof(struct wb_softc)
724 };
725 
726 static devclass_t wb_devclass;
727 
728 DRIVER_MODULE(wb, isa, wb_isa_driver, wb_devclass, NULL, NULL);
729