1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for DM&P Electronics, Inc, Vortex86 RDC R6040 FastEthernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/lock.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/mutex.h> 42 #include <sys/rman.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 61 #include <dev/mii/mii.h> 62 #include <dev/mii/miivar.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <machine/bus.h> 68 69 #include <dev/vte/if_vtereg.h> 70 #include <dev/vte/if_vtevar.h> 71 72 /* "device miibus" required. See GENERIC if you get errors here. */ 73 #include "miibus_if.h" 74 75 MODULE_DEPEND(vte, pci, 1, 1, 1); 76 MODULE_DEPEND(vte, ether, 1, 1, 1); 77 MODULE_DEPEND(vte, miibus, 1, 1, 1); 78 79 /* Tunables. */ 80 static int tx_deep_copy = 1; 81 TUNABLE_INT("hw.vte.tx_deep_copy", &tx_deep_copy); 82 83 /* 84 * Devices supported by this driver. 85 */ 86 static const struct vte_ident vte_ident_table[] = { 87 { VENDORID_RDC, DEVICEID_RDC_R6040, "RDC R6040 FastEthernet"}, 88 { 0, 0, NULL} 89 }; 90 91 static int vte_attach(device_t); 92 static int vte_detach(device_t); 93 static int vte_dma_alloc(struct vte_softc *); 94 static void vte_dma_free(struct vte_softc *); 95 static void vte_dmamap_cb(void *, bus_dma_segment_t *, int, int); 96 static struct vte_txdesc * 97 vte_encap(struct vte_softc *, struct mbuf **); 98 static const struct vte_ident * 99 vte_find_ident(device_t); 100 #ifndef __NO_STRICT_ALIGNMENT 101 static struct mbuf * 102 vte_fixup_rx(if_t, struct mbuf *); 103 #endif 104 static void vte_get_macaddr(struct vte_softc *); 105 static void vte_init(void *); 106 static void vte_init_locked(struct vte_softc *); 107 static int vte_init_rx_ring(struct vte_softc *); 108 static int vte_init_tx_ring(struct vte_softc *); 109 static void vte_intr(void *); 110 static int vte_ioctl(if_t, u_long, caddr_t); 111 static uint64_t vte_get_counter(if_t, ift_counter); 112 static void vte_mac_config(struct vte_softc *); 113 static int vte_miibus_readreg(device_t, int, int); 114 static void vte_miibus_statchg(device_t); 115 static int vte_miibus_writereg(device_t, int, int, int); 116 static int vte_mediachange(if_t); 117 static int vte_mediachange_locked(if_t); 118 static void vte_mediastatus(if_t, struct ifmediareq *); 119 static int vte_newbuf(struct vte_softc *, struct vte_rxdesc *); 120 static int vte_probe(device_t); 121 static void vte_reset(struct vte_softc *); 122 static int vte_resume(device_t); 123 static void vte_rxeof(struct vte_softc *); 124 static void vte_rxfilter(struct vte_softc *); 125 static int vte_shutdown(device_t); 126 static void vte_start(if_t); 127 static void vte_start_locked(struct vte_softc *); 128 static void vte_start_mac(struct vte_softc *); 129 static void vte_stats_clear(struct vte_softc *); 130 static void vte_stats_update(struct vte_softc *); 131 static void vte_stop(struct vte_softc *); 132 static void vte_stop_mac(struct vte_softc *); 133 static int vte_suspend(device_t); 134 static void vte_sysctl_node(struct vte_softc *); 135 static void vte_tick(void *); 136 static void vte_txeof(struct vte_softc *); 137 static void vte_watchdog(struct vte_softc *); 138 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 139 static int sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS); 140 141 static device_method_t vte_methods[] = { 142 /* Device interface. */ 143 DEVMETHOD(device_probe, vte_probe), 144 DEVMETHOD(device_attach, vte_attach), 145 DEVMETHOD(device_detach, vte_detach), 146 DEVMETHOD(device_shutdown, vte_shutdown), 147 DEVMETHOD(device_suspend, vte_suspend), 148 DEVMETHOD(device_resume, vte_resume), 149 150 /* MII interface. */ 151 DEVMETHOD(miibus_readreg, vte_miibus_readreg), 152 DEVMETHOD(miibus_writereg, vte_miibus_writereg), 153 DEVMETHOD(miibus_statchg, vte_miibus_statchg), 154 155 DEVMETHOD_END 156 }; 157 158 static driver_t vte_driver = { 159 "vte", 160 vte_methods, 161 sizeof(struct vte_softc) 162 }; 163 164 DRIVER_MODULE(vte, pci, vte_driver, 0, 0); 165 DRIVER_MODULE(miibus, vte, miibus_driver, 0, 0); 166 167 static int 168 vte_miibus_readreg(device_t dev, int phy, int reg) 169 { 170 struct vte_softc *sc; 171 int i; 172 173 sc = device_get_softc(dev); 174 175 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | 176 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 177 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 178 DELAY(5); 179 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_READ) == 0) 180 break; 181 } 182 183 if (i == 0) { 184 device_printf(sc->vte_dev, "phy read timeout : %d\n", reg); 185 return (0); 186 } 187 188 return (CSR_READ_2(sc, VTE_MMRD)); 189 } 190 191 static int 192 vte_miibus_writereg(device_t dev, int phy, int reg, int val) 193 { 194 struct vte_softc *sc; 195 int i; 196 197 sc = device_get_softc(dev); 198 199 CSR_WRITE_2(sc, VTE_MMWD, val); 200 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | 201 (phy << MMDIO_PHY_ADDR_SHIFT) | (reg << MMDIO_REG_ADDR_SHIFT)); 202 for (i = VTE_PHY_TIMEOUT; i > 0; i--) { 203 DELAY(5); 204 if ((CSR_READ_2(sc, VTE_MMDIO) & MMDIO_WRITE) == 0) 205 break; 206 } 207 208 if (i == 0) 209 device_printf(sc->vte_dev, "phy write timeout : %d\n", reg); 210 211 return (0); 212 } 213 214 static void 215 vte_miibus_statchg(device_t dev) 216 { 217 struct vte_softc *sc; 218 struct mii_data *mii; 219 if_t ifp; 220 uint16_t val; 221 222 sc = device_get_softc(dev); 223 224 mii = device_get_softc(sc->vte_miibus); 225 ifp = sc->vte_ifp; 226 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 227 return; 228 229 sc->vte_flags &= ~VTE_FLAG_LINK; 230 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 231 (IFM_ACTIVE | IFM_AVALID)) { 232 switch (IFM_SUBTYPE(mii->mii_media_active)) { 233 case IFM_10_T: 234 case IFM_100_TX: 235 sc->vte_flags |= VTE_FLAG_LINK; 236 break; 237 default: 238 break; 239 } 240 } 241 242 /* Stop RX/TX MACs. */ 243 vte_stop_mac(sc); 244 /* Program MACs with resolved duplex and flow control. */ 245 if ((sc->vte_flags & VTE_FLAG_LINK) != 0) { 246 /* 247 * Timer waiting time : (63 + TIMER * 64) MII clock. 248 * MII clock : 25MHz(100Mbps) or 2.5MHz(10Mbps). 249 */ 250 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 251 val = 18 << VTE_IM_TIMER_SHIFT; 252 else 253 val = 1 << VTE_IM_TIMER_SHIFT; 254 val |= sc->vte_int_rx_mod << VTE_IM_BUNDLE_SHIFT; 255 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 256 CSR_WRITE_2(sc, VTE_MRICR, val); 257 258 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) 259 val = 18 << VTE_IM_TIMER_SHIFT; 260 else 261 val = 1 << VTE_IM_TIMER_SHIFT; 262 val |= sc->vte_int_tx_mod << VTE_IM_BUNDLE_SHIFT; 263 /* 48.6us for 100Mbps, 50.8us for 10Mbps */ 264 CSR_WRITE_2(sc, VTE_MTICR, val); 265 266 vte_mac_config(sc); 267 vte_start_mac(sc); 268 } 269 } 270 271 static void 272 vte_mediastatus(if_t ifp, struct ifmediareq *ifmr) 273 { 274 struct vte_softc *sc; 275 struct mii_data *mii; 276 277 sc = if_getsoftc(ifp); 278 VTE_LOCK(sc); 279 if ((if_getflags(ifp) & IFF_UP) == 0) { 280 VTE_UNLOCK(sc); 281 return; 282 } 283 mii = device_get_softc(sc->vte_miibus); 284 285 mii_pollstat(mii); 286 ifmr->ifm_status = mii->mii_media_status; 287 ifmr->ifm_active = mii->mii_media_active; 288 VTE_UNLOCK(sc); 289 } 290 291 static int 292 vte_mediachange(if_t ifp) 293 { 294 struct vte_softc *sc; 295 int error; 296 297 sc = if_getsoftc(ifp); 298 VTE_LOCK(sc); 299 error = vte_mediachange_locked(ifp); 300 VTE_UNLOCK(sc); 301 return (error); 302 } 303 304 static int 305 vte_mediachange_locked(if_t ifp) 306 { 307 struct vte_softc *sc; 308 struct mii_data *mii; 309 struct mii_softc *miisc; 310 int error; 311 312 sc = if_getsoftc(ifp); 313 mii = device_get_softc(sc->vte_miibus); 314 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 315 PHY_RESET(miisc); 316 error = mii_mediachg(mii); 317 318 return (error); 319 } 320 321 static const struct vte_ident * 322 vte_find_ident(device_t dev) 323 { 324 const struct vte_ident *ident; 325 uint16_t vendor, devid; 326 327 vendor = pci_get_vendor(dev); 328 devid = pci_get_device(dev); 329 for (ident = vte_ident_table; ident->name != NULL; ident++) { 330 if (vendor == ident->vendorid && devid == ident->deviceid) 331 return (ident); 332 } 333 334 return (NULL); 335 } 336 337 static int 338 vte_probe(device_t dev) 339 { 340 const struct vte_ident *ident; 341 342 ident = vte_find_ident(dev); 343 if (ident != NULL) { 344 device_set_desc(dev, ident->name); 345 return (BUS_PROBE_DEFAULT); 346 } 347 348 return (ENXIO); 349 } 350 351 static void 352 vte_get_macaddr(struct vte_softc *sc) 353 { 354 uint16_t mid; 355 356 /* 357 * It seems there is no way to reload station address and 358 * it is supposed to be set by BIOS. 359 */ 360 mid = CSR_READ_2(sc, VTE_MID0L); 361 sc->vte_eaddr[0] = (mid >> 0) & 0xFF; 362 sc->vte_eaddr[1] = (mid >> 8) & 0xFF; 363 mid = CSR_READ_2(sc, VTE_MID0M); 364 sc->vte_eaddr[2] = (mid >> 0) & 0xFF; 365 sc->vte_eaddr[3] = (mid >> 8) & 0xFF; 366 mid = CSR_READ_2(sc, VTE_MID0H); 367 sc->vte_eaddr[4] = (mid >> 0) & 0xFF; 368 sc->vte_eaddr[5] = (mid >> 8) & 0xFF; 369 } 370 371 static int 372 vte_attach(device_t dev) 373 { 374 struct vte_softc *sc; 375 if_t ifp; 376 uint16_t macid; 377 int error, rid; 378 379 error = 0; 380 sc = device_get_softc(dev); 381 sc->vte_dev = dev; 382 383 mtx_init(&sc->vte_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 384 MTX_DEF); 385 callout_init_mtx(&sc->vte_tick_ch, &sc->vte_mtx, 0); 386 sc->vte_ident = vte_find_ident(dev); 387 388 /* Map the device. */ 389 pci_enable_busmaster(dev); 390 sc->vte_res_id = PCIR_BAR(1); 391 sc->vte_res_type = SYS_RES_MEMORY; 392 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 393 &sc->vte_res_id, RF_ACTIVE); 394 if (sc->vte_res == NULL) { 395 sc->vte_res_id = PCIR_BAR(0); 396 sc->vte_res_type = SYS_RES_IOPORT; 397 sc->vte_res = bus_alloc_resource_any(dev, sc->vte_res_type, 398 &sc->vte_res_id, RF_ACTIVE); 399 if (sc->vte_res == NULL) { 400 device_printf(dev, "cannot map memory/ports.\n"); 401 mtx_destroy(&sc->vte_mtx); 402 return (ENXIO); 403 } 404 } 405 if (bootverbose) { 406 device_printf(dev, "using %s space register mapping\n", 407 sc->vte_res_type == SYS_RES_MEMORY ? "memory" : "I/O"); 408 device_printf(dev, "MAC Identifier : 0x%04x\n", 409 CSR_READ_2(sc, VTE_MACID)); 410 macid = CSR_READ_2(sc, VTE_MACID_REV); 411 device_printf(dev, "MAC Id. 0x%02x, Rev. 0x%02x\n", 412 (macid & VTE_MACID_MASK) >> VTE_MACID_SHIFT, 413 (macid & VTE_MACID_REV_MASK) >> VTE_MACID_REV_SHIFT); 414 } 415 416 rid = 0; 417 sc->vte_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 418 RF_SHAREABLE | RF_ACTIVE); 419 if (sc->vte_irq == NULL) { 420 device_printf(dev, "cannot allocate IRQ resources.\n"); 421 error = ENXIO; 422 goto fail; 423 } 424 425 /* Reset the ethernet controller. */ 426 vte_reset(sc); 427 428 if ((error = vte_dma_alloc(sc)) != 0) 429 goto fail; 430 431 /* Create device sysctl node. */ 432 vte_sysctl_node(sc); 433 434 /* Load station address. */ 435 vte_get_macaddr(sc); 436 437 ifp = sc->vte_ifp = if_alloc(IFT_ETHER); 438 if_setsoftc(ifp, sc); 439 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 440 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 441 if_setioctlfn(ifp, vte_ioctl); 442 if_setstartfn(ifp, vte_start); 443 if_setinitfn(ifp, vte_init); 444 if_setgetcounterfn(ifp, vte_get_counter); 445 if_setsendqlen(ifp, VTE_TX_RING_CNT - 1); 446 if_setsendqready(ifp); 447 448 /* 449 * Set up MII bus. 450 * BIOS would have initialized VTE_MPSCCR to catch PHY 451 * status changes so driver may be able to extract 452 * configured PHY address. Since it's common to see BIOS 453 * fails to initialize the register(including the sample 454 * board I have), let mii(4) probe it. This is more 455 * reliable than relying on BIOS's initialization. 456 * 457 * Advertising flow control capability to mii(4) was 458 * intentionally disabled due to severe problems in TX 459 * pause frame generation. See vte_rxeof() for more 460 * details. 461 */ 462 error = mii_attach(dev, &sc->vte_miibus, ifp, vte_mediachange, 463 vte_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 464 if (error != 0) { 465 device_printf(dev, "attaching PHYs failed\n"); 466 goto fail; 467 } 468 469 ether_ifattach(ifp, sc->vte_eaddr); 470 471 /* VLAN capability setup. */ 472 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 473 if_setcapenable(ifp, if_getcapabilities(ifp)); 474 /* Tell the upper layer we support VLAN over-sized frames. */ 475 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 476 477 error = bus_setup_intr(dev, sc->vte_irq, INTR_TYPE_NET | INTR_MPSAFE, 478 NULL, vte_intr, sc, &sc->vte_intrhand); 479 if (error != 0) { 480 device_printf(dev, "could not set up interrupt handler.\n"); 481 ether_ifdetach(ifp); 482 goto fail; 483 } 484 485 fail: 486 if (error != 0) 487 vte_detach(dev); 488 489 return (error); 490 } 491 492 static int 493 vte_detach(device_t dev) 494 { 495 struct vte_softc *sc; 496 if_t ifp; 497 498 sc = device_get_softc(dev); 499 500 ifp = sc->vte_ifp; 501 if (device_is_attached(dev)) { 502 VTE_LOCK(sc); 503 vte_stop(sc); 504 VTE_UNLOCK(sc); 505 callout_drain(&sc->vte_tick_ch); 506 ether_ifdetach(ifp); 507 } 508 509 bus_generic_detach(dev); 510 511 if (sc->vte_intrhand != NULL) { 512 bus_teardown_intr(dev, sc->vte_irq, sc->vte_intrhand); 513 sc->vte_intrhand = NULL; 514 } 515 if (sc->vte_irq != NULL) { 516 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vte_irq); 517 sc->vte_irq = NULL; 518 } 519 if (sc->vte_res != NULL) { 520 bus_release_resource(dev, sc->vte_res_type, sc->vte_res_id, 521 sc->vte_res); 522 sc->vte_res = NULL; 523 } 524 if (ifp != NULL) { 525 if_free(ifp); 526 sc->vte_ifp = NULL; 527 } 528 vte_dma_free(sc); 529 mtx_destroy(&sc->vte_mtx); 530 531 return (0); 532 } 533 534 #define VTE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 535 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 536 537 static void 538 vte_sysctl_node(struct vte_softc *sc) 539 { 540 struct sysctl_ctx_list *ctx; 541 struct sysctl_oid_list *child, *parent; 542 struct sysctl_oid *tree; 543 struct vte_hw_stats *stats; 544 int error; 545 546 stats = &sc->vte_stats; 547 ctx = device_get_sysctl_ctx(sc->vte_dev); 548 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vte_dev)); 549 550 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 551 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 552 &sc->vte_int_rx_mod, 0, sysctl_hw_vte_int_mod, "I", 553 "vte RX interrupt moderation"); 554 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 555 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 556 &sc->vte_int_tx_mod, 0, sysctl_hw_vte_int_mod, "I", 557 "vte TX interrupt moderation"); 558 /* Pull in device tunables. */ 559 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 560 error = resource_int_value(device_get_name(sc->vte_dev), 561 device_get_unit(sc->vte_dev), "int_rx_mod", &sc->vte_int_rx_mod); 562 if (error == 0) { 563 if (sc->vte_int_rx_mod < VTE_IM_BUNDLE_MIN || 564 sc->vte_int_rx_mod > VTE_IM_BUNDLE_MAX) { 565 device_printf(sc->vte_dev, "int_rx_mod value out of " 566 "range; using default: %d\n", 567 VTE_IM_RX_BUNDLE_DEFAULT); 568 sc->vte_int_rx_mod = VTE_IM_RX_BUNDLE_DEFAULT; 569 } 570 } 571 572 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 573 error = resource_int_value(device_get_name(sc->vte_dev), 574 device_get_unit(sc->vte_dev), "int_tx_mod", &sc->vte_int_tx_mod); 575 if (error == 0) { 576 if (sc->vte_int_tx_mod < VTE_IM_BUNDLE_MIN || 577 sc->vte_int_tx_mod > VTE_IM_BUNDLE_MAX) { 578 device_printf(sc->vte_dev, "int_tx_mod value out of " 579 "range; using default: %d\n", 580 VTE_IM_TX_BUNDLE_DEFAULT); 581 sc->vte_int_tx_mod = VTE_IM_TX_BUNDLE_DEFAULT; 582 } 583 } 584 585 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 586 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VTE statistics"); 587 parent = SYSCTL_CHILDREN(tree); 588 589 /* RX statistics. */ 590 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 591 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 592 child = SYSCTL_CHILDREN(tree); 593 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 594 &stats->rx_frames, "Good frames"); 595 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 596 &stats->rx_bcast_frames, "Good broadcast frames"); 597 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 598 &stats->rx_mcast_frames, "Good multicast frames"); 599 VTE_SYSCTL_STAT_ADD32(ctx, child, "runt", 600 &stats->rx_runts, "Too short frames"); 601 VTE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 602 &stats->rx_crcerrs, "CRC errors"); 603 VTE_SYSCTL_STAT_ADD32(ctx, child, "long_frames", 604 &stats->rx_long_frames, 605 "Frames that have longer length than maximum packet length"); 606 VTE_SYSCTL_STAT_ADD32(ctx, child, "fifo_full", 607 &stats->rx_fifo_full, "FIFO full"); 608 VTE_SYSCTL_STAT_ADD32(ctx, child, "desc_unavail", 609 &stats->rx_desc_unavail, "Descriptor unavailable frames"); 610 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 611 &stats->rx_pause_frames, "Pause control frames"); 612 613 /* TX statistics. */ 614 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 615 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 616 child = SYSCTL_CHILDREN(tree); 617 VTE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 618 &stats->tx_frames, "Good frames"); 619 VTE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 620 &stats->tx_underruns, "FIFO underruns"); 621 VTE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 622 &stats->tx_late_colls, "Late collisions"); 623 VTE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 624 &stats->tx_pause_frames, "Pause control frames"); 625 } 626 627 #undef VTE_SYSCTL_STAT_ADD32 628 629 struct vte_dmamap_arg { 630 bus_addr_t vte_busaddr; 631 }; 632 633 static void 634 vte_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 635 { 636 struct vte_dmamap_arg *ctx; 637 638 if (error != 0) 639 return; 640 641 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 642 643 ctx = (struct vte_dmamap_arg *)arg; 644 ctx->vte_busaddr = segs[0].ds_addr; 645 } 646 647 static int 648 vte_dma_alloc(struct vte_softc *sc) 649 { 650 struct vte_txdesc *txd; 651 struct vte_rxdesc *rxd; 652 struct vte_dmamap_arg ctx; 653 int error, i; 654 655 /* Create parent DMA tag. */ 656 error = bus_dma_tag_create( 657 bus_get_dma_tag(sc->vte_dev), /* parent */ 658 1, 0, /* alignment, boundary */ 659 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 660 BUS_SPACE_MAXADDR, /* highaddr */ 661 NULL, NULL, /* filter, filterarg */ 662 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 663 0, /* nsegments */ 664 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 665 0, /* flags */ 666 NULL, NULL, /* lockfunc, lockarg */ 667 &sc->vte_cdata.vte_parent_tag); 668 if (error != 0) { 669 device_printf(sc->vte_dev, 670 "could not create parent DMA tag.\n"); 671 goto fail; 672 } 673 674 /* Create DMA tag for TX descriptor ring. */ 675 error = bus_dma_tag_create( 676 sc->vte_cdata.vte_parent_tag, /* parent */ 677 VTE_TX_RING_ALIGN, 0, /* alignment, boundary */ 678 BUS_SPACE_MAXADDR, /* lowaddr */ 679 BUS_SPACE_MAXADDR, /* highaddr */ 680 NULL, NULL, /* filter, filterarg */ 681 VTE_TX_RING_SZ, /* maxsize */ 682 1, /* nsegments */ 683 VTE_TX_RING_SZ, /* maxsegsize */ 684 0, /* flags */ 685 NULL, NULL, /* lockfunc, lockarg */ 686 &sc->vte_cdata.vte_tx_ring_tag); 687 if (error != 0) { 688 device_printf(sc->vte_dev, 689 "could not create TX ring DMA tag.\n"); 690 goto fail; 691 } 692 693 /* Create DMA tag for RX free descriptor ring. */ 694 error = bus_dma_tag_create( 695 sc->vte_cdata.vte_parent_tag, /* parent */ 696 VTE_RX_RING_ALIGN, 0, /* alignment, boundary */ 697 BUS_SPACE_MAXADDR, /* lowaddr */ 698 BUS_SPACE_MAXADDR, /* highaddr */ 699 NULL, NULL, /* filter, filterarg */ 700 VTE_RX_RING_SZ, /* maxsize */ 701 1, /* nsegments */ 702 VTE_RX_RING_SZ, /* maxsegsize */ 703 0, /* flags */ 704 NULL, NULL, /* lockfunc, lockarg */ 705 &sc->vte_cdata.vte_rx_ring_tag); 706 if (error != 0) { 707 device_printf(sc->vte_dev, 708 "could not create RX ring DMA tag.\n"); 709 goto fail; 710 } 711 712 /* Allocate DMA'able memory and load the DMA map for TX ring. */ 713 error = bus_dmamem_alloc(sc->vte_cdata.vte_tx_ring_tag, 714 (void **)&sc->vte_cdata.vte_tx_ring, 715 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 716 &sc->vte_cdata.vte_tx_ring_map); 717 if (error != 0) { 718 device_printf(sc->vte_dev, 719 "could not allocate DMA'able memory for TX ring.\n"); 720 goto fail; 721 } 722 ctx.vte_busaddr = 0; 723 error = bus_dmamap_load(sc->vte_cdata.vte_tx_ring_tag, 724 sc->vte_cdata.vte_tx_ring_map, sc->vte_cdata.vte_tx_ring, 725 VTE_TX_RING_SZ, vte_dmamap_cb, &ctx, 0); 726 if (error != 0 || ctx.vte_busaddr == 0) { 727 device_printf(sc->vte_dev, 728 "could not load DMA'able memory for TX ring.\n"); 729 goto fail; 730 } 731 sc->vte_cdata.vte_tx_ring_paddr = ctx.vte_busaddr; 732 733 /* Allocate DMA'able memory and load the DMA map for RX ring. */ 734 error = bus_dmamem_alloc(sc->vte_cdata.vte_rx_ring_tag, 735 (void **)&sc->vte_cdata.vte_rx_ring, 736 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 737 &sc->vte_cdata.vte_rx_ring_map); 738 if (error != 0) { 739 device_printf(sc->vte_dev, 740 "could not allocate DMA'able memory for RX ring.\n"); 741 goto fail; 742 } 743 ctx.vte_busaddr = 0; 744 error = bus_dmamap_load(sc->vte_cdata.vte_rx_ring_tag, 745 sc->vte_cdata.vte_rx_ring_map, sc->vte_cdata.vte_rx_ring, 746 VTE_RX_RING_SZ, vte_dmamap_cb, &ctx, 0); 747 if (error != 0 || ctx.vte_busaddr == 0) { 748 device_printf(sc->vte_dev, 749 "could not load DMA'able memory for RX ring.\n"); 750 goto fail; 751 } 752 sc->vte_cdata.vte_rx_ring_paddr = ctx.vte_busaddr; 753 754 /* Create TX buffer parent tag. */ 755 error = bus_dma_tag_create( 756 bus_get_dma_tag(sc->vte_dev), /* parent */ 757 1, 0, /* alignment, boundary */ 758 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 759 BUS_SPACE_MAXADDR, /* highaddr */ 760 NULL, NULL, /* filter, filterarg */ 761 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 762 0, /* nsegments */ 763 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 764 0, /* flags */ 765 NULL, NULL, /* lockfunc, lockarg */ 766 &sc->vte_cdata.vte_buffer_tag); 767 if (error != 0) { 768 device_printf(sc->vte_dev, 769 "could not create parent buffer DMA tag.\n"); 770 goto fail; 771 } 772 773 /* Create DMA tag for TX buffers. */ 774 error = bus_dma_tag_create( 775 sc->vte_cdata.vte_buffer_tag, /* parent */ 776 1, 0, /* alignment, boundary */ 777 BUS_SPACE_MAXADDR, /* lowaddr */ 778 BUS_SPACE_MAXADDR, /* highaddr */ 779 NULL, NULL, /* filter, filterarg */ 780 MCLBYTES, /* maxsize */ 781 1, /* nsegments */ 782 MCLBYTES, /* maxsegsize */ 783 0, /* flags */ 784 NULL, NULL, /* lockfunc, lockarg */ 785 &sc->vte_cdata.vte_tx_tag); 786 if (error != 0) { 787 device_printf(sc->vte_dev, "could not create TX DMA tag.\n"); 788 goto fail; 789 } 790 791 /* Create DMA tag for RX buffers. */ 792 error = bus_dma_tag_create( 793 sc->vte_cdata.vte_buffer_tag, /* parent */ 794 VTE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 795 BUS_SPACE_MAXADDR, /* lowaddr */ 796 BUS_SPACE_MAXADDR, /* highaddr */ 797 NULL, NULL, /* filter, filterarg */ 798 MCLBYTES, /* maxsize */ 799 1, /* nsegments */ 800 MCLBYTES, /* maxsegsize */ 801 0, /* flags */ 802 NULL, NULL, /* lockfunc, lockarg */ 803 &sc->vte_cdata.vte_rx_tag); 804 if (error != 0) { 805 device_printf(sc->vte_dev, "could not create RX DMA tag.\n"); 806 goto fail; 807 } 808 /* Create DMA maps for TX buffers. */ 809 for (i = 0; i < VTE_TX_RING_CNT; i++) { 810 txd = &sc->vte_cdata.vte_txdesc[i]; 811 txd->tx_m = NULL; 812 txd->tx_dmamap = NULL; 813 error = bus_dmamap_create(sc->vte_cdata.vte_tx_tag, 0, 814 &txd->tx_dmamap); 815 if (error != 0) { 816 device_printf(sc->vte_dev, 817 "could not create TX dmamap.\n"); 818 goto fail; 819 } 820 } 821 /* Create DMA maps for RX buffers. */ 822 if ((error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 823 &sc->vte_cdata.vte_rx_sparemap)) != 0) { 824 device_printf(sc->vte_dev, 825 "could not create spare RX dmamap.\n"); 826 goto fail; 827 } 828 for (i = 0; i < VTE_RX_RING_CNT; i++) { 829 rxd = &sc->vte_cdata.vte_rxdesc[i]; 830 rxd->rx_m = NULL; 831 rxd->rx_dmamap = NULL; 832 error = bus_dmamap_create(sc->vte_cdata.vte_rx_tag, 0, 833 &rxd->rx_dmamap); 834 if (error != 0) { 835 device_printf(sc->vte_dev, 836 "could not create RX dmamap.\n"); 837 goto fail; 838 } 839 } 840 841 fail: 842 return (error); 843 } 844 845 static void 846 vte_dma_free(struct vte_softc *sc) 847 { 848 struct vte_txdesc *txd; 849 struct vte_rxdesc *rxd; 850 int i; 851 852 /* TX buffers. */ 853 if (sc->vte_cdata.vte_tx_tag != NULL) { 854 for (i = 0; i < VTE_TX_RING_CNT; i++) { 855 txd = &sc->vte_cdata.vte_txdesc[i]; 856 if (txd->tx_dmamap != NULL) { 857 bus_dmamap_destroy(sc->vte_cdata.vte_tx_tag, 858 txd->tx_dmamap); 859 txd->tx_dmamap = NULL; 860 } 861 } 862 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_tag); 863 sc->vte_cdata.vte_tx_tag = NULL; 864 } 865 /* RX buffers */ 866 if (sc->vte_cdata.vte_rx_tag != NULL) { 867 for (i = 0; i < VTE_RX_RING_CNT; i++) { 868 rxd = &sc->vte_cdata.vte_rxdesc[i]; 869 if (rxd->rx_dmamap != NULL) { 870 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 871 rxd->rx_dmamap); 872 rxd->rx_dmamap = NULL; 873 } 874 } 875 if (sc->vte_cdata.vte_rx_sparemap != NULL) { 876 bus_dmamap_destroy(sc->vte_cdata.vte_rx_tag, 877 sc->vte_cdata.vte_rx_sparemap); 878 sc->vte_cdata.vte_rx_sparemap = NULL; 879 } 880 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_tag); 881 sc->vte_cdata.vte_rx_tag = NULL; 882 } 883 /* TX descriptor ring. */ 884 if (sc->vte_cdata.vte_tx_ring_tag != NULL) { 885 if (sc->vte_cdata.vte_tx_ring_paddr != 0) 886 bus_dmamap_unload(sc->vte_cdata.vte_tx_ring_tag, 887 sc->vte_cdata.vte_tx_ring_map); 888 if (sc->vte_cdata.vte_tx_ring != NULL) 889 bus_dmamem_free(sc->vte_cdata.vte_tx_ring_tag, 890 sc->vte_cdata.vte_tx_ring, 891 sc->vte_cdata.vte_tx_ring_map); 892 sc->vte_cdata.vte_tx_ring = NULL; 893 sc->vte_cdata.vte_tx_ring_paddr = 0; 894 bus_dma_tag_destroy(sc->vte_cdata.vte_tx_ring_tag); 895 sc->vte_cdata.vte_tx_ring_tag = NULL; 896 } 897 /* RX ring. */ 898 if (sc->vte_cdata.vte_rx_ring_tag != NULL) { 899 if (sc->vte_cdata.vte_rx_ring_paddr != 0) 900 bus_dmamap_unload(sc->vte_cdata.vte_rx_ring_tag, 901 sc->vte_cdata.vte_rx_ring_map); 902 if (sc->vte_cdata.vte_rx_ring != NULL) 903 bus_dmamem_free(sc->vte_cdata.vte_rx_ring_tag, 904 sc->vte_cdata.vte_rx_ring, 905 sc->vte_cdata.vte_rx_ring_map); 906 sc->vte_cdata.vte_rx_ring = NULL; 907 sc->vte_cdata.vte_rx_ring_paddr = 0; 908 bus_dma_tag_destroy(sc->vte_cdata.vte_rx_ring_tag); 909 sc->vte_cdata.vte_rx_ring_tag = NULL; 910 } 911 if (sc->vte_cdata.vte_buffer_tag != NULL) { 912 bus_dma_tag_destroy(sc->vte_cdata.vte_buffer_tag); 913 sc->vte_cdata.vte_buffer_tag = NULL; 914 } 915 if (sc->vte_cdata.vte_parent_tag != NULL) { 916 bus_dma_tag_destroy(sc->vte_cdata.vte_parent_tag); 917 sc->vte_cdata.vte_parent_tag = NULL; 918 } 919 } 920 921 static int 922 vte_shutdown(device_t dev) 923 { 924 925 return (vte_suspend(dev)); 926 } 927 928 static int 929 vte_suspend(device_t dev) 930 { 931 struct vte_softc *sc; 932 if_t ifp; 933 934 sc = device_get_softc(dev); 935 936 VTE_LOCK(sc); 937 ifp = sc->vte_ifp; 938 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 939 vte_stop(sc); 940 VTE_UNLOCK(sc); 941 942 return (0); 943 } 944 945 static int 946 vte_resume(device_t dev) 947 { 948 struct vte_softc *sc; 949 if_t ifp; 950 951 sc = device_get_softc(dev); 952 953 VTE_LOCK(sc); 954 ifp = sc->vte_ifp; 955 if ((if_getflags(ifp) & IFF_UP) != 0) { 956 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 957 vte_init_locked(sc); 958 } 959 VTE_UNLOCK(sc); 960 961 return (0); 962 } 963 964 static struct vte_txdesc * 965 vte_encap(struct vte_softc *sc, struct mbuf **m_head) 966 { 967 struct vte_txdesc *txd; 968 struct mbuf *m, *n; 969 bus_dma_segment_t txsegs[1]; 970 int copy, error, nsegs, padlen; 971 972 VTE_LOCK_ASSERT(sc); 973 974 M_ASSERTPKTHDR((*m_head)); 975 976 txd = &sc->vte_cdata.vte_txdesc[sc->vte_cdata.vte_tx_prod]; 977 m = *m_head; 978 /* 979 * Controller doesn't auto-pad, so we have to make sure pad 980 * short frames out to the minimum frame length. 981 */ 982 if (m->m_pkthdr.len < VTE_MIN_FRAMELEN) 983 padlen = VTE_MIN_FRAMELEN - m->m_pkthdr.len; 984 else 985 padlen = 0; 986 987 /* 988 * Controller does not support multi-fragmented TX buffers. 989 * Controller spends most of its TX processing time in 990 * de-fragmenting TX buffers. Either faster CPU or more 991 * advanced controller DMA engine is required to speed up 992 * TX path processing. 993 * To mitigate the de-fragmenting issue, perform deep copy 994 * from fragmented mbuf chains to a pre-allocated mbuf 995 * cluster with extra cost of kernel memory. For frames 996 * that is composed of single TX buffer, the deep copy is 997 * bypassed. 998 */ 999 if (tx_deep_copy != 0) { 1000 copy = 0; 1001 if (m->m_next != NULL) 1002 copy++; 1003 if (padlen > 0 && (M_WRITABLE(m) == 0 || 1004 padlen > M_TRAILINGSPACE(m))) 1005 copy++; 1006 if (copy != 0) { 1007 /* Avoid expensive m_defrag(9) and do deep copy. */ 1008 n = sc->vte_cdata.vte_txmbufs[sc->vte_cdata.vte_tx_prod]; 1009 m_copydata(m, 0, m->m_pkthdr.len, mtod(n, char *)); 1010 n->m_pkthdr.len = m->m_pkthdr.len; 1011 n->m_len = m->m_pkthdr.len; 1012 m = n; 1013 txd->tx_flags |= VTE_TXMBUF; 1014 } 1015 1016 if (padlen > 0) { 1017 /* Zero out the bytes in the pad area. */ 1018 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1019 m->m_pkthdr.len += padlen; 1020 m->m_len = m->m_pkthdr.len; 1021 } 1022 } else { 1023 if (M_WRITABLE(m) == 0) { 1024 if (m->m_next != NULL || padlen > 0) { 1025 /* Get a writable copy. */ 1026 m = m_dup(*m_head, M_NOWAIT); 1027 /* Release original mbuf chains. */ 1028 m_freem(*m_head); 1029 if (m == NULL) { 1030 *m_head = NULL; 1031 return (NULL); 1032 } 1033 *m_head = m; 1034 } 1035 } 1036 1037 if (m->m_next != NULL) { 1038 m = m_defrag(*m_head, M_NOWAIT); 1039 if (m == NULL) { 1040 m_freem(*m_head); 1041 *m_head = NULL; 1042 return (NULL); 1043 } 1044 *m_head = m; 1045 } 1046 1047 if (padlen > 0) { 1048 if (M_TRAILINGSPACE(m) < padlen) { 1049 m = m_defrag(*m_head, M_NOWAIT); 1050 if (m == NULL) { 1051 m_freem(*m_head); 1052 *m_head = NULL; 1053 return (NULL); 1054 } 1055 *m_head = m; 1056 } 1057 /* Zero out the bytes in the pad area. */ 1058 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1059 m->m_pkthdr.len += padlen; 1060 m->m_len = m->m_pkthdr.len; 1061 } 1062 } 1063 1064 error = bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_tx_tag, 1065 txd->tx_dmamap, m, txsegs, &nsegs, 0); 1066 if (error != 0) { 1067 txd->tx_flags &= ~VTE_TXMBUF; 1068 return (NULL); 1069 } 1070 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1071 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1072 BUS_DMASYNC_PREWRITE); 1073 1074 txd->tx_desc->dtlen = htole16(VTE_TX_LEN(txsegs[0].ds_len)); 1075 txd->tx_desc->dtbp = htole32(txsegs[0].ds_addr); 1076 sc->vte_cdata.vte_tx_cnt++; 1077 /* Update producer index. */ 1078 VTE_DESC_INC(sc->vte_cdata.vte_tx_prod, VTE_TX_RING_CNT); 1079 1080 /* Finally hand over ownership to controller. */ 1081 txd->tx_desc->dtst = htole16(VTE_DTST_TX_OWN); 1082 txd->tx_m = m; 1083 1084 return (txd); 1085 } 1086 1087 static void 1088 vte_start(if_t ifp) 1089 { 1090 struct vte_softc *sc; 1091 1092 sc = if_getsoftc(ifp); 1093 VTE_LOCK(sc); 1094 vte_start_locked(sc); 1095 VTE_UNLOCK(sc); 1096 } 1097 1098 static void 1099 vte_start_locked(struct vte_softc *sc) 1100 { 1101 if_t ifp; 1102 struct vte_txdesc *txd; 1103 struct mbuf *m_head; 1104 int enq; 1105 1106 ifp = sc->vte_ifp; 1107 1108 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1109 IFF_DRV_RUNNING || (sc->vte_flags & VTE_FLAG_LINK) == 0) 1110 return; 1111 1112 for (enq = 0; !if_sendq_empty(ifp); ) { 1113 /* Reserve one free TX descriptor. */ 1114 if (sc->vte_cdata.vte_tx_cnt >= VTE_TX_RING_CNT - 1) { 1115 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1116 break; 1117 } 1118 m_head = if_dequeue(ifp); 1119 if (m_head == NULL) 1120 break; 1121 /* 1122 * Pack the data into the transmit ring. If we 1123 * don't have room, set the OACTIVE flag and wait 1124 * for the NIC to drain the ring. 1125 */ 1126 if ((txd = vte_encap(sc, &m_head)) == NULL) { 1127 if (m_head != NULL) 1128 if_sendq_prepend(ifp, m_head); 1129 break; 1130 } 1131 1132 enq++; 1133 /* 1134 * If there's a BPF listener, bounce a copy of this frame 1135 * to him. 1136 */ 1137 ETHER_BPF_MTAP(ifp, m_head); 1138 /* Free consumed TX frame. */ 1139 if ((txd->tx_flags & VTE_TXMBUF) != 0) 1140 m_freem(m_head); 1141 } 1142 1143 if (enq > 0) { 1144 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1145 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1146 BUS_DMASYNC_PREWRITE); 1147 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); 1148 sc->vte_watchdog_timer = VTE_TX_TIMEOUT; 1149 } 1150 } 1151 1152 static void 1153 vte_watchdog(struct vte_softc *sc) 1154 { 1155 if_t ifp; 1156 1157 VTE_LOCK_ASSERT(sc); 1158 1159 if (sc->vte_watchdog_timer == 0 || --sc->vte_watchdog_timer) 1160 return; 1161 1162 ifp = sc->vte_ifp; 1163 if_printf(sc->vte_ifp, "watchdog timeout -- resetting\n"); 1164 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1165 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1166 vte_init_locked(sc); 1167 if (!if_sendq_empty(ifp)) 1168 vte_start_locked(sc); 1169 } 1170 1171 static int 1172 vte_ioctl(if_t ifp, u_long cmd, caddr_t data) 1173 { 1174 struct vte_softc *sc; 1175 struct ifreq *ifr; 1176 struct mii_data *mii; 1177 int error; 1178 1179 sc = if_getsoftc(ifp); 1180 ifr = (struct ifreq *)data; 1181 error = 0; 1182 switch (cmd) { 1183 case SIOCSIFFLAGS: 1184 VTE_LOCK(sc); 1185 if ((if_getflags(ifp) & IFF_UP) != 0) { 1186 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1187 ((if_getflags(ifp) ^ sc->vte_if_flags) & 1188 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1189 vte_rxfilter(sc); 1190 else 1191 vte_init_locked(sc); 1192 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1193 vte_stop(sc); 1194 sc->vte_if_flags = if_getflags(ifp); 1195 VTE_UNLOCK(sc); 1196 break; 1197 case SIOCADDMULTI: 1198 case SIOCDELMULTI: 1199 VTE_LOCK(sc); 1200 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1201 vte_rxfilter(sc); 1202 VTE_UNLOCK(sc); 1203 break; 1204 case SIOCSIFMEDIA: 1205 case SIOCGIFMEDIA: 1206 mii = device_get_softc(sc->vte_miibus); 1207 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1208 break; 1209 default: 1210 error = ether_ioctl(ifp, cmd, data); 1211 break; 1212 } 1213 1214 return (error); 1215 } 1216 1217 static void 1218 vte_mac_config(struct vte_softc *sc) 1219 { 1220 struct mii_data *mii; 1221 uint16_t mcr; 1222 1223 VTE_LOCK_ASSERT(sc); 1224 1225 mii = device_get_softc(sc->vte_miibus); 1226 mcr = CSR_READ_2(sc, VTE_MCR0); 1227 mcr &= ~(MCR0_FC_ENB | MCR0_FULL_DUPLEX); 1228 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1229 mcr |= MCR0_FULL_DUPLEX; 1230 #ifdef notyet 1231 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1232 mcr |= MCR0_FC_ENB; 1233 /* 1234 * The data sheet is not clear whether the controller 1235 * honors received pause frames or not. The is no 1236 * separate control bit for RX pause frame so just 1237 * enable MCR0_FC_ENB bit. 1238 */ 1239 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1240 mcr |= MCR0_FC_ENB; 1241 #endif 1242 } 1243 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1244 } 1245 1246 static void 1247 vte_stats_clear(struct vte_softc *sc) 1248 { 1249 1250 /* Reading counter registers clears its contents. */ 1251 CSR_READ_2(sc, VTE_CNT_RX_DONE); 1252 CSR_READ_2(sc, VTE_CNT_MECNT0); 1253 CSR_READ_2(sc, VTE_CNT_MECNT1); 1254 CSR_READ_2(sc, VTE_CNT_MECNT2); 1255 CSR_READ_2(sc, VTE_CNT_MECNT3); 1256 CSR_READ_2(sc, VTE_CNT_TX_DONE); 1257 CSR_READ_2(sc, VTE_CNT_MECNT4); 1258 CSR_READ_2(sc, VTE_CNT_PAUSE); 1259 } 1260 1261 static void 1262 vte_stats_update(struct vte_softc *sc) 1263 { 1264 struct vte_hw_stats *stat; 1265 uint16_t value; 1266 1267 VTE_LOCK_ASSERT(sc); 1268 1269 stat = &sc->vte_stats; 1270 1271 CSR_READ_2(sc, VTE_MECISR); 1272 /* RX stats. */ 1273 stat->rx_frames += CSR_READ_2(sc, VTE_CNT_RX_DONE); 1274 value = CSR_READ_2(sc, VTE_CNT_MECNT0); 1275 stat->rx_bcast_frames += (value >> 8); 1276 stat->rx_mcast_frames += (value & 0xFF); 1277 value = CSR_READ_2(sc, VTE_CNT_MECNT1); 1278 stat->rx_runts += (value >> 8); 1279 stat->rx_crcerrs += (value & 0xFF); 1280 value = CSR_READ_2(sc, VTE_CNT_MECNT2); 1281 stat->rx_long_frames += (value & 0xFF); 1282 value = CSR_READ_2(sc, VTE_CNT_MECNT3); 1283 stat->rx_fifo_full += (value >> 8); 1284 stat->rx_desc_unavail += (value & 0xFF); 1285 1286 /* TX stats. */ 1287 stat->tx_frames += CSR_READ_2(sc, VTE_CNT_TX_DONE); 1288 value = CSR_READ_2(sc, VTE_CNT_MECNT4); 1289 stat->tx_underruns += (value >> 8); 1290 stat->tx_late_colls += (value & 0xFF); 1291 1292 value = CSR_READ_2(sc, VTE_CNT_PAUSE); 1293 stat->tx_pause_frames += (value >> 8); 1294 stat->rx_pause_frames += (value & 0xFF); 1295 } 1296 1297 static uint64_t 1298 vte_get_counter(if_t ifp, ift_counter cnt) 1299 { 1300 struct vte_softc *sc; 1301 struct vte_hw_stats *stat; 1302 1303 sc = if_getsoftc(ifp); 1304 stat = &sc->vte_stats; 1305 1306 switch (cnt) { 1307 case IFCOUNTER_OPACKETS: 1308 return (stat->tx_frames); 1309 case IFCOUNTER_COLLISIONS: 1310 return (stat->tx_late_colls); 1311 case IFCOUNTER_OERRORS: 1312 return (stat->tx_late_colls + stat->tx_underruns); 1313 case IFCOUNTER_IPACKETS: 1314 return (stat->rx_frames); 1315 case IFCOUNTER_IERRORS: 1316 return (stat->rx_crcerrs + stat->rx_runts + 1317 stat->rx_long_frames + stat->rx_fifo_full); 1318 default: 1319 return (if_get_counter_default(ifp, cnt)); 1320 } 1321 } 1322 1323 static void 1324 vte_intr(void *arg) 1325 { 1326 struct vte_softc *sc; 1327 if_t ifp; 1328 uint16_t status; 1329 int n; 1330 1331 sc = (struct vte_softc *)arg; 1332 VTE_LOCK(sc); 1333 1334 ifp = sc->vte_ifp; 1335 /* Reading VTE_MISR acknowledges interrupts. */ 1336 status = CSR_READ_2(sc, VTE_MISR); 1337 if ((status & VTE_INTRS) == 0) { 1338 /* Not ours. */ 1339 VTE_UNLOCK(sc); 1340 return; 1341 } 1342 1343 /* Disable interrupts. */ 1344 CSR_WRITE_2(sc, VTE_MIER, 0); 1345 for (n = 8; (status & VTE_INTRS) != 0;) { 1346 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1347 break; 1348 if ((status & (MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | 1349 MISR_RX_FIFO_FULL)) != 0) 1350 vte_rxeof(sc); 1351 if ((status & MISR_TX_DONE) != 0) 1352 vte_txeof(sc); 1353 if ((status & MISR_EVENT_CNT_OFLOW) != 0) 1354 vte_stats_update(sc); 1355 if (!if_sendq_empty(ifp)) 1356 vte_start_locked(sc); 1357 if (--n > 0) 1358 status = CSR_READ_2(sc, VTE_MISR); 1359 else 1360 break; 1361 } 1362 1363 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1364 /* Re-enable interrupts. */ 1365 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1366 } 1367 VTE_UNLOCK(sc); 1368 } 1369 1370 static void 1371 vte_txeof(struct vte_softc *sc) 1372 { 1373 if_t ifp; 1374 struct vte_txdesc *txd; 1375 uint16_t status; 1376 int cons, prog; 1377 1378 VTE_LOCK_ASSERT(sc); 1379 1380 ifp = sc->vte_ifp; 1381 1382 if (sc->vte_cdata.vte_tx_cnt == 0) 1383 return; 1384 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1385 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_POSTREAD | 1386 BUS_DMASYNC_POSTWRITE); 1387 cons = sc->vte_cdata.vte_tx_cons; 1388 /* 1389 * Go through our TX list and free mbufs for those 1390 * frames which have been transmitted. 1391 */ 1392 for (prog = 0; sc->vte_cdata.vte_tx_cnt > 0; prog++) { 1393 txd = &sc->vte_cdata.vte_txdesc[cons]; 1394 status = le16toh(txd->tx_desc->dtst); 1395 if ((status & VTE_DTST_TX_OWN) != 0) 1396 break; 1397 sc->vte_cdata.vte_tx_cnt--; 1398 /* Reclaim transmitted mbufs. */ 1399 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap, 1400 BUS_DMASYNC_POSTWRITE); 1401 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, txd->tx_dmamap); 1402 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1403 m_freem(txd->tx_m); 1404 txd->tx_flags &= ~VTE_TXMBUF; 1405 txd->tx_m = NULL; 1406 prog++; 1407 VTE_DESC_INC(cons, VTE_TX_RING_CNT); 1408 } 1409 1410 if (prog > 0) { 1411 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1412 sc->vte_cdata.vte_tx_cons = cons; 1413 /* 1414 * Unarm watchdog timer only when there is no pending 1415 * frames in TX queue. 1416 */ 1417 if (sc->vte_cdata.vte_tx_cnt == 0) 1418 sc->vte_watchdog_timer = 0; 1419 } 1420 } 1421 1422 static int 1423 vte_newbuf(struct vte_softc *sc, struct vte_rxdesc *rxd) 1424 { 1425 struct mbuf *m; 1426 bus_dma_segment_t segs[1]; 1427 bus_dmamap_t map; 1428 int nsegs; 1429 1430 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1431 if (m == NULL) 1432 return (ENOBUFS); 1433 m->m_len = m->m_pkthdr.len = MCLBYTES; 1434 m_adj(m, sizeof(uint32_t)); 1435 1436 if (bus_dmamap_load_mbuf_sg(sc->vte_cdata.vte_rx_tag, 1437 sc->vte_cdata.vte_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1438 m_freem(m); 1439 return (ENOBUFS); 1440 } 1441 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1442 1443 if (rxd->rx_m != NULL) { 1444 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1445 BUS_DMASYNC_POSTREAD); 1446 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap); 1447 } 1448 map = rxd->rx_dmamap; 1449 rxd->rx_dmamap = sc->vte_cdata.vte_rx_sparemap; 1450 sc->vte_cdata.vte_rx_sparemap = map; 1451 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, rxd->rx_dmamap, 1452 BUS_DMASYNC_PREREAD); 1453 rxd->rx_m = m; 1454 rxd->rx_desc->drbp = htole32(segs[0].ds_addr); 1455 rxd->rx_desc->drlen = htole16(VTE_RX_LEN(segs[0].ds_len)); 1456 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1457 1458 return (0); 1459 } 1460 1461 /* 1462 * It's not supposed to see this controller on strict-alignment 1463 * architectures but make it work for completeness. 1464 */ 1465 #ifndef __NO_STRICT_ALIGNMENT 1466 static struct mbuf * 1467 vte_fixup_rx(if_t ifp, struct mbuf *m) 1468 { 1469 uint16_t *src, *dst; 1470 int i; 1471 1472 src = mtod(m, uint16_t *); 1473 dst = src - 1; 1474 1475 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1476 *dst++ = *src++; 1477 m->m_data -= ETHER_ALIGN; 1478 return (m); 1479 } 1480 #endif 1481 1482 static void 1483 vte_rxeof(struct vte_softc *sc) 1484 { 1485 if_t ifp; 1486 struct vte_rxdesc *rxd; 1487 struct mbuf *m; 1488 uint16_t status, total_len; 1489 int cons, prog; 1490 1491 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1492 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_POSTREAD | 1493 BUS_DMASYNC_POSTWRITE); 1494 cons = sc->vte_cdata.vte_rx_cons; 1495 ifp = sc->vte_ifp; 1496 for (prog = 0; (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; prog++, 1497 VTE_DESC_INC(cons, VTE_RX_RING_CNT)) { 1498 rxd = &sc->vte_cdata.vte_rxdesc[cons]; 1499 status = le16toh(rxd->rx_desc->drst); 1500 if ((status & VTE_DRST_RX_OWN) != 0) 1501 break; 1502 total_len = VTE_RX_LEN(le16toh(rxd->rx_desc->drlen)); 1503 m = rxd->rx_m; 1504 if ((status & VTE_DRST_RX_OK) == 0) { 1505 /* Discard errored frame. */ 1506 rxd->rx_desc->drlen = 1507 htole16(MCLBYTES - sizeof(uint32_t)); 1508 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1509 continue; 1510 } 1511 if (vte_newbuf(sc, rxd) != 0) { 1512 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1513 rxd->rx_desc->drlen = 1514 htole16(MCLBYTES - sizeof(uint32_t)); 1515 rxd->rx_desc->drst = htole16(VTE_DRST_RX_OWN); 1516 continue; 1517 } 1518 1519 /* 1520 * It seems there is no way to strip FCS bytes. 1521 */ 1522 m->m_pkthdr.len = m->m_len = total_len - ETHER_CRC_LEN; 1523 m->m_pkthdr.rcvif = ifp; 1524 #ifndef __NO_STRICT_ALIGNMENT 1525 vte_fixup_rx(ifp, m); 1526 #endif 1527 VTE_UNLOCK(sc); 1528 if_input(ifp, m); 1529 VTE_LOCK(sc); 1530 } 1531 1532 if (prog > 0) { 1533 /* Update the consumer index. */ 1534 sc->vte_cdata.vte_rx_cons = cons; 1535 /* 1536 * Sync updated RX descriptors such that controller see 1537 * modified RX buffer addresses. 1538 */ 1539 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1540 sc->vte_cdata.vte_rx_ring_map, 1541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1542 #ifdef notyet 1543 /* 1544 * Update residue counter. Controller does not 1545 * keep track of number of available RX descriptors 1546 * such that driver should have to update VTE_MRDCR 1547 * to make controller know how many free RX 1548 * descriptors were added to controller. This is 1549 * a similar mechanism used in VIA velocity 1550 * controllers and it indicates controller just 1551 * polls OWN bit of current RX descriptor pointer. 1552 * A couple of severe issues were seen on sample 1553 * board where the controller continuously emits TX 1554 * pause frames once RX pause threshold crossed. 1555 * Once triggered it never recovered form that 1556 * state, I couldn't find a way to make it back to 1557 * work at least. This issue effectively 1558 * disconnected the system from network. Also, the 1559 * controller used 00:00:00:00:00:00 as source 1560 * station address of TX pause frame. Probably this 1561 * is one of reason why vendor recommends not to 1562 * enable flow control on R6040 controller. 1563 */ 1564 CSR_WRITE_2(sc, VTE_MRDCR, prog | 1565 (((VTE_RX_RING_CNT * 2) / 10) << 1566 VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1567 #endif 1568 } 1569 } 1570 1571 static void 1572 vte_tick(void *arg) 1573 { 1574 struct vte_softc *sc; 1575 struct mii_data *mii; 1576 1577 sc = (struct vte_softc *)arg; 1578 1579 VTE_LOCK_ASSERT(sc); 1580 1581 mii = device_get_softc(sc->vte_miibus); 1582 mii_tick(mii); 1583 vte_stats_update(sc); 1584 vte_txeof(sc); 1585 vte_watchdog(sc); 1586 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1587 } 1588 1589 static void 1590 vte_reset(struct vte_softc *sc) 1591 { 1592 uint16_t mcr, mdcsc; 1593 int i; 1594 1595 mdcsc = CSR_READ_2(sc, VTE_MDCSC); 1596 mcr = CSR_READ_2(sc, VTE_MCR1); 1597 CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET); 1598 for (i = VTE_RESET_TIMEOUT; i > 0; i--) { 1599 DELAY(10); 1600 if ((CSR_READ_2(sc, VTE_MCR1) & MCR1_MAC_RESET) == 0) 1601 break; 1602 } 1603 if (i == 0) 1604 device_printf(sc->vte_dev, "reset timeout(0x%04x)!\n", mcr); 1605 /* 1606 * Follow the guide of vendor recommended way to reset MAC. 1607 * Vendor confirms relying on MCR1_MAC_RESET of VTE_MCR1 is 1608 * not reliable so manually reset internal state machine. 1609 */ 1610 CSR_WRITE_2(sc, VTE_MACSM, 0x0002); 1611 CSR_WRITE_2(sc, VTE_MACSM, 0); 1612 DELAY(5000); 1613 1614 /* 1615 * On some SoCs (like Vortex86DX3) MDC speed control register value 1616 * needs to be restored to original value instead of default one, 1617 * otherwise some PHY registers may fail to be read. 1618 */ 1619 if (mdcsc != MDCSC_DEFAULT) 1620 CSR_WRITE_2(sc, VTE_MDCSC, mdcsc); 1621 } 1622 1623 static void 1624 vte_init(void *xsc) 1625 { 1626 struct vte_softc *sc; 1627 1628 sc = (struct vte_softc *)xsc; 1629 VTE_LOCK(sc); 1630 vte_init_locked(sc); 1631 VTE_UNLOCK(sc); 1632 } 1633 1634 static void 1635 vte_init_locked(struct vte_softc *sc) 1636 { 1637 if_t ifp; 1638 bus_addr_t paddr; 1639 uint8_t *eaddr; 1640 1641 VTE_LOCK_ASSERT(sc); 1642 1643 ifp = sc->vte_ifp; 1644 1645 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1646 return; 1647 /* 1648 * Cancel any pending I/O. 1649 */ 1650 vte_stop(sc); 1651 /* 1652 * Reset the chip to a known state. 1653 */ 1654 vte_reset(sc); 1655 1656 /* Initialize RX descriptors. */ 1657 if (vte_init_rx_ring(sc) != 0) { 1658 device_printf(sc->vte_dev, "no memory for RX buffers.\n"); 1659 vte_stop(sc); 1660 return; 1661 } 1662 if (vte_init_tx_ring(sc) != 0) { 1663 device_printf(sc->vte_dev, "no memory for TX buffers.\n"); 1664 vte_stop(sc); 1665 return; 1666 } 1667 1668 /* 1669 * Reprogram the station address. Controller supports up 1670 * to 4 different station addresses so driver programs the 1671 * first station address as its own ethernet address and 1672 * configure the remaining three addresses as perfect 1673 * multicast addresses. 1674 */ 1675 eaddr = if_getlladdr(sc->vte_ifp); 1676 CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]); 1677 CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]); 1678 CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]); 1679 1680 /* Set TX descriptor base addresses. */ 1681 paddr = sc->vte_cdata.vte_tx_ring_paddr; 1682 CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16); 1683 CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF); 1684 /* Set RX descriptor base addresses. */ 1685 paddr = sc->vte_cdata.vte_rx_ring_paddr; 1686 CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16); 1687 CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF); 1688 /* 1689 * Initialize RX descriptor residue counter and set RX 1690 * pause threshold to 20% of available RX descriptors. 1691 * See comments on vte_rxeof() for details on flow control 1692 * issues. 1693 */ 1694 CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) | 1695 (((VTE_RX_RING_CNT * 2) / 10) << VTE_MRDCR_RX_PAUSE_THRESH_SHIFT)); 1696 1697 /* 1698 * Always use maximum frame size that controller can 1699 * support. Otherwise received frames that has longer 1700 * frame length than vte(4) MTU would be silently dropped 1701 * in controller. This would break path-MTU discovery as 1702 * sender wouldn't get any responses from receiver. The 1703 * RX buffer size should be multiple of 4. 1704 * Note, jumbo frames are silently ignored by controller 1705 * and even MAC counters do not detect them. 1706 */ 1707 CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX); 1708 1709 /* Configure FIFO. */ 1710 CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 | 1711 MBCR_TX_FIFO_THRESH_64 | MBCR_RX_FIFO_THRESH_16 | 1712 MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT); 1713 1714 /* 1715 * Configure TX/RX MACs. Actual resolved duplex and flow 1716 * control configuration is done after detecting a valid 1717 * link. Note, we don't generate early interrupt here 1718 * as well since FreeBSD does not have interrupt latency 1719 * problems like Windows. 1720 */ 1721 CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT); 1722 /* 1723 * We manually keep track of PHY status changes to 1724 * configure resolved duplex and flow control since only 1725 * duplex configuration can be automatically reflected to 1726 * MCR0. 1727 */ 1728 CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 | 1729 MCR1_EXCESS_COL_RETRY_16); 1730 1731 /* Initialize RX filter. */ 1732 vte_rxfilter(sc); 1733 1734 /* Disable TX/RX interrupt moderation control. */ 1735 CSR_WRITE_2(sc, VTE_MRICR, 0); 1736 CSR_WRITE_2(sc, VTE_MTICR, 0); 1737 1738 /* Enable MAC event counter interrupts. */ 1739 CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS); 1740 /* Clear MAC statistics. */ 1741 vte_stats_clear(sc); 1742 1743 /* Acknowledge all pending interrupts and clear it. */ 1744 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); 1745 CSR_WRITE_2(sc, VTE_MISR, 0); 1746 1747 sc->vte_flags &= ~VTE_FLAG_LINK; 1748 /* Switch to the current media. */ 1749 vte_mediachange_locked(ifp); 1750 1751 callout_reset(&sc->vte_tick_ch, hz, vte_tick, sc); 1752 1753 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1754 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1755 } 1756 1757 static void 1758 vte_stop(struct vte_softc *sc) 1759 { 1760 if_t ifp; 1761 struct vte_txdesc *txd; 1762 struct vte_rxdesc *rxd; 1763 int i; 1764 1765 VTE_LOCK_ASSERT(sc); 1766 /* 1767 * Mark the interface down and cancel the watchdog timer. 1768 */ 1769 ifp = sc->vte_ifp; 1770 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1771 sc->vte_flags &= ~VTE_FLAG_LINK; 1772 callout_stop(&sc->vte_tick_ch); 1773 sc->vte_watchdog_timer = 0; 1774 vte_stats_update(sc); 1775 /* Disable interrupts. */ 1776 CSR_WRITE_2(sc, VTE_MIER, 0); 1777 CSR_WRITE_2(sc, VTE_MECIER, 0); 1778 /* Stop RX/TX MACs. */ 1779 vte_stop_mac(sc); 1780 /* Clear interrupts. */ 1781 CSR_READ_2(sc, VTE_MISR); 1782 /* 1783 * Free TX/RX mbufs still in the queues. 1784 */ 1785 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1786 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1787 if (rxd->rx_m != NULL) { 1788 bus_dmamap_sync(sc->vte_cdata.vte_rx_tag, 1789 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1790 bus_dmamap_unload(sc->vte_cdata.vte_rx_tag, 1791 rxd->rx_dmamap); 1792 m_freem(rxd->rx_m); 1793 rxd->rx_m = NULL; 1794 } 1795 } 1796 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1797 txd = &sc->vte_cdata.vte_txdesc[i]; 1798 if (txd->tx_m != NULL) { 1799 bus_dmamap_sync(sc->vte_cdata.vte_tx_tag, 1800 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1801 bus_dmamap_unload(sc->vte_cdata.vte_tx_tag, 1802 txd->tx_dmamap); 1803 if ((txd->tx_flags & VTE_TXMBUF) == 0) 1804 m_freem(txd->tx_m); 1805 txd->tx_m = NULL; 1806 txd->tx_flags &= ~VTE_TXMBUF; 1807 } 1808 } 1809 /* Free TX mbuf pools used for deep copy. */ 1810 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1811 if (sc->vte_cdata.vte_txmbufs[i] != NULL) { 1812 m_freem(sc->vte_cdata.vte_txmbufs[i]); 1813 sc->vte_cdata.vte_txmbufs[i] = NULL; 1814 } 1815 } 1816 } 1817 1818 static void 1819 vte_start_mac(struct vte_softc *sc) 1820 { 1821 uint16_t mcr; 1822 int i; 1823 1824 VTE_LOCK_ASSERT(sc); 1825 1826 /* Enable RX/TX MACs. */ 1827 mcr = CSR_READ_2(sc, VTE_MCR0); 1828 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 1829 (MCR0_RX_ENB | MCR0_TX_ENB)) { 1830 mcr |= MCR0_RX_ENB | MCR0_TX_ENB; 1831 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1832 for (i = VTE_TIMEOUT; i > 0; i--) { 1833 mcr = CSR_READ_2(sc, VTE_MCR0); 1834 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 1835 (MCR0_RX_ENB | MCR0_TX_ENB)) 1836 break; 1837 DELAY(10); 1838 } 1839 if (i == 0) 1840 device_printf(sc->vte_dev, 1841 "could not enable RX/TX MAC(0x%04x)!\n", mcr); 1842 } 1843 } 1844 1845 static void 1846 vte_stop_mac(struct vte_softc *sc) 1847 { 1848 uint16_t mcr; 1849 int i; 1850 1851 VTE_LOCK_ASSERT(sc); 1852 1853 /* Disable RX/TX MACs. */ 1854 mcr = CSR_READ_2(sc, VTE_MCR0); 1855 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) != 0) { 1856 mcr &= ~(MCR0_RX_ENB | MCR0_TX_ENB); 1857 CSR_WRITE_2(sc, VTE_MCR0, mcr); 1858 for (i = VTE_TIMEOUT; i > 0; i--) { 1859 mcr = CSR_READ_2(sc, VTE_MCR0); 1860 if ((mcr & (MCR0_RX_ENB | MCR0_TX_ENB)) == 0) 1861 break; 1862 DELAY(10); 1863 } 1864 if (i == 0) 1865 device_printf(sc->vte_dev, 1866 "could not disable RX/TX MAC(0x%04x)!\n", mcr); 1867 } 1868 } 1869 1870 static int 1871 vte_init_tx_ring(struct vte_softc *sc) 1872 { 1873 struct vte_tx_desc *desc; 1874 struct vte_txdesc *txd; 1875 bus_addr_t addr; 1876 int i; 1877 1878 VTE_LOCK_ASSERT(sc); 1879 1880 sc->vte_cdata.vte_tx_prod = 0; 1881 sc->vte_cdata.vte_tx_cons = 0; 1882 sc->vte_cdata.vte_tx_cnt = 0; 1883 1884 /* Pre-allocate TX mbufs for deep copy. */ 1885 if (tx_deep_copy != 0) { 1886 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1887 sc->vte_cdata.vte_txmbufs[i] = m_getcl(M_NOWAIT, 1888 MT_DATA, M_PKTHDR); 1889 if (sc->vte_cdata.vte_txmbufs[i] == NULL) 1890 return (ENOBUFS); 1891 sc->vte_cdata.vte_txmbufs[i]->m_pkthdr.len = MCLBYTES; 1892 sc->vte_cdata.vte_txmbufs[i]->m_len = MCLBYTES; 1893 } 1894 } 1895 desc = sc->vte_cdata.vte_tx_ring; 1896 bzero(desc, VTE_TX_RING_SZ); 1897 for (i = 0; i < VTE_TX_RING_CNT; i++) { 1898 txd = &sc->vte_cdata.vte_txdesc[i]; 1899 txd->tx_m = NULL; 1900 if (i != VTE_TX_RING_CNT - 1) 1901 addr = sc->vte_cdata.vte_tx_ring_paddr + 1902 sizeof(struct vte_tx_desc) * (i + 1); 1903 else 1904 addr = sc->vte_cdata.vte_tx_ring_paddr + 1905 sizeof(struct vte_tx_desc) * 0; 1906 desc = &sc->vte_cdata.vte_tx_ring[i]; 1907 desc->dtnp = htole32(addr); 1908 txd->tx_desc = desc; 1909 } 1910 1911 bus_dmamap_sync(sc->vte_cdata.vte_tx_ring_tag, 1912 sc->vte_cdata.vte_tx_ring_map, BUS_DMASYNC_PREREAD | 1913 BUS_DMASYNC_PREWRITE); 1914 return (0); 1915 } 1916 1917 static int 1918 vte_init_rx_ring(struct vte_softc *sc) 1919 { 1920 struct vte_rx_desc *desc; 1921 struct vte_rxdesc *rxd; 1922 bus_addr_t addr; 1923 int i; 1924 1925 VTE_LOCK_ASSERT(sc); 1926 1927 sc->vte_cdata.vte_rx_cons = 0; 1928 desc = sc->vte_cdata.vte_rx_ring; 1929 bzero(desc, VTE_RX_RING_SZ); 1930 for (i = 0; i < VTE_RX_RING_CNT; i++) { 1931 rxd = &sc->vte_cdata.vte_rxdesc[i]; 1932 rxd->rx_m = NULL; 1933 if (i != VTE_RX_RING_CNT - 1) 1934 addr = sc->vte_cdata.vte_rx_ring_paddr + 1935 sizeof(struct vte_rx_desc) * (i + 1); 1936 else 1937 addr = sc->vte_cdata.vte_rx_ring_paddr + 1938 sizeof(struct vte_rx_desc) * 0; 1939 desc = &sc->vte_cdata.vte_rx_ring[i]; 1940 desc->drnp = htole32(addr); 1941 rxd->rx_desc = desc; 1942 if (vte_newbuf(sc, rxd) != 0) 1943 return (ENOBUFS); 1944 } 1945 1946 bus_dmamap_sync(sc->vte_cdata.vte_rx_ring_tag, 1947 sc->vte_cdata.vte_rx_ring_map, BUS_DMASYNC_PREREAD | 1948 BUS_DMASYNC_PREWRITE); 1949 1950 return (0); 1951 } 1952 1953 struct vte_maddr_ctx { 1954 uint16_t rxfilt_perf[VTE_RXFILT_PERFECT_CNT][3]; 1955 uint16_t mchash[4]; 1956 u_int nperf; 1957 }; 1958 1959 static u_int 1960 vte_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1961 { 1962 struct vte_maddr_ctx *ctx = arg; 1963 uint8_t *eaddr; 1964 uint32_t crc; 1965 1966 /* 1967 * Program the first 3 multicast groups into the perfect filter. 1968 * For all others, use the hash table. 1969 */ 1970 if (ctx->nperf < VTE_RXFILT_PERFECT_CNT) { 1971 eaddr = LLADDR(sdl); 1972 ctx->rxfilt_perf[ctx->nperf][0] = eaddr[1] << 8 | eaddr[0]; 1973 ctx->rxfilt_perf[ctx->nperf][1] = eaddr[3] << 8 | eaddr[2]; 1974 ctx->rxfilt_perf[ctx->nperf][2] = eaddr[5] << 8 | eaddr[4]; 1975 ctx->nperf++; 1976 1977 return (1); 1978 } 1979 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 1980 ctx->mchash[crc >> 30] |= 1 << ((crc >> 26) & 0x0F); 1981 1982 return (1); 1983 } 1984 1985 static void 1986 vte_rxfilter(struct vte_softc *sc) 1987 { 1988 if_t ifp; 1989 struct vte_maddr_ctx ctx; 1990 uint16_t mcr; 1991 int i; 1992 1993 VTE_LOCK_ASSERT(sc); 1994 1995 ifp = sc->vte_ifp; 1996 1997 bzero(ctx.mchash, sizeof(ctx.mchash)); 1998 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 1999 ctx.rxfilt_perf[i][0] = 0xFFFF; 2000 ctx.rxfilt_perf[i][1] = 0xFFFF; 2001 ctx.rxfilt_perf[i][2] = 0xFFFF; 2002 } 2003 ctx.nperf = 0; 2004 2005 mcr = CSR_READ_2(sc, VTE_MCR0); 2006 mcr &= ~(MCR0_PROMISC | MCR0_MULTICAST); 2007 mcr |= MCR0_BROADCAST_DIS; 2008 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2009 mcr &= ~MCR0_BROADCAST_DIS; 2010 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2011 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2012 mcr |= MCR0_PROMISC; 2013 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2014 mcr |= MCR0_MULTICAST; 2015 ctx.mchash[0] = 0xFFFF; 2016 ctx.mchash[1] = 0xFFFF; 2017 ctx.mchash[2] = 0xFFFF; 2018 ctx.mchash[3] = 0xFFFF; 2019 goto chipit; 2020 } 2021 2022 if_foreach_llmaddr(ifp, vte_hash_maddr, &ctx); 2023 if (ctx.mchash[0] != 0 || ctx.mchash[1] != 0 || 2024 ctx.mchash[2] != 0 || ctx.mchash[3] != 0) 2025 mcr |= MCR0_MULTICAST; 2026 2027 chipit: 2028 /* Program multicast hash table. */ 2029 CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]); 2030 CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]); 2031 CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]); 2032 CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]); 2033 /* Program perfect filter table. */ 2034 for (i = 0; i < VTE_RXFILT_PERFECT_CNT; i++) { 2035 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0, 2036 ctx.rxfilt_perf[i][0]); 2037 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2, 2038 ctx.rxfilt_perf[i][1]); 2039 CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4, 2040 ctx.rxfilt_perf[i][2]); 2041 } 2042 CSR_WRITE_2(sc, VTE_MCR0, mcr); 2043 CSR_READ_2(sc, VTE_MCR0); 2044 } 2045 2046 static int 2047 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2048 { 2049 int error, value; 2050 2051 if (arg1 == NULL) 2052 return (EINVAL); 2053 value = *(int *)arg1; 2054 error = sysctl_handle_int(oidp, &value, 0, req); 2055 if (error || req->newptr == NULL) 2056 return (error); 2057 if (value < low || value > high) 2058 return (EINVAL); 2059 *(int *)arg1 = value; 2060 2061 return (0); 2062 } 2063 2064 static int 2065 sysctl_hw_vte_int_mod(SYSCTL_HANDLER_ARGS) 2066 { 2067 2068 return (sysctl_int_range(oidp, arg1, arg2, req, 2069 VTE_IM_BUNDLE_MIN, VTE_IM_BUNDLE_MAX)); 2070 } 2071