1 /*- 2 * Copyright (c) 2005 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef _DEV_VT_HW_VGA_VGA_REG_H_ 28 #define _DEV_VT_HW_VGA_VGA_REG_H_ 29 30 /* 31 * The VGA adapter uses two I/O port blocks. One of these blocks, the CRT 32 * controller registers, can be located either at 0x3B0 or at 0x3D0 in I/O 33 * port space. This allows compatibility with the monochrome adapter, which 34 * has the CRT controller registers at 0x3B0. 35 * 36 * It is assumed that compatibility with the monochrome adapter is not of 37 * interest anymore. As such, the CRT controller can be located at 0x3D0 in 38 * I/O port space unconditionally. This means that the 2 I/O blocks are 39 * always adjacent and can therefore be treated as a single logical I/O port 40 * range. In practical terms: there only has to be a single tag and handle 41 * to access all registers. 42 * 43 * The following definitions are taken from or inspired by: 44 * Programmer's Guide to the EGA, VGA, and Super VGA Cards -- 3rd ed., 45 * Richard F. Ferraro, Addison-Wesley, ISBN 0-201-62490-7 46 */ 47 48 #define VGA_MEM_BASE 0xA0000 49 #define VGA_MEM_SIZE 0x10000 50 #define VGA_TXT_BASE 0xB8000 51 #define VGA_TXT_SIZE 0x08000 52 #define VGA_REG_BASE 0x3c0 53 #define VGA_REG_SIZE 0x10+0x0c 54 55 /* Attribute controller registers. */ 56 #define VGA_AC_WRITE 0x00 57 #define VGA_AC_READ 0x01 58 #define VGA_AC_PALETTE(x) (x) /* 0 <= x <= 15 */ 59 #define VGA_AC_PAL_SR 0x20 /* Secondary red */ 60 #define VGA_AC_PAL_SG 0x10 /* Secondary green */ 61 #define VGA_AC_PAL_SB 0x08 /* Secondary blue */ 62 #define VGA_AC_PAL_R 0x04 /* Red */ 63 #define VGA_AC_PAL_G 0x02 /* Green */ 64 #define VGA_AC_PAL_B 0x01 /* Blue */ 65 #define VGA_AC_MODE_CONTROL (32+16) 66 #define VGA_AC_MC_IPS 0x80 /* Internal palette size */ 67 #define VGA_AC_MC_PCS 0x40 /* Pixel clock select */ 68 #define VGA_AC_MC_PPC 0x20 /* Pixel panning compat. */ 69 #define VGA_AC_MC_BI 0x08 /* Blink/intensity */ 70 #define VGA_AC_MC_ELG 0x04 /* Enable line graphics cc. */ 71 #define VGA_AC_MC_DT 0x02 /* Display type */ 72 #define VGA_AC_MC_GA 0x01 /* Graphics/alphanumeric */ 73 #define VGA_AC_OVERSCAN_COLOR (32+17) 74 #define VGA_AC_COLOR_PLANE_ENABLE (32+18) 75 #define VGA_AC_HORIZ_PIXEL_PANNING (32+19) 76 #define VGA_AC_COLOR_SELECT (32+20) 77 #define VGA_AC_CS_C67 0x0C /* Color reg. addr. bits 6+7 */ 78 #define VGA_AC_CS_C45 0x03 /* Color reg. addr. bits 4+5 */ 79 80 /* General registers. */ 81 #define VGA_GEN_MISC_OUTPUT_W 0x02 /* Write only. */ 82 #define VGA_GEN_MISC_OUTPUT_R 0x0c /* Read only. */ 83 #define VGA_GEN_MO_VSP 0x80 /* Vertical sync. polarity */ 84 #define VGA_GEN_MO_HSP 0x40 /* Horiz. sync. polarity */ 85 #define VGA_GEN_MO_PB 0x20 /* Page bit for odd/even */ 86 #define VGA_GEN_MO_CS 0x0C /* Clock select */ 87 #define VGA_GEN_MO_ER 0x02 /* Enable RAM */ 88 #define VGA_GEN_MO_IOA 0x01 /* Input/output address */ 89 #define VGA_GEN_INPUT_STAT_0 0x02 /* Read only. */ 90 #define VGA_GEN_FEATURE_CTRL_W 0x1a /* Write only. */ 91 #define VGA_GEN_FEATURE_CTRL_R 0x0a /* Read only. */ 92 #define VGA_GEN_INPUT_STAT_1 0x1a /* Read only. */ 93 #define VGA_GEN_IS1_VR 0x08 /* Vertical retrace */ 94 #define VGA_GEN_IS1_DE 0x01 /* Display enable not */ 95 96 /* Sequencer registers. */ 97 #define VGA_SEQ_ADDRESS 0x04 98 #define VGA_SEQ_RESET 0 99 #define VGA_SEQ_RST_SR 0x02 /* Synchronous reset */ 100 #define VGA_SEQ_RST_NAR 0x01 /* No async. reset */ 101 #define VGA_SEQ_CLOCKING_MODE 1 102 #define VGA_SEQ_CM_SO 0x20 /* Screen off */ 103 #define VGA_SEQ_CM_S4 0x10 /* Shift four */ 104 #define VGA_SEQ_CM_DC 0x08 /* Dot clock */ 105 #define VGA_SEQ_CM_SL 0x04 /* Shift load */ 106 #define VGA_SEQ_CM_89 0x01 /* 8/9 Dot clocks */ 107 #define VGA_SEQ_MAP_MASK 2 108 #define VGA_SEQ_MM_EM3 0x08 /* Enable memory plane 3 */ 109 #define VGA_SEQ_MM_EM2 0x04 /* Enable memory plane 2 */ 110 #define VGA_SEQ_MM_EM1 0x02 /* Enable memory plane 1 */ 111 #define VGA_SEQ_MM_EM0 0x01 /* Enable memory plane 0 */ 112 #define VGA_SEQ_CHAR_MAP_SELECT 3 113 #define VGA_SEQ_CMS_SAH 0x20 /* Char. A (bit 2) */ 114 #define VGA_SEQ_CMS_SBH 0x10 /* Char. B (bit 2) */ 115 #define VGA_SEQ_CMS_SA 0x0C /* Char. A (bit 0+1) */ 116 #define VGA_SEQ_CMS_SB 0x03 /* Char. B (bit 0+1) */ 117 #define VGA_SEQ_MEMORY_MODE 4 118 #define VGA_SEQ_MM_C4 0x08 /* Chain four */ 119 #define VGA_SEQ_MM_OE 0x04 /* Odd/even */ 120 #define VGA_SEQ_MM_EM 0x02 /* Extended memory */ 121 #define VGA_SEQ_DATA 0x05 122 123 /* Color registers. */ 124 #define VGA_PEL_MASK 0x06 125 #define VGA_PEL_ADDR_RD_MODE 0x07 /* Write only. */ 126 #define VGA_DAC_STATE 0x07 /* Read only. */ 127 #define VGA_PEL_ADDR_WR_MODE 0x08 128 #define VGA_PEL_DATA 0x09 129 130 /* Graphics controller registers. */ 131 #define VGA_GC_ADDRESS 0x0e 132 #define VGA_GC_SET_RESET 0 133 #define VGA_GC_ENABLE_SET_RESET 1 134 #define VGA_GC_COLOR_COMPARE 2 135 #define VGA_GC_DATA_ROTATE 3 136 #define VGA_GC_DR_FS_XOR 0x18 /* Function select - XOR */ 137 #define VGA_GC_DR_FS_OR 0x10 /* Function select - OR */ 138 #define VGA_GC_DR_FS_AND 0x08 /* Function select - AND */ 139 #define VGA_GC_DR_RC 0x07 /* Rotate count */ 140 #define VGA_GC_READ_MAP_SELECT 4 141 #define VGA_GC_MODE 5 142 #define VGA_GC_MODE_SR 0x60 /* Shift register */ 143 #define VGA_GC_MODE_OE 0x10 /* Odd/even */ 144 #define VGA_GC_MODE_RM 0x08 /* Read mode */ 145 #define VGA_GC_MODE_WM 0x03 /* Write mode */ 146 #define VGA_GC_MISCELLANEOUS 6 147 #define VGA_GC_MISC_MM 0x0C /* memory map */ 148 #define VGA_GC_MISC_COE 0x02 /* Chain odd/even */ 149 #define VGA_GC_MISC_GA 0x01 /* Graphics/text mode */ 150 #define VGA_GC_COLOR_DONT_CARE 7 151 #define VGA_GC_BIT_MASK 8 152 #define VGA_GC_DATA 0x0f 153 154 /* CRT controller registers. */ 155 #define VGA_CRTC_ADDRESS 0x14 156 #define VGA_CRTC_HORIZ_TOTAL 0 157 #define VGA_CRTC_HORIZ_DISP_END 1 158 #define VGA_CRTC_START_HORIZ_BLANK 2 159 #define VGA_CRTC_END_HORIZ_BLANK 3 160 #define VGA_CRTC_EHB_CR 0x80 /* Compatible read */ 161 #define VGA_CRTC_EHB_DES 0x60 /* Display enable skew */ 162 #define VGA_CRTC_EHB_EHB 0x1F /* End horizontal blank */ 163 #define VGA_CRTC_START_HORIZ_RETRACE 4 164 #define VGA_CRTC_END_HORIZ_RETRACE 5 165 #define VGA_CRTC_EHR_EHB 0x80 /* End horizontal blanking */ 166 #define VGA_CRTC_EHR_HRD 0x60 /* Horizontal retrace delay */ 167 #define VGA_CRTC_EHR_EHR 0x1F /* End horizontal retrace */ 168 #define VGA_CRTC_VERT_TOTAL 6 169 #define VGA_CRTC_OVERFLOW 7 170 #define VGA_CRTC_OF_VRS9 0x80 /* Vertical retrace start */ 171 #define VGA_CRTC_OF_VDE9 0x40 /* Vertical disp. enable end */ 172 #define VGA_CRTC_OF_VT9 0x20 /* Vertical total (bit 9) */ 173 #define VGA_CRTC_OF_LC8 0x10 /* Line compare */ 174 #define VGA_CRTC_OF_VBS8 0x08 /* Start vertical blanking */ 175 #define VGA_CRTC_OF_VRS8 0x04 /* Vertical retrace start */ 176 #define VGA_CRTC_OF_VDE8 0x02 /* Vertical disp. enable end */ 177 #define VGA_CRTC_OF_VT8 0x01 /* Vertical total (bit 8) */ 178 #define VGA_CRTC_PRESET_ROW_SCAN 8 179 #define VGA_CRTC_PRS_BP 0x60 /* Byte panning */ 180 #define VGA_CRTC_PRS_PRS 0x1F /* Preset row scan */ 181 #define VGA_CRTC_MAX_SCAN_LINE 9 182 #define VGA_CRTC_MSL_2T4 0x80 /* 200-to-400 line conversion */ 183 #define VGA_CRTC_MSL_LC9 0x40 /* Line compare (bit 9) */ 184 #define VGA_CRTC_MSL_VBS9 0x20 /* Start vertical blanking */ 185 #define VGA_CRTC_MSL_MSL 0x1F /* Maximum scan line */ 186 #define VGA_CRTC_CURSOR_START 10 187 #define VGA_CRTC_CS_COO 0x20 /* Cursor on/off */ 188 #define VGA_CRTC_CS_CS 0x1F /* Cursor start */ 189 #define VGA_CRTC_CURSOR_END 11 190 #define VGA_CRTC_CE_CSK 0x60 /* Cursor skew */ 191 #define VGA_CRTC_CE_CE 0x1F /* Cursor end */ 192 #define VGA_CRTC_START_ADDR_HIGH 12 193 #define VGA_CRTC_START_ADDR_LOW 13 194 #define VGA_CRTC_CURSOR_LOC_HIGH 14 195 #define VGA_CRTC_CURSOR_LOC_LOW 15 196 #define VGA_CRTC_VERT_RETRACE_START 16 197 #define VGA_CRTC_VERT_RETRACE_END 17 198 #define VGA_CRTC_VRE_PR 0x80 /* Protect register 0-7 */ 199 #define VGA_CRTC_VRE_BW 0x40 /* Bandwidth */ 200 #define VGA_CRTC_VRE_VRE 0x1F /* Vertical retrace end */ 201 #define VGA_CRTC_VERT_DISPLAY_END 18 202 #define VGA_CRTC_OFFSET 19 203 #define VGA_CRTC_UNDERLINE_LOC 20 204 #define VGA_CRTC_UL_DW 0x40 /* Double word mode */ 205 #define VGA_CRTC_UL_CB4 0x20 /* Count by four */ 206 #define VGA_CRTC_UL_UL 0x1F /* Underline location */ 207 #define VGA_CRTC_START_VERT_BLANK 21 208 #define VGA_CRTC_END_VERT_BLANK 22 209 #define VGA_CRTC_MODE_CONTROL 23 210 #define VGA_CRTC_MC_HR 0x80 /* hardware reset */ 211 #define VGA_CRTC_MC_WB 0x40 /* Word/byte mode */ 212 #define VGA_CRTC_MC_AW 0x20 /* Address wrap */ 213 #define VGA_CRTC_MC_CBT 0x08 /* Count by two */ 214 #define VGA_CRTC_MC_HRS 0x04 /* Horizontal retrace select */ 215 #define VGA_CRTC_MC_SRS 0x02 /* Select row scan counter */ 216 #define VGA_CRTC_MC_CMS 0x01 /* Compatibility mode support */ 217 #define VGA_CRTC_LINE_COMPARE 24 218 #define VGA_CRTC_DATA 0x15 219 220 #endif /* !_DEV_VT_HW_VGA_VGA_REG_H_ */ 221