1 /*- 2 * Copyright (c) 2005 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Copyright (c) 2009 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by Ed Schouten 9 * under sponsorship from the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include "opt_acpi.h" 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 #include <sys/param.h> 39 #include <sys/kernel.h> 40 #include <sys/systm.h> 41 #include <sys/bus.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 45 #include <dev/vt/vt.h> 46 #include <dev/vt/colors/vt_termcolors.h> 47 #include <dev/vt/hw/vga/vt_vga_reg.h> 48 #include <dev/pci/pcivar.h> 49 50 #include <machine/bus.h> 51 52 #if ((defined(__amd64__) || defined(__i386__)) && defined(DEV_ACPI)) 53 #include <contrib/dev/acpica/include/acpi.h> 54 #endif 55 56 struct vga_softc { 57 bus_space_tag_t vga_fb_tag; 58 bus_space_handle_t vga_fb_handle; 59 bus_space_tag_t vga_reg_tag; 60 bus_space_handle_t vga_reg_handle; 61 int vga_wmode; 62 term_color_t vga_curfg, vga_curbg; 63 boolean_t vga_enabled; 64 }; 65 66 /* Convenience macros. */ 67 #define MEM_READ1(sc, ofs) \ 68 bus_space_read_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs) 69 #define MEM_WRITE1(sc, ofs, val) \ 70 bus_space_write_1(sc->vga_fb_tag, sc->vga_fb_handle, ofs, val) 71 #define REG_READ1(sc, reg) \ 72 bus_space_read_1(sc->vga_reg_tag, sc->vga_reg_handle, reg) 73 #define REG_WRITE1(sc, reg, val) \ 74 bus_space_write_1(sc->vga_reg_tag, sc->vga_reg_handle, reg, val) 75 76 #define VT_VGA_WIDTH 640 77 #define VT_VGA_HEIGHT 480 78 #define VT_VGA_MEMSIZE (VT_VGA_WIDTH * VT_VGA_HEIGHT / 8) 79 80 /* 81 * VGA is designed to handle 8 pixels at a time (8 pixels in one byte of 82 * memory). 83 */ 84 #define VT_VGA_PIXELS_BLOCK 8 85 86 /* 87 * We use an off-screen addresses to: 88 * o store the background color; 89 * o store pixels pattern. 90 * Those addresses are then loaded in the latches once. 91 */ 92 #define VT_VGA_BGCOLOR_OFFSET VT_VGA_MEMSIZE 93 94 static vd_probe_t vga_probe; 95 static vd_init_t vga_init; 96 static vd_blank_t vga_blank; 97 static vd_bitblt_text_t vga_bitblt_text; 98 static vd_bitblt_bmp_t vga_bitblt_bitmap; 99 static vd_drawrect_t vga_drawrect; 100 static vd_setpixel_t vga_setpixel; 101 static vd_postswitch_t vga_postswitch; 102 103 static const struct vt_driver vt_vga_driver = { 104 .vd_name = "vga", 105 .vd_probe = vga_probe, 106 .vd_init = vga_init, 107 .vd_blank = vga_blank, 108 .vd_bitblt_text = vga_bitblt_text, 109 .vd_bitblt_bmp = vga_bitblt_bitmap, 110 .vd_drawrect = vga_drawrect, 111 .vd_setpixel = vga_setpixel, 112 .vd_postswitch = vga_postswitch, 113 .vd_priority = VD_PRIORITY_GENERIC, 114 }; 115 116 /* 117 * Driver supports both text mode and graphics mode. Make sure the 118 * buffer is always big enough to support both. 119 */ 120 static struct vga_softc vga_conssoftc; 121 VT_DRIVER_DECLARE(vt_vga, vt_vga_driver); 122 123 static inline void 124 vga_setwmode(struct vt_device *vd, int wmode) 125 { 126 struct vga_softc *sc = vd->vd_softc; 127 128 if (sc->vga_wmode == wmode) 129 return; 130 131 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); 132 REG_WRITE1(sc, VGA_GC_DATA, wmode); 133 sc->vga_wmode = wmode; 134 135 switch (wmode) { 136 case 3: 137 /* Re-enable all plans. */ 138 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); 139 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | 140 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); 141 break; 142 } 143 } 144 145 static inline void 146 vga_setfg(struct vt_device *vd, term_color_t color) 147 { 148 struct vga_softc *sc = vd->vd_softc; 149 150 vga_setwmode(vd, 3); 151 152 if (sc->vga_curfg == color) 153 return; 154 155 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); 156 REG_WRITE1(sc, VGA_GC_DATA, cons_to_vga_colors[color]); 157 sc->vga_curfg = color; 158 } 159 160 static inline void 161 vga_setbg(struct vt_device *vd, term_color_t color) 162 { 163 struct vga_softc *sc = vd->vd_softc; 164 165 vga_setwmode(vd, 3); 166 167 if (sc->vga_curbg == color) 168 return; 169 170 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); 171 REG_WRITE1(sc, VGA_GC_DATA, cons_to_vga_colors[color]); 172 173 /* 174 * Write 8 pixels using the background color to an off-screen 175 * byte in the video memory. 176 */ 177 MEM_WRITE1(sc, VT_VGA_BGCOLOR_OFFSET, 0xff); 178 179 /* 180 * Read those 8 pixels back to load the background color in the 181 * latches register. 182 */ 183 MEM_READ1(sc, VT_VGA_BGCOLOR_OFFSET); 184 185 sc->vga_curbg = color; 186 187 /* 188 * The Set/Reset register doesn't contain the fg color anymore, 189 * store an invalid color. 190 */ 191 sc->vga_curfg = 0xff; 192 } 193 194 /* 195 * Binary searchable table for Unicode to CP437 conversion. 196 */ 197 198 struct unicp437 { 199 uint16_t unicode_base; 200 uint8_t cp437_base; 201 uint8_t length; 202 }; 203 204 static const struct unicp437 cp437table[] = { 205 { 0x0020, 0x20, 0x5e }, { 0x00a0, 0x20, 0x00 }, 206 { 0x00a1, 0xad, 0x00 }, { 0x00a2, 0x9b, 0x00 }, 207 { 0x00a3, 0x9c, 0x00 }, { 0x00a5, 0x9d, 0x00 }, 208 { 0x00a6, 0x7c, 0x00 }, 209 { 0x00a7, 0x15, 0x00 }, { 0x00aa, 0xa6, 0x00 }, 210 { 0x00ab, 0xae, 0x00 }, { 0x00ac, 0xaa, 0x00 }, 211 { 0x00b0, 0xf8, 0x00 }, { 0x00b1, 0xf1, 0x00 }, 212 { 0x00b2, 0xfd, 0x00 }, { 0x00b5, 0xe6, 0x00 }, 213 { 0x00b6, 0x14, 0x00 }, { 0x00b7, 0xfa, 0x00 }, 214 { 0x00ba, 0xa7, 0x00 }, { 0x00bb, 0xaf, 0x00 }, 215 { 0x00bc, 0xac, 0x00 }, { 0x00bd, 0xab, 0x00 }, 216 { 0x00bf, 0xa8, 0x00 }, { 0x00c4, 0x8e, 0x01 }, 217 { 0x00c6, 0x92, 0x00 }, { 0x00c7, 0x80, 0x00 }, 218 { 0x00c9, 0x90, 0x00 }, { 0x00d1, 0xa5, 0x00 }, 219 { 0x00d6, 0x99, 0x00 }, { 0x00dc, 0x9a, 0x00 }, 220 { 0x00df, 0xe1, 0x00 }, { 0x00e0, 0x85, 0x00 }, 221 { 0x00e1, 0xa0, 0x00 }, { 0x00e2, 0x83, 0x00 }, 222 { 0x00e4, 0x84, 0x00 }, { 0x00e5, 0x86, 0x00 }, 223 { 0x00e6, 0x91, 0x00 }, { 0x00e7, 0x87, 0x00 }, 224 { 0x00e8, 0x8a, 0x00 }, { 0x00e9, 0x82, 0x00 }, 225 { 0x00ea, 0x88, 0x01 }, { 0x00ec, 0x8d, 0x00 }, 226 { 0x00ed, 0xa1, 0x00 }, { 0x00ee, 0x8c, 0x00 }, 227 { 0x00ef, 0x8b, 0x00 }, { 0x00f0, 0xeb, 0x00 }, 228 { 0x00f1, 0xa4, 0x00 }, { 0x00f2, 0x95, 0x00 }, 229 { 0x00f3, 0xa2, 0x00 }, { 0x00f4, 0x93, 0x00 }, 230 { 0x00f6, 0x94, 0x00 }, { 0x00f7, 0xf6, 0x00 }, 231 { 0x00f8, 0xed, 0x00 }, { 0x00f9, 0x97, 0x00 }, 232 { 0x00fa, 0xa3, 0x00 }, { 0x00fb, 0x96, 0x00 }, 233 { 0x00fc, 0x81, 0x00 }, { 0x00ff, 0x98, 0x00 }, 234 { 0x0192, 0x9f, 0x00 }, { 0x0393, 0xe2, 0x00 }, 235 { 0x0398, 0xe9, 0x00 }, { 0x03a3, 0xe4, 0x00 }, 236 { 0x03a6, 0xe8, 0x00 }, { 0x03a9, 0xea, 0x00 }, 237 { 0x03b1, 0xe0, 0x01 }, { 0x03b4, 0xeb, 0x00 }, 238 { 0x03b5, 0xee, 0x00 }, { 0x03bc, 0xe6, 0x00 }, 239 { 0x03c0, 0xe3, 0x00 }, { 0x03c3, 0xe5, 0x00 }, 240 { 0x03c4, 0xe7, 0x00 }, { 0x03c6, 0xed, 0x00 }, 241 { 0x03d5, 0xed, 0x00 }, { 0x2010, 0x2d, 0x00 }, 242 { 0x2013, 0x2d, 0x00 }, 243 { 0x2014, 0x2d, 0x00 }, { 0x2018, 0x60, 0x00 }, 244 { 0x2019, 0x27, 0x00 }, { 0x201c, 0x22, 0x00 }, 245 { 0x201d, 0x22, 0x00 }, { 0x2022, 0x07, 0x00 }, 246 { 0x203c, 0x13, 0x00 }, { 0x207f, 0xfc, 0x00 }, 247 { 0x20a7, 0x9e, 0x00 }, { 0x20ac, 0xee, 0x00 }, 248 { 0x2126, 0xea, 0x00 }, { 0x2190, 0x1b, 0x00 }, 249 { 0x2191, 0x18, 0x00 }, { 0x2192, 0x1a, 0x00 }, 250 { 0x2193, 0x19, 0x00 }, { 0x2194, 0x1d, 0x00 }, 251 { 0x2195, 0x12, 0x00 }, { 0x21a8, 0x17, 0x00 }, 252 { 0x2202, 0xeb, 0x00 }, { 0x2208, 0xee, 0x00 }, 253 { 0x2211, 0xe4, 0x00 }, { 0x2212, 0x2d, 0x00 }, 254 { 0x2219, 0xf9, 0x00 }, { 0x221a, 0xfb, 0x00 }, 255 { 0x221e, 0xec, 0x00 }, { 0x221f, 0x1c, 0x00 }, 256 { 0x2229, 0xef, 0x00 }, { 0x2248, 0xf7, 0x00 }, 257 { 0x2261, 0xf0, 0x00 }, { 0x2264, 0xf3, 0x00 }, 258 { 0x2265, 0xf2, 0x00 }, { 0x2302, 0x7f, 0x00 }, 259 { 0x2310, 0xa9, 0x00 }, { 0x2320, 0xf4, 0x00 }, 260 { 0x2321, 0xf5, 0x00 }, { 0x2500, 0xc4, 0x00 }, 261 { 0x2502, 0xb3, 0x00 }, { 0x250c, 0xda, 0x00 }, 262 { 0x2510, 0xbf, 0x00 }, { 0x2514, 0xc0, 0x00 }, 263 { 0x2518, 0xd9, 0x00 }, { 0x251c, 0xc3, 0x00 }, 264 { 0x2524, 0xb4, 0x00 }, { 0x252c, 0xc2, 0x00 }, 265 { 0x2534, 0xc1, 0x00 }, { 0x253c, 0xc5, 0x00 }, 266 { 0x2550, 0xcd, 0x00 }, { 0x2551, 0xba, 0x00 }, 267 { 0x2552, 0xd5, 0x00 }, { 0x2553, 0xd6, 0x00 }, 268 { 0x2554, 0xc9, 0x00 }, { 0x2555, 0xb8, 0x00 }, 269 { 0x2556, 0xb7, 0x00 }, { 0x2557, 0xbb, 0x00 }, 270 { 0x2558, 0xd4, 0x00 }, { 0x2559, 0xd3, 0x00 }, 271 { 0x255a, 0xc8, 0x00 }, { 0x255b, 0xbe, 0x00 }, 272 { 0x255c, 0xbd, 0x00 }, { 0x255d, 0xbc, 0x00 }, 273 { 0x255e, 0xc6, 0x01 }, { 0x2560, 0xcc, 0x00 }, 274 { 0x2561, 0xb5, 0x00 }, { 0x2562, 0xb6, 0x00 }, 275 { 0x2563, 0xb9, 0x00 }, { 0x2564, 0xd1, 0x01 }, 276 { 0x2566, 0xcb, 0x00 }, { 0x2567, 0xcf, 0x00 }, 277 { 0x2568, 0xd0, 0x00 }, { 0x2569, 0xca, 0x00 }, 278 { 0x256a, 0xd8, 0x00 }, { 0x256b, 0xd7, 0x00 }, 279 { 0x256c, 0xce, 0x00 }, { 0x2580, 0xdf, 0x00 }, 280 { 0x2584, 0xdc, 0x00 }, { 0x2588, 0xdb, 0x00 }, 281 { 0x258c, 0xdd, 0x00 }, { 0x2590, 0xde, 0x00 }, 282 { 0x2591, 0xb0, 0x02 }, { 0x25a0, 0xfe, 0x00 }, 283 { 0x25ac, 0x16, 0x00 }, { 0x25b2, 0x1e, 0x00 }, 284 { 0x25ba, 0x10, 0x00 }, { 0x25bc, 0x1f, 0x00 }, 285 { 0x25c4, 0x11, 0x00 }, { 0x25cb, 0x09, 0x00 }, 286 { 0x25d8, 0x08, 0x00 }, { 0x25d9, 0x0a, 0x00 }, 287 { 0x263a, 0x01, 0x01 }, { 0x263c, 0x0f, 0x00 }, 288 { 0x2640, 0x0c, 0x00 }, { 0x2642, 0x0b, 0x00 }, 289 { 0x2660, 0x06, 0x00 }, { 0x2663, 0x05, 0x00 }, 290 { 0x2665, 0x03, 0x01 }, { 0x266a, 0x0d, 0x00 }, 291 { 0x266c, 0x0e, 0x00 }, { 0x2713, 0xfb, 0x00 }, 292 { 0x27e8, 0x3c, 0x00 }, { 0x27e9, 0x3e, 0x00 }, 293 }; 294 295 static uint8_t 296 vga_get_cp437(term_char_t c) 297 { 298 int min, mid, max; 299 300 min = 0; 301 max = nitems(cp437table) - 1; 302 303 if (c < cp437table[0].unicode_base || 304 c > cp437table[max].unicode_base + cp437table[max].length) 305 return '?'; 306 307 while (max >= min) { 308 mid = (min + max) / 2; 309 if (c < cp437table[mid].unicode_base) 310 max = mid - 1; 311 else if (c > cp437table[mid].unicode_base + 312 cp437table[mid].length) 313 min = mid + 1; 314 else 315 return (c - cp437table[mid].unicode_base + 316 cp437table[mid].cp437_base); 317 } 318 319 return '?'; 320 } 321 322 static void 323 vga_blank(struct vt_device *vd, term_color_t color) 324 { 325 struct vga_softc *sc = vd->vd_softc; 326 u_int ofs; 327 328 vga_setfg(vd, color); 329 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) 330 MEM_WRITE1(sc, ofs, 0xff); 331 } 332 333 static inline void 334 vga_bitblt_put(struct vt_device *vd, u_long dst, term_color_t color, 335 uint8_t v) 336 { 337 struct vga_softc *sc = vd->vd_softc; 338 339 /* Skip empty writes, in order to avoid palette changes. */ 340 if (v != 0x00) { 341 vga_setfg(vd, color); 342 /* 343 * When this MEM_READ1() gets disabled, all sorts of 344 * artifacts occur. This is because this read loads the 345 * set of 8 pixels that are about to be changed. There 346 * is one scenario where we can avoid the read, namely 347 * if all pixels are about to be overwritten anyway. 348 */ 349 if (v != 0xff) { 350 MEM_READ1(sc, dst); 351 352 /* The bg color was trashed by the reads. */ 353 sc->vga_curbg = 0xff; 354 } 355 MEM_WRITE1(sc, dst, v); 356 } 357 } 358 359 static void 360 vga_setpixel(struct vt_device *vd, int x, int y, term_color_t color) 361 { 362 363 if (vd->vd_flags & VDF_TEXTMODE) 364 return; 365 366 vga_bitblt_put(vd, (y * VT_VGA_WIDTH / 8) + (x / 8), color, 367 0x80 >> (x % 8)); 368 } 369 370 static void 371 vga_drawrect(struct vt_device *vd, int x1, int y1, int x2, int y2, int fill, 372 term_color_t color) 373 { 374 int x, y; 375 376 if (vd->vd_flags & VDF_TEXTMODE) 377 return; 378 379 for (y = y1; y <= y2; y++) { 380 if (fill || (y == y1) || (y == y2)) { 381 for (x = x1; x <= x2; x++) 382 vga_setpixel(vd, x, y, color); 383 } else { 384 vga_setpixel(vd, x1, y, color); 385 vga_setpixel(vd, x2, y, color); 386 } 387 } 388 } 389 390 static void 391 vga_compute_shifted_pattern(const uint8_t *src, unsigned int bytes, 392 unsigned int src_x, unsigned int x_count, unsigned int dst_x, 393 uint8_t *pattern, uint8_t *mask) 394 { 395 unsigned int n; 396 397 n = src_x / 8; 398 399 /* 400 * This mask has bits set, where a pixel (ether 0 or 1) 401 * comes from the source bitmap. 402 */ 403 if (mask != NULL) { 404 *mask = (0xff 405 >> (8 - x_count)) 406 << (8 - x_count - dst_x); 407 } 408 409 if (n == (src_x + x_count - 1) / 8) { 410 /* All the pixels we want are in the same byte. */ 411 *pattern = src[n]; 412 if (dst_x >= src_x) 413 *pattern >>= (dst_x - src_x % 8); 414 else 415 *pattern <<= (src_x % 8 - dst_x); 416 } else { 417 /* The pixels we want are split into two bytes. */ 418 if (dst_x >= src_x % 8) { 419 *pattern = 420 src[n] << (8 - dst_x - src_x % 8) | 421 src[n + 1] >> (dst_x - src_x % 8); 422 } else { 423 *pattern = 424 src[n] << (src_x % 8 - dst_x) | 425 src[n + 1] >> (8 - src_x % 8 - dst_x); 426 } 427 } 428 } 429 430 static void 431 vga_copy_bitmap_portion(uint8_t *pattern_2colors, uint8_t *pattern_ncolors, 432 const uint8_t *src, const uint8_t *src_mask, unsigned int src_width, 433 unsigned int src_x, unsigned int dst_x, unsigned int x_count, 434 unsigned int src_y, unsigned int dst_y, unsigned int y_count, 435 term_color_t fg, term_color_t bg, int overwrite) 436 { 437 unsigned int i, bytes; 438 uint8_t pattern, relevant_bits, mask; 439 440 bytes = (src_width + 7) / 8; 441 442 for (i = 0; i < y_count; ++i) { 443 vga_compute_shifted_pattern(src + (src_y + i) * bytes, 444 bytes, src_x, x_count, dst_x, &pattern, &relevant_bits); 445 446 if (src_mask == NULL) { 447 /* 448 * No src mask. Consider that all wanted bits 449 * from the source are "authoritative". 450 */ 451 mask = relevant_bits; 452 } else { 453 /* 454 * There's an src mask. We shift it the same way 455 * we shifted the source pattern. 456 */ 457 vga_compute_shifted_pattern( 458 src_mask + (src_y + i) * bytes, 459 bytes, src_x, x_count, dst_x, 460 &mask, NULL); 461 462 /* Now, only keep the wanted bits among them. */ 463 mask &= relevant_bits; 464 } 465 466 /* 467 * Clear bits from the pattern which must be 468 * transparent, according to the source mask. 469 */ 470 pattern &= mask; 471 472 /* Set the bits in the 2-colors array. */ 473 if (overwrite) 474 pattern_2colors[dst_y + i] &= ~mask; 475 pattern_2colors[dst_y + i] |= pattern; 476 477 if (pattern_ncolors == NULL) 478 continue; 479 480 /* 481 * Set the same bits in the n-colors array. This one 482 * supports transparency, when a given bit is cleared in 483 * all colors. 484 */ 485 if (overwrite) { 486 /* 487 * Ensure that the pixels used by this bitmap are 488 * cleared in other colors. 489 */ 490 for (int j = 0; j < 16; ++j) 491 pattern_ncolors[(dst_y + i) * 16 + j] &= 492 ~mask; 493 } 494 pattern_ncolors[(dst_y + i) * 16 + fg] |= pattern; 495 pattern_ncolors[(dst_y + i) * 16 + bg] |= (~pattern & mask); 496 } 497 } 498 499 static void 500 vga_bitblt_pixels_block_2colors(struct vt_device *vd, const uint8_t *masks, 501 term_color_t fg, term_color_t bg, 502 unsigned int x, unsigned int y, unsigned int height) 503 { 504 unsigned int i, offset; 505 struct vga_softc *sc; 506 507 /* 508 * The great advantage of Write Mode 3 is that we just need 509 * to load the foreground in the Set/Reset register, load the 510 * background color in the latches register (this is done 511 * through a write in offscreen memory followed by a read of 512 * that data), then write the pattern to video memory. This 513 * pattern indicates if the pixel should use the foreground 514 * color (bit set) or the background color (bit cleared). 515 */ 516 517 vga_setbg(vd, bg); 518 vga_setfg(vd, fg); 519 520 sc = vd->vd_softc; 521 offset = (VT_VGA_WIDTH * y + x) / 8; 522 523 for (i = 0; i < height; ++i, offset += VT_VGA_WIDTH / 8) { 524 MEM_WRITE1(sc, offset, masks[i]); 525 } 526 } 527 528 static void 529 vga_bitblt_pixels_block_ncolors(struct vt_device *vd, const uint8_t *masks, 530 unsigned int x, unsigned int y, unsigned int height) 531 { 532 unsigned int i, j, plan, color, offset; 533 struct vga_softc *sc; 534 uint8_t mask, plans[height * 4]; 535 536 sc = vd->vd_softc; 537 538 memset(plans, 0, sizeof(plans)); 539 540 /* 541 * To write a group of pixels using 3 or more colors, we select 542 * Write Mode 0 and write one byte to each plan separately. 543 */ 544 545 /* 546 * We first compute each byte: each plan contains one bit of the 547 * color code for each of the 8 pixels. 548 * 549 * For example, if the 8 pixels are like this: 550 * GBBBBBBY 551 * where: 552 * G (gray) = 0b0111 553 * B (black) = 0b0000 554 * Y (yellow) = 0b0011 555 * 556 * The corresponding for bytes are: 557 * GBBBBBBY 558 * Plan 0: 10000001 = 0x81 559 * Plan 1: 10000001 = 0x81 560 * Plan 2: 10000000 = 0x80 561 * Plan 3: 00000000 = 0x00 562 * | | | 563 * | | +-> 0b0011 (Y) 564 * | +-----> 0b0000 (B) 565 * +--------> 0b0111 (G) 566 */ 567 568 for (i = 0; i < height; ++i) { 569 for (color = 0; color < 16; ++color) { 570 mask = masks[i * 16 + color]; 571 if (mask == 0x00) 572 continue; 573 574 for (j = 0; j < 8; ++j) { 575 if (!((mask >> (7 - j)) & 0x1)) 576 continue; 577 578 /* The pixel "j" uses color "color". */ 579 for (plan = 0; plan < 4; ++plan) 580 plans[i * 4 + plan] |= 581 ((color >> plan) & 0x1) << (7 - j); 582 } 583 } 584 } 585 586 /* 587 * The bytes are ready: we now switch to Write Mode 0 and write 588 * all bytes, one plan at a time. 589 */ 590 vga_setwmode(vd, 0); 591 592 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); 593 for (plan = 0; plan < 4; ++plan) { 594 /* Select plan. */ 595 REG_WRITE1(sc, VGA_SEQ_DATA, 1 << plan); 596 597 /* Write all bytes for this plan, from Y to Y+height. */ 598 for (i = 0; i < height; ++i) { 599 offset = (VT_VGA_WIDTH * (y + i) + x) / 8; 600 MEM_WRITE1(sc, offset, plans[i * 4 + plan]); 601 } 602 } 603 } 604 605 static void 606 vga_bitblt_one_text_pixels_block(struct vt_device *vd, 607 const struct vt_window *vw, unsigned int x, unsigned int y) 608 { 609 const struct vt_buf *vb; 610 const struct vt_font *vf; 611 unsigned int i, col, row, src_x, x_count; 612 unsigned int used_colors_list[16], used_colors; 613 uint8_t pattern_2colors[vw->vw_font->vf_height]; 614 uint8_t pattern_ncolors[vw->vw_font->vf_height * 16]; 615 term_char_t c; 616 term_color_t fg, bg; 617 const uint8_t *src; 618 619 vb = &vw->vw_buf; 620 vf = vw->vw_font; 621 622 /* 623 * The current pixels block. 624 * 625 * We fill it with portions of characters, because both "grids" 626 * may not match. 627 * 628 * i is the index in this pixels block. 629 */ 630 631 i = x; 632 used_colors = 0; 633 memset(used_colors_list, 0, sizeof(used_colors_list)); 634 memset(pattern_2colors, 0, sizeof(pattern_2colors)); 635 memset(pattern_ncolors, 0, sizeof(pattern_ncolors)); 636 637 if (i < vw->vw_draw_area.tr_begin.tp_col) { 638 /* 639 * i is in the margin used to center the text area on 640 * the screen. 641 */ 642 643 i = vw->vw_draw_area.tr_begin.tp_col; 644 } 645 646 while (i < x + VT_VGA_PIXELS_BLOCK && 647 i < vw->vw_draw_area.tr_end.tp_col) { 648 /* 649 * Find which character is drawn on this pixel in the 650 * pixels block. 651 * 652 * While here, record what colors it uses. 653 */ 654 655 col = (i - vw->vw_draw_area.tr_begin.tp_col) / vf->vf_width; 656 row = (y - vw->vw_draw_area.tr_begin.tp_row) / vf->vf_height; 657 658 c = VTBUF_GET_FIELD(vb, row, col); 659 src = vtfont_lookup(vf, c); 660 661 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col), &fg, &bg); 662 if ((used_colors_list[fg] & 0x1) != 0x1) 663 used_colors++; 664 if ((used_colors_list[bg] & 0x2) != 0x2) 665 used_colors++; 666 used_colors_list[fg] |= 0x1; 667 used_colors_list[bg] |= 0x2; 668 669 /* 670 * Compute the portion of the character we want to draw, 671 * because the pixels block may start in the middle of a 672 * character. 673 * 674 * The first pixel to draw in the character is 675 * the current position - 676 * the start position of the character 677 * 678 * The last pixel to draw is either 679 * - the last pixel of the character, or 680 * - the pixel of the character matching the end of 681 * the pixels block 682 * whichever comes first. This position is then 683 * changed to be relative to the start position of the 684 * character. 685 */ 686 687 src_x = i - 688 (col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col); 689 x_count = min(min( 690 (col + 1) * vf->vf_width + 691 vw->vw_draw_area.tr_begin.tp_col, 692 x + VT_VGA_PIXELS_BLOCK), 693 vw->vw_draw_area.tr_end.tp_col); 694 x_count -= col * vf->vf_width + 695 vw->vw_draw_area.tr_begin.tp_col; 696 x_count -= src_x; 697 698 /* Copy a portion of the character. */ 699 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors, 700 src, NULL, vf->vf_width, 701 src_x, i % VT_VGA_PIXELS_BLOCK, x_count, 702 0, 0, vf->vf_height, fg, bg, 0); 703 704 /* We move to the next portion. */ 705 i += x_count; 706 } 707 708 #ifndef SC_NO_CUTPASTE 709 /* 710 * Copy the mouse pointer bitmap if it's over the current pixels 711 * block. 712 * 713 * We use the saved cursor position (saved in vt_flush()), because 714 * the current position could be different than the one used 715 * to mark the area dirty. 716 */ 717 term_rect_t drawn_area; 718 719 drawn_area.tr_begin.tp_col = x; 720 drawn_area.tr_begin.tp_row = y; 721 drawn_area.tr_end.tp_col = x + VT_VGA_PIXELS_BLOCK; 722 drawn_area.tr_end.tp_row = y + vf->vf_height; 723 if (vd->vd_mshown && vt_is_cursor_in_area(vd, &drawn_area)) { 724 struct vt_mouse_cursor *cursor; 725 unsigned int mx, my; 726 unsigned int dst_x, src_y, dst_y, y_count; 727 728 cursor = vd->vd_mcursor; 729 mx = vd->vd_mx_drawn + vw->vw_draw_area.tr_begin.tp_col; 730 my = vd->vd_my_drawn + vw->vw_draw_area.tr_begin.tp_row; 731 732 /* Compute the portion of the cursor we want to copy. */ 733 src_x = x > mx ? x - mx : 0; 734 dst_x = mx > x ? mx - x : 0; 735 x_count = min(min(min( 736 cursor->width - src_x, 737 x + VT_VGA_PIXELS_BLOCK - mx), 738 vw->vw_draw_area.tr_end.tp_col - mx), 739 VT_VGA_PIXELS_BLOCK); 740 741 /* 742 * The cursor isn't aligned on the Y-axis with 743 * characters, so we need to compute the vertical 744 * start/count. 745 */ 746 src_y = y > my ? y - my : 0; 747 dst_y = my > y ? my - y : 0; 748 y_count = min( 749 min(cursor->height - src_y, y + vf->vf_height - my), 750 vf->vf_height); 751 752 /* Copy the cursor portion. */ 753 vga_copy_bitmap_portion(pattern_2colors, pattern_ncolors, 754 cursor->map, cursor->mask, cursor->width, 755 src_x, dst_x, x_count, src_y, dst_y, y_count, 756 vd->vd_mcursor_fg, vd->vd_mcursor_bg, 1); 757 758 if ((used_colors_list[vd->vd_mcursor_fg] & 0x1) != 0x1) 759 used_colors++; 760 if ((used_colors_list[vd->vd_mcursor_bg] & 0x2) != 0x2) 761 used_colors++; 762 } 763 #endif 764 765 /* 766 * The pixels block is completed, we can now draw it on the 767 * screen. 768 */ 769 if (used_colors == 2) 770 vga_bitblt_pixels_block_2colors(vd, pattern_2colors, fg, bg, 771 x, y, vf->vf_height); 772 else 773 vga_bitblt_pixels_block_ncolors(vd, pattern_ncolors, 774 x, y, vf->vf_height); 775 } 776 777 static void 778 vga_bitblt_text_gfxmode(struct vt_device *vd, const struct vt_window *vw, 779 const term_rect_t *area) 780 { 781 const struct vt_font *vf; 782 unsigned int col, row; 783 unsigned int x1, y1, x2, y2, x, y; 784 785 vf = vw->vw_font; 786 787 /* 788 * Compute the top-left pixel position aligned with the video 789 * adapter pixels block size. 790 * 791 * This is calculated from the top-left column of te dirty area: 792 * 793 * 1. Compute the top-left pixel of the character: 794 * col * font width + x offset 795 * 796 * NOTE: x offset is used to center the text area on the 797 * screen. It's expressed in pixels, not in characters 798 * col/row! 799 * 800 * 2. Find the pixel further on the left marking the start of 801 * an aligned pixels block (eg. chunk of 8 pixels): 802 * character's x / blocksize * blocksize 803 * 804 * The division, being made on integers, achieves the 805 * alignment. 806 * 807 * For the Y-axis, we need to compute the character's y 808 * coordinate, but we don't need to align it. 809 */ 810 811 col = area->tr_begin.tp_col; 812 row = area->tr_begin.tp_row; 813 x1 = (int)((col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col) 814 / VT_VGA_PIXELS_BLOCK) 815 * VT_VGA_PIXELS_BLOCK; 816 y1 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row; 817 818 /* 819 * Compute the bottom right pixel position, again, aligned with 820 * the pixels block size. 821 * 822 * The same rules apply, we just add 1 to base the computation 823 * on the "right border" of the dirty area. 824 */ 825 826 col = area->tr_end.tp_col; 827 row = area->tr_end.tp_row; 828 x2 = (int)howmany(col * vf->vf_width + vw->vw_draw_area.tr_begin.tp_col, 829 VT_VGA_PIXELS_BLOCK) 830 * VT_VGA_PIXELS_BLOCK; 831 y2 = row * vf->vf_height + vw->vw_draw_area.tr_begin.tp_row; 832 833 /* Clip the area to the screen size. */ 834 x2 = min(x2, vw->vw_draw_area.tr_end.tp_col); 835 y2 = min(y2, vw->vw_draw_area.tr_end.tp_row); 836 837 /* 838 * Now, we take care of N pixels line at a time (the first for 839 * loop, N = font height), and for these lines, draw one pixels 840 * block at a time (the second for loop), not a character at a 841 * time. 842 * 843 * Therefore, on the X-axis, characters my be drawn partially if 844 * they are not aligned on 8-pixels boundary. 845 * 846 * However, the operation is repeated for the full height of the 847 * font before moving to the next character, because it allows 848 * to keep the color settings and write mode, before perhaps 849 * changing them with the next one. 850 */ 851 852 for (y = y1; y < y2; y += vf->vf_height) { 853 for (x = x1; x < x2; x += VT_VGA_PIXELS_BLOCK) { 854 vga_bitblt_one_text_pixels_block(vd, vw, x, y); 855 } 856 } 857 } 858 859 static void 860 vga_bitblt_text_txtmode(struct vt_device *vd, const struct vt_window *vw, 861 const term_rect_t *area) 862 { 863 struct vga_softc *sc; 864 const struct vt_buf *vb; 865 unsigned int col, row; 866 term_char_t c; 867 term_color_t fg, bg; 868 uint8_t ch, attr; 869 870 sc = vd->vd_softc; 871 vb = &vw->vw_buf; 872 873 for (row = area->tr_begin.tp_row; row < area->tr_end.tp_row; ++row) { 874 for (col = area->tr_begin.tp_col; 875 col < area->tr_end.tp_col; 876 ++col) { 877 /* 878 * Get next character and its associated fg/bg 879 * colors. 880 */ 881 c = VTBUF_GET_FIELD(vb, row, col); 882 vt_determine_colors(c, VTBUF_ISCURSOR(vb, row, col), 883 &fg, &bg); 884 885 /* 886 * Convert character to CP437, which is the 887 * character set used by the VGA hardware by 888 * default. 889 */ 890 ch = vga_get_cp437(TCHAR_CHARACTER(c)); 891 892 /* Convert colors to VGA attributes. */ 893 attr = 894 cons_to_vga_colors[bg] << 4 | 895 cons_to_vga_colors[fg]; 896 897 MEM_WRITE1(sc, (row * 80 + col) * 2 + 0, 898 ch); 899 MEM_WRITE1(sc, (row * 80 + col) * 2 + 1, 900 attr); 901 } 902 } 903 } 904 905 static void 906 vga_bitblt_text(struct vt_device *vd, const struct vt_window *vw, 907 const term_rect_t *area) 908 { 909 910 if (!(vd->vd_flags & VDF_TEXTMODE)) { 911 vga_bitblt_text_gfxmode(vd, vw, area); 912 } else { 913 vga_bitblt_text_txtmode(vd, vw, area); 914 } 915 } 916 917 static void 918 vga_bitblt_bitmap(struct vt_device *vd, const struct vt_window *vw, 919 const uint8_t *pattern, const uint8_t *mask, 920 unsigned int width, unsigned int height, 921 unsigned int x, unsigned int y, term_color_t fg, term_color_t bg) 922 { 923 unsigned int x1, y1, x2, y2, i, j, src_x, dst_x, x_count; 924 uint8_t pattern_2colors; 925 926 /* Align coordinates with the 8-pxels grid. */ 927 x1 = rounddown(x, VT_VGA_PIXELS_BLOCK); 928 y1 = y; 929 930 x2 = roundup(x + width, VT_VGA_PIXELS_BLOCK); 931 y2 = y + height; 932 x2 = min(x2, vd->vd_width - 1); 933 y2 = min(y2, vd->vd_height - 1); 934 935 for (j = y1; j < y2; ++j) { 936 src_x = 0; 937 dst_x = x - x1; 938 x_count = VT_VGA_PIXELS_BLOCK - dst_x; 939 940 for (i = x1; i < x2; i += VT_VGA_PIXELS_BLOCK) { 941 pattern_2colors = 0; 942 943 vga_copy_bitmap_portion( 944 &pattern_2colors, NULL, 945 pattern, mask, width, 946 src_x, dst_x, x_count, 947 j - y1, 0, 1, fg, bg, 0); 948 949 vga_bitblt_pixels_block_2colors(vd, 950 &pattern_2colors, fg, bg, 951 i, j, 1); 952 953 src_x += x_count; 954 dst_x = (dst_x + x_count) % VT_VGA_PIXELS_BLOCK; 955 x_count = min(width - src_x, VT_VGA_PIXELS_BLOCK); 956 } 957 } 958 } 959 960 static void 961 vga_initialize_graphics(struct vt_device *vd) 962 { 963 struct vga_softc *sc = vd->vd_softc; 964 965 /* Clock select. */ 966 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, VGA_GEN_MO_VSP | VGA_GEN_MO_HSP | 967 VGA_GEN_MO_PB | VGA_GEN_MO_ER | VGA_GEN_MO_IOA); 968 /* Set sequencer clocking and memory mode. */ 969 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CLOCKING_MODE); 970 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_CM_89); 971 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MEMORY_MODE); 972 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_OE | VGA_SEQ_MM_EM); 973 974 /* Set the graphics controller in graphics mode. */ 975 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MISCELLANEOUS); 976 REG_WRITE1(sc, VGA_GC_DATA, 0x04 + VGA_GC_MISC_GA); 977 /* Program the CRT controller. */ 978 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_TOTAL); 979 REG_WRITE1(sc, VGA_CRTC_DATA, 0x5f); /* 760 */ 980 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_HORIZ_DISP_END); 981 REG_WRITE1(sc, VGA_CRTC_DATA, 0x4f); /* 640 - 8 */ 982 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_BLANK); 983 REG_WRITE1(sc, VGA_CRTC_DATA, 0x50); /* 640 */ 984 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_BLANK); 985 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHB_CR + 2); 986 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_HORIZ_RETRACE); 987 REG_WRITE1(sc, VGA_CRTC_DATA, 0x54); /* 672 */ 988 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_HORIZ_RETRACE); 989 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_EHR_EHB + 0); 990 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_TOTAL); 991 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0b); /* 523 */ 992 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OVERFLOW); 993 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_OF_VT9 | VGA_CRTC_OF_LC8 | 994 VGA_CRTC_OF_VBS8 | VGA_CRTC_OF_VRS8 | VGA_CRTC_OF_VDE8); 995 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MAX_SCAN_LINE); 996 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MSL_LC9); 997 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_START); 998 REG_WRITE1(sc, VGA_CRTC_DATA, 0xea); /* 480 + 10 */ 999 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); 1000 REG_WRITE1(sc, VGA_CRTC_DATA, 0x0c); 1001 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_DISPLAY_END); 1002 REG_WRITE1(sc, VGA_CRTC_DATA, 0xdf); /* 480 - 1*/ 1003 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_OFFSET); 1004 REG_WRITE1(sc, VGA_CRTC_DATA, 0x28); 1005 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_VERT_BLANK); 1006 REG_WRITE1(sc, VGA_CRTC_DATA, 0xe7); /* 480 + 7 */ 1007 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_END_VERT_BLANK); 1008 REG_WRITE1(sc, VGA_CRTC_DATA, 0x04); 1009 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 1010 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_MC_WB | VGA_CRTC_MC_AW | 1011 VGA_CRTC_MC_SRS | VGA_CRTC_MC_CMS); 1012 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_LINE_COMPARE); 1013 REG_WRITE1(sc, VGA_CRTC_DATA, 0xff); /* 480 + 31 */ 1014 1015 REG_WRITE1(sc, VGA_GEN_FEATURE_CTRL_W, 0); 1016 1017 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_MAP_MASK); 1018 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_MM_EM3 | VGA_SEQ_MM_EM2 | 1019 VGA_SEQ_MM_EM1 | VGA_SEQ_MM_EM0); 1020 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_CHAR_MAP_SELECT); 1021 REG_WRITE1(sc, VGA_SEQ_DATA, 0); 1022 1023 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_SET_RESET); 1024 REG_WRITE1(sc, VGA_GC_DATA, 0); 1025 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); 1026 REG_WRITE1(sc, VGA_GC_DATA, 0x0f); 1027 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_COMPARE); 1028 REG_WRITE1(sc, VGA_GC_DATA, 0); 1029 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_DATA_ROTATE); 1030 REG_WRITE1(sc, VGA_GC_DATA, 0); 1031 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_READ_MAP_SELECT); 1032 REG_WRITE1(sc, VGA_GC_DATA, 0); 1033 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); 1034 REG_WRITE1(sc, VGA_GC_DATA, 0); 1035 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_COLOR_DONT_CARE); 1036 REG_WRITE1(sc, VGA_GC_DATA, 0x0f); 1037 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_BIT_MASK); 1038 REG_WRITE1(sc, VGA_GC_DATA, 0xff); 1039 } 1040 1041 static int 1042 vga_initialize(struct vt_device *vd, int textmode) 1043 { 1044 struct vga_softc *sc = vd->vd_softc; 1045 uint8_t x; 1046 int timeout; 1047 1048 /* Make sure the VGA adapter is not in monochrome emulation mode. */ 1049 x = REG_READ1(sc, VGA_GEN_MISC_OUTPUT_R); 1050 REG_WRITE1(sc, VGA_GEN_MISC_OUTPUT_W, x | VGA_GEN_MO_IOA); 1051 1052 /* Unprotect CRTC registers 0-7. */ 1053 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_VERT_RETRACE_END); 1054 x = REG_READ1(sc, VGA_CRTC_DATA); 1055 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_VRE_PR); 1056 1057 /* 1058 * Wait for the vertical retrace. 1059 * NOTE: this code reads the VGA_GEN_INPUT_STAT_1 register, which has 1060 * the side-effect of clearing the internal flip-flip of the attribute 1061 * controller's write register. This means that because this code is 1062 * here, we know for sure that the first write to the attribute 1063 * controller will be a write to the address register. Removing this 1064 * code therefore also removes that guarantee and appropriate measures 1065 * need to be taken. 1066 */ 1067 timeout = 10000; 1068 do { 1069 DELAY(10); 1070 x = REG_READ1(sc, VGA_GEN_INPUT_STAT_1); 1071 x &= VGA_GEN_IS1_VR | VGA_GEN_IS1_DE; 1072 } while (x != (VGA_GEN_IS1_VR | VGA_GEN_IS1_DE) && --timeout != 0); 1073 if (timeout == 0) { 1074 printf("Timeout initializing vt_vga\n"); 1075 return (ENXIO); 1076 } 1077 1078 /* Now, disable the sync. signals. */ 1079 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 1080 x = REG_READ1(sc, VGA_CRTC_DATA); 1081 REG_WRITE1(sc, VGA_CRTC_DATA, x & ~VGA_CRTC_MC_HR); 1082 1083 /* Asynchronous sequencer reset. */ 1084 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); 1085 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR); 1086 1087 if (!textmode) 1088 vga_initialize_graphics(vd); 1089 1090 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_PRESET_ROW_SCAN); 1091 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 1092 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_START); 1093 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_CS_COO); 1094 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_END); 1095 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 1096 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_HIGH); 1097 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 1098 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_START_ADDR_LOW); 1099 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 1100 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_HIGH); 1101 REG_WRITE1(sc, VGA_CRTC_DATA, 0); 1102 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_CURSOR_LOC_LOW); 1103 REG_WRITE1(sc, VGA_CRTC_DATA, 0x59); 1104 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_UNDERLINE_LOC); 1105 REG_WRITE1(sc, VGA_CRTC_DATA, VGA_CRTC_UL_UL); 1106 1107 if (textmode) { 1108 /* Set the attribute controller to blink disable. */ 1109 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); 1110 REG_WRITE1(sc, VGA_AC_WRITE, 0); 1111 } else { 1112 /* Set the attribute controller in graphics mode. */ 1113 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MODE_CONTROL); 1114 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_MC_GA); 1115 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_HORIZ_PIXEL_PANNING); 1116 REG_WRITE1(sc, VGA_AC_WRITE, 0); 1117 } 1118 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(0)); 1119 REG_WRITE1(sc, VGA_AC_WRITE, 0); 1120 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(1)); 1121 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_B); 1122 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(2)); 1123 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G); 1124 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(3)); 1125 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_G | VGA_AC_PAL_B); 1126 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(4)); 1127 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R); 1128 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(5)); 1129 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_B); 1130 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(6)); 1131 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SG | VGA_AC_PAL_R); 1132 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(7)); 1133 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); 1134 1135 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(8)); 1136 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1137 VGA_AC_PAL_SB); 1138 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(9)); 1139 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1140 VGA_AC_PAL_SB | VGA_AC_PAL_B); 1141 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(10)); 1142 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1143 VGA_AC_PAL_SB | VGA_AC_PAL_G); 1144 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(11)); 1145 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1146 VGA_AC_PAL_SB | VGA_AC_PAL_G | VGA_AC_PAL_B); 1147 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(12)); 1148 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1149 VGA_AC_PAL_SB | VGA_AC_PAL_R); 1150 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(13)); 1151 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1152 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_B); 1153 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(14)); 1154 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1155 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G); 1156 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PALETTE(15)); 1157 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_PAL_SR | VGA_AC_PAL_SG | 1158 VGA_AC_PAL_SB | VGA_AC_PAL_R | VGA_AC_PAL_G | VGA_AC_PAL_B); 1159 1160 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_OVERSCAN_COLOR); 1161 REG_WRITE1(sc, VGA_AC_WRITE, 0); 1162 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_PLANE_ENABLE); 1163 REG_WRITE1(sc, VGA_AC_WRITE, 0x0f); 1164 REG_WRITE1(sc, VGA_AC_WRITE, VGA_AC_COLOR_SELECT); 1165 REG_WRITE1(sc, VGA_AC_WRITE, 0); 1166 1167 if (!textmode) { 1168 u_int ofs; 1169 1170 /* 1171 * Done. Clear the frame buffer. All bit planes are 1172 * enabled, so a single-paged loop should clear all 1173 * planes. 1174 */ 1175 for (ofs = 0; ofs < VT_VGA_MEMSIZE; ofs++) { 1176 MEM_WRITE1(sc, ofs, 0); 1177 } 1178 } 1179 1180 /* Re-enable the sequencer. */ 1181 REG_WRITE1(sc, VGA_SEQ_ADDRESS, VGA_SEQ_RESET); 1182 REG_WRITE1(sc, VGA_SEQ_DATA, VGA_SEQ_RST_SR | VGA_SEQ_RST_NAR); 1183 /* Re-enable the sync signals. */ 1184 REG_WRITE1(sc, VGA_CRTC_ADDRESS, VGA_CRTC_MODE_CONTROL); 1185 x = REG_READ1(sc, VGA_CRTC_DATA); 1186 REG_WRITE1(sc, VGA_CRTC_DATA, x | VGA_CRTC_MC_HR); 1187 1188 if (!textmode) { 1189 /* Switch to write mode 3, because we'll mainly do bitblt. */ 1190 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_MODE); 1191 REG_WRITE1(sc, VGA_GC_DATA, 3); 1192 sc->vga_wmode = 3; 1193 1194 /* 1195 * In Write Mode 3, Enable Set/Reset is ignored, but we 1196 * use Write Mode 0 to write a group of 8 pixels using 1197 * 3 or more colors. In this case, we want to disable 1198 * Set/Reset: set Enable Set/Reset to 0. 1199 */ 1200 REG_WRITE1(sc, VGA_GC_ADDRESS, VGA_GC_ENABLE_SET_RESET); 1201 REG_WRITE1(sc, VGA_GC_DATA, 0x00); 1202 1203 /* 1204 * Clear the colors we think are loaded into Set/Reset or 1205 * the latches. 1206 */ 1207 sc->vga_curfg = sc->vga_curbg = 0xff; 1208 } 1209 1210 return (0); 1211 } 1212 1213 static bool 1214 vga_acpi_disabled(void) 1215 { 1216 #if ((defined(__amd64__) || defined(__i386__)) && defined(DEV_ACPI)) 1217 ACPI_TABLE_FADT *fadt; 1218 vm_paddr_t physaddr; 1219 uint16_t flags; 1220 1221 physaddr = acpi_find_table(ACPI_SIG_FADT); 1222 if (physaddr == 0) 1223 return (false); 1224 1225 fadt = acpi_map_table(physaddr, ACPI_SIG_FADT); 1226 if (fadt == NULL) { 1227 printf("vt_vga: unable to map FADT ACPI table\n"); 1228 return (false); 1229 } 1230 1231 flags = fadt->BootFlags; 1232 acpi_unmap_table(fadt); 1233 1234 if (flags & ACPI_FADT_NO_VGA) 1235 return (true); 1236 #endif 1237 1238 return (false); 1239 } 1240 1241 static int 1242 vga_probe(struct vt_device *vd) 1243 { 1244 1245 return (vga_acpi_disabled() ? CN_DEAD : CN_INTERNAL); 1246 } 1247 1248 static int 1249 vga_init(struct vt_device *vd) 1250 { 1251 struct vga_softc *sc; 1252 int textmode; 1253 1254 if (vd->vd_softc == NULL) 1255 vd->vd_softc = (void *)&vga_conssoftc; 1256 sc = vd->vd_softc; 1257 1258 if (vd->vd_flags & VDF_DOWNGRADE && vd->vd_video_dev != NULL) 1259 vga_pci_repost(vd->vd_video_dev); 1260 1261 #if defined(__amd64__) || defined(__i386__) 1262 sc->vga_fb_tag = X86_BUS_SPACE_MEM; 1263 sc->vga_reg_tag = X86_BUS_SPACE_IO; 1264 #else 1265 # error "Architecture not yet supported!" 1266 #endif 1267 1268 bus_space_map(sc->vga_reg_tag, VGA_REG_BASE, VGA_REG_SIZE, 0, 1269 &sc->vga_reg_handle); 1270 1271 /* 1272 * If "hw.vga.textmode" is not set and we're running on hypervisor, 1273 * we use text mode by default, this is because when we're on 1274 * hypervisor, vt(4) is usually much slower in graphics mode than 1275 * in text mode, especially when we're on Hyper-V. 1276 */ 1277 textmode = vm_guest != VM_GUEST_NO; 1278 TUNABLE_INT_FETCH("hw.vga.textmode", &textmode); 1279 if (textmode) { 1280 vd->vd_flags |= VDF_TEXTMODE; 1281 vd->vd_width = 80; 1282 vd->vd_height = 25; 1283 bus_space_map(sc->vga_fb_tag, VGA_TXT_BASE, VGA_TXT_SIZE, 0, 1284 &sc->vga_fb_handle); 1285 } else { 1286 vd->vd_width = VT_VGA_WIDTH; 1287 vd->vd_height = VT_VGA_HEIGHT; 1288 bus_space_map(sc->vga_fb_tag, VGA_MEM_BASE, VGA_MEM_SIZE, 0, 1289 &sc->vga_fb_handle); 1290 } 1291 if (vga_initialize(vd, textmode) != 0) 1292 return (CN_DEAD); 1293 sc->vga_enabled = true; 1294 1295 return (CN_INTERNAL); 1296 } 1297 1298 static void 1299 vga_postswitch(struct vt_device *vd) 1300 { 1301 1302 /* Reinit VGA mode, to restore view after app which change mode. */ 1303 vga_initialize(vd, (vd->vd_flags & VDF_TEXTMODE)); 1304 /* Ask vt(9) to update chars on visible area. */ 1305 vd->vd_flags |= VDF_INVALID; 1306 } 1307 1308 /* Dummy NewBus functions to reserve the resources used by the vt_vga driver */ 1309 static void 1310 vtvga_identify(driver_t *driver, device_t parent) 1311 { 1312 1313 if (!vga_conssoftc.vga_enabled) 1314 return; 1315 1316 if (BUS_ADD_CHILD(parent, 0, driver->name, 0) == NULL) 1317 panic("Unable to attach vt_vga console"); 1318 } 1319 1320 static int 1321 vtvga_probe(device_t dev) 1322 { 1323 1324 device_set_desc(dev, "VT VGA driver"); 1325 1326 return (BUS_PROBE_NOWILDCARD); 1327 } 1328 1329 static int 1330 vtvga_attach(device_t dev) 1331 { 1332 struct resource *pseudo_phys_res; 1333 int res_id; 1334 1335 res_id = 0; 1336 pseudo_phys_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 1337 &res_id, VGA_MEM_BASE, VGA_MEM_BASE + VGA_MEM_SIZE - 1, 1338 VGA_MEM_SIZE, RF_ACTIVE); 1339 if (pseudo_phys_res == NULL) 1340 panic("Unable to reserve vt_vga memory"); 1341 return (0); 1342 } 1343 1344 /*-------------------- Private Device Attachment Data -----------------------*/ 1345 static device_method_t vtvga_methods[] = { 1346 /* Device interface */ 1347 DEVMETHOD(device_identify, vtvga_identify), 1348 DEVMETHOD(device_probe, vtvga_probe), 1349 DEVMETHOD(device_attach, vtvga_attach), 1350 1351 DEVMETHOD_END 1352 }; 1353 1354 DEFINE_CLASS_0(vtvga, vtvga_driver, vtvga_methods, 0); 1355 devclass_t vtvga_devclass; 1356 1357 DRIVER_MODULE(vtvga, nexus, vtvga_driver, vtvga_devclass, NULL, NULL); 1358