1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Rhine register definitions. 37 */ 38 39 #define VR_PAR0 0x00 /* node address 0 to 4 */ 40 #define VR_PAR1 0x04 /* node address 2 to 6 */ 41 #define VR_RXCFG 0x06 /* receiver config register */ 42 #define VR_TXCFG 0x07 /* transmit config register */ 43 #define VR_CR0 0x08 /* command register 0 */ 44 #define VR_CR1 0x09 /* command register 1 */ 45 #define VR_TQW 0x0A /* tx queue wake 6105M, 8bits */ 46 #define VR_ISR 0x0C /* interrupt/status register */ 47 #define VR_IMR 0x0E /* interrupt mask register */ 48 #define VR_MAR0 0x10 /* multicast hash 0 */ 49 #define VR_MAR1 0x14 /* multicast hash 1 */ 50 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 51 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 52 #define VR_CURRXDESC0 0x20 53 #define VR_CURRXDESC1 0x24 54 #define VR_CURRXDESC2 0x28 55 #define VR_CURRXDESC3 0x2C 56 #define VR_NEXTRXDESC0 0x30 57 #define VR_NEXTRXDESC1 0x34 58 #define VR_NEXTRXDESC2 0x38 59 #define VR_NEXTRXDESC3 0x3C 60 #define VR_CURTXDESC0 0x40 61 #define VR_CURTXDESC1 0x44 62 #define VR_CURTXDESC2 0x48 63 #define VR_CURTXDESC3 0x4C 64 #define VR_NEXTTXDESC0 0x50 65 #define VR_NEXTTXDESC1 0x54 66 #define VR_NEXTTXDESC2 0x58 67 #define VR_NEXTTXDESC3 0x5C 68 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 69 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 70 #define VR_TALLYCNT 0x68 /* tally counter test register */ 71 #define VR_PHYADDR 0x6C 72 #define VR_MIISTAT 0x6D 73 #define VR_BCR0 0x6E 74 #define VR_BCR1 0x6F 75 #define VR_MIICMD 0x70 76 #define VR_MIIADDR 0x71 77 #define VR_MIIDATA 0x72 78 #define VR_EECSR 0x74 79 #define VR_TEST 0x75 80 #define VR_GPIO 0x76 81 #define VR_CFGA 0x78 82 #define VR_CFGB 0x79 83 #define VR_CFGC 0x7A 84 #define VR_CFGD 0x7B 85 #define VR_MPA_CNT 0x7C 86 #define VR_CRC_CNT 0x7E 87 #define VR_MISC_CR0 0x80 /* VT6102, 8bits */ 88 #define VR_MISC_CR1 0x81 89 #define VR_STICKHW 0x83 90 #define VR_MII_ISR 0x84 91 #define VR_MII_IMR 0x86 92 #define VR_CAMMASK 0x88 /* VT6105M, 32bits */ 93 #define VR_CAMCTL 0x92 /* VT6105M, 8bits */ 94 #define VR_CAMADDR 0x93 /* VT6105M, 8bits */ 95 #define VR_FLOWCR0 0x98 96 #define VR_FLOWCR1 0x99 97 #define VR_PAUSETIMER 0x9A /* 16bit */ 98 #define VR_WOLCR_SET 0xA0 99 #define VR_PWRCFG_SET 0xA1 100 #define VR_TESTREG_SET 0xA2 101 #define VR_WOLCFG_SET 0xA3 102 #define VR_WOLCR_CLR 0xA4 103 #define VR_PWRCFG_CLR 0xA5 104 #define VR_TESTREG_CLR 0xA6 105 #define VR_WOLCFG_CLR 0xA7 106 #define VR_PWRCSR_SET 0xA8 107 #define VR_PWRCSR1_SET 0xA9 108 #define VR_PWRCSR_CLR 0xAC 109 #define VR_PWRCSR1_CLR 0xAD 110 111 /* Misc Registers */ 112 #define VR_MISCCR0_RXPAUSE 0x08 113 #define VR_MISCCR1_FORSRST 0x40 114 115 /* 116 * RX config bits. 117 */ 118 #define VR_RXCFG_RX_ERRPKTS 0x01 119 #define VR_RXCFG_RX_RUNT 0x02 120 #define VR_RXCFG_RX_MULTI 0x04 121 #define VR_RXCFG_RX_BROAD 0x08 122 #define VR_RXCFG_RX_PROMISC 0x10 123 #define VR_RXCFG_RX_THRESH 0xE0 124 125 #define VR_RXTHRESH_32BYTES 0x00 126 #define VR_RXTHRESH_64BYTES 0x20 127 #define VR_RXTHRESH_128BYTES 0x40 128 #define VR_RXTHRESH_256BYTES 0x60 129 #define VR_RXTHRESH_512BYTES 0x80 130 #define VR_RXTHRESH_768BYTES 0xA0 131 #define VR_RXTHRESH_1024BYTES 0xC0 132 #define VR_RXTHRESH_STORENFWD 0xE0 133 134 /* 135 * TX config bits. 136 */ 137 #define VR_TXCFG_TXTAGEN 0x01 /* 6105M */ 138 #define VR_TXCFG_LOOPBKMODE 0x06 139 #define VR_TXCFG_BACKOFF 0x08 140 #define VR_TXCFG_RXTAGCTL 0x10 /* 6105M */ 141 #define VR_TXCFG_TX_THRESH 0xE0 142 143 #define VR_TXTHRESH_32BYTES 0x00 144 #define VR_TXTHRESH_64BYTES 0x20 145 #define VR_TXTHRESH_128BYTES 0x40 146 #define VR_TXTHRESH_256BYTES 0x60 147 #define VR_TXTHRESH_512BYTES 0x80 148 #define VR_TXTHRESH_768BYTES 0xA0 149 #define VR_TXTHRESH_1024BYTES 0xC0 150 #define VR_TXTHRESH_STORENFWD 0xE0 151 #define VR_TXTHRESH_MIN 1 /* 64 bytes */ 152 #define VR_TXTHRESH_MAX 5 /* store and forward */ 153 154 /* 155 * Command register bits. 156 */ 157 #define VR_CR0_INIT 0x01 158 #define VR_CR0_START 0x02 159 #define VR_CR0_STOP 0x04 160 #define VR_CR0_RX_ON 0x08 161 #define VR_CR0_TX_ON 0x10 162 #define VR_CR0_TX_GO 0x20 163 #define VR_CR0_RX_GO 0x40 164 #define VR_CR0_RSVD 0x80 165 #define VR_CR1_RX_EARLY 0x01 166 #define VR_CR1_TX_EARLY 0x02 167 #define VR_CR1_FULLDUPLEX 0x04 168 #define VR_CR1_TX_NOPOLL 0x08 169 170 #define VR_CR1_RESET 0x80 171 172 /* 173 * Interrupt status bits. 174 */ 175 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 176 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 177 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 178 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 179 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 180 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 181 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 182 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 183 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 184 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 185 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */ 186 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (6102) */ 187 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 188 #define VR_ISR_RX_DROPPED 0x0800 189 #define VR_ISR_RX_NOBUF2 0x1000 /* Rx descriptor running up */ 190 #define VR_ISR_TX_ABRT2 0x2000 191 #define VR_ISR_LINKSTAT2 0x4000 192 #define VR_ISR_MAGICPACKET 0x8000 193 194 #define VR_ISR_ERR_BITS "\20" \ 195 "\3RXERR\4TXABRT\5TXUNDERRUN" \ 196 "\6RXNOBUF\7BUSERR\10STATSOFLOW" \ 197 "\12TXUDF\13RXOFLOW\14RXDROPPED" \ 198 "\15RXNOBUF2\16TXABRT2" 199 /* 200 * Interrupt mask bits. 201 */ 202 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 203 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 204 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 205 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 206 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 207 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 208 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 209 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 210 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 211 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 212 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 213 #define VR_IMR_RX_DROPPED 0x0800 214 #define VR_IMR_RX_NOBUF2 0x1000 215 #define VR_IMR_TX_ABRT2 0x2000 216 #define VR_IMR_LINKSTAT2 0x4000 217 #define VR_IMR_MAGICPACKET 0x8000 218 219 #define VR_INTRS \ 220 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 221 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 222 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 223 224 /* 225 * MII status register. 226 */ 227 228 #define VR_MIISTAT_SPEED 0x01 229 #define VR_MIISTAT_LINKFAULT 0x02 230 #define VR_MIISTAT_MGTREADERR 0x04 231 #define VR_MIISTAT_MIIERR 0x08 232 #define VR_MIISTAT_PHYOPT 0x10 233 #define VR_MIISTAT_MDC_SPEED 0x20 234 #define VR_MIISTAT_RSVD 0x40 235 #define VR_MIISTAT_GPIO1POLL 0x80 236 237 /* 238 * MII command register bits. 239 */ 240 #define VR_MIICMD_CLK 0x01 241 #define VR_MIICMD_DATAOUT 0x02 242 #define VR_MIICMD_DATAIN 0x04 243 #define VR_MIICMD_DIR 0x08 244 #define VR_MIICMD_DIRECTPGM 0x10 245 #define VR_MIICMD_WRITE_ENB 0x20 246 #define VR_MIICMD_READ_ENB 0x40 247 #define VR_MIICMD_AUTOPOLL 0x80 248 249 /* 250 * EEPROM control bits. 251 */ 252 #define VR_EECSR_DATAIN 0x01 /* data out */ 253 #define VR_EECSR_DATAOUT 0x02 /* data in */ 254 #define VR_EECSR_CLK 0x04 /* clock */ 255 #define VR_EECSR_CS 0x08 /* chip select */ 256 #define VR_EECSR_DPM 0x10 257 #define VR_EECSR_LOAD 0x20 258 #define VR_EECSR_EMBP 0x40 259 #define VR_EECSR_EEPR 0x80 260 261 #define VR_EECMD_WRITE 0x140 262 #define VR_EECMD_READ 0x180 263 #define VR_EECMD_ERASE 0x1c0 264 265 /* 266 * Test register bits. 267 */ 268 #define VR_TEST_TEST0 0x01 269 #define VR_TEST_TEST1 0x02 270 #define VR_TEST_TEST2 0x04 271 #define VR_TEST_TSTUD 0x08 272 #define VR_TEST_TSTOV 0x10 273 #define VR_TEST_BKOFF 0x20 274 #define VR_TEST_FCOL 0x40 275 #define VR_TEST_HBDES 0x80 276 277 /* 278 * Config A register bits. 279 */ 280 #define VR_CFG_GPIO2OUTENB 0x01 281 #define VR_CFG_GPIO2OUT 0x02 /* gen. purp. pin */ 282 #define VR_CFG_GPIO2IN 0x04 /* gen. purp. pin */ 283 #define VR_CFG_AUTOOPT 0x08 /* enable rx/tx autopoll */ 284 #define VR_CFG_MIIOPT 0x10 285 #define VR_CFG_MMIENB 0x20 /* memory mapped mode enb */ 286 #define VR_CFG_JUMPER 0x40 /* PHY and oper. mode select */ 287 #define VR_CFG_EELOAD 0x80 /* enable EEPROM programming */ 288 289 /* 290 * Config B register bits. 291 */ 292 #define VR_CFG_LATMENB 0x01 /* larency timer effect enb. */ 293 #define VR_CFG_MRREADWAIT 0x02 294 #define VR_CFG_MRWRITEWAIT 0x04 295 #define VR_CFG_RX_ARB 0x08 296 #define VR_CFG_TX_ARB 0x10 297 #define VR_CFG_READMULTI 0x20 298 #define VR_CFG_TX_PACE 0x40 299 #define VR_CFG_TX_QDIS 0x80 300 301 /* 302 * Config C register bits. 303 */ 304 #define VR_CFG_ROMSEL0 0x01 305 #define VR_CFG_ROMSEL1 0x02 306 #define VR_CFG_ROMSEL2 0x04 307 #define VR_CFG_ROMTIMESEL 0x08 308 #define VR_CFG_RSVD0 0x10 309 #define VR_CFG_ROMDLY 0x20 310 #define VR_CFG_ROMOPT 0x40 311 #define VR_CFG_RSVD1 0x80 312 313 /* 314 * Config D register bits. 315 */ 316 #define VR_CFG_BACKOFFOPT 0x01 317 #define VR_CFG_BACKOFFMOD 0x02 318 #define VR_CFG_CAPEFFECT 0x04 319 #define VR_CFG_BACKOFFRAND 0x08 320 #define VR_CFG_MAGICKPACKET 0x10 321 #define VR_CFG_PCIREADLINE 0x20 322 #define VR_CFG_DIAG 0x40 323 #define VR_CFG_GPIOEN 0x80 324 325 /* Sticky HW bits */ 326 #define VR_STICKHW_DS0 0x01 327 #define VR_STICKHW_DS1 0x02 328 #define VR_STICKHW_WOL_ENB 0x04 329 #define VR_STICKHW_WOL_STS 0x08 330 #define VR_STICKHW_LEGWOL_ENB 0x80 331 332 /* 333 * BCR0 register bits. (At least for the VT6102 chip.) 334 */ 335 #define VR_BCR0_DMA_LENGTH 0x07 336 337 #define VR_BCR0_DMA_32BYTES 0x00 338 #define VR_BCR0_DMA_64BYTES 0x01 339 #define VR_BCR0_DMA_128BYTES 0x02 340 #define VR_BCR0_DMA_256BYTES 0x03 341 #define VR_BCR0_DMA_512BYTES 0x04 342 #define VR_BCR0_DMA_1024BYTES 0x05 343 #define VR_BCR0_DMA_STORENFWD 0x07 344 345 #define VR_BCR0_RX_THRESH 0x38 346 347 #define VR_BCR0_RXTHRESHCFG 0x00 348 #define VR_BCR0_RXTHRESH64BYTES 0x08 349 #define VR_BCR0_RXTHRESH128BYTES 0x10 350 #define VR_BCR0_RXTHRESH256BYTES 0x18 351 #define VR_BCR0_RXTHRESH512BYTES 0x20 352 #define VR_BCR0_RXTHRESH1024BYTES 0x28 353 #define VR_BCR0_RXTHRESHSTORENFWD 0x38 354 #define VR_BCR0_EXTLED 0x40 355 #define VR_BCR0_MED2 0x80 356 357 /* 358 * BCR1 register bits. (At least for the VT6102 chip.) 359 */ 360 #define VR_BCR1_POT0 0x01 361 #define VR_BCR1_POT1 0x02 362 #define VR_BCR1_POT2 0x04 363 #define VR_BCR1_TX_THRESH 0x38 364 #define VR_BCR1_TXTHRESHCFG 0x00 365 #define VR_BCR1_TXTHRESH64BYTES 0x08 366 #define VR_BCR1_TXTHRESH128BYTES 0x10 367 #define VR_BCR1_TXTHRESH256BYTES 0x18 368 #define VR_BCR1_TXTHRESH512BYTES 0x20 369 #define VR_BCR1_TXTHRESH1024BYTES 0x28 370 #define VR_BCR1_TXTHRESHSTORENFWD 0x38 371 372 /* 373 * CAMCTL register bits. (VT6105M only) 374 */ 375 #define VR_CAMCTL_ENA 0x01 376 #define VR_CAMCTL_VLAN 0x02 377 #define VR_CAMCTL_MCAST 0x00 378 #define VR_CAMCTL_WRITE 0x04 379 #define VR_CAMCTL_READ 0x08 380 381 #define VR_CAM_MCAST_CNT 32 382 #define VR_CAM_VLAN_CNT 32 383 384 /* 385 * FLOWCR1 register bits. (VT6105LOM, VT6105M only) 386 */ 387 #define VR_FLOWCR1_TXLO4 0x00 388 #define VR_FLOWCR1_TXLO8 0x40 389 #define VR_FLOWCR1_TXLO16 0x80 390 #define VR_FLOWCR1_TXLO24 0xC0 391 #define VR_FLOWCR1_TXHI24 0x00 392 #define VR_FLOWCR1_TXHI32 0x10 393 #define VR_FLOWCR1_TXHI48 0x20 394 #define VR_FLOWCR1_TXHI64 0x30 395 #define VR_FLOWCR1_XONXOFF 0x08 396 #define VR_FLOWCR1_TXPAUSE 0x04 397 #define VR_FLOWCR1_RXPAUSE 0x02 398 #define VR_FLOWCR1_HDX 0x01 399 400 /* 401 * WOLCR register bits. (VT6102 or higher only) 402 */ 403 #define VR_WOLCR_PATTERN0 0x01 404 #define VR_WOLCR_PATTERN1 0x02 405 #define VR_WOLCR_PATTERN2 0x04 406 #define VR_WOLCR_PATTERN3 0x08 407 #define VR_WOLCR_UCAST 0x10 408 #define VR_WOLCR_MAGIC 0x20 409 #define VR_WOLCR_LINKON 0x40 410 #define VR_WOLCR_LINKOFF 0x80 411 412 /* 413 * PWRCFG register bits. (VT6102 or higher only) 414 */ 415 #define VR_PWRCFG_WOLEN 0x01 416 #define VR_PWRCFG_WOLSR 0x02 417 #define VR_PWRCFG_LEGACY_WOL 0x10 418 #define VR_PWRCFG_WOLTYPE_PULSE 0x20 419 #define VR_PWRCFG_SMIITIME 0x80 420 421 /* 422 * WOLCFG register bits. (VT6102 or higher only) 423 */ 424 #define VR_WOLCFG_PATTERN_PAGE 0x04 /* VT6505 B0 */ 425 #define VR_WOLCFG_SMIIOPT 0x04 426 #define VR_WOLCFG_SMIIACC 0x08 427 #define VR_WOLCFG_SAB 0x10 428 #define VR_WOLCFG_SAM 0x20 429 #define VR_WOLCFG_SFDX 0x40 430 #define VR_WOLCFG_PMEOVR 0x80 431 432 /* 433 * Rhine TX/RX list structure. 434 */ 435 436 struct vr_desc { 437 uint32_t vr_status; 438 uint32_t vr_ctl; 439 uint32_t vr_data; 440 uint32_t vr_nextphys; 441 }; 442 443 #define VR_RXSTAT_RXERR 0x00000001 444 #define VR_RXSTAT_CRCERR 0x00000002 445 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 446 #define VR_RXSTAT_FIFOOFLOW 0x00000008 447 #define VR_RXSTAT_GIANT 0x00000010 448 #define VR_RXSTAT_RUNT 0x00000020 449 #define VR_RXSTAT_BUSERR 0x00000040 450 #define VR_RXSTAT_FRAG 0x00000040 /* 6105M */ 451 #define VR_RXSTAT_BUFFERR 0x00000080 452 #define VR_RXSTAT_LASTFRAG 0x00000100 453 #define VR_RXSTAT_FIRSTFRAG 0x00000200 454 #define VR_RXSTAT_RLINK 0x00000400 455 #define VR_RXSTAT_RX_PHYS 0x00000800 456 #define VR_RXSTAT_RX_BROAD 0x00001000 457 #define VR_RXSTAT_RX_MULTI 0x00002000 458 #define VR_RXSTAT_RX_OK 0x00004000 459 #define VR_RXSTAT_RXLEN 0x07FF0000 460 #define VR_RXSTAT_RXLEN_EXT 0x78000000 461 #define VR_RXSTAT_OWN 0x80000000 462 463 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 464 #define VR_RXSTAT_ERR_BITS "\20" \ 465 "\1RXERR\2CRCERR\3FRAMEALIGN" \ 466 "\4FIFOOFLOW\5GIANT\6RUNT" \ 467 "\10BUFERR" 468 469 #define VR_RXCTL_BUFLEN 0x000007FF 470 #define VR_RXCTL_BUFLEN_EXT 0x00007800 471 #define VR_RXCTL_CHAIN 0x00008000 472 #define VR_RXCTL_TAG 0x00010000 473 #define VR_RXCTL_UDP 0x00020000 474 #define VR_RXCTL_TCP 0x00040000 475 #define VR_RXCTL_IP 0x00080000 476 #define VR_RXCTL_TCPUDPOK 0x00100000 477 #define VR_RXCTL_IPOK 0x00200000 478 #define VR_RXCTL_SNAPTAG 0x00400000 479 #define VR_RXCTL_RXLERR 0x00800000 /* 6105M */ 480 #define VR_RXCTL_RX_INTR 0x00800000 481 482 483 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 484 485 #define VR_TXSTAT_DEFER 0x00000001 486 #define VR_TXSTAT_UNDERRUN 0x00000002 487 #define VR_TXSTAT_COLLCNT 0x00000078 488 #define VR_TXSTAT_SQE 0x00000080 489 #define VR_TXSTAT_ABRT 0x00000100 490 #define VR_TXSTAT_LATECOLL 0x00000200 491 #define VR_TXSTAT_CARRLOST 0x00000400 492 #define VR_TXSTAT_UDF 0x00000800 493 #define VR_TXSTAT_TBUFF 0x00001000 494 #define VR_TXSTAT_BUSERR 0x00002000 495 #define VR_TXSTAT_JABTIMEO 0x00004000 496 #define VR_TXSTAT_ERRSUM 0x00008000 497 #define VR_TXSTAT_OWN 0x80000000 498 499 #define VR_TXCTL_BUFLEN 0x000007FF 500 #define VR_TXCTL_BUFLEN_EXT 0x00007800 501 #define VR_TXCTL_TLINK 0x00008000 502 #define VR_TXCTL_NOCRC 0x00010000 503 #define VR_TXCTL_INSERTTAG 0x00020000 504 #define VR_TXCTL_IPCSUM 0x00040000 505 #define VR_TXCTL_UDPCSUM 0x00080000 506 #define VR_TXCTL_TCPCSUM 0x00100000 507 #define VR_TXCTL_FIRSTFRAG 0x00200000 508 #define VR_TXCTL_LASTFRAG 0x00400000 509 #define VR_TXCTL_FINT 0x00800000 510 511 #define VR_MIN_FRAMELEN 60 512 513 #define VR_FLAG_FORCEDELAY 1 514 #define VR_FLAG_SCHEDDELAY 2 515 #define VR_FLAG_DELAYTIMEO 3 516 517 518 #define VR_TIMEOUT 1000 519 #define VR_MII_TIMEOUT 10000 520 521 #define VR_PHYADDR_MASK 0x1f 522 523 /* 524 * General constants that are fun to know. 525 * 526 * VIA vendor ID 527 */ 528 #define VIA_VENDORID 0x1106 529 530 /* 531 * VIA Rhine device IDs. 532 */ 533 #define VIA_DEVICEID_RHINE 0x3043 534 #define VIA_DEVICEID_RHINE_II 0x6100 535 #define VIA_DEVICEID_RHINE_II_2 0x3065 536 #define VIA_DEVICEID_RHINE_III 0x3106 537 #define VIA_DEVICEID_RHINE_III_M 0x3053 538 539 /* 540 * Delta Electronics device ID. 541 */ 542 #define DELTA_VENDORID 0x1500 543 544 /* 545 * Delta device IDs. 546 */ 547 #define DELTA_DEVICEID_RHINE_II 0x1320 548 549 /* 550 * Addtron vendor ID. 551 */ 552 #define ADDTRON_VENDORID 0x4033 553 554 /* 555 * Addtron device IDs. 556 */ 557 #define ADDTRON_DEVICEID_RHINE_II 0x1320 558 559 /* 560 * VIA Rhine revision IDs 561 */ 562 563 #define REV_ID_VT3043_E 0x04 564 #define REV_ID_VT3071_A 0x20 565 #define REV_ID_VT3071_B 0x21 566 #define REV_ID_VT6102_A 0x40 567 #define REV_ID_VT6102_B 0x41 568 #define REV_ID_VT6102_C 0x42 569 #define REV_ID_VT6102_APOLLO 0x74 570 #define REV_ID_VT6105_A0 0x80 571 #define REV_ID_VT6105_B0 0x83 572 #define REV_ID_VT6105_LOM 0x8A 573 #define REV_ID_VT6107_A0 0x8C 574 #define REV_ID_VT6107_A1 0x8D 575 #define REV_ID_VT6105M_A0 0x90 576 #define REV_ID_VT6105M_B1 0x94 577 578 /* 579 * PCI low memory base and low I/O base register, and 580 * other PCI registers. 581 */ 582 583 #define VR_PCI_VENDOR_ID 0x00 584 #define VR_PCI_DEVICE_ID 0x02 585 #define VR_PCI_COMMAND 0x04 586 #define VR_PCI_STATUS 0x06 587 #define VR_PCI_REVID 0x08 588 #define VR_PCI_CLASSCODE 0x09 589 #define VR_PCI_LATENCY_TIMER 0x0D 590 #define VR_PCI_HEADER_TYPE 0x0E 591 #define VR_PCI_LOIO 0x10 592 #define VR_PCI_LOMEM 0x14 593 #define VR_PCI_BIOSROM 0x30 594 #define VR_PCI_INTLINE 0x3C 595 #define VR_PCI_INTPIN 0x3D 596 #define VR_PCI_MINGNT 0x3E 597 #define VR_PCI_MINLAT 0x0F 598 #define VR_PCI_RESETOPT 0x48 599 #define VR_PCI_EEPROM_DATA 0x4C 600 #define VR_PCI_MODE0 0x50 601 #define VR_PCI_MODE2 0x52 602 #define VR_PCI_MODE3 0x53 603 604 #define VR_MODE2_PCEROPT 0x80 /* VT6102 only */ 605 #define VR_MODE2_DISABT 0x40 606 #define VR_MODE2_MRDPL 0x08 /* VT6107A1 and above */ 607 #define VR_MODE2_MODE10T 0x02 608 609 #define VR_MODE3_XONOPT 0x80 610 #define VR_MODE3_TPACEN 0x40 611 #define VR_MODE3_BACKOPT 0x20 612 #define VR_MODE3_DLTSEL 0x10 613 #define VR_MODE3_MIIDMY 0x08 614 #define VR_MODE3_MIION 0x04 615 616 /* power management registers */ 617 #define VR_PCI_CAPID 0xDC /* 8 bits */ 618 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 619 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 620 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 621 622 #define VR_PSTATE_MASK 0x0003 623 #define VR_PSTATE_D0 0x0000 624 #define VR_PSTATE_D1 0x0002 625 #define VR_PSTATE_D2 0x0002 626 #define VR_PSTATE_D3 0x0003 627 #define VR_PME_EN 0x0010 628 #define VR_PME_STATUS 0x8000 629 630 #define VR_RX_RING_CNT 128 631 #define VR_TX_RING_CNT 128 632 #define VR_TX_RING_SIZE sizeof(struct vr_desc) * VR_TX_RING_CNT 633 #define VR_RX_RING_SIZE sizeof(struct vr_desc) * VR_RX_RING_CNT 634 #define VR_RING_ALIGN sizeof(struct vr_desc) 635 #define VR_RX_ALIGN sizeof(uint32_t) 636 #define VR_MAXFRAGS 8 637 #define VR_TX_INTR_THRESH 8 638 639 #define VR_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 640 #define VR_ADDR_HI(x) ((uint64_t)(x) >> 32) 641 #define VR_TX_RING_ADDR(sc, i) \ 642 ((sc)->vr_rdata.vr_tx_ring_paddr + sizeof(struct vr_desc) * (i)) 643 #define VR_RX_RING_ADDR(sc, i) \ 644 ((sc)->vr_rdata.vr_rx_ring_paddr + sizeof(struct vr_desc) * (i)) 645 #define VR_INC(x,y) (x) = (((x) + 1) % y) 646 647 struct vr_txdesc { 648 struct mbuf *tx_m; 649 bus_dmamap_t tx_dmamap; 650 }; 651 652 struct vr_rxdesc { 653 struct mbuf *rx_m; 654 bus_dmamap_t rx_dmamap; 655 struct vr_desc *desc; 656 }; 657 658 struct vr_chain_data { 659 bus_dma_tag_t vr_parent_tag; 660 bus_dma_tag_t vr_tx_tag; 661 struct vr_txdesc vr_txdesc[VR_TX_RING_CNT]; 662 bus_dma_tag_t vr_rx_tag; 663 struct vr_rxdesc vr_rxdesc[VR_RX_RING_CNT]; 664 bus_dma_tag_t vr_tx_ring_tag; 665 bus_dma_tag_t vr_rx_ring_tag; 666 bus_dmamap_t vr_tx_ring_map; 667 bus_dmamap_t vr_rx_ring_map; 668 bus_dmamap_t vr_rx_sparemap; 669 int vr_tx_pkts; 670 int vr_tx_prod; 671 int vr_tx_cons; 672 int vr_tx_cnt; 673 int vr_rx_cons; 674 }; 675 676 struct vr_ring_data { 677 struct vr_desc *vr_rx_ring; 678 struct vr_desc *vr_tx_ring; 679 bus_addr_t vr_rx_ring_paddr; 680 bus_addr_t vr_tx_ring_paddr; 681 }; 682 683 struct vr_statistics { 684 uint64_t tx_ok; 685 uint64_t rx_ok; 686 uint32_t tx_errors; 687 uint32_t rx_errors; 688 uint32_t rx_no_buffers; 689 uint32_t rx_no_mbufs; 690 uint32_t rx_crc_errors; 691 uint32_t rx_alignment; 692 uint32_t rx_fifo_overflows; 693 uint32_t rx_giants; 694 uint32_t rx_runts; 695 uint32_t tx_abort; 696 uint32_t tx_collisions; 697 uint32_t tx_late_collisions; 698 uint32_t tx_underrun; 699 uint32_t bus_errors; 700 uint32_t num_restart; 701 }; 702 703 struct vr_softc { 704 struct ifnet *vr_ifp; /* interface info */ 705 device_t vr_dev; 706 struct resource *vr_res; 707 int vr_res_id; 708 int vr_res_type; 709 struct resource *vr_irq; 710 void *vr_intrhand; 711 device_t vr_miibus; 712 uint8_t vr_revid; /* Rhine chip revision */ 713 uint8_t vr_flags; /* See VR_F_* below */ 714 #define VR_F_RESTART 0x01 /* Restart unit on next tick */ 715 int vr_phyaddr; 716 int vr_if_flags; 717 struct task vr_link_task; 718 struct vr_chain_data vr_cdata; 719 struct vr_ring_data vr_rdata; 720 struct vr_statistics vr_stat; 721 struct callout vr_stat_callout; 722 struct mtx vr_mtx; 723 int vr_suspended; /* if 1, sleeping/detaching */ 724 int vr_quirks; 725 int vr_link; 726 int vr_watchdog_timer; 727 int vr_txthresh; 728 int vr_detach; 729 #ifdef DEVICE_POLLING 730 int rxcycles; 731 #endif 732 }; 733 734 #define VR_LOCK(_sc) mtx_lock(&(_sc)->vr_mtx) 735 #define VR_UNLOCK(_sc) mtx_unlock(&(_sc)->vr_mtx) 736 #define VR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vr_mtx, MA_OWNED) 737 738 /* 739 * register space access macros 740 */ 741 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->vr_res, reg, val) 742 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) 743 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) 744 745 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) 746 #define CSR_READ_1(sc, reg) bus_read_1(sc->vr_res, reg) 747 748 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 749 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 750 751 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 752 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 753