1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Rhine register definitions. 37 */ 38 39 #define VR_PAR0 0x00 /* node address 0 to 4 */ 40 #define VR_PAR1 0x04 /* node address 2 to 6 */ 41 #define VR_RXCFG 0x06 /* receiver config register */ 42 #define VR_TXCFG 0x07 /* transmit config register */ 43 #define VR_COMMAND 0x08 /* command register */ 44 #define VR_ISR 0x0C /* interrupt/status register */ 45 #define VR_IMR 0x0E /* interrupt mask register */ 46 #define VR_MAR0 0x10 /* multicast hash 0 */ 47 #define VR_MAR1 0x14 /* multicast hash 1 */ 48 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 49 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 50 #define VR_CURRXDESC0 0x20 51 #define VR_CURRXDESC1 0x24 52 #define VR_CURRXDESC2 0x28 53 #define VR_CURRXDESC3 0x2C 54 #define VR_NEXTRXDESC0 0x30 55 #define VR_NEXTRXDESC1 0x34 56 #define VR_NEXTRXDESC2 0x38 57 #define VR_NEXTRXDESC3 0x3C 58 #define VR_CURTXDESC0 0x40 59 #define VR_CURTXDESC1 0x44 60 #define VR_CURTXDESC2 0x48 61 #define VR_CURTXDESC3 0x4C 62 #define VR_NEXTTXDESC0 0x50 63 #define VR_NEXTTXDESC1 0x54 64 #define VR_NEXTTXDESC2 0x58 65 #define VR_NEXTTXDESC3 0x5C 66 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 67 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 68 #define VR_TALLYCNT 0x68 /* tally counter test register */ 69 #define VR_PHYADDR 0x6C 70 #define VR_MIISTAT 0x6D 71 #define VR_BCR0 0x6E 72 #define VR_BCR1 0x6F 73 #define VR_MIICMD 0x70 74 #define VR_MIIADDR 0x71 75 #define VR_MIIDATA 0x72 76 #define VR_EECSR 0x74 77 #define VR_TEST 0x75 78 #define VR_GPIO 0x76 79 #define VR_CONFIG 0x78 80 #define VR_MPA_CNT 0x7C 81 #define VR_CRC_CNT 0x7E 82 #define VR_STICKHW 0x83 83 84 /* 85 * RX config bits. 86 */ 87 #define VR_RXCFG_RX_ERRPKTS 0x01 88 #define VR_RXCFG_RX_RUNT 0x02 89 #define VR_RXCFG_RX_MULTI 0x04 90 #define VR_RXCFG_RX_BROAD 0x08 91 #define VR_RXCFG_RX_PROMISC 0x10 92 #define VR_RXCFG_RX_THRESH 0xE0 93 94 #define VR_RXTHRESH_32BYTES 0x00 95 #define VR_RXTHRESH_64BYTES 0x20 96 #define VR_RXTHRESH_128BYTES 0x40 97 #define VR_RXTHRESH_256BYTES 0x60 98 #define VR_RXTHRESH_512BYTES 0x80 99 #define VR_RXTHRESH_768BYTES 0xA0 100 #define VR_RXTHRESH_1024BYTES 0xC0 101 #define VR_RXTHRESH_STORENFWD 0xE0 102 103 /* 104 * TX config bits. 105 */ 106 #define VR_TXCFG_RSVD0 0x01 107 #define VR_TXCFG_LOOPBKMODE 0x06 108 #define VR_TXCFG_BACKOFF 0x08 109 #define VR_TXCFG_RSVD1 0x10 110 #define VR_TXCFG_TX_THRESH 0xE0 111 112 #define VR_TXTHRESH_32BYTES 0x00 113 #define VR_TXTHRESH_64BYTES 0x20 114 #define VR_TXTHRESH_128BYTES 0x40 115 #define VR_TXTHRESH_256BYTES 0x60 116 #define VR_TXTHRESH_512BYTES 0x80 117 #define VR_TXTHRESH_768BYTES 0xA0 118 #define VR_TXTHRESH_1024BYTES 0xC0 119 #define VR_TXTHRESH_STORENFWD 0xE0 120 121 /* 122 * Command register bits. 123 */ 124 #define VR_CMD_INIT 0x0001 125 #define VR_CMD_START 0x0002 126 #define VR_CMD_STOP 0x0004 127 #define VR_CMD_RX_ON 0x0008 128 #define VR_CMD_TX_ON 0x0010 129 #define VR_CMD_TX_GO 0x0020 130 #define VR_CMD_RX_GO 0x0040 131 #define VR_CMD_RSVD 0x0080 132 #define VR_CMD_RX_EARLY 0x0100 133 #define VR_CMD_TX_EARLY 0x0200 134 #define VR_CMD_FULLDUPLEX 0x0400 135 #define VR_CMD_TX_NOPOLL 0x0800 136 137 #define VR_CMD_RESET 0x8000 138 139 /* 140 * Interrupt status bits. 141 */ 142 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 143 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 144 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 145 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 146 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 147 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 148 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 149 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 150 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 151 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 152 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */ 153 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (3065) */ 154 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 155 #define VR_ISR_RX_DROPPED 0x0800 156 #define VR_ISR_RX_NOBUF2 0x1000 157 #define VR_ISR_TX_ABRT2 0x2000 158 #define VR_ISR_LINKSTAT2 0x4000 159 #define VR_ISR_MAGICPACKET 0x8000 160 161 /* 162 * Interrupt mask bits. 163 */ 164 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 165 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 166 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 167 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 168 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 169 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 170 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 171 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 172 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 173 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 174 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 175 #define VR_IMR_RX_DROPPED 0x0800 176 #define VR_IMR_RX_NOBUF2 0x1000 177 #define VR_IMR_TX_ABRT2 0x2000 178 #define VR_IMR_LINKSTAT2 0x4000 179 #define VR_IMR_MAGICPACKET 0x8000 180 181 #define VR_INTRS \ 182 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 183 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 184 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 185 186 /* 187 * MII status register. 188 */ 189 190 #define VR_MIISTAT_SPEED 0x01 191 #define VR_MIISTAT_LINKFAULT 0x02 192 #define VR_MIISTAT_MGTREADERR 0x04 193 #define VR_MIISTAT_MIIERR 0x08 194 #define VR_MIISTAT_PHYOPT 0x10 195 #define VR_MIISTAT_MDC_SPEED 0x20 196 #define VR_MIISTAT_RSVD 0x40 197 #define VR_MIISTAT_GPIO1POLL 0x80 198 199 /* 200 * MII command register bits. 201 */ 202 #define VR_MIICMD_CLK 0x01 203 #define VR_MIICMD_DATAOUT 0x02 204 #define VR_MIICMD_DATAIN 0x04 205 #define VR_MIICMD_DIR 0x08 206 #define VR_MIICMD_DIRECTPGM 0x10 207 #define VR_MIICMD_WRITE_ENB 0x20 208 #define VR_MIICMD_READ_ENB 0x40 209 #define VR_MIICMD_AUTOPOLL 0x80 210 211 /* 212 * EEPROM control bits. 213 */ 214 #define VR_EECSR_DATAIN 0x01 /* data out */ 215 #define VR_EECSR_DATAOUT 0x02 /* data in */ 216 #define VR_EECSR_CLK 0x04 /* clock */ 217 #define VR_EECSR_CS 0x08 /* chip select */ 218 #define VR_EECSR_DPM 0x10 219 #define VR_EECSR_LOAD 0x20 220 #define VR_EECSR_EMBP 0x40 221 #define VR_EECSR_EEPR 0x80 222 223 #define VR_EECMD_WRITE 0x140 224 #define VR_EECMD_READ 0x180 225 #define VR_EECMD_ERASE 0x1c0 226 227 /* 228 * Test register bits. 229 */ 230 #define VR_TEST_TEST0 0x01 231 #define VR_TEST_TEST1 0x02 232 #define VR_TEST_TEST2 0x04 233 #define VR_TEST_TSTUD 0x08 234 #define VR_TEST_TSTOV 0x10 235 #define VR_TEST_BKOFF 0x20 236 #define VR_TEST_FCOL 0x40 237 #define VR_TEST_HBDES 0x80 238 239 /* 240 * Config register bits. 241 */ 242 #define VR_CFG_GPIO2OUTENB 0x00000001 243 #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 244 #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 245 #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 246 #define VR_CFG_MIIOPT 0x00000010 247 #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 248 #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 249 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 250 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 251 #define VR_CFG_MRREADWAIT 0x00000200 252 #define VR_CFG_MRWRITEWAIT 0x00000400 253 #define VR_CFG_RX_ARB 0x00000800 254 #define VR_CFG_TX_ARB 0x00001000 255 #define VR_CFG_READMULTI 0x00002000 256 #define VR_CFG_TX_PACE 0x00004000 257 #define VR_CFG_TX_QDIS 0x00008000 258 #define VR_CFG_ROMSEL0 0x00010000 259 #define VR_CFG_ROMSEL1 0x00020000 260 #define VR_CFG_ROMSEL2 0x00040000 261 #define VR_CFG_ROMTIMESEL 0x00080000 262 #define VR_CFG_RSVD0 0x00100000 263 #define VR_CFG_ROMDLY 0x00200000 264 #define VR_CFG_ROMOPT 0x00400000 265 #define VR_CFG_RSVD1 0x00800000 266 #define VR_CFG_BACKOFFOPT 0x01000000 267 #define VR_CFG_BACKOFFMOD 0x02000000 268 #define VR_CFG_CAPEFFECT 0x04000000 269 #define VR_CFG_BACKOFFRAND 0x08000000 270 #define VR_CFG_MAGICKPACKET 0x10000000 271 #define VR_CFG_PCIREADLINE 0x20000000 272 #define VR_CFG_DIAG 0x40000000 273 #define VR_CFG_GPIOEN 0x80000000 274 275 /* Sticky HW bits */ 276 #define VR_STICKHW_DS0 0x01 277 #define VR_STICKHW_DS1 0x02 278 #define VR_STICKHW_WOL_ENB 0x04 279 #define VR_STICKHW_WOL_STS 0x08 280 #define VR_STICKHW_LEGWOL_ENB 0x80 281 282 /* 283 * BCR0 register bits. (At least for the VT6102 chip.) 284 */ 285 #define VR_BCR0_DMA_LENGTH 0x07 286 287 #define VR_BCR0_DMA_32BYTES 0x00 288 #define VR_BCR0_DMA_64BYTES 0x01 289 #define VR_BCR0_DMA_128BYTES 0x02 290 #define VR_BCR0_DMA_256BYTES 0x03 291 #define VR_BCR0_DMA_512BYTES 0x04 292 #define VR_BCR0_DMA_1024BYTES 0x05 293 #define VR_BCR0_DMA_STORENFWD 0x07 294 295 #define VR_BCR0_RX_THRESH 0x38 296 297 #define VR_BCR0_RXTHRESHCFG 0x00 298 #define VR_BCR0_RXTHRESH64BYTES 0x08 299 #define VR_BCR0_RXTHRESH128BYTES 0x10 300 #define VR_BCR0_RXTHRESH256BYTES 0x18 301 #define VR_BCR0_RXTHRESH512BYTES 0x20 302 #define VR_BCR0_RXTHRESH1024BYTES 0x28 303 #define VR_BCR0_RXTHRESHSTORENFWD 0x38 304 #define VR_BCR0_EXTLED 0x40 305 #define VR_BCR0_MED2 0x80 306 307 /* 308 * BCR1 register bits. (At least for the VT6102 chip.) 309 */ 310 #define VR_BCR1_POT0 0x01 311 #define VR_BCR1_POT1 0x02 312 #define VR_BCR1_POT2 0x04 313 #define VR_BCR1_TX_THRESH 0x38 314 #define VR_BCR1_TXTHRESHCFG 0x00 315 #define VR_BCR1_TXTHRESH64BYTES 0x08 316 #define VR_BCR1_TXTHRESH128BYTES 0x10 317 #define VR_BCR1_TXTHRESH256BYTES 0x18 318 #define VR_BCR1_TXTHRESH512BYTES 0x20 319 #define VR_BCR1_TXTHRESH1024BYTES 0x28 320 #define VR_BCR1_TXTHRESHSTORENFWD 0x38 321 322 /* 323 * Rhine TX/RX list structure. 324 */ 325 326 struct vr_desc { 327 u_int32_t vr_status; 328 u_int32_t vr_ctl; 329 u_int32_t vr_ptr1; 330 u_int32_t vr_ptr2; 331 }; 332 333 #define vr_data vr_ptr1 334 #define vr_next vr_ptr2 335 336 337 #define VR_RXSTAT_RXERR 0x00000001 338 #define VR_RXSTAT_CRCERR 0x00000002 339 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 340 #define VR_RXSTAT_FIFOOFLOW 0x00000008 341 #define VR_RXSTAT_GIANT 0x00000010 342 #define VR_RXSTAT_RUNT 0x00000020 343 #define VR_RXSTAT_BUSERR 0x00000040 344 #define VR_RXSTAT_BUFFERR 0x00000080 345 #define VR_RXSTAT_LASTFRAG 0x00000100 346 #define VR_RXSTAT_FIRSTFRAG 0x00000200 347 #define VR_RXSTAT_RLINK 0x00000400 348 #define VR_RXSTAT_RX_PHYS 0x00000800 349 #define VR_RXSTAT_RX_BROAD 0x00001000 350 #define VR_RXSTAT_RX_MULTI 0x00002000 351 #define VR_RXSTAT_RX_OK 0x00004000 352 #define VR_RXSTAT_RXLEN 0x07FF0000 353 #define VR_RXSTAT_RXLEN_EXT 0x78000000 354 #define VR_RXSTAT_OWN 0x80000000 355 356 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 357 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 358 359 #define VR_RXCTL_BUFLEN 0x000007FF 360 #define VR_RXCTL_BUFLEN_EXT 0x00007800 361 #define VR_RXCTL_CHAIN 0x00008000 362 #define VR_RXCTL_RX_INTR 0x00800000 363 364 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 365 366 #define VR_TXSTAT_DEFER 0x00000001 367 #define VR_TXSTAT_UNDERRUN 0x00000002 368 #define VR_TXSTAT_COLLCNT 0x00000078 369 #define VR_TXSTAT_SQE 0x00000080 370 #define VR_TXSTAT_ABRT 0x00000100 371 #define VR_TXSTAT_LATECOLL 0x00000200 372 #define VR_TXSTAT_CARRLOST 0x00000400 373 #define VR_TXSTAT_UDF 0x00000800 374 #define VR_TXSTAT_BUSERR 0x00002000 375 #define VR_TXSTAT_JABTIMEO 0x00004000 376 #define VR_TXSTAT_ERRSUM 0x00008000 377 #define VR_TXSTAT_OWN 0x80000000 378 379 #define VR_TXCTL_BUFLEN 0x000007FF 380 #define VR_TXCTL_BUFLEN_EXT 0x00007800 381 #define VR_TXCTL_TLINK 0x00008000 382 #define VR_TXCTL_FIRSTFRAG 0x00200000 383 #define VR_TXCTL_LASTFRAG 0x00400000 384 #define VR_TXCTL_FINT 0x00800000 385 386 387 #define VR_MAXFRAGS 16 388 #define VR_RX_LIST_CNT 64 389 #define VR_TX_LIST_CNT 128 390 #define VR_MIN_FRAMELEN 60 391 #define VR_FRAMELEN 1536 392 #define VR_RXLEN 1520 393 394 #define VR_TXOWN(x) x->vr_ptr->vr_status 395 396 struct vr_list_data { 397 struct vr_desc vr_rx_list[VR_RX_LIST_CNT]; 398 struct vr_desc vr_tx_list[VR_TX_LIST_CNT]; 399 }; 400 401 struct vr_chain { 402 struct vr_desc *vr_ptr; 403 struct mbuf *vr_mbuf; 404 struct vr_chain *vr_nextdesc; 405 }; 406 407 struct vr_chain_onefrag { 408 struct vr_desc *vr_ptr; 409 struct mbuf *vr_mbuf; 410 struct vr_chain_onefrag *vr_nextdesc; 411 }; 412 413 struct vr_chain_data { 414 struct vr_chain_onefrag vr_rx_chain[VR_RX_LIST_CNT]; 415 struct vr_chain vr_tx_chain[VR_TX_LIST_CNT]; 416 417 struct vr_chain_onefrag *vr_rx_head; 418 419 struct vr_chain *vr_tx_head; 420 struct vr_chain *vr_tx_tail; 421 struct vr_chain *vr_tx_free; 422 }; 423 424 struct vr_type { 425 u_int16_t vr_vid; 426 u_int16_t vr_did; 427 char *vr_name; 428 }; 429 430 struct vr_mii_frame { 431 u_int8_t mii_stdelim; 432 u_int8_t mii_opcode; 433 u_int8_t mii_phyaddr; 434 u_int8_t mii_regaddr; 435 u_int8_t mii_turnaround; 436 u_int16_t mii_data; 437 }; 438 439 /* 440 * MII constants 441 */ 442 #define VR_MII_STARTDELIM 0x01 443 #define VR_MII_READOP 0x02 444 #define VR_MII_WRITEOP 0x01 445 #define VR_MII_TURNAROUND 0x02 446 447 #define VR_FLAG_FORCEDELAY 1 448 #define VR_FLAG_SCHEDDELAY 2 449 #define VR_FLAG_DELAYTIMEO 3 450 451 struct vr_softc { 452 struct arpcom arpcom; /* interface info */ 453 bus_space_handle_t vr_bhandle; /* bus space handle */ 454 bus_space_tag_t vr_btag; /* bus space tag */ 455 struct resource *vr_res; 456 struct resource *vr_irq; 457 void *vr_intrhand; 458 device_t vr_miibus; 459 struct vr_type *vr_info; /* Rhine adapter info */ 460 u_int8_t vr_unit; /* interface number */ 461 u_int8_t vr_type; 462 struct vr_list_data *vr_ldata; 463 struct vr_chain_data vr_cdata; 464 struct callout_handle vr_stat_ch; 465 struct mtx vr_mtx; 466 }; 467 468 #define VR_LOCK(_sc) mtx_lock(&(_sc)->vr_mtx) 469 #define VR_UNLOCK(_sc) mtx_unlock(&(_sc)->vr_mtx) 470 471 /* 472 * register space access macros 473 */ 474 #define CSR_WRITE_4(sc, reg, val) \ 475 bus_space_write_4(sc->vr_btag, sc->vr_bhandle, reg, val) 476 #define CSR_WRITE_2(sc, reg, val) \ 477 bus_space_write_2(sc->vr_btag, sc->vr_bhandle, reg, val) 478 #define CSR_WRITE_1(sc, reg, val) \ 479 bus_space_write_1(sc->vr_btag, sc->vr_bhandle, reg, val) 480 481 #define CSR_READ_4(sc, reg) \ 482 bus_space_read_4(sc->vr_btag, sc->vr_bhandle, reg) 483 #define CSR_READ_2(sc, reg) \ 484 bus_space_read_2(sc->vr_btag, sc->vr_bhandle, reg) 485 #define CSR_READ_1(sc, reg) \ 486 bus_space_read_1(sc->vr_btag, sc->vr_bhandle, reg) 487 488 #define VR_TIMEOUT 1000 489 #define ETHER_ALIGN 2 490 491 /* 492 * General constants that are fun to know. 493 * 494 * VIA vendor ID 495 */ 496 #define VIA_VENDORID 0x1106 497 498 /* 499 * VIA Rhine device IDs. 500 */ 501 #define VIA_DEVICEID_RHINE 0x3043 502 #define VIA_DEVICEID_RHINE_II 0x6100 503 #define VIA_DEVICEID_RHINE_II_2 0x3065 504 505 /* 506 * Delta Electronics device ID. 507 */ 508 #define DELTA_VENDORID 0x1500 509 510 /* 511 * Delta device IDs. 512 */ 513 #define DELTA_DEVICEID_RHINE_II 0x1320 514 515 /* 516 * Addtron vendor ID. 517 */ 518 #define ADDTRON_VENDORID 0x4033 519 520 /* 521 * Addtron device IDs. 522 */ 523 #define ADDTRON_DEVICEID_RHINE_II 0x1320 524 525 526 /* 527 * PCI low memory base and low I/O base register, and 528 * other PCI registers. 529 */ 530 531 #define VR_PCI_VENDOR_ID 0x00 532 #define VR_PCI_DEVICE_ID 0x02 533 #define VR_PCI_COMMAND 0x04 534 #define VR_PCI_STATUS 0x06 535 #define VR_PCI_CLASSCODE 0x09 536 #define VR_PCI_LATENCY_TIMER 0x0D 537 #define VR_PCI_HEADER_TYPE 0x0E 538 #define VR_PCI_LOIO 0x10 539 #define VR_PCI_LOMEM 0x14 540 #define VR_PCI_BIOSROM 0x30 541 #define VR_PCI_INTLINE 0x3C 542 #define VR_PCI_INTPIN 0x3D 543 #define VR_PCI_MINGNT 0x3E 544 #define VR_PCI_MINLAT 0x0F 545 #define VR_PCI_RESETOPT 0x48 546 #define VR_PCI_EEPROM_DATA 0x4C 547 548 /* power management registers */ 549 #define VR_PCI_CAPID 0xDC /* 8 bits */ 550 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 551 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 552 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 553 554 #define VR_PSTATE_MASK 0x0003 555 #define VR_PSTATE_D0 0x0000 556 #define VR_PSTATE_D1 0x0002 557 #define VR_PSTATE_D2 0x0002 558 #define VR_PSTATE_D3 0x0003 559 #define VR_PME_EN 0x0010 560 #define VR_PME_STATUS 0x8000 561 562 563 #ifdef __alpha__ 564 #undef vtophys 565 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 566 #endif 567