1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Rhine register definitions. 37 */ 38 39 #define VR_PAR0 0x00 /* node address 0 to 4 */ 40 #define VR_PAR1 0x04 /* node address 2 to 6 */ 41 #define VR_RXCFG 0x06 /* receiver config register */ 42 #define VR_TXCFG 0x07 /* transmit config register */ 43 #define VR_COMMAND 0x08 /* command register */ 44 #define VR_ISR 0x0C /* interrupt/status register */ 45 #define VR_IMR 0x0E /* interrupt mask register */ 46 #define VR_MAR0 0x10 /* multicast hash 0 */ 47 #define VR_MAR1 0x14 /* multicast hash 1 */ 48 #define VR_RXADDR 0x18 /* rx descriptor list start addr */ 49 #define VR_TXADDR 0x1C /* tx descriptor list start addr */ 50 #define VR_CURRXDESC0 0x20 51 #define VR_CURRXDESC1 0x24 52 #define VR_CURRXDESC2 0x28 53 #define VR_CURRXDESC3 0x2C 54 #define VR_NEXTRXDESC0 0x30 55 #define VR_NEXTRXDESC1 0x34 56 #define VR_NEXTRXDESC2 0x38 57 #define VR_NEXTRXDESC3 0x3C 58 #define VR_CURTXDESC0 0x40 59 #define VR_CURTXDESC1 0x44 60 #define VR_CURTXDESC2 0x48 61 #define VR_CURTXDESC3 0x4C 62 #define VR_NEXTTXDESC0 0x50 63 #define VR_NEXTTXDESC1 0x54 64 #define VR_NEXTTXDESC2 0x58 65 #define VR_NEXTTXDESC3 0x5C 66 #define VR_CURRXDMA 0x60 /* current RX DMA address */ 67 #define VR_CURTXDMA 0x64 /* current TX DMA address */ 68 #define VR_TALLYCNT 0x68 /* tally counter test register */ 69 #define VR_PHYADDR 0x6C 70 #define VR_MIISTAT 0x6D 71 #define VR_BCR0 0x6E 72 #define VR_BCR1 0x6F 73 #define VR_MIICMD 0x70 74 #define VR_MIIADDR 0x71 75 #define VR_MIIDATA 0x72 76 #define VR_EECSR 0x74 77 #define VR_TEST 0x75 78 #define VR_GPIO 0x76 79 #define VR_CONFIG 0x78 80 #define VR_MPA_CNT 0x7C 81 #define VR_CRC_CNT 0x7E 82 #define VR_STICKHW 0x83 83 84 /* Misc Registers */ 85 #define VR_MISC_CR1 0x81 86 #define VR_MISCCR1_FORSRST 0x40 87 88 /* 89 * RX config bits. 90 */ 91 #define VR_RXCFG_RX_ERRPKTS 0x01 92 #define VR_RXCFG_RX_RUNT 0x02 93 #define VR_RXCFG_RX_MULTI 0x04 94 #define VR_RXCFG_RX_BROAD 0x08 95 #define VR_RXCFG_RX_PROMISC 0x10 96 #define VR_RXCFG_RX_THRESH 0xE0 97 98 #define VR_RXTHRESH_32BYTES 0x00 99 #define VR_RXTHRESH_64BYTES 0x20 100 #define VR_RXTHRESH_128BYTES 0x40 101 #define VR_RXTHRESH_256BYTES 0x60 102 #define VR_RXTHRESH_512BYTES 0x80 103 #define VR_RXTHRESH_768BYTES 0xA0 104 #define VR_RXTHRESH_1024BYTES 0xC0 105 #define VR_RXTHRESH_STORENFWD 0xE0 106 107 /* 108 * TX config bits. 109 */ 110 #define VR_TXCFG_RSVD0 0x01 111 #define VR_TXCFG_LOOPBKMODE 0x06 112 #define VR_TXCFG_BACKOFF 0x08 113 #define VR_TXCFG_RSVD1 0x10 114 #define VR_TXCFG_TX_THRESH 0xE0 115 116 #define VR_TXTHRESH_32BYTES 0x00 117 #define VR_TXTHRESH_64BYTES 0x20 118 #define VR_TXTHRESH_128BYTES 0x40 119 #define VR_TXTHRESH_256BYTES 0x60 120 #define VR_TXTHRESH_512BYTES 0x80 121 #define VR_TXTHRESH_768BYTES 0xA0 122 #define VR_TXTHRESH_1024BYTES 0xC0 123 #define VR_TXTHRESH_STORENFWD 0xE0 124 125 /* 126 * Command register bits. 127 */ 128 #define VR_CMD_INIT 0x0001 129 #define VR_CMD_START 0x0002 130 #define VR_CMD_STOP 0x0004 131 #define VR_CMD_RX_ON 0x0008 132 #define VR_CMD_TX_ON 0x0010 133 #define VR_CMD_TX_GO 0x0020 134 #define VR_CMD_RX_GO 0x0040 135 #define VR_CMD_RSVD 0x0080 136 #define VR_CMD_RX_EARLY 0x0100 137 #define VR_CMD_TX_EARLY 0x0200 138 #define VR_CMD_FULLDUPLEX 0x0400 139 #define VR_CMD_TX_NOPOLL 0x0800 140 141 #define VR_CMD_RESET 0x8000 142 143 /* 144 * Interrupt status bits. 145 */ 146 #define VR_ISR_RX_OK 0x0001 /* packet rx ok */ 147 #define VR_ISR_TX_OK 0x0002 /* packet tx ok */ 148 #define VR_ISR_RX_ERR 0x0004 /* packet rx with err */ 149 #define VR_ISR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 150 #define VR_ISR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 151 #define VR_ISR_RX_NOBUF 0x0020 /* no rx buffer available */ 152 #define VR_ISR_BUSERR 0x0040 /* PCI bus error */ 153 #define VR_ISR_STATSOFLOW 0x0080 /* stats counter oflow */ 154 #define VR_ISR_RX_EARLY 0x0100 /* rx early */ 155 #define VR_ISR_LINKSTAT 0x0200 /* MII status change */ 156 #define VR_ISR_ETI 0x0200 /* Tx early (3043/3071) */ 157 #define VR_ISR_UDFI 0x0200 /* Tx FIFO underflow (3065) */ 158 #define VR_ISR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 159 #define VR_ISR_RX_DROPPED 0x0800 160 #define VR_ISR_RX_NOBUF2 0x1000 161 #define VR_ISR_TX_ABRT2 0x2000 162 #define VR_ISR_LINKSTAT2 0x4000 163 #define VR_ISR_MAGICPACKET 0x8000 164 165 /* 166 * Interrupt mask bits. 167 */ 168 #define VR_IMR_RX_OK 0x0001 /* packet rx ok */ 169 #define VR_IMR_TX_OK 0x0002 /* packet tx ok */ 170 #define VR_IMR_RX_ERR 0x0004 /* packet rx with err */ 171 #define VR_IMR_TX_ABRT 0x0008 /* tx aborted due to excess colls */ 172 #define VR_IMR_TX_UNDERRUN 0x0010 /* tx buffer underflow */ 173 #define VR_IMR_RX_NOBUF 0x0020 /* no rx buffer available */ 174 #define VR_IMR_BUSERR 0x0040 /* PCI bus error */ 175 #define VR_IMR_STATSOFLOW 0x0080 /* stats counter oflow */ 176 #define VR_IMR_RX_EARLY 0x0100 /* rx early */ 177 #define VR_IMR_LINKSTAT 0x0200 /* MII status change */ 178 #define VR_IMR_RX_OFLOW 0x0400 /* rx FIFO overflow */ 179 #define VR_IMR_RX_DROPPED 0x0800 180 #define VR_IMR_RX_NOBUF2 0x1000 181 #define VR_IMR_TX_ABRT2 0x2000 182 #define VR_IMR_LINKSTAT2 0x4000 183 #define VR_IMR_MAGICPACKET 0x8000 184 185 #define VR_INTRS \ 186 (VR_IMR_RX_OK|VR_IMR_TX_OK|VR_IMR_RX_NOBUF| \ 187 VR_IMR_TX_ABRT|VR_IMR_TX_UNDERRUN|VR_IMR_BUSERR| \ 188 VR_IMR_RX_ERR|VR_ISR_RX_DROPPED) 189 190 /* 191 * MII status register. 192 */ 193 194 #define VR_MIISTAT_SPEED 0x01 195 #define VR_MIISTAT_LINKFAULT 0x02 196 #define VR_MIISTAT_MGTREADERR 0x04 197 #define VR_MIISTAT_MIIERR 0x08 198 #define VR_MIISTAT_PHYOPT 0x10 199 #define VR_MIISTAT_MDC_SPEED 0x20 200 #define VR_MIISTAT_RSVD 0x40 201 #define VR_MIISTAT_GPIO1POLL 0x80 202 203 /* 204 * MII command register bits. 205 */ 206 #define VR_MIICMD_CLK 0x01 207 #define VR_MIICMD_DATAOUT 0x02 208 #define VR_MIICMD_DATAIN 0x04 209 #define VR_MIICMD_DIR 0x08 210 #define VR_MIICMD_DIRECTPGM 0x10 211 #define VR_MIICMD_WRITE_ENB 0x20 212 #define VR_MIICMD_READ_ENB 0x40 213 #define VR_MIICMD_AUTOPOLL 0x80 214 215 /* 216 * EEPROM control bits. 217 */ 218 #define VR_EECSR_DATAIN 0x01 /* data out */ 219 #define VR_EECSR_DATAOUT 0x02 /* data in */ 220 #define VR_EECSR_CLK 0x04 /* clock */ 221 #define VR_EECSR_CS 0x08 /* chip select */ 222 #define VR_EECSR_DPM 0x10 223 #define VR_EECSR_LOAD 0x20 224 #define VR_EECSR_EMBP 0x40 225 #define VR_EECSR_EEPR 0x80 226 227 #define VR_EECMD_WRITE 0x140 228 #define VR_EECMD_READ 0x180 229 #define VR_EECMD_ERASE 0x1c0 230 231 /* 232 * Test register bits. 233 */ 234 #define VR_TEST_TEST0 0x01 235 #define VR_TEST_TEST1 0x02 236 #define VR_TEST_TEST2 0x04 237 #define VR_TEST_TSTUD 0x08 238 #define VR_TEST_TSTOV 0x10 239 #define VR_TEST_BKOFF 0x20 240 #define VR_TEST_FCOL 0x40 241 #define VR_TEST_HBDES 0x80 242 243 /* 244 * Config register bits. 245 */ 246 #define VR_CFG_GPIO2OUTENB 0x00000001 247 #define VR_CFG_GPIO2OUT 0x00000002 /* gen. purp. pin */ 248 #define VR_CFG_GPIO2IN 0x00000004 /* gen. purp. pin */ 249 #define VR_CFG_AUTOOPT 0x00000008 /* enable rx/tx autopoll */ 250 #define VR_CFG_MIIOPT 0x00000010 251 #define VR_CFG_MMIENB 0x00000020 /* memory mapped mode enb */ 252 #define VR_CFG_JUMPER 0x00000040 /* PHY and oper. mode select */ 253 #define VR_CFG_EELOAD 0x00000080 /* enable EEPROM programming */ 254 #define VR_CFG_LATMENB 0x00000100 /* larency timer effect enb. */ 255 #define VR_CFG_MRREADWAIT 0x00000200 256 #define VR_CFG_MRWRITEWAIT 0x00000400 257 #define VR_CFG_RX_ARB 0x00000800 258 #define VR_CFG_TX_ARB 0x00001000 259 #define VR_CFG_READMULTI 0x00002000 260 #define VR_CFG_TX_PACE 0x00004000 261 #define VR_CFG_TX_QDIS 0x00008000 262 #define VR_CFG_ROMSEL0 0x00010000 263 #define VR_CFG_ROMSEL1 0x00020000 264 #define VR_CFG_ROMSEL2 0x00040000 265 #define VR_CFG_ROMTIMESEL 0x00080000 266 #define VR_CFG_RSVD0 0x00100000 267 #define VR_CFG_ROMDLY 0x00200000 268 #define VR_CFG_ROMOPT 0x00400000 269 #define VR_CFG_RSVD1 0x00800000 270 #define VR_CFG_BACKOFFOPT 0x01000000 271 #define VR_CFG_BACKOFFMOD 0x02000000 272 #define VR_CFG_CAPEFFECT 0x04000000 273 #define VR_CFG_BACKOFFRAND 0x08000000 274 #define VR_CFG_MAGICKPACKET 0x10000000 275 #define VR_CFG_PCIREADLINE 0x20000000 276 #define VR_CFG_DIAG 0x40000000 277 #define VR_CFG_GPIOEN 0x80000000 278 279 /* Sticky HW bits */ 280 #define VR_STICKHW_DS0 0x01 281 #define VR_STICKHW_DS1 0x02 282 #define VR_STICKHW_WOL_ENB 0x04 283 #define VR_STICKHW_WOL_STS 0x08 284 #define VR_STICKHW_LEGWOL_ENB 0x80 285 286 /* 287 * BCR0 register bits. (At least for the VT6102 chip.) 288 */ 289 #define VR_BCR0_DMA_LENGTH 0x07 290 291 #define VR_BCR0_DMA_32BYTES 0x00 292 #define VR_BCR0_DMA_64BYTES 0x01 293 #define VR_BCR0_DMA_128BYTES 0x02 294 #define VR_BCR0_DMA_256BYTES 0x03 295 #define VR_BCR0_DMA_512BYTES 0x04 296 #define VR_BCR0_DMA_1024BYTES 0x05 297 #define VR_BCR0_DMA_STORENFWD 0x07 298 299 #define VR_BCR0_RX_THRESH 0x38 300 301 #define VR_BCR0_RXTHRESHCFG 0x00 302 #define VR_BCR0_RXTHRESH64BYTES 0x08 303 #define VR_BCR0_RXTHRESH128BYTES 0x10 304 #define VR_BCR0_RXTHRESH256BYTES 0x18 305 #define VR_BCR0_RXTHRESH512BYTES 0x20 306 #define VR_BCR0_RXTHRESH1024BYTES 0x28 307 #define VR_BCR0_RXTHRESHSTORENFWD 0x38 308 #define VR_BCR0_EXTLED 0x40 309 #define VR_BCR0_MED2 0x80 310 311 /* 312 * BCR1 register bits. (At least for the VT6102 chip.) 313 */ 314 #define VR_BCR1_POT0 0x01 315 #define VR_BCR1_POT1 0x02 316 #define VR_BCR1_POT2 0x04 317 #define VR_BCR1_TX_THRESH 0x38 318 #define VR_BCR1_TXTHRESHCFG 0x00 319 #define VR_BCR1_TXTHRESH64BYTES 0x08 320 #define VR_BCR1_TXTHRESH128BYTES 0x10 321 #define VR_BCR1_TXTHRESH256BYTES 0x18 322 #define VR_BCR1_TXTHRESH512BYTES 0x20 323 #define VR_BCR1_TXTHRESH1024BYTES 0x28 324 #define VR_BCR1_TXTHRESHSTORENFWD 0x38 325 326 /* 327 * Rhine TX/RX list structure. 328 */ 329 330 struct vr_desc { 331 u_int32_t vr_status; 332 u_int32_t vr_ctl; 333 u_int32_t vr_data; 334 u_int32_t vr_nextphys; 335 struct mbuf *vr_mbuf; 336 struct vr_desc *vr_next; 337 u_int32_t *vxr1; 338 u_int32_t *vxr2; 339 }; 340 341 342 #define VR_RXSTAT_RXERR 0x00000001 343 #define VR_RXSTAT_CRCERR 0x00000002 344 #define VR_RXSTAT_FRAMEALIGNERR 0x00000004 345 #define VR_RXSTAT_FIFOOFLOW 0x00000008 346 #define VR_RXSTAT_GIANT 0x00000010 347 #define VR_RXSTAT_RUNT 0x00000020 348 #define VR_RXSTAT_BUSERR 0x00000040 349 #define VR_RXSTAT_BUFFERR 0x00000080 350 #define VR_RXSTAT_LASTFRAG 0x00000100 351 #define VR_RXSTAT_FIRSTFRAG 0x00000200 352 #define VR_RXSTAT_RLINK 0x00000400 353 #define VR_RXSTAT_RX_PHYS 0x00000800 354 #define VR_RXSTAT_RX_BROAD 0x00001000 355 #define VR_RXSTAT_RX_MULTI 0x00002000 356 #define VR_RXSTAT_RX_OK 0x00004000 357 #define VR_RXSTAT_RXLEN 0x07FF0000 358 #define VR_RXSTAT_RXLEN_EXT 0x78000000 359 #define VR_RXSTAT_OWN 0x80000000 360 361 #define VR_RXBYTES(x) ((x & VR_RXSTAT_RXLEN) >> 16) 362 #define VR_RXSTAT (VR_RXSTAT_FIRSTFRAG|VR_RXSTAT_LASTFRAG|VR_RXSTAT_OWN) 363 364 #define VR_RXCTL_BUFLEN 0x000007FF 365 #define VR_RXCTL_BUFLEN_EXT 0x00007800 366 #define VR_RXCTL_CHAIN 0x00008000 367 #define VR_RXCTL_RX_INTR 0x00800000 368 #define VR_RXCTL_GOODIP 0x00280000 369 #define VR_RXCTL_GOODTCPUDP 0x00100000 370 371 #define VR_RXCTL (VR_RXCTL_CHAIN|VR_RXCTL_RX_INTR) 372 373 #define VR_TXSTAT_DEFER 0x00000001 374 #define VR_TXSTAT_UNDERRUN 0x00000002 375 #define VR_TXSTAT_COLLCNT 0x00000078 376 #define VR_TXSTAT_SQE 0x00000080 377 #define VR_TXSTAT_ABRT 0x00000100 378 #define VR_TXSTAT_LATECOLL 0x00000200 379 #define VR_TXSTAT_CARRLOST 0x00000400 380 #define VR_TXSTAT_UDF 0x00000800 381 #define VR_TXSTAT_BUSERR 0x00002000 382 #define VR_TXSTAT_JABTIMEO 0x00004000 383 #define VR_TXSTAT_ERRSUM 0x00008000 384 #define VR_TXSTAT_OWN 0x80000000 385 386 #define VR_TXCTL_BUFLEN 0x000007FF 387 #define VR_TXCTL_BUFLEN_EXT 0x00007800 388 #define VR_TXCTL_TLINK 0x00008000 389 #define VR_TXCTL_NOCRC 0x00010000 390 #define VR_TXCTL_INSERTTAG 0x00020000 391 #define VR_TXCTL_IPCSUM 0x00040000 392 #define VR_TXCTL_UDPCSUM 0x00080000 393 #define VR_TXCTL_TCPCSUM 0x00100000 394 #define VR_TXCTL_FIRSTFRAG 0x00200000 395 #define VR_TXCTL_LASTFRAG 0x00400000 396 #define VR_TXCTL_FINT 0x00800000 397 398 399 #define VR_MAXFRAGS 16 400 #define VR_RX_LIST_CNT 256 401 #define VR_TX_LIST_CNT 256 402 #define VR_MIN_FRAMELEN 60 403 #define VR_FRAMELEN 1536 404 #define VR_RXLEN 1524 405 406 struct vr_mii_frame { 407 u_int8_t mii_stdelim; 408 u_int8_t mii_opcode; 409 u_int8_t mii_phyaddr; 410 u_int8_t mii_regaddr; 411 u_int8_t mii_turnaround; 412 u_int16_t mii_data; 413 }; 414 415 /* 416 * MII constants 417 */ 418 #define VR_MII_STARTDELIM 0x01 419 #define VR_MII_READOP 0x02 420 #define VR_MII_WRITEOP 0x01 421 #define VR_MII_TURNAROUND 0x02 422 423 #define VR_FLAG_FORCEDELAY 1 424 #define VR_FLAG_SCHEDDELAY 2 425 #define VR_FLAG_DELAYTIMEO 3 426 427 428 #define VR_TIMEOUT 1000 429 #define ETHER_ALIGN 2 430 431 /* 432 * General constants that are fun to know. 433 * 434 * VIA vendor ID 435 */ 436 #define VIA_VENDORID 0x1106 437 438 /* 439 * VIA Rhine device IDs. 440 */ 441 #define VIA_DEVICEID_RHINE 0x3043 442 #define VIA_DEVICEID_RHINE_II 0x6100 443 #define VIA_DEVICEID_RHINE_II_2 0x3065 444 #define VIA_DEVICEID_RHINE_III 0x3106 445 #define VIA_DEVICEID_RHINE_III_M 0x3053 446 447 /* 448 * Delta Electronics device ID. 449 */ 450 #define DELTA_VENDORID 0x1500 451 452 /* 453 * Delta device IDs. 454 */ 455 #define DELTA_DEVICEID_RHINE_II 0x1320 456 457 /* 458 * Addtron vendor ID. 459 */ 460 #define ADDTRON_VENDORID 0x4033 461 462 /* 463 * Addtron device IDs. 464 */ 465 #define ADDTRON_DEVICEID_RHINE_II 0x1320 466 467 /* 468 * VIA Rhine revision IDs 469 */ 470 471 #define REV_ID_VT3043_E 0x04 472 #define REV_ID_VT3071_A 0x20 473 #define REV_ID_VT3071_B 0x21 474 #define REV_ID_VT3065_A 0x40 475 #define REV_ID_VT3065_B 0x41 476 #define REV_ID_VT3065_C 0x42 477 #define REV_ID_VT6102_APOLLO 0x74 478 #define REV_ID_VT3106 0x80 479 #define REV_ID_VT3106_J 0x80 /* 0x80-0x8F */ 480 #define REV_ID_VT3106_S 0x90 /* 0x90-0xA0 */ 481 482 /* 483 * PCI low memory base and low I/O base register, and 484 * other PCI registers. 485 */ 486 487 #define VR_PCI_VENDOR_ID 0x00 488 #define VR_PCI_DEVICE_ID 0x02 489 #define VR_PCI_COMMAND 0x04 490 #define VR_PCI_STATUS 0x06 491 #define VR_PCI_REVID 0x08 492 #define VR_PCI_CLASSCODE 0x09 493 #define VR_PCI_LATENCY_TIMER 0x0D 494 #define VR_PCI_HEADER_TYPE 0x0E 495 #define VR_PCI_LOIO 0x10 496 #define VR_PCI_LOMEM 0x14 497 #define VR_PCI_BIOSROM 0x30 498 #define VR_PCI_INTLINE 0x3C 499 #define VR_PCI_INTPIN 0x3D 500 #define VR_PCI_MINGNT 0x3E 501 #define VR_PCI_MINLAT 0x0F 502 #define VR_PCI_RESETOPT 0x48 503 #define VR_PCI_EEPROM_DATA 0x4C 504 #define VR_PCI_MODE 0x50 505 506 #define VR_MODE3_MIION 0x04 507 508 /* power management registers */ 509 #define VR_PCI_CAPID 0xDC /* 8 bits */ 510 #define VR_PCI_NEXTPTR 0xDD /* 8 bits */ 511 #define VR_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 512 #define VR_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 513 514 #define VR_PSTATE_MASK 0x0003 515 #define VR_PSTATE_D0 0x0000 516 #define VR_PSTATE_D1 0x0002 517 #define VR_PSTATE_D2 0x0002 518 #define VR_PSTATE_D3 0x0003 519 #define VR_PME_EN 0x0010 520 #define VR_PME_STATUS 0x8000 521