1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/module.h> 70 #include <sys/socket.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/bpf.h> 79 80 #include <vm/vm.h> /* for vtophys */ 81 #include <vm/pmap.h> /* for vtophys */ 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 93 #define VR_USEIOSPACE 94 95 #include <pci/if_vrreg.h> 96 97 MODULE_DEPEND(vr, pci, 1, 1, 1); 98 MODULE_DEPEND(vr, ether, 1, 1, 1); 99 MODULE_DEPEND(vr, miibus, 1, 1, 1); 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe(device_t); 128 static int vr_attach(device_t); 129 static int vr_detach(device_t); 130 131 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 132 struct mbuf *); 133 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 134 135 static void vr_rxeof(struct vr_softc *); 136 static void vr_rxeoc(struct vr_softc *); 137 static void vr_txeof(struct vr_softc *); 138 static void vr_tick(void *); 139 static void vr_intr(void *); 140 static void vr_start(struct ifnet *); 141 static void vr_start_locked(struct ifnet *); 142 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 143 static void vr_init(void *); 144 static void vr_init_locked(struct vr_softc *); 145 static void vr_stop(struct vr_softc *); 146 static void vr_watchdog(struct ifnet *); 147 static void vr_shutdown(device_t); 148 static int vr_ifmedia_upd(struct ifnet *); 149 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150 151 #ifdef VR_USESWSHIFT 152 static void vr_mii_sync(struct vr_softc *); 153 static void vr_mii_send(struct vr_softc *, uint32_t, int); 154 #endif 155 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 156 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 157 static int vr_miibus_readreg(device_t, uint16_t, uint16_t); 158 static int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 159 static void vr_miibus_statchg(device_t); 160 161 static void vr_setcfg(struct vr_softc *, int); 162 static void vr_setmulti(struct vr_softc *); 163 static void vr_reset(struct vr_softc *); 164 static int vr_list_rx_init(struct vr_softc *); 165 static int vr_list_tx_init(struct vr_softc *); 166 167 #ifdef VR_USEIOSPACE 168 #define VR_RES SYS_RES_IOPORT 169 #define VR_RID VR_PCI_LOIO 170 #else 171 #define VR_RES SYS_RES_MEMORY 172 #define VR_RID VR_PCI_LOMEM 173 #endif 174 175 static device_method_t vr_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, vr_probe), 178 DEVMETHOD(device_attach, vr_attach), 179 DEVMETHOD(device_detach, vr_detach), 180 DEVMETHOD(device_shutdown, vr_shutdown), 181 182 /* bus interface */ 183 DEVMETHOD(bus_print_child, bus_generic_print_child), 184 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 185 186 /* MII interface */ 187 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 188 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 189 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 190 191 { 0, 0 } 192 }; 193 194 static driver_t vr_driver = { 195 "vr", 196 vr_methods, 197 sizeof(struct vr_softc) 198 }; 199 200 static devclass_t vr_devclass; 201 202 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 203 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 204 205 #define VR_SETBIT(sc, reg, x) \ 206 CSR_WRITE_1(sc, reg, \ 207 CSR_READ_1(sc, reg) | (x)) 208 209 #define VR_CLRBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) & ~(x)) 212 213 #define VR_SETBIT16(sc, reg, x) \ 214 CSR_WRITE_2(sc, reg, \ 215 CSR_READ_2(sc, reg) | (x)) 216 217 #define VR_CLRBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) & ~(x)) 220 221 #define VR_SETBIT32(sc, reg, x) \ 222 CSR_WRITE_4(sc, reg, \ 223 CSR_READ_4(sc, reg) | (x)) 224 225 #define VR_CLRBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) & ~(x)) 228 229 #define SIO_SET(x) \ 230 CSR_WRITE_1(sc, VR_MIICMD, \ 231 CSR_READ_1(sc, VR_MIICMD) | (x)) 232 233 #define SIO_CLR(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 236 237 #ifdef VR_USESWSHIFT 238 /* 239 * Sync the PHYs by setting data bit and strobing the clock 32 times. 240 */ 241 static void 242 vr_mii_sync(struct vr_softc *sc) 243 { 244 register int i; 245 246 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 247 248 for (i = 0; i < 32; i++) { 249 SIO_SET(VR_MIICMD_CLK); 250 DELAY(1); 251 SIO_CLR(VR_MIICMD_CLK); 252 DELAY(1); 253 } 254 } 255 256 /* 257 * Clock a series of bits through the MII. 258 */ 259 static void 260 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 261 { 262 int i; 263 264 SIO_CLR(VR_MIICMD_CLK); 265 266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 267 if (bits & i) { 268 SIO_SET(VR_MIICMD_DATAIN); 269 } else { 270 SIO_CLR(VR_MIICMD_DATAIN); 271 } 272 DELAY(1); 273 SIO_CLR(VR_MIICMD_CLK); 274 DELAY(1); 275 SIO_SET(VR_MIICMD_CLK); 276 } 277 } 278 #endif 279 280 /* 281 * Read an PHY register through the MII. 282 */ 283 static int 284 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 285 #ifdef VR_USESWSHIFT 286 { 287 int i, ack; 288 289 /* Set up frame for RX. */ 290 frame->mii_stdelim = VR_MII_STARTDELIM; 291 frame->mii_opcode = VR_MII_READOP; 292 frame->mii_turnaround = 0; 293 frame->mii_data = 0; 294 295 CSR_WRITE_1(sc, VR_MIICMD, 0); 296 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 297 298 /* Turn on data xmit. */ 299 SIO_SET(VR_MIICMD_DIR); 300 301 vr_mii_sync(sc); 302 303 /* Send command/address info. */ 304 vr_mii_send(sc, frame->mii_stdelim, 2); 305 vr_mii_send(sc, frame->mii_opcode, 2); 306 vr_mii_send(sc, frame->mii_phyaddr, 5); 307 vr_mii_send(sc, frame->mii_regaddr, 5); 308 309 /* Idle bit. */ 310 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 311 DELAY(1); 312 SIO_SET(VR_MIICMD_CLK); 313 DELAY(1); 314 315 /* Turn off xmit. */ 316 SIO_CLR(VR_MIICMD_DIR); 317 318 /* Check for ack */ 319 SIO_CLR(VR_MIICMD_CLK); 320 DELAY(1); 321 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 322 SIO_SET(VR_MIICMD_CLK); 323 DELAY(1); 324 325 /* 326 * Now try reading data bits. If the ack failed, we still 327 * need to clock through 16 cycles to keep the PHY(s) in sync. 328 */ 329 if (ack) { 330 for(i = 0; i < 16; i++) { 331 SIO_CLR(VR_MIICMD_CLK); 332 DELAY(1); 333 SIO_SET(VR_MIICMD_CLK); 334 DELAY(1); 335 } 336 goto fail; 337 } 338 339 for (i = 0x8000; i; i >>= 1) { 340 SIO_CLR(VR_MIICMD_CLK); 341 DELAY(1); 342 if (!ack) { 343 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 344 frame->mii_data |= i; 345 DELAY(1); 346 } 347 SIO_SET(VR_MIICMD_CLK); 348 DELAY(1); 349 } 350 351 fail: 352 SIO_CLR(VR_MIICMD_CLK); 353 DELAY(1); 354 SIO_SET(VR_MIICMD_CLK); 355 DELAY(1); 356 357 if (ack) 358 return (1); 359 return (0); 360 } 361 #else 362 { 363 int i; 364 365 /* Set the PHY address. */ 366 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 367 frame->mii_phyaddr); 368 369 /* Set the register address. */ 370 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 371 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 372 373 for (i = 0; i < 10000; i++) { 374 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 375 break; 376 DELAY(1); 377 } 378 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 379 380 return (0); 381 } 382 #endif 383 384 385 /* 386 * Write to a PHY register through the MII. 387 */ 388 static int 389 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 390 #ifdef VR_USESWSHIFT 391 { 392 CSR_WRITE_1(sc, VR_MIICMD, 0); 393 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 394 395 /* Set up frame for TX. */ 396 frame->mii_stdelim = VR_MII_STARTDELIM; 397 frame->mii_opcode = VR_MII_WRITEOP; 398 frame->mii_turnaround = VR_MII_TURNAROUND; 399 400 /* Turn on data output. */ 401 SIO_SET(VR_MIICMD_DIR); 402 403 vr_mii_sync(sc); 404 405 vr_mii_send(sc, frame->mii_stdelim, 2); 406 vr_mii_send(sc, frame->mii_opcode, 2); 407 vr_mii_send(sc, frame->mii_phyaddr, 5); 408 vr_mii_send(sc, frame->mii_regaddr, 5); 409 vr_mii_send(sc, frame->mii_turnaround, 2); 410 vr_mii_send(sc, frame->mii_data, 16); 411 412 /* Idle bit. */ 413 SIO_SET(VR_MIICMD_CLK); 414 DELAY(1); 415 SIO_CLR(VR_MIICMD_CLK); 416 DELAY(1); 417 418 /* Turn off xmit. */ 419 SIO_CLR(VR_MIICMD_DIR); 420 421 return (0); 422 } 423 #else 424 { 425 int i; 426 427 /* Set the PHY address. */ 428 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 429 frame->mii_phyaddr); 430 431 /* Set the register address and data to write. */ 432 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 433 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 434 435 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 436 437 for (i = 0; i < 10000; i++) { 438 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 439 break; 440 DELAY(1); 441 } 442 443 return (0); 444 } 445 #endif 446 447 static int 448 vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 449 { 450 struct vr_mii_frame frame; 451 struct vr_softc *sc = device_get_softc(dev); 452 453 switch (sc->vr_revid) { 454 case REV_ID_VT6102_APOLLO: 455 if (phy != 1) { 456 frame.mii_data = 0; 457 goto out; 458 } 459 default: 460 break; 461 } 462 463 bzero((char *)&frame, sizeof(frame)); 464 frame.mii_phyaddr = phy; 465 frame.mii_regaddr = reg; 466 vr_mii_readreg(sc, &frame); 467 468 out: 469 return (frame.mii_data); 470 } 471 472 static int 473 vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 474 { 475 struct vr_mii_frame frame; 476 struct vr_softc *sc = device_get_softc(dev); 477 478 switch (sc->vr_revid) { 479 case REV_ID_VT6102_APOLLO: 480 if (phy != 1) 481 return (0); 482 default: 483 break; 484 } 485 486 bzero((char *)&frame, sizeof(frame)); 487 frame.mii_phyaddr = phy; 488 frame.mii_regaddr = reg; 489 frame.mii_data = data; 490 vr_mii_writereg(sc, &frame); 491 492 return (0); 493 } 494 495 static void 496 vr_miibus_statchg(device_t dev) 497 { 498 struct mii_data *mii; 499 struct vr_softc *sc = device_get_softc(dev); 500 501 mii = device_get_softc(sc->vr_miibus); 502 vr_setcfg(sc, mii->mii_media_active); 503 } 504 505 /* 506 * Program the 64-bit multicast hash filter. 507 */ 508 static void 509 vr_setmulti(struct vr_softc *sc) 510 { 511 struct ifnet *ifp = &sc->arpcom.ac_if; 512 int h = 0; 513 uint32_t hashes[2] = { 0, 0 }; 514 struct ifmultiaddr *ifma; 515 uint8_t rxfilt; 516 int mcnt = 0; 517 518 VR_LOCK_ASSERT(sc); 519 520 rxfilt = CSR_READ_1(sc, VR_RXCFG); 521 522 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 523 rxfilt |= VR_RXCFG_RX_MULTI; 524 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 525 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 526 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 527 return; 528 } 529 530 /* First, zero out all the existing hash bits. */ 531 CSR_WRITE_4(sc, VR_MAR0, 0); 532 CSR_WRITE_4(sc, VR_MAR1, 0); 533 534 /* Now program new ones. */ 535 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 536 if (ifma->ifma_addr->sa_family != AF_LINK) 537 continue; 538 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 539 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 540 if (h < 32) 541 hashes[0] |= (1 << h); 542 else 543 hashes[1] |= (1 << (h - 32)); 544 mcnt++; 545 } 546 547 if (mcnt) 548 rxfilt |= VR_RXCFG_RX_MULTI; 549 else 550 rxfilt &= ~VR_RXCFG_RX_MULTI; 551 552 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 553 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 554 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 555 } 556 557 /* 558 * In order to fiddle with the 559 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 560 * first have to put the transmit and/or receive logic in the idle state. 561 */ 562 static void 563 vr_setcfg(struct vr_softc *sc, int media) 564 { 565 int restart = 0; 566 567 VR_LOCK_ASSERT(sc); 568 569 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 570 restart = 1; 571 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 572 } 573 574 if ((media & IFM_GMASK) == IFM_FDX) 575 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 else 577 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 578 579 if (restart) 580 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 581 } 582 583 static void 584 vr_reset(struct vr_softc *sc) 585 { 586 register int i; 587 588 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during detach w/o lock. */ 589 590 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 591 592 for (i = 0; i < VR_TIMEOUT; i++) { 593 DELAY(10); 594 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 595 break; 596 } 597 if (i == VR_TIMEOUT) { 598 if (sc->vr_revid < REV_ID_VT3065_A) 599 printf("vr%d: reset never completed!\n", sc->vr_unit); 600 else { 601 /* Use newer force reset command */ 602 printf("vr%d: Using force reset command.\n", 603 sc->vr_unit); 604 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 605 } 606 } 607 608 /* Wait a little while for the chip to get its brains in order. */ 609 DELAY(1000); 610 } 611 612 /* 613 * Probe for a VIA Rhine chip. Check the PCI vendor and device 614 * IDs against our list and return a device name if we find a match. 615 */ 616 static int 617 vr_probe(device_t dev) 618 { 619 struct vr_type *t = vr_devs; 620 621 while (t->vr_name != NULL) { 622 if ((pci_get_vendor(dev) == t->vr_vid) && 623 (pci_get_device(dev) == t->vr_did)) { 624 device_set_desc(dev, t->vr_name); 625 return (BUS_PROBE_DEFAULT); 626 } 627 t++; 628 } 629 630 return (ENXIO); 631 } 632 633 /* 634 * Attach the interface. Allocate softc structures, do ifmedia 635 * setup and ethernet/BPF attach. 636 */ 637 static int 638 vr_attach(dev) 639 device_t dev; 640 { 641 int i; 642 u_char eaddr[ETHER_ADDR_LEN]; 643 struct vr_softc *sc; 644 struct ifnet *ifp; 645 int unit, error = 0, rid; 646 647 sc = device_get_softc(dev); 648 unit = device_get_unit(dev); 649 650 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 651 MTX_DEF); 652 /* 653 * Map control/status registers. 654 */ 655 pci_enable_busmaster(dev); 656 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 657 658 rid = VR_RID; 659 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 660 661 if (sc->vr_res == NULL) { 662 printf("vr%d: couldn't map ports/memory\n", unit); 663 error = ENXIO; 664 goto fail; 665 } 666 667 sc->vr_btag = rman_get_bustag(sc->vr_res); 668 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 669 670 /* Allocate interrupt */ 671 rid = 0; 672 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 673 RF_SHAREABLE | RF_ACTIVE); 674 675 if (sc->vr_irq == NULL) { 676 printf("vr%d: couldn't map interrupt\n", unit); 677 error = ENXIO; 678 goto fail; 679 } 680 681 /* 682 * Windows may put the chip in suspend mode when it 683 * shuts down. Be sure to kick it in the head to wake it 684 * up again. 685 */ 686 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 687 688 /* Reset the adapter. */ 689 vr_reset(sc); 690 691 /* 692 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 693 * initialization and disable AUTOPOLL. 694 */ 695 pci_write_config(dev, VR_PCI_MODE, 696 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 697 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 698 699 /* 700 * Get station address. The way the Rhine chips work, 701 * you're not allowed to directly access the EEPROM once 702 * they've been programmed a special way. Consequently, 703 * we need to read the node address from the PAR0 and PAR1 704 * registers. 705 */ 706 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 707 DELAY(200); 708 for (i = 0; i < ETHER_ADDR_LEN; i++) 709 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 710 711 sc->vr_unit = unit; 712 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 713 714 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 715 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 716 717 if (sc->vr_ldata == NULL) { 718 printf("vr%d: no memory for list buffers!\n", unit); 719 error = ENXIO; 720 goto fail; 721 } 722 723 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 724 725 ifp = &sc->arpcom.ac_if; 726 ifp->if_softc = sc; 727 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 728 ifp->if_mtu = ETHERMTU; 729 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 730 ifp->if_ioctl = vr_ioctl; 731 ifp->if_start = vr_start; 732 ifp->if_watchdog = vr_watchdog; 733 ifp->if_init = vr_init; 734 ifp->if_baudrate = 10000000; 735 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 736 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 737 IFQ_SET_READY(&ifp->if_snd); 738 #ifdef DEVICE_POLLING 739 ifp->if_capabilities |= IFCAP_POLLING; 740 #endif 741 ifp->if_capenable = ifp->if_capabilities; 742 743 /* Do MII setup. */ 744 if (mii_phy_probe(dev, &sc->vr_miibus, 745 vr_ifmedia_upd, vr_ifmedia_sts)) { 746 printf("vr%d: MII without any phy!\n", sc->vr_unit); 747 error = ENXIO; 748 goto fail; 749 } 750 751 callout_handle_init(&sc->vr_stat_ch); 752 753 /* Call MI attach routine. */ 754 ether_ifattach(ifp, eaddr); 755 756 sc->suspended = 0; 757 758 /* Hook interrupt last to avoid having to lock softc */ 759 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 760 vr_intr, sc, &sc->vr_intrhand); 761 762 if (error) { 763 printf("vr%d: couldn't set up irq\n", unit); 764 ether_ifdetach(ifp); 765 goto fail; 766 } 767 768 fail: 769 if (error) 770 vr_detach(dev); 771 772 return (error); 773 } 774 775 /* 776 * Shutdown hardware and free up resources. This can be called any 777 * time after the mutex has been initialized. It is called in both 778 * the error case in attach and the normal detach case so it needs 779 * to be careful about only freeing resources that have actually been 780 * allocated. 781 */ 782 static int 783 vr_detach(device_t dev) 784 { 785 struct vr_softc *sc = device_get_softc(dev); 786 struct ifnet *ifp = &sc->arpcom.ac_if; 787 788 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 789 790 VR_LOCK(sc); 791 792 sc->suspended = 1; 793 794 /* These should only be active if attach succeeded */ 795 if (device_is_attached(dev)) { 796 vr_stop(sc); 797 VR_UNLOCK(sc); /* XXX: Avoid recursive acquire. */ 798 ether_ifdetach(ifp); 799 VR_LOCK(sc); 800 } 801 if (sc->vr_miibus) 802 device_delete_child(dev, sc->vr_miibus); 803 bus_generic_detach(dev); 804 805 if (sc->vr_intrhand) 806 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 807 if (sc->vr_irq) 808 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 809 if (sc->vr_res) 810 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 811 812 if (sc->vr_ldata) 813 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 814 815 VR_UNLOCK(sc); 816 mtx_destroy(&sc->vr_mtx); 817 818 return (0); 819 } 820 821 /* 822 * Initialize the transmit descriptors. 823 */ 824 static int 825 vr_list_tx_init(struct vr_softc *sc) 826 { 827 struct vr_chain_data *cd; 828 struct vr_list_data *ld; 829 int i; 830 831 cd = &sc->vr_cdata; 832 ld = sc->vr_ldata; 833 for (i = 0; i < VR_TX_LIST_CNT; i++) { 834 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 835 if (i == (VR_TX_LIST_CNT - 1)) 836 cd->vr_tx_chain[i].vr_nextdesc = 837 &cd->vr_tx_chain[0]; 838 else 839 cd->vr_tx_chain[i].vr_nextdesc = 840 &cd->vr_tx_chain[i + 1]; 841 } 842 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 843 844 return (0); 845 } 846 847 848 /* 849 * Initialize the RX descriptors and allocate mbufs for them. Note that 850 * we arrange the descriptors in a closed ring, so that the last descriptor 851 * points back to the first. 852 */ 853 static int 854 vr_list_rx_init(struct vr_softc *sc) 855 { 856 struct vr_chain_data *cd; 857 struct vr_list_data *ld; 858 int i; 859 860 VR_LOCK_ASSERT(sc); 861 862 cd = &sc->vr_cdata; 863 ld = sc->vr_ldata; 864 865 for (i = 0; i < VR_RX_LIST_CNT; i++) { 866 cd->vr_rx_chain[i].vr_ptr = 867 (struct vr_desc *)&ld->vr_rx_list[i]; 868 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 869 return (ENOBUFS); 870 if (i == (VR_RX_LIST_CNT - 1)) { 871 cd->vr_rx_chain[i].vr_nextdesc = 872 &cd->vr_rx_chain[0]; 873 ld->vr_rx_list[i].vr_next = 874 vtophys(&ld->vr_rx_list[0]); 875 } else { 876 cd->vr_rx_chain[i].vr_nextdesc = 877 &cd->vr_rx_chain[i + 1]; 878 ld->vr_rx_list[i].vr_next = 879 vtophys(&ld->vr_rx_list[i + 1]); 880 } 881 } 882 883 cd->vr_rx_head = &cd->vr_rx_chain[0]; 884 885 return (0); 886 } 887 888 /* 889 * Initialize an RX descriptor and attach an MBUF cluster. 890 * Note: the length fields are only 11 bits wide, which means the 891 * largest size we can specify is 2047. This is important because 892 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 893 * overflow the field and make a mess. 894 */ 895 static int 896 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 897 { 898 struct mbuf *m_new = NULL; 899 900 if (m == NULL) { 901 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 902 if (m_new == NULL) 903 return (ENOBUFS); 904 905 MCLGET(m_new, M_DONTWAIT); 906 if (!(m_new->m_flags & M_EXT)) { 907 m_freem(m_new); 908 return (ENOBUFS); 909 } 910 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 911 } else { 912 m_new = m; 913 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 914 m_new->m_data = m_new->m_ext.ext_buf; 915 } 916 917 m_adj(m_new, sizeof(uint64_t)); 918 919 c->vr_mbuf = m_new; 920 c->vr_ptr->vr_status = VR_RXSTAT; 921 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 922 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 923 924 return (0); 925 } 926 927 /* 928 * A frame has been uploaded: pass the resulting mbuf chain up to 929 * the higher level protocols. 930 */ 931 static void 932 vr_rxeof(struct vr_softc *sc) 933 { 934 struct mbuf *m, *m0; 935 struct ifnet *ifp; 936 struct vr_chain_onefrag *cur_rx; 937 int total_len = 0; 938 uint32_t rxstat; 939 940 VR_LOCK_ASSERT(sc); 941 ifp = &sc->arpcom.ac_if; 942 943 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 944 VR_RXSTAT_OWN)) { 945 #ifdef DEVICE_POLLING 946 if (ifp->if_flags & IFF_POLLING) { 947 if (sc->rxcycles <= 0) 948 break; 949 sc->rxcycles--; 950 } 951 #endif /* DEVICE_POLLING */ 952 m0 = NULL; 953 cur_rx = sc->vr_cdata.vr_rx_head; 954 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 955 m = cur_rx->vr_mbuf; 956 957 /* 958 * If an error occurs, update stats, clear the 959 * status word and leave the mbuf cluster in place: 960 * it should simply get re-used next time this descriptor 961 * comes up in the ring. 962 */ 963 if (rxstat & VR_RXSTAT_RXERR) { 964 ifp->if_ierrors++; 965 printf("vr%d: rx error (%02x):", sc->vr_unit, 966 rxstat & 0x000000ff); 967 if (rxstat & VR_RXSTAT_CRCERR) 968 printf(" crc error"); 969 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 970 printf(" frame alignment error\n"); 971 if (rxstat & VR_RXSTAT_FIFOOFLOW) 972 printf(" FIFO overflow"); 973 if (rxstat & VR_RXSTAT_GIANT) 974 printf(" received giant packet"); 975 if (rxstat & VR_RXSTAT_RUNT) 976 printf(" received runt packet"); 977 if (rxstat & VR_RXSTAT_BUSERR) 978 printf(" system bus error"); 979 if (rxstat & VR_RXSTAT_BUFFERR) 980 printf("rx buffer error"); 981 printf("\n"); 982 vr_newbuf(sc, cur_rx, m); 983 continue; 984 } 985 986 /* No errors; receive the packet. */ 987 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 988 989 /* 990 * XXX The VIA Rhine chip includes the CRC with every 991 * received frame, and there's no way to turn this 992 * behavior off (at least, I can't find anything in 993 * the manual that explains how to do it) so we have 994 * to trim off the CRC manually. 995 */ 996 total_len -= ETHER_CRC_LEN; 997 998 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 999 NULL); 1000 vr_newbuf(sc, cur_rx, m); 1001 if (m0 == NULL) { 1002 ifp->if_ierrors++; 1003 continue; 1004 } 1005 m = m0; 1006 1007 ifp->if_ipackets++; 1008 VR_UNLOCK(sc); 1009 (*ifp->if_input)(ifp, m); 1010 VR_LOCK(sc); 1011 } 1012 } 1013 1014 static void 1015 vr_rxeoc(struct vr_softc *sc) 1016 { 1017 struct ifnet *ifp = &sc->arpcom.ac_if; 1018 int i; 1019 1020 VR_LOCK_ASSERT(sc); 1021 1022 ifp->if_ierrors++; 1023 1024 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1025 DELAY(10000); 1026 1027 /* Wait for receiver to stop */ 1028 for (i = 0x400; 1029 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1030 i--) { 1031 ; 1032 } 1033 1034 if (!i) { 1035 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1036 sc->vr_flags |= VR_F_RESTART; 1037 return; 1038 } 1039 1040 vr_rxeof(sc); 1041 1042 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1043 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1044 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1045 } 1046 1047 /* 1048 * A frame was downloaded to the chip. It's safe for us to clean up 1049 * the list buffers. 1050 */ 1051 static void 1052 vr_txeof(struct vr_softc *sc) 1053 { 1054 struct vr_chain *cur_tx; 1055 struct ifnet *ifp = &sc->arpcom.ac_if; 1056 1057 VR_LOCK_ASSERT(sc); 1058 1059 /* 1060 * Go through our tx list and free mbufs for those 1061 * frames that have been transmitted. 1062 */ 1063 cur_tx = sc->vr_cdata.vr_tx_cons; 1064 while (cur_tx->vr_mbuf != NULL) { 1065 uint32_t txstat; 1066 int i; 1067 1068 txstat = cur_tx->vr_ptr->vr_status; 1069 1070 if ((txstat & VR_TXSTAT_ABRT) || 1071 (txstat & VR_TXSTAT_UDF)) { 1072 for (i = 0x400; 1073 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1074 i--) 1075 ; /* Wait for chip to shutdown */ 1076 if (!i) { 1077 printf("vr%d: tx shutdown timeout\n", 1078 sc->vr_unit); 1079 sc->vr_flags |= VR_F_RESTART; 1080 break; 1081 } 1082 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1083 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1084 break; 1085 } 1086 1087 if (txstat & VR_TXSTAT_OWN) 1088 break; 1089 1090 if (txstat & VR_TXSTAT_ERRSUM) { 1091 ifp->if_oerrors++; 1092 if (txstat & VR_TXSTAT_DEFER) 1093 ifp->if_collisions++; 1094 if (txstat & VR_TXSTAT_LATECOLL) 1095 ifp->if_collisions++; 1096 } 1097 1098 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1099 1100 ifp->if_opackets++; 1101 m_freem(cur_tx->vr_mbuf); 1102 cur_tx->vr_mbuf = NULL; 1103 ifp->if_flags &= ~IFF_OACTIVE; 1104 1105 cur_tx = cur_tx->vr_nextdesc; 1106 } 1107 sc->vr_cdata.vr_tx_cons = cur_tx; 1108 if (cur_tx->vr_mbuf == NULL) 1109 ifp->if_timer = 0; 1110 } 1111 1112 static void 1113 vr_tick(void *xsc) 1114 { 1115 struct vr_softc *sc = xsc; 1116 struct mii_data *mii; 1117 1118 VR_LOCK(sc); 1119 1120 if (sc->vr_flags & VR_F_RESTART) { 1121 printf("vr%d: restarting\n", sc->vr_unit); 1122 vr_stop(sc); 1123 vr_reset(sc); 1124 vr_init_locked(sc); 1125 sc->vr_flags &= ~VR_F_RESTART; 1126 } 1127 1128 mii = device_get_softc(sc->vr_miibus); 1129 mii_tick(mii); 1130 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1131 1132 VR_UNLOCK(sc); 1133 } 1134 1135 #ifdef DEVICE_POLLING 1136 static poll_handler_t vr_poll; 1137 static poll_handler_t vr_poll_locked; 1138 1139 static void 1140 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1141 { 1142 struct vr_softc *sc = ifp->if_softc; 1143 1144 VR_LOCK(sc); 1145 vr_poll_locked(ifp, cmd, count); 1146 VR_UNLOCK(sc); 1147 } 1148 1149 static void 1150 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1151 { 1152 struct vr_softc *sc = ifp->if_softc; 1153 1154 VR_LOCK_ASSERT(sc); 1155 1156 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1157 ether_poll_deregister(ifp); 1158 cmd = POLL_DEREGISTER; 1159 } 1160 1161 if (cmd == POLL_DEREGISTER) { 1162 /* Final call, enable interrupts. */ 1163 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1164 return; 1165 } 1166 1167 sc->rxcycles = count; 1168 vr_rxeof(sc); 1169 vr_txeof(sc); 1170 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1171 vr_start_locked(ifp); 1172 1173 if (cmd == POLL_AND_CHECK_STATUS) { 1174 uint16_t status; 1175 1176 /* Also check status register. */ 1177 status = CSR_READ_2(sc, VR_ISR); 1178 if (status) 1179 CSR_WRITE_2(sc, VR_ISR, status); 1180 1181 if ((status & VR_INTRS) == 0) 1182 return; 1183 1184 if (status & VR_ISR_RX_DROPPED) { 1185 printf("vr%d: rx packet lost\n", sc->vr_unit); 1186 ifp->if_ierrors++; 1187 } 1188 1189 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1190 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1191 printf("vr%d: receive error (%04x)", 1192 sc->vr_unit, status); 1193 if (status & VR_ISR_RX_NOBUF) 1194 printf(" no buffers"); 1195 if (status & VR_ISR_RX_OFLOW) 1196 printf(" overflow"); 1197 if (status & VR_ISR_RX_DROPPED) 1198 printf(" packet lost"); 1199 printf("\n"); 1200 vr_rxeoc(sc); 1201 } 1202 1203 if ((status & VR_ISR_BUSERR) || 1204 (status & VR_ISR_TX_UNDERRUN)) { 1205 vr_reset(sc); 1206 vr_init_locked(sc); 1207 return; 1208 } 1209 1210 if ((status & VR_ISR_UDFI) || 1211 (status & VR_ISR_TX_ABRT2) || 1212 (status & VR_ISR_TX_ABRT)) { 1213 ifp->if_oerrors++; 1214 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1215 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1216 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1217 } 1218 } 1219 } 1220 } 1221 #endif /* DEVICE_POLLING */ 1222 1223 static void 1224 vr_intr(void *arg) 1225 { 1226 struct vr_softc *sc = arg; 1227 struct ifnet *ifp = &sc->arpcom.ac_if; 1228 uint16_t status; 1229 1230 VR_LOCK(sc); 1231 1232 if (sc->suspended) { 1233 /* 1234 * Forcibly disable interrupts. 1235 * XXX: Mobile VIA based platforms may need 1236 * interrupt re-enable on resume. 1237 */ 1238 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1239 goto done_locked; 1240 } 1241 1242 #ifdef DEVICE_POLLING 1243 if (ifp->if_flags & IFF_POLLING) 1244 goto done_locked; 1245 1246 if ((ifp->if_capenable & IFCAP_POLLING) && 1247 ether_poll_register(vr_poll, ifp)) { 1248 /* OK, disable interrupts. */ 1249 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1250 vr_poll_locked(ifp, 0, 1); 1251 goto done_locked; 1252 } 1253 #endif /* DEVICE_POLLING */ 1254 1255 /* Suppress unwanted interrupts. */ 1256 if (!(ifp->if_flags & IFF_UP)) { 1257 vr_stop(sc); 1258 goto done_locked; 1259 } 1260 1261 /* Disable interrupts. */ 1262 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1263 1264 for (;;) { 1265 status = CSR_READ_2(sc, VR_ISR); 1266 if (status) 1267 CSR_WRITE_2(sc, VR_ISR, status); 1268 1269 if ((status & VR_INTRS) == 0) 1270 break; 1271 1272 if (status & VR_ISR_RX_OK) 1273 vr_rxeof(sc); 1274 1275 if (status & VR_ISR_RX_DROPPED) { 1276 printf("vr%d: rx packet lost\n", sc->vr_unit); 1277 ifp->if_ierrors++; 1278 } 1279 1280 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1281 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1282 printf("vr%d: receive error (%04x)", 1283 sc->vr_unit, status); 1284 if (status & VR_ISR_RX_NOBUF) 1285 printf(" no buffers"); 1286 if (status & VR_ISR_RX_OFLOW) 1287 printf(" overflow"); 1288 if (status & VR_ISR_RX_DROPPED) 1289 printf(" packet lost"); 1290 printf("\n"); 1291 vr_rxeoc(sc); 1292 } 1293 1294 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1295 vr_reset(sc); 1296 vr_init_locked(sc); 1297 break; 1298 } 1299 1300 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1301 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1302 vr_txeof(sc); 1303 if ((status & VR_ISR_UDFI) || 1304 (status & VR_ISR_TX_ABRT2) || 1305 (status & VR_ISR_TX_ABRT)) { 1306 ifp->if_oerrors++; 1307 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1308 VR_SETBIT16(sc, VR_COMMAND, 1309 VR_CMD_TX_ON); 1310 VR_SETBIT16(sc, VR_COMMAND, 1311 VR_CMD_TX_GO); 1312 } 1313 } 1314 } 1315 } 1316 1317 /* Re-enable interrupts. */ 1318 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1319 1320 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1321 vr_start_locked(ifp); 1322 1323 done_locked: 1324 VR_UNLOCK(sc); 1325 } 1326 1327 /* 1328 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1329 * pointers to the fragment pointers. 1330 */ 1331 static int 1332 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1333 { 1334 struct vr_desc *f = NULL; 1335 struct mbuf *m; 1336 1337 VR_LOCK_ASSERT(sc); 1338 /* 1339 * The VIA Rhine wants packet buffers to be longword 1340 * aligned, but very often our mbufs aren't. Rather than 1341 * waste time trying to decide when to copy and when not 1342 * to copy, just do it all the time. 1343 */ 1344 m = m_defrag(m_head, M_DONTWAIT); 1345 if (m == NULL) 1346 return (1); 1347 1348 /* 1349 * The Rhine chip doesn't auto-pad, so we have to make 1350 * sure to pad short frames out to the minimum frame length 1351 * ourselves. 1352 */ 1353 if (m->m_len < VR_MIN_FRAMELEN) { 1354 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1355 m->m_len = m->m_pkthdr.len; 1356 } 1357 1358 c->vr_mbuf = m; 1359 f = c->vr_ptr; 1360 f->vr_data = vtophys(mtod(m, caddr_t)); 1361 f->vr_ctl = m->m_len; 1362 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1363 f->vr_status = 0; 1364 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1365 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1366 1367 return (0); 1368 } 1369 1370 /* 1371 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1372 * to the mbuf data regions directly in the transmit lists. We also save a 1373 * copy of the pointers since the transmit list fragment pointers are 1374 * physical addresses. 1375 */ 1376 1377 static void 1378 vr_start(struct ifnet *ifp) 1379 { 1380 struct vr_softc *sc = ifp->if_softc; 1381 1382 VR_LOCK(sc); 1383 vr_start_locked(ifp); 1384 VR_UNLOCK(sc); 1385 } 1386 1387 static void 1388 vr_start_locked(struct ifnet *ifp) 1389 { 1390 struct vr_softc *sc = ifp->if_softc; 1391 struct mbuf *m_head; 1392 struct vr_chain *cur_tx; 1393 1394 if (ifp->if_flags & IFF_OACTIVE) 1395 return; 1396 1397 cur_tx = sc->vr_cdata.vr_tx_prod; 1398 while (cur_tx->vr_mbuf == NULL) { 1399 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1400 if (m_head == NULL) 1401 break; 1402 1403 /* Pack the data into the descriptor. */ 1404 if (vr_encap(sc, cur_tx, m_head)) { 1405 /* Rollback, send what we were able to encap. */ 1406 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1407 break; 1408 } 1409 1410 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1411 1412 /* 1413 * If there's a BPF listener, bounce a copy of this frame 1414 * to him. 1415 */ 1416 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1417 1418 cur_tx = cur_tx->vr_nextdesc; 1419 } 1420 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1421 sc->vr_cdata.vr_tx_prod = cur_tx; 1422 1423 /* Tell the chip to start transmitting. */ 1424 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1425 1426 /* Set a timeout in case the chip goes out to lunch. */ 1427 ifp->if_timer = 5; 1428 1429 if (cur_tx->vr_mbuf != NULL) 1430 ifp->if_flags |= IFF_OACTIVE; 1431 } 1432 } 1433 1434 static void 1435 vr_init(void *xsc) 1436 { 1437 struct vr_softc *sc = xsc; 1438 1439 VR_LOCK(sc); 1440 vr_init_locked(sc); 1441 VR_UNLOCK(sc); 1442 } 1443 1444 static void 1445 vr_init_locked(struct vr_softc *sc) 1446 { 1447 struct ifnet *ifp = &sc->arpcom.ac_if; 1448 struct mii_data *mii; 1449 int i; 1450 1451 VR_LOCK_ASSERT(sc); 1452 1453 mii = device_get_softc(sc->vr_miibus); 1454 1455 /* Cancel pending I/O and free all RX/TX buffers. */ 1456 vr_stop(sc); 1457 vr_reset(sc); 1458 1459 /* Set our station address. */ 1460 for (i = 0; i < ETHER_ADDR_LEN; i++) 1461 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1462 1463 /* Set DMA size. */ 1464 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1465 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1466 1467 /* 1468 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1469 * so we must set both. 1470 */ 1471 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1472 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1473 1474 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1475 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1476 1477 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1478 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1479 1480 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1481 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1482 1483 /* Init circular RX list. */ 1484 if (vr_list_rx_init(sc) == ENOBUFS) { 1485 printf( 1486 "vr%d: initialization failed: no memory for rx buffers\n", sc->vr_unit); 1487 vr_stop(sc); 1488 return; 1489 } 1490 1491 /* Init tx descriptors. */ 1492 vr_list_tx_init(sc); 1493 1494 /* If we want promiscuous mode, set the allframes bit. */ 1495 if (ifp->if_flags & IFF_PROMISC) 1496 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1497 else 1498 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1499 1500 /* Set capture broadcast bit to capture broadcast frames. */ 1501 if (ifp->if_flags & IFF_BROADCAST) 1502 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1503 else 1504 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1505 1506 /* 1507 * Program the multicast filter, if necessary. 1508 */ 1509 vr_setmulti(sc); 1510 1511 /* 1512 * Load the address of the RX list. 1513 */ 1514 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1515 1516 /* Enable receiver and transmitter. */ 1517 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1518 VR_CMD_TX_ON|VR_CMD_RX_ON| 1519 VR_CMD_RX_GO); 1520 1521 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1522 1523 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1524 #ifdef DEVICE_POLLING 1525 /* 1526 * Disable interrupts if we are polling. 1527 */ 1528 if (ifp->if_flags & IFF_POLLING) 1529 CSR_WRITE_2(sc, VR_IMR, 0); 1530 else 1531 #endif /* DEVICE_POLLING */ 1532 /* 1533 * Enable interrupts. 1534 */ 1535 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1536 1537 mii_mediachg(mii); 1538 1539 ifp->if_flags |= IFF_RUNNING; 1540 ifp->if_flags &= ~IFF_OACTIVE; 1541 1542 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1543 } 1544 1545 /* 1546 * Set media options. 1547 */ 1548 static int 1549 vr_ifmedia_upd(struct ifnet *ifp) 1550 { 1551 struct vr_softc *sc = ifp->if_softc; 1552 1553 if (ifp->if_flags & IFF_UP) 1554 vr_init(sc); 1555 1556 return (0); 1557 } 1558 1559 /* 1560 * Report current media status. 1561 */ 1562 static void 1563 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1564 { 1565 struct vr_softc *sc = ifp->if_softc; 1566 struct mii_data *mii; 1567 1568 mii = device_get_softc(sc->vr_miibus); 1569 VR_LOCK(sc); 1570 mii_pollstat(mii); 1571 VR_UNLOCK(sc); 1572 ifmr->ifm_active = mii->mii_media_active; 1573 ifmr->ifm_status = mii->mii_media_status; 1574 } 1575 1576 static int 1577 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1578 { 1579 struct vr_softc *sc = ifp->if_softc; 1580 struct ifreq *ifr = (struct ifreq *) data; 1581 struct mii_data *mii; 1582 int error = 0; 1583 1584 switch (command) { 1585 case SIOCSIFFLAGS: 1586 VR_LOCK(sc); 1587 if (ifp->if_flags & IFF_UP) { 1588 vr_init_locked(sc); 1589 } else { 1590 if (ifp->if_flags & IFF_RUNNING) 1591 vr_stop(sc); 1592 } 1593 VR_UNLOCK(sc); 1594 error = 0; 1595 break; 1596 case SIOCADDMULTI: 1597 case SIOCDELMULTI: 1598 VR_LOCK(sc); 1599 vr_setmulti(sc); 1600 VR_UNLOCK(sc); 1601 error = 0; 1602 break; 1603 case SIOCGIFMEDIA: 1604 case SIOCSIFMEDIA: 1605 mii = device_get_softc(sc->vr_miibus); 1606 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1607 break; 1608 case SIOCSIFCAP: 1609 ifp->if_capenable = ifr->ifr_reqcap; 1610 break; 1611 default: 1612 error = ether_ioctl(ifp, command, data); 1613 break; 1614 } 1615 1616 return (error); 1617 } 1618 1619 static void 1620 vr_watchdog(struct ifnet *ifp) 1621 { 1622 struct vr_softc *sc = ifp->if_softc; 1623 1624 VR_LOCK(sc); 1625 1626 ifp->if_oerrors++; 1627 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1628 1629 vr_stop(sc); 1630 vr_reset(sc); 1631 vr_init_locked(sc); 1632 1633 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1634 vr_start_locked(ifp); 1635 1636 VR_UNLOCK(sc); 1637 } 1638 1639 /* 1640 * Stop the adapter and free any mbufs allocated to the 1641 * RX and TX lists. 1642 */ 1643 static void 1644 vr_stop(struct vr_softc *sc) 1645 { 1646 register int i; 1647 struct ifnet *ifp; 1648 1649 VR_LOCK_ASSERT(sc); 1650 1651 ifp = &sc->arpcom.ac_if; 1652 ifp->if_timer = 0; 1653 1654 untimeout(vr_tick, sc, sc->vr_stat_ch); 1655 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1656 #ifdef DEVICE_POLLING 1657 ether_poll_deregister(ifp); 1658 #endif /* DEVICE_POLLING */ 1659 1660 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1661 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1662 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1663 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1664 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1665 1666 /* 1667 * Free data in the RX lists. 1668 */ 1669 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1670 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1671 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1672 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1673 } 1674 } 1675 bzero((char *)&sc->vr_ldata->vr_rx_list, 1676 sizeof(sc->vr_ldata->vr_rx_list)); 1677 1678 /* 1679 * Free the TX list buffers. 1680 */ 1681 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1682 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1683 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1684 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1685 } 1686 } 1687 bzero((char *)&sc->vr_ldata->vr_tx_list, 1688 sizeof(sc->vr_ldata->vr_tx_list)); 1689 } 1690 1691 /* 1692 * Stop all chip I/O so that the kernel's probe routines don't 1693 * get confused by errant DMAs when rebooting. 1694 */ 1695 static void 1696 vr_shutdown(device_t dev) 1697 { 1698 1699 vr_detach(dev); 1700 } 1701