1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <pci/pcireg.h> 91 #include <pci/pcivar.h> 92 93 #define VR_USEIOSPACE 94 95 #include <pci/if_vrreg.h> 96 97 MODULE_DEPEND(vr, miibus, 1, 1, 1); 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #ifndef lint 103 static const char rcsid[] = 104 "$FreeBSD$"; 105 #endif 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 118 "Delta Electronics Rhine II 10/100BaseTX" }, 119 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 120 "Addtron Technology Rhine II 10/100BaseTX" }, 121 { 0, 0, NULL } 122 }; 123 124 static int vr_probe __P((device_t)); 125 static int vr_attach __P((device_t)); 126 static int vr_detach __P((device_t)); 127 128 static int vr_newbuf __P((struct vr_softc *, 129 struct vr_chain_onefrag *, 130 struct mbuf *)); 131 static int vr_encap __P((struct vr_softc *, struct vr_chain *, 132 struct mbuf * )); 133 134 static void vr_rxeof __P((struct vr_softc *)); 135 static void vr_rxeoc __P((struct vr_softc *)); 136 static void vr_txeof __P((struct vr_softc *)); 137 static void vr_txeoc __P((struct vr_softc *)); 138 static void vr_tick __P((void *)); 139 static void vr_intr __P((void *)); 140 static void vr_start __P((struct ifnet *)); 141 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 142 static void vr_init __P((void *)); 143 static void vr_stop __P((struct vr_softc *)); 144 static void vr_watchdog __P((struct ifnet *)); 145 static void vr_shutdown __P((device_t)); 146 static int vr_ifmedia_upd __P((struct ifnet *)); 147 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 148 149 static void vr_mii_sync __P((struct vr_softc *)); 150 static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 151 static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 152 static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 153 static int vr_miibus_readreg __P((device_t, int, int)); 154 static int vr_miibus_writereg __P((device_t, int, int, int)); 155 static void vr_miibus_statchg __P((device_t)); 156 157 static void vr_setcfg __P((struct vr_softc *, int)); 158 static u_int8_t vr_calchash __P((u_int8_t *)); 159 static void vr_setmulti __P((struct vr_softc *)); 160 static void vr_reset __P((struct vr_softc *)); 161 static int vr_list_rx_init __P((struct vr_softc *)); 162 static int vr_list_tx_init __P((struct vr_softc *)); 163 164 #ifdef VR_USEIOSPACE 165 #define VR_RES SYS_RES_IOPORT 166 #define VR_RID VR_PCI_LOIO 167 #else 168 #define VR_RES SYS_RES_MEMORY 169 #define VR_RID VR_PCI_LOMEM 170 #endif 171 172 static device_method_t vr_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, vr_probe), 175 DEVMETHOD(device_attach, vr_attach), 176 DEVMETHOD(device_detach, vr_detach), 177 DEVMETHOD(device_shutdown, vr_shutdown), 178 179 /* bus interface */ 180 DEVMETHOD(bus_print_child, bus_generic_print_child), 181 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182 183 /* MII interface */ 184 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 185 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 186 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 187 188 { 0, 0 } 189 }; 190 191 static driver_t vr_driver = { 192 "vr", 193 vr_methods, 194 sizeof(struct vr_softc) 195 }; 196 197 static devclass_t vr_devclass; 198 199 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 200 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 201 202 #define VR_SETBIT(sc, reg, x) \ 203 CSR_WRITE_1(sc, reg, \ 204 CSR_READ_1(sc, reg) | x) 205 206 #define VR_CLRBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) & ~x) 209 210 #define VR_SETBIT16(sc, reg, x) \ 211 CSR_WRITE_2(sc, reg, \ 212 CSR_READ_2(sc, reg) | x) 213 214 #define VR_CLRBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) & ~x) 217 218 #define VR_SETBIT32(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, \ 220 CSR_READ_4(sc, reg) | x) 221 222 #define VR_CLRBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) & ~x) 225 226 #define SIO_SET(x) \ 227 CSR_WRITE_1(sc, VR_MIICMD, \ 228 CSR_READ_1(sc, VR_MIICMD) | x) 229 230 #define SIO_CLR(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) & ~x) 233 234 /* 235 * Sync the PHYs by setting data bit and strobing the clock 32 times. 236 */ 237 static void vr_mii_sync(sc) 238 struct vr_softc *sc; 239 { 240 register int i; 241 242 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 243 244 for (i = 0; i < 32; i++) { 245 SIO_SET(VR_MIICMD_CLK); 246 DELAY(1); 247 SIO_CLR(VR_MIICMD_CLK); 248 DELAY(1); 249 } 250 251 return; 252 } 253 254 /* 255 * Clock a series of bits through the MII. 256 */ 257 static void vr_mii_send(sc, bits, cnt) 258 struct vr_softc *sc; 259 u_int32_t bits; 260 int cnt; 261 { 262 int i; 263 264 SIO_CLR(VR_MIICMD_CLK); 265 266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 267 if (bits & i) { 268 SIO_SET(VR_MIICMD_DATAIN); 269 } else { 270 SIO_CLR(VR_MIICMD_DATAIN); 271 } 272 DELAY(1); 273 SIO_CLR(VR_MIICMD_CLK); 274 DELAY(1); 275 SIO_SET(VR_MIICMD_CLK); 276 } 277 } 278 279 /* 280 * Read an PHY register through the MII. 281 */ 282 static int vr_mii_readreg(sc, frame) 283 struct vr_softc *sc; 284 struct vr_mii_frame *frame; 285 286 { 287 int i, ack; 288 289 VR_LOCK(sc); 290 291 /* 292 * Set up frame for RX. 293 */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* 303 * Turn on data xmit. 304 */ 305 SIO_SET(VR_MIICMD_DIR); 306 307 vr_mii_sync(sc); 308 309 /* 310 * Send command/address info. 311 */ 312 vr_mii_send(sc, frame->mii_stdelim, 2); 313 vr_mii_send(sc, frame->mii_opcode, 2); 314 vr_mii_send(sc, frame->mii_phyaddr, 5); 315 vr_mii_send(sc, frame->mii_regaddr, 5); 316 317 /* Idle bit */ 318 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 319 DELAY(1); 320 SIO_SET(VR_MIICMD_CLK); 321 DELAY(1); 322 323 /* Turn off xmit. */ 324 SIO_CLR(VR_MIICMD_DIR); 325 326 /* Check for ack */ 327 SIO_CLR(VR_MIICMD_CLK); 328 DELAY(1); 329 SIO_SET(VR_MIICMD_CLK); 330 DELAY(1); 331 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 332 333 /* 334 * Now try reading data bits. If the ack failed, we still 335 * need to clock through 16 cycles to keep the PHY(s) in sync. 336 */ 337 if (ack) { 338 for(i = 0; i < 16; i++) { 339 SIO_CLR(VR_MIICMD_CLK); 340 DELAY(1); 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 } 344 goto fail; 345 } 346 347 for (i = 0x8000; i; i >>= 1) { 348 SIO_CLR(VR_MIICMD_CLK); 349 DELAY(1); 350 if (!ack) { 351 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 352 frame->mii_data |= i; 353 DELAY(1); 354 } 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 } 358 359 fail: 360 361 SIO_CLR(VR_MIICMD_CLK); 362 DELAY(1); 363 SIO_SET(VR_MIICMD_CLK); 364 DELAY(1); 365 366 VR_UNLOCK(sc); 367 368 if (ack) 369 return(1); 370 return(0); 371 } 372 373 /* 374 * Write to a PHY register through the MII. 375 */ 376 static int vr_mii_writereg(sc, frame) 377 struct vr_softc *sc; 378 struct vr_mii_frame *frame; 379 380 { 381 VR_LOCK(sc); 382 383 CSR_WRITE_1(sc, VR_MIICMD, 0); 384 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 385 386 /* 387 * Set up frame for TX. 388 */ 389 390 frame->mii_stdelim = VR_MII_STARTDELIM; 391 frame->mii_opcode = VR_MII_WRITEOP; 392 frame->mii_turnaround = VR_MII_TURNAROUND; 393 394 /* 395 * Turn on data output. 396 */ 397 SIO_SET(VR_MIICMD_DIR); 398 399 vr_mii_sync(sc); 400 401 vr_mii_send(sc, frame->mii_stdelim, 2); 402 vr_mii_send(sc, frame->mii_opcode, 2); 403 vr_mii_send(sc, frame->mii_phyaddr, 5); 404 vr_mii_send(sc, frame->mii_regaddr, 5); 405 vr_mii_send(sc, frame->mii_turnaround, 2); 406 vr_mii_send(sc, frame->mii_data, 16); 407 408 /* Idle bit. */ 409 SIO_SET(VR_MIICMD_CLK); 410 DELAY(1); 411 SIO_CLR(VR_MIICMD_CLK); 412 DELAY(1); 413 414 /* 415 * Turn off xmit. 416 */ 417 SIO_CLR(VR_MIICMD_DIR); 418 419 VR_UNLOCK(sc); 420 421 return(0); 422 } 423 424 static int vr_miibus_readreg(dev, phy, reg) 425 device_t dev; 426 int phy, reg; 427 { 428 struct vr_softc *sc; 429 struct vr_mii_frame frame; 430 431 sc = device_get_softc(dev); 432 bzero((char *)&frame, sizeof(frame)); 433 434 frame.mii_phyaddr = phy; 435 frame.mii_regaddr = reg; 436 vr_mii_readreg(sc, &frame); 437 438 return(frame.mii_data); 439 } 440 441 static int vr_miibus_writereg(dev, phy, reg, data) 442 device_t dev; 443 u_int16_t phy, reg, data; 444 { 445 struct vr_softc *sc; 446 struct vr_mii_frame frame; 447 448 sc = device_get_softc(dev); 449 bzero((char *)&frame, sizeof(frame)); 450 451 frame.mii_phyaddr = phy; 452 frame.mii_regaddr = reg; 453 frame.mii_data = data; 454 455 vr_mii_writereg(sc, &frame); 456 457 return(0); 458 } 459 460 static void vr_miibus_statchg(dev) 461 device_t dev; 462 { 463 struct vr_softc *sc; 464 struct mii_data *mii; 465 466 sc = device_get_softc(dev); 467 VR_LOCK(sc); 468 mii = device_get_softc(sc->vr_miibus); 469 vr_setcfg(sc, mii->mii_media_active); 470 VR_UNLOCK(sc); 471 472 return; 473 } 474 475 /* 476 * Calculate CRC of a multicast group address, return the lower 6 bits. 477 */ 478 static u_int8_t vr_calchash(addr) 479 u_int8_t *addr; 480 { 481 u_int32_t crc, carry; 482 int i, j; 483 u_int8_t c; 484 485 /* Compute CRC for the address value. */ 486 crc = 0xFFFFFFFF; /* initial value */ 487 488 for (i = 0; i < 6; i++) { 489 c = *(addr + i); 490 for (j = 0; j < 8; j++) { 491 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 492 crc <<= 1; 493 c >>= 1; 494 if (carry) 495 crc = (crc ^ 0x04c11db6) | carry; 496 } 497 } 498 499 /* return the filter bit position */ 500 return((crc >> 26) & 0x0000003F); 501 } 502 503 /* 504 * Program the 64-bit multicast hash filter. 505 */ 506 static void vr_setmulti(sc) 507 struct vr_softc *sc; 508 { 509 struct ifnet *ifp; 510 int h = 0; 511 u_int32_t hashes[2] = { 0, 0 }; 512 struct ifmultiaddr *ifma; 513 u_int8_t rxfilt; 514 int mcnt = 0; 515 516 ifp = &sc->arpcom.ac_if; 517 518 rxfilt = CSR_READ_1(sc, VR_RXCFG); 519 520 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 521 rxfilt |= VR_RXCFG_RX_MULTI; 522 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 523 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 524 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 525 return; 526 } 527 528 /* first, zot all the existing hash bits */ 529 CSR_WRITE_4(sc, VR_MAR0, 0); 530 CSR_WRITE_4(sc, VR_MAR1, 0); 531 532 /* now program new ones */ 533 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 534 if (ifma->ifma_addr->sa_family != AF_LINK) 535 continue; 536 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 537 if (h < 32) 538 hashes[0] |= (1 << h); 539 else 540 hashes[1] |= (1 << (h - 32)); 541 mcnt++; 542 } 543 544 if (mcnt) 545 rxfilt |= VR_RXCFG_RX_MULTI; 546 else 547 rxfilt &= ~VR_RXCFG_RX_MULTI; 548 549 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 550 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 551 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 552 553 return; 554 } 555 556 /* 557 * In order to fiddle with the 558 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 559 * first have to put the transmit and/or receive logic in the idle state. 560 */ 561 static void vr_setcfg(sc, media) 562 struct vr_softc *sc; 563 int media; 564 { 565 int restart = 0; 566 567 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 568 restart = 1; 569 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 570 } 571 572 if ((media & IFM_GMASK) == IFM_FDX) 573 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 574 else 575 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 577 if (restart) 578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 579 580 return; 581 } 582 583 static void vr_reset(sc) 584 struct vr_softc *sc; 585 { 586 register int i; 587 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 589 590 for (i = 0; i < VR_TIMEOUT; i++) { 591 DELAY(10); 592 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 593 break; 594 } 595 if (i == VR_TIMEOUT) 596 printf("vr%d: reset never completed!\n", sc->vr_unit); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600 601 return; 602 } 603 604 /* 605 * Probe for a VIA Rhine chip. Check the PCI vendor and device 606 * IDs against our list and return a device name if we find a match. 607 */ 608 static int vr_probe(dev) 609 device_t dev; 610 { 611 struct vr_type *t; 612 613 t = vr_devs; 614 615 while(t->vr_name != NULL) { 616 if ((pci_get_vendor(dev) == t->vr_vid) && 617 (pci_get_device(dev) == t->vr_did)) { 618 device_set_desc(dev, t->vr_name); 619 return(0); 620 } 621 t++; 622 } 623 624 return(ENXIO); 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 static int vr_attach(dev) 632 device_t dev; 633 { 634 int i; 635 u_char eaddr[ETHER_ADDR_LEN]; 636 u_int32_t command; 637 struct vr_softc *sc; 638 struct ifnet *ifp; 639 int unit, error = 0, rid; 640 641 sc = device_get_softc(dev); 642 unit = device_get_unit(dev); 643 bzero(sc, sizeof(struct vr_softc *)); 644 645 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 646 VR_LOCK(sc); 647 648 /* 649 * Handle power management nonsense. 650 */ 651 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 652 u_int32_t iobase, membase, irq; 653 654 /* Save important PCI config data. */ 655 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 656 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 657 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 658 659 /* Reset the power state. */ 660 printf("vr%d: chip is in D%d power mode " 661 "-- setting to D0\n", unit, 662 pci_get_powerstate(dev)); 663 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 664 665 /* Restore PCI config data. */ 666 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 667 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 668 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 669 } 670 671 /* 672 * Map control/status registers. 673 */ 674 pci_enable_busmaster(dev); 675 pci_enable_io(dev, SYS_RES_IOPORT); 676 pci_enable_io(dev, SYS_RES_MEMORY); 677 command = pci_read_config(dev, PCIR_COMMAND, 4); 678 679 #ifdef VR_USEIOSPACE 680 if (!(command & PCIM_CMD_PORTEN)) { 681 printf("vr%d: failed to enable I/O ports!\n", unit); 682 free(sc, M_DEVBUF); 683 goto fail; 684 } 685 #else 686 if (!(command & PCIM_CMD_MEMEN)) { 687 printf("vr%d: failed to enable memory mapping!\n", unit); 688 goto fail; 689 } 690 #endif 691 692 rid = VR_RID; 693 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 694 0, ~0, 1, RF_ACTIVE); 695 696 if (sc->vr_res == NULL) { 697 printf("vr%d: couldn't map ports/memory\n", unit); 698 error = ENXIO; 699 goto fail; 700 } 701 702 sc->vr_btag = rman_get_bustag(sc->vr_res); 703 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 704 705 /* Allocate interrupt */ 706 rid = 0; 707 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 708 RF_SHAREABLE | RF_ACTIVE); 709 710 if (sc->vr_irq == NULL) { 711 printf("vr%d: couldn't map interrupt\n", unit); 712 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 713 error = ENXIO; 714 goto fail; 715 } 716 717 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 718 vr_intr, sc, &sc->vr_intrhand); 719 720 if (error) { 721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 722 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 723 printf("vr%d: couldn't set up irq\n", unit); 724 goto fail; 725 } 726 727 /* 728 * Windows may put the chip in suspend mode when it 729 * shuts down. Be sure to kick it in the head to wake it 730 * up again. 731 */ 732 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 733 734 /* Reset the adapter. */ 735 vr_reset(sc); 736 737 /* 738 * Get station address. The way the Rhine chips work, 739 * you're not allowed to directly access the EEPROM once 740 * they've been programmed a special way. Consequently, 741 * we need to read the node address from the PAR0 and PAR1 742 * registers. 743 */ 744 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 745 DELAY(200); 746 for (i = 0; i < ETHER_ADDR_LEN; i++) 747 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 748 749 /* 750 * A Rhine chip was detected. Inform the world. 751 */ 752 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 753 754 sc->vr_unit = unit; 755 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 756 757 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 758 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 759 760 if (sc->vr_ldata == NULL) { 761 printf("vr%d: no memory for list buffers!\n", unit); 762 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 764 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 765 error = ENXIO; 766 goto fail; 767 } 768 769 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 770 771 ifp = &sc->arpcom.ac_if; 772 ifp->if_softc = sc; 773 ifp->if_unit = unit; 774 ifp->if_name = "vr"; 775 ifp->if_mtu = ETHERMTU; 776 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 777 ifp->if_ioctl = vr_ioctl; 778 ifp->if_output = ether_output; 779 ifp->if_start = vr_start; 780 ifp->if_watchdog = vr_watchdog; 781 ifp->if_init = vr_init; 782 ifp->if_baudrate = 10000000; 783 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 784 785 /* 786 * Do MII setup. 787 */ 788 if (mii_phy_probe(dev, &sc->vr_miibus, 789 vr_ifmedia_upd, vr_ifmedia_sts)) { 790 printf("vr%d: MII without any phy!\n", sc->vr_unit); 791 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 792 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 793 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 794 contigfree(sc->vr_ldata, 795 sizeof(struct vr_list_data), M_DEVBUF); 796 error = ENXIO; 797 goto fail; 798 } 799 800 callout_handle_init(&sc->vr_stat_ch); 801 802 /* 803 * Call MI attach routine. 804 */ 805 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 806 VR_UNLOCK(sc); 807 return(0); 808 809 fail: 810 VR_UNLOCK(sc); 811 mtx_destroy(&sc->vr_mtx); 812 813 return(error); 814 } 815 816 static int vr_detach(dev) 817 device_t dev; 818 { 819 struct vr_softc *sc; 820 struct ifnet *ifp; 821 822 sc = device_get_softc(dev); 823 VR_LOCK(sc); 824 ifp = &sc->arpcom.ac_if; 825 826 vr_stop(sc); 827 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 828 829 bus_generic_detach(dev); 830 device_delete_child(dev, sc->vr_miibus); 831 832 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 833 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 834 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 835 836 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 837 838 VR_UNLOCK(sc); 839 mtx_destroy(&sc->vr_mtx); 840 841 return(0); 842 } 843 844 /* 845 * Initialize the transmit descriptors. 846 */ 847 static int vr_list_tx_init(sc) 848 struct vr_softc *sc; 849 { 850 struct vr_chain_data *cd; 851 struct vr_list_data *ld; 852 int i; 853 854 cd = &sc->vr_cdata; 855 ld = sc->vr_ldata; 856 for (i = 0; i < VR_TX_LIST_CNT; i++) { 857 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 858 if (i == (VR_TX_LIST_CNT - 1)) 859 cd->vr_tx_chain[i].vr_nextdesc = 860 &cd->vr_tx_chain[0]; 861 else 862 cd->vr_tx_chain[i].vr_nextdesc = 863 &cd->vr_tx_chain[i + 1]; 864 } 865 866 cd->vr_tx_free = &cd->vr_tx_chain[0]; 867 cd->vr_tx_tail = cd->vr_tx_head = NULL; 868 869 return(0); 870 } 871 872 873 /* 874 * Initialize the RX descriptors and allocate mbufs for them. Note that 875 * we arrange the descriptors in a closed ring, so that the last descriptor 876 * points back to the first. 877 */ 878 static int vr_list_rx_init(sc) 879 struct vr_softc *sc; 880 { 881 struct vr_chain_data *cd; 882 struct vr_list_data *ld; 883 int i; 884 885 cd = &sc->vr_cdata; 886 ld = sc->vr_ldata; 887 888 for (i = 0; i < VR_RX_LIST_CNT; i++) { 889 cd->vr_rx_chain[i].vr_ptr = 890 (struct vr_desc *)&ld->vr_rx_list[i]; 891 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 892 return(ENOBUFS); 893 if (i == (VR_RX_LIST_CNT - 1)) { 894 cd->vr_rx_chain[i].vr_nextdesc = 895 &cd->vr_rx_chain[0]; 896 ld->vr_rx_list[i].vr_next = 897 vtophys(&ld->vr_rx_list[0]); 898 } else { 899 cd->vr_rx_chain[i].vr_nextdesc = 900 &cd->vr_rx_chain[i + 1]; 901 ld->vr_rx_list[i].vr_next = 902 vtophys(&ld->vr_rx_list[i + 1]); 903 } 904 } 905 906 cd->vr_rx_head = &cd->vr_rx_chain[0]; 907 908 return(0); 909 } 910 911 /* 912 * Initialize an RX descriptor and attach an MBUF cluster. 913 * Note: the length fields are only 11 bits wide, which means the 914 * largest size we can specify is 2047. This is important because 915 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 916 * overflow the field and make a mess. 917 */ 918 static int vr_newbuf(sc, c, m) 919 struct vr_softc *sc; 920 struct vr_chain_onefrag *c; 921 struct mbuf *m; 922 { 923 struct mbuf *m_new = NULL; 924 925 if (m == NULL) { 926 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 927 if (m_new == NULL) 928 return(ENOBUFS); 929 930 MCLGET(m_new, M_DONTWAIT); 931 if (!(m_new->m_flags & M_EXT)) { 932 m_freem(m_new); 933 return(ENOBUFS); 934 } 935 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 936 } else { 937 m_new = m; 938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 939 m_new->m_data = m_new->m_ext.ext_buf; 940 } 941 942 m_adj(m_new, sizeof(u_int64_t)); 943 944 c->vr_mbuf = m_new; 945 c->vr_ptr->vr_status = VR_RXSTAT; 946 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 947 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 948 949 return(0); 950 } 951 952 /* 953 * A frame has been uploaded: pass the resulting mbuf chain up to 954 * the higher level protocols. 955 */ 956 static void vr_rxeof(sc) 957 struct vr_softc *sc; 958 { 959 struct ether_header *eh; 960 struct mbuf *m; 961 struct ifnet *ifp; 962 struct vr_chain_onefrag *cur_rx; 963 int total_len = 0; 964 u_int32_t rxstat; 965 966 ifp = &sc->arpcom.ac_if; 967 968 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 969 VR_RXSTAT_OWN)) { 970 struct mbuf *m0 = NULL; 971 972 cur_rx = sc->vr_cdata.vr_rx_head; 973 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 974 m = cur_rx->vr_mbuf; 975 976 /* 977 * If an error occurs, update stats, clear the 978 * status word and leave the mbuf cluster in place: 979 * it should simply get re-used next time this descriptor 980 * comes up in the ring. 981 */ 982 if (rxstat & VR_RXSTAT_RXERR) { 983 ifp->if_ierrors++; 984 printf("vr%d: rx error: ", sc->vr_unit); 985 switch(rxstat & 0x000000FF) { 986 case VR_RXSTAT_CRCERR: 987 printf("crc error\n"); 988 break; 989 case VR_RXSTAT_FRAMEALIGNERR: 990 printf("frame alignment error\n"); 991 break; 992 case VR_RXSTAT_FIFOOFLOW: 993 printf("FIFO overflow\n"); 994 break; 995 case VR_RXSTAT_GIANT: 996 printf("received giant packet\n"); 997 break; 998 case VR_RXSTAT_RUNT: 999 printf("received runt packet\n"); 1000 break; 1001 case VR_RXSTAT_BUSERR: 1002 printf("system bus error\n"); 1003 break; 1004 case VR_RXSTAT_BUFFERR: 1005 printf("rx buffer error\n"); 1006 break; 1007 default: 1008 printf("unknown rx error\n"); 1009 break; 1010 } 1011 vr_newbuf(sc, cur_rx, m); 1012 continue; 1013 } 1014 1015 /* No errors; receive the packet. */ 1016 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1017 1018 /* 1019 * XXX The VIA Rhine chip includes the CRC with every 1020 * received frame, and there's no way to turn this 1021 * behavior off (at least, I can't find anything in 1022 * the manual that explains how to do it) so we have 1023 * to trim off the CRC manually. 1024 */ 1025 total_len -= ETHER_CRC_LEN; 1026 1027 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1028 NULL); 1029 vr_newbuf(sc, cur_rx, m); 1030 if (m0 == NULL) { 1031 ifp->if_ierrors++; 1032 continue; 1033 } 1034 m = m0; 1035 1036 ifp->if_ipackets++; 1037 eh = mtod(m, struct ether_header *); 1038 1039 /* Remove header from mbuf and pass it on. */ 1040 m_adj(m, sizeof(struct ether_header)); 1041 ether_input(ifp, eh, m); 1042 } 1043 1044 return; 1045 } 1046 1047 void vr_rxeoc(sc) 1048 struct vr_softc *sc; 1049 { 1050 1051 vr_rxeof(sc); 1052 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1053 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1056 1057 return; 1058 } 1059 1060 /* 1061 * A frame was downloaded to the chip. It's safe for us to clean up 1062 * the list buffers. 1063 */ 1064 1065 static void vr_txeof(sc) 1066 struct vr_softc *sc; 1067 { 1068 struct vr_chain *cur_tx; 1069 struct ifnet *ifp; 1070 1071 ifp = &sc->arpcom.ac_if; 1072 1073 /* Clear the timeout timer. */ 1074 ifp->if_timer = 0; 1075 1076 /* Sanity check. */ 1077 if (sc->vr_cdata.vr_tx_head == NULL) 1078 return; 1079 1080 /* 1081 * Go through our tx list and free mbufs for those 1082 * frames that have been transmitted. 1083 */ 1084 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1085 u_int32_t txstat; 1086 1087 cur_tx = sc->vr_cdata.vr_tx_head; 1088 txstat = cur_tx->vr_ptr->vr_status; 1089 1090 if (txstat & VR_TXSTAT_OWN) 1091 break; 1092 1093 if (txstat & VR_TXSTAT_ERRSUM) { 1094 ifp->if_oerrors++; 1095 if (txstat & VR_TXSTAT_DEFER) 1096 ifp->if_collisions++; 1097 if (txstat & VR_TXSTAT_LATECOLL) 1098 ifp->if_collisions++; 1099 } 1100 1101 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1102 1103 ifp->if_opackets++; 1104 if (cur_tx->vr_mbuf != NULL) { 1105 m_freem(cur_tx->vr_mbuf); 1106 cur_tx->vr_mbuf = NULL; 1107 } 1108 1109 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1110 sc->vr_cdata.vr_tx_head = NULL; 1111 sc->vr_cdata.vr_tx_tail = NULL; 1112 break; 1113 } 1114 1115 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1116 } 1117 1118 return; 1119 } 1120 1121 /* 1122 * TX 'end of channel' interrupt handler. 1123 */ 1124 static void vr_txeoc(sc) 1125 struct vr_softc *sc; 1126 { 1127 struct ifnet *ifp; 1128 1129 ifp = &sc->arpcom.ac_if; 1130 1131 ifp->if_timer = 0; 1132 1133 if (sc->vr_cdata.vr_tx_head == NULL) { 1134 ifp->if_flags &= ~IFF_OACTIVE; 1135 sc->vr_cdata.vr_tx_tail = NULL; 1136 } 1137 1138 return; 1139 } 1140 1141 static void vr_tick(xsc) 1142 void *xsc; 1143 { 1144 struct vr_softc *sc; 1145 struct mii_data *mii; 1146 1147 sc = xsc; 1148 VR_LOCK(sc); 1149 mii = device_get_softc(sc->vr_miibus); 1150 mii_tick(mii); 1151 1152 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1153 1154 VR_UNLOCK(sc); 1155 1156 return; 1157 } 1158 1159 static void vr_intr(arg) 1160 void *arg; 1161 { 1162 struct vr_softc *sc; 1163 struct ifnet *ifp; 1164 u_int16_t status; 1165 1166 sc = arg; 1167 VR_LOCK(sc); 1168 ifp = &sc->arpcom.ac_if; 1169 1170 /* Supress unwanted interrupts. */ 1171 if (!(ifp->if_flags & IFF_UP)) { 1172 vr_stop(sc); 1173 VR_UNLOCK(sc); 1174 return; 1175 } 1176 1177 /* Disable interrupts. */ 1178 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1179 1180 for (;;) { 1181 1182 status = CSR_READ_2(sc, VR_ISR); 1183 if (status) 1184 CSR_WRITE_2(sc, VR_ISR, status); 1185 1186 if ((status & VR_INTRS) == 0) 1187 break; 1188 1189 if (status & VR_ISR_RX_OK) 1190 vr_rxeof(sc); 1191 1192 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1193 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1194 (status & VR_ISR_RX_DROPPED)) { 1195 vr_rxeof(sc); 1196 vr_rxeoc(sc); 1197 } 1198 1199 if (status & VR_ISR_TX_OK) { 1200 vr_txeof(sc); 1201 vr_txeoc(sc); 1202 } 1203 1204 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1205 ifp->if_oerrors++; 1206 vr_txeof(sc); 1207 if (sc->vr_cdata.vr_tx_head != NULL) { 1208 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1209 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1210 } 1211 } 1212 1213 if (status & VR_ISR_BUSERR) { 1214 vr_reset(sc); 1215 vr_init(sc); 1216 } 1217 } 1218 1219 /* Re-enable interrupts. */ 1220 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1221 1222 if (ifp->if_snd.ifq_head != NULL) { 1223 vr_start(ifp); 1224 } 1225 1226 VR_UNLOCK(sc); 1227 1228 return; 1229 } 1230 1231 /* 1232 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1233 * pointers to the fragment pointers. 1234 */ 1235 static int vr_encap(sc, c, m_head) 1236 struct vr_softc *sc; 1237 struct vr_chain *c; 1238 struct mbuf *m_head; 1239 { 1240 int frag = 0; 1241 struct vr_desc *f = NULL; 1242 int total_len; 1243 struct mbuf *m; 1244 1245 m = m_head; 1246 total_len = 0; 1247 1248 /* 1249 * The VIA Rhine wants packet buffers to be longword 1250 * aligned, but very often our mbufs aren't. Rather than 1251 * waste time trying to decide when to copy and when not 1252 * to copy, just do it all the time. 1253 */ 1254 if (m != NULL) { 1255 struct mbuf *m_new = NULL; 1256 1257 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1258 if (m_new == NULL) { 1259 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1260 return(1); 1261 } 1262 if (m_head->m_pkthdr.len > MHLEN) { 1263 MCLGET(m_new, M_DONTWAIT); 1264 if (!(m_new->m_flags & M_EXT)) { 1265 m_freem(m_new); 1266 printf("vr%d: no memory for tx list\n", 1267 sc->vr_unit); 1268 return(1); 1269 } 1270 } 1271 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1272 mtod(m_new, caddr_t)); 1273 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1274 m_freem(m_head); 1275 m_head = m_new; 1276 /* 1277 * The Rhine chip doesn't auto-pad, so we have to make 1278 * sure to pad short frames out to the minimum frame length 1279 * ourselves. 1280 */ 1281 if (m_head->m_len < VR_MIN_FRAMELEN) { 1282 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1283 m_new->m_len = m_new->m_pkthdr.len; 1284 } 1285 f = c->vr_ptr; 1286 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1287 f->vr_ctl = total_len = m_new->m_len; 1288 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1289 f->vr_status = 0; 1290 frag = 1; 1291 } 1292 1293 c->vr_mbuf = m_head; 1294 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1295 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1296 1297 return(0); 1298 } 1299 1300 /* 1301 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1302 * to the mbuf data regions directly in the transmit lists. We also save a 1303 * copy of the pointers since the transmit list fragment pointers are 1304 * physical addresses. 1305 */ 1306 1307 static void vr_start(ifp) 1308 struct ifnet *ifp; 1309 { 1310 struct vr_softc *sc; 1311 struct mbuf *m_head = NULL; 1312 struct vr_chain *cur_tx = NULL, *start_tx; 1313 1314 sc = ifp->if_softc; 1315 1316 VR_LOCK(sc); 1317 if (ifp->if_flags & IFF_OACTIVE) { 1318 VR_UNLOCK(sc); 1319 return; 1320 } 1321 1322 /* 1323 * Check for an available queue slot. If there are none, 1324 * punt. 1325 */ 1326 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1327 ifp->if_flags |= IFF_OACTIVE; 1328 return; 1329 } 1330 1331 start_tx = sc->vr_cdata.vr_tx_free; 1332 1333 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1334 IF_DEQUEUE(&ifp->if_snd, m_head); 1335 if (m_head == NULL) 1336 break; 1337 1338 /* Pick a descriptor off the free list. */ 1339 cur_tx = sc->vr_cdata.vr_tx_free; 1340 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1341 1342 /* Pack the data into the descriptor. */ 1343 if (vr_encap(sc, cur_tx, m_head)) { 1344 IF_PREPEND(&ifp->if_snd, m_head); 1345 ifp->if_flags |= IFF_OACTIVE; 1346 cur_tx = NULL; 1347 break; 1348 } 1349 1350 if (cur_tx != start_tx) 1351 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1352 1353 /* 1354 * If there's a BPF listener, bounce a copy of this frame 1355 * to him. 1356 */ 1357 if (ifp->if_bpf) 1358 bpf_mtap(ifp, cur_tx->vr_mbuf); 1359 1360 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1361 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1362 } 1363 1364 /* 1365 * If there are no frames queued, bail. 1366 */ 1367 if (cur_tx == NULL) { 1368 VR_UNLOCK(sc); 1369 return; 1370 } 1371 1372 sc->vr_cdata.vr_tx_tail = cur_tx; 1373 1374 if (sc->vr_cdata.vr_tx_head == NULL) 1375 sc->vr_cdata.vr_tx_head = start_tx; 1376 1377 /* 1378 * Set a timeout in case the chip goes out to lunch. 1379 */ 1380 ifp->if_timer = 5; 1381 VR_UNLOCK(sc); 1382 1383 return; 1384 } 1385 1386 static void vr_init(xsc) 1387 void *xsc; 1388 { 1389 struct vr_softc *sc = xsc; 1390 struct ifnet *ifp = &sc->arpcom.ac_if; 1391 struct mii_data *mii; 1392 int i; 1393 1394 VR_LOCK(sc); 1395 1396 mii = device_get_softc(sc->vr_miibus); 1397 1398 /* 1399 * Cancel pending I/O and free all RX/TX buffers. 1400 */ 1401 vr_stop(sc); 1402 vr_reset(sc); 1403 1404 /* 1405 * Set our station address. 1406 */ 1407 for (i = 0; i < ETHER_ADDR_LEN; i++) 1408 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1409 1410 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1411 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1412 1413 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1414 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1415 1416 /* Init circular RX list. */ 1417 if (vr_list_rx_init(sc) == ENOBUFS) { 1418 printf("vr%d: initialization failed: no " 1419 "memory for rx buffers\n", sc->vr_unit); 1420 vr_stop(sc); 1421 VR_UNLOCK(sc); 1422 return; 1423 } 1424 1425 /* 1426 * Init tx descriptors. 1427 */ 1428 vr_list_tx_init(sc); 1429 1430 /* If we want promiscuous mode, set the allframes bit. */ 1431 if (ifp->if_flags & IFF_PROMISC) 1432 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1433 else 1434 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1435 1436 /* Set capture broadcast bit to capture broadcast frames. */ 1437 if (ifp->if_flags & IFF_BROADCAST) 1438 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1439 else 1440 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1441 1442 /* 1443 * Program the multicast filter, if necessary. 1444 */ 1445 vr_setmulti(sc); 1446 1447 /* 1448 * Load the address of the RX list. 1449 */ 1450 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1451 1452 /* Enable receiver and transmitter. */ 1453 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1454 VR_CMD_TX_ON|VR_CMD_RX_ON| 1455 VR_CMD_RX_GO); 1456 1457 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1458 1459 /* 1460 * Enable interrupts. 1461 */ 1462 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1463 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1464 1465 mii_mediachg(mii); 1466 1467 ifp->if_flags |= IFF_RUNNING; 1468 ifp->if_flags &= ~IFF_OACTIVE; 1469 1470 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1471 1472 VR_UNLOCK(sc); 1473 1474 return; 1475 } 1476 1477 /* 1478 * Set media options. 1479 */ 1480 static int vr_ifmedia_upd(ifp) 1481 struct ifnet *ifp; 1482 { 1483 struct vr_softc *sc; 1484 1485 sc = ifp->if_softc; 1486 1487 if (ifp->if_flags & IFF_UP) 1488 vr_init(sc); 1489 1490 return(0); 1491 } 1492 1493 /* 1494 * Report current media status. 1495 */ 1496 static void vr_ifmedia_sts(ifp, ifmr) 1497 struct ifnet *ifp; 1498 struct ifmediareq *ifmr; 1499 { 1500 struct vr_softc *sc; 1501 struct mii_data *mii; 1502 1503 sc = ifp->if_softc; 1504 mii = device_get_softc(sc->vr_miibus); 1505 mii_pollstat(mii); 1506 ifmr->ifm_active = mii->mii_media_active; 1507 ifmr->ifm_status = mii->mii_media_status; 1508 1509 return; 1510 } 1511 1512 static int vr_ioctl(ifp, command, data) 1513 struct ifnet *ifp; 1514 u_long command; 1515 caddr_t data; 1516 { 1517 struct vr_softc *sc = ifp->if_softc; 1518 struct ifreq *ifr = (struct ifreq *) data; 1519 struct mii_data *mii; 1520 int error = 0; 1521 1522 VR_LOCK(sc); 1523 1524 switch(command) { 1525 case SIOCSIFADDR: 1526 case SIOCGIFADDR: 1527 case SIOCSIFMTU: 1528 error = ether_ioctl(ifp, command, data); 1529 break; 1530 case SIOCSIFFLAGS: 1531 if (ifp->if_flags & IFF_UP) { 1532 vr_init(sc); 1533 } else { 1534 if (ifp->if_flags & IFF_RUNNING) 1535 vr_stop(sc); 1536 } 1537 error = 0; 1538 break; 1539 case SIOCADDMULTI: 1540 case SIOCDELMULTI: 1541 vr_setmulti(sc); 1542 error = 0; 1543 break; 1544 case SIOCGIFMEDIA: 1545 case SIOCSIFMEDIA: 1546 mii = device_get_softc(sc->vr_miibus); 1547 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1548 break; 1549 default: 1550 error = EINVAL; 1551 break; 1552 } 1553 1554 VR_UNLOCK(sc); 1555 1556 return(error); 1557 } 1558 1559 static void vr_watchdog(ifp) 1560 struct ifnet *ifp; 1561 { 1562 struct vr_softc *sc; 1563 1564 sc = ifp->if_softc; 1565 1566 VR_LOCK(sc); 1567 ifp->if_oerrors++; 1568 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1569 1570 vr_stop(sc); 1571 vr_reset(sc); 1572 vr_init(sc); 1573 1574 if (ifp->if_snd.ifq_head != NULL) 1575 vr_start(ifp); 1576 1577 VR_UNLOCK(sc); 1578 1579 return; 1580 } 1581 1582 /* 1583 * Stop the adapter and free any mbufs allocated to the 1584 * RX and TX lists. 1585 */ 1586 static void vr_stop(sc) 1587 struct vr_softc *sc; 1588 { 1589 register int i; 1590 struct ifnet *ifp; 1591 1592 VR_LOCK(sc); 1593 1594 ifp = &sc->arpcom.ac_if; 1595 ifp->if_timer = 0; 1596 1597 untimeout(vr_tick, sc, sc->vr_stat_ch); 1598 1599 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1600 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1601 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1602 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1603 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1604 1605 /* 1606 * Free data in the RX lists. 1607 */ 1608 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1609 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1610 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1611 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1612 } 1613 } 1614 bzero((char *)&sc->vr_ldata->vr_rx_list, 1615 sizeof(sc->vr_ldata->vr_rx_list)); 1616 1617 /* 1618 * Free the TX list buffers. 1619 */ 1620 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1621 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1622 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1623 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1624 } 1625 } 1626 1627 bzero((char *)&sc->vr_ldata->vr_tx_list, 1628 sizeof(sc->vr_ldata->vr_tx_list)); 1629 1630 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1631 VR_UNLOCK(sc); 1632 1633 return; 1634 } 1635 1636 /* 1637 * Stop all chip I/O so that the kernel's probe routines don't 1638 * get confused by errant DMAs when rebooting. 1639 */ 1640 static void vr_shutdown(dev) 1641 device_t dev; 1642 { 1643 struct vr_softc *sc; 1644 1645 sc = device_get_softc(dev); 1646 1647 vr_stop(sc); 1648 1649 return; 1650 } 1651