1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/module.h> 69 #include <sys/socket.h> 70 71 #include <net/if.h> 72 #include <net/if_arp.h> 73 #include <net/ethernet.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 77 #include <net/bpf.h> 78 79 #include <vm/vm.h> /* for vtophys */ 80 #include <vm/pmap.h> /* for vtophys */ 81 #include <machine/bus_pio.h> 82 #include <machine/bus_memio.h> 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/bus.h> 86 #include <sys/rman.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 94 #define VR_USEIOSPACE 95 96 #include <pci/if_vrreg.h> 97 98 MODULE_DEPEND(vr, pci, 1, 1, 1); 99 MODULE_DEPEND(vr, ether, 1, 1, 1); 100 MODULE_DEPEND(vr, miibus, 1, 1, 1); 101 102 /* "controller miibus0" required. See GENERIC if you get errors here. */ 103 #include "miibus_if.h" 104 105 #undef VR_USESWSHIFT 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 118 "VIA VT6105 Rhine III 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 120 "VIA VT6105M Rhine III 10/100BaseTX" }, 121 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 122 "Delta Electronics Rhine II 10/100BaseTX" }, 123 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 124 "Addtron Technology Rhine II 10/100BaseTX" }, 125 { 0, 0, NULL } 126 }; 127 128 static int vr_probe (device_t); 129 static int vr_attach (device_t); 130 static int vr_detach (device_t); 131 132 static int vr_newbuf (struct vr_softc *, 133 struct vr_chain_onefrag *, 134 struct mbuf *); 135 static int vr_encap (struct vr_softc *, struct vr_chain *, 136 struct mbuf * ); 137 138 static void vr_rxeof (struct vr_softc *); 139 static void vr_rxeoc (struct vr_softc *); 140 static void vr_txeof (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 145 static void vr_init (void *); 146 static void vr_stop (struct vr_softc *); 147 static void vr_watchdog (struct ifnet *); 148 static void vr_shutdown (device_t); 149 static int vr_ifmedia_upd (struct ifnet *); 150 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152 #ifdef VR_USESWSHIFT 153 static void vr_mii_sync (struct vr_softc *); 154 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 155 #endif 156 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 157 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_miibus_readreg (device_t, int, int); 159 static int vr_miibus_writereg (device_t, int, int, int); 160 static void vr_miibus_statchg (device_t); 161 162 static void vr_setcfg (struct vr_softc *, int); 163 static void vr_setmulti (struct vr_softc *); 164 static void vr_reset (struct vr_softc *); 165 static int vr_list_rx_init (struct vr_softc *); 166 static int vr_list_tx_init (struct vr_softc *); 167 168 #ifdef VR_USEIOSPACE 169 #define VR_RES SYS_RES_IOPORT 170 #define VR_RID VR_PCI_LOIO 171 #else 172 #define VR_RES SYS_RES_MEMORY 173 #define VR_RID VR_PCI_LOMEM 174 #endif 175 176 static device_method_t vr_methods[] = { 177 /* Device interface */ 178 DEVMETHOD(device_probe, vr_probe), 179 DEVMETHOD(device_attach, vr_attach), 180 DEVMETHOD(device_detach, vr_detach), 181 DEVMETHOD(device_shutdown, vr_shutdown), 182 183 /* bus interface */ 184 DEVMETHOD(bus_print_child, bus_generic_print_child), 185 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 186 187 /* MII interface */ 188 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 189 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 190 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 191 192 { 0, 0 } 193 }; 194 195 static driver_t vr_driver = { 196 "vr", 197 vr_methods, 198 sizeof(struct vr_softc) 199 }; 200 201 static devclass_t vr_devclass; 202 203 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 204 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 205 206 #define VR_SETBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) | (x)) 209 210 #define VR_CLRBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) & ~(x)) 213 214 #define VR_SETBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) | (x)) 217 218 #define VR_CLRBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) & ~(x)) 221 222 #define VR_SETBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) | (x)) 225 226 #define VR_CLRBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) & ~(x)) 229 230 #define SIO_SET(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) | (x)) 233 234 #define SIO_CLR(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 237 238 #ifdef VR_USESWSHIFT 239 /* 240 * Sync the PHYs by setting data bit and strobing the clock 32 times. 241 */ 242 static void 243 vr_mii_sync(sc) 244 struct vr_softc *sc; 245 { 246 register int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 257 return; 258 } 259 260 /* 261 * Clock a series of bits through the MII. 262 */ 263 static void 264 vr_mii_send(sc, bits, cnt) 265 struct vr_softc *sc; 266 u_int32_t bits; 267 int cnt; 268 { 269 int i; 270 271 SIO_CLR(VR_MIICMD_CLK); 272 273 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 274 if (bits & i) { 275 SIO_SET(VR_MIICMD_DATAIN); 276 } else { 277 SIO_CLR(VR_MIICMD_DATAIN); 278 } 279 DELAY(1); 280 SIO_CLR(VR_MIICMD_CLK); 281 DELAY(1); 282 SIO_SET(VR_MIICMD_CLK); 283 } 284 } 285 #endif 286 287 /* 288 * Read an PHY register through the MII. 289 */ 290 static int 291 vr_mii_readreg(sc, frame) 292 struct vr_softc *sc; 293 struct vr_mii_frame *frame; 294 295 #ifdef VR_USESWSHIFT 296 { 297 int i, ack; 298 299 VR_LOCK(sc); 300 301 /* 302 * Set up frame for RX. 303 */ 304 frame->mii_stdelim = VR_MII_STARTDELIM; 305 frame->mii_opcode = VR_MII_READOP; 306 frame->mii_turnaround = 0; 307 frame->mii_data = 0; 308 309 CSR_WRITE_1(sc, VR_MIICMD, 0); 310 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 311 312 /* 313 * Turn on data xmit. 314 */ 315 SIO_SET(VR_MIICMD_DIR); 316 317 vr_mii_sync(sc); 318 319 /* 320 * Send command/address info. 321 */ 322 vr_mii_send(sc, frame->mii_stdelim, 2); 323 vr_mii_send(sc, frame->mii_opcode, 2); 324 vr_mii_send(sc, frame->mii_phyaddr, 5); 325 vr_mii_send(sc, frame->mii_regaddr, 5); 326 327 /* Idle bit */ 328 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 329 DELAY(1); 330 SIO_SET(VR_MIICMD_CLK); 331 DELAY(1); 332 333 /* Turn off xmit. */ 334 SIO_CLR(VR_MIICMD_DIR); 335 336 /* Check for ack */ 337 SIO_CLR(VR_MIICMD_CLK); 338 DELAY(1); 339 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 343 /* 344 * Now try reading data bits. If the ack failed, we still 345 * need to clock through 16 cycles to keep the PHY(s) in sync. 346 */ 347 if (ack) { 348 for(i = 0; i < 16; i++) { 349 SIO_CLR(VR_MIICMD_CLK); 350 DELAY(1); 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 goto fail; 355 } 356 357 for (i = 0x8000; i; i >>= 1) { 358 SIO_CLR(VR_MIICMD_CLK); 359 DELAY(1); 360 if (!ack) { 361 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 362 frame->mii_data |= i; 363 DELAY(1); 364 } 365 SIO_SET(VR_MIICMD_CLK); 366 DELAY(1); 367 } 368 369 fail: 370 371 SIO_CLR(VR_MIICMD_CLK); 372 DELAY(1); 373 SIO_SET(VR_MIICMD_CLK); 374 DELAY(1); 375 376 VR_UNLOCK(sc); 377 378 if (ack) 379 return(1); 380 return(0); 381 } 382 #else 383 { 384 int s, i; 385 386 s = splimp(); 387 388 /* Set the PHY-adress */ 389 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 390 frame->mii_phyaddr); 391 392 /* Set the register-adress */ 393 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 394 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 395 396 for (i = 0; i < 10000; i++) { 397 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 398 break; 399 DELAY(1); 400 } 401 402 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 403 404 (void)splx(s); 405 406 return(0); 407 } 408 #endif 409 410 411 /* 412 * Write to a PHY register through the MII. 413 */ 414 static int 415 vr_mii_writereg(sc, frame) 416 struct vr_softc *sc; 417 struct vr_mii_frame *frame; 418 419 #ifdef VR_USESWSHIFT 420 { 421 VR_LOCK(sc); 422 423 CSR_WRITE_1(sc, VR_MIICMD, 0); 424 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 425 426 /* 427 * Set up frame for TX. 428 */ 429 430 frame->mii_stdelim = VR_MII_STARTDELIM; 431 frame->mii_opcode = VR_MII_WRITEOP; 432 frame->mii_turnaround = VR_MII_TURNAROUND; 433 434 /* 435 * Turn on data output. 436 */ 437 SIO_SET(VR_MIICMD_DIR); 438 439 vr_mii_sync(sc); 440 441 vr_mii_send(sc, frame->mii_stdelim, 2); 442 vr_mii_send(sc, frame->mii_opcode, 2); 443 vr_mii_send(sc, frame->mii_phyaddr, 5); 444 vr_mii_send(sc, frame->mii_regaddr, 5); 445 vr_mii_send(sc, frame->mii_turnaround, 2); 446 vr_mii_send(sc, frame->mii_data, 16); 447 448 /* Idle bit. */ 449 SIO_SET(VR_MIICMD_CLK); 450 DELAY(1); 451 SIO_CLR(VR_MIICMD_CLK); 452 DELAY(1); 453 454 /* 455 * Turn off xmit. 456 */ 457 SIO_CLR(VR_MIICMD_DIR); 458 459 VR_UNLOCK(sc); 460 461 return(0); 462 } 463 #else 464 { 465 int s, i; 466 467 s = splimp(); 468 469 /* Set the PHY-adress */ 470 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 471 frame->mii_phyaddr); 472 473 /* Set the register-adress and data to write */ 474 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 475 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 476 477 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 478 479 for (i = 0; i < 10000; i++) { 480 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 481 break; 482 DELAY(1); 483 } 484 485 (void)splx(s); 486 487 return(0); 488 } 489 #endif 490 491 static int 492 vr_miibus_readreg(dev, phy, reg) 493 device_t dev; 494 int phy, reg; 495 { 496 struct vr_softc *sc; 497 struct vr_mii_frame frame; 498 499 sc = device_get_softc(dev); 500 501 switch (sc->vr_revid) { 502 case REV_ID_VT6102_APOLLO: 503 if (phy != 1) 504 return 0; 505 default: 506 break; 507 } 508 509 bzero((char *)&frame, sizeof(frame)); 510 511 frame.mii_phyaddr = phy; 512 frame.mii_regaddr = reg; 513 vr_mii_readreg(sc, &frame); 514 515 return(frame.mii_data); 516 } 517 518 static int 519 vr_miibus_writereg(dev, phy, reg, data) 520 device_t dev; 521 u_int16_t phy, reg, data; 522 { 523 struct vr_softc *sc; 524 struct vr_mii_frame frame; 525 526 sc = device_get_softc(dev); 527 528 switch (sc->vr_revid) { 529 case REV_ID_VT6102_APOLLO: 530 if (phy != 1) 531 return 0; 532 default: 533 break; 534 } 535 536 bzero((char *)&frame, sizeof(frame)); 537 538 frame.mii_phyaddr = phy; 539 frame.mii_regaddr = reg; 540 frame.mii_data = data; 541 542 vr_mii_writereg(sc, &frame); 543 544 return(0); 545 } 546 547 static void 548 vr_miibus_statchg(dev) 549 device_t dev; 550 { 551 struct vr_softc *sc; 552 struct mii_data *mii; 553 554 sc = device_get_softc(dev); 555 VR_LOCK(sc); 556 mii = device_get_softc(sc->vr_miibus); 557 vr_setcfg(sc, mii->mii_media_active); 558 VR_UNLOCK(sc); 559 560 return; 561 } 562 563 /* 564 * Program the 64-bit multicast hash filter. 565 */ 566 static void 567 vr_setmulti(sc) 568 struct vr_softc *sc; 569 { 570 struct ifnet *ifp; 571 int h = 0; 572 u_int32_t hashes[2] = { 0, 0 }; 573 struct ifmultiaddr *ifma; 574 u_int8_t rxfilt; 575 int mcnt = 0; 576 577 ifp = &sc->arpcom.ac_if; 578 579 rxfilt = CSR_READ_1(sc, VR_RXCFG); 580 581 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 582 rxfilt |= VR_RXCFG_RX_MULTI; 583 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 584 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 585 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 586 return; 587 } 588 589 /* first, zot all the existing hash bits */ 590 CSR_WRITE_4(sc, VR_MAR0, 0); 591 CSR_WRITE_4(sc, VR_MAR1, 0); 592 593 /* now program new ones */ 594 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 595 if (ifma->ifma_addr->sa_family != AF_LINK) 596 continue; 597 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 598 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 599 if (h < 32) 600 hashes[0] |= (1 << h); 601 else 602 hashes[1] |= (1 << (h - 32)); 603 mcnt++; 604 } 605 606 if (mcnt) 607 rxfilt |= VR_RXCFG_RX_MULTI; 608 else 609 rxfilt &= ~VR_RXCFG_RX_MULTI; 610 611 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 612 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 613 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 614 615 return; 616 } 617 618 /* 619 * In order to fiddle with the 620 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 621 * first have to put the transmit and/or receive logic in the idle state. 622 */ 623 static void 624 vr_setcfg(sc, media) 625 struct vr_softc *sc; 626 int media; 627 { 628 int restart = 0; 629 630 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 631 restart = 1; 632 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 633 } 634 635 if ((media & IFM_GMASK) == IFM_FDX) 636 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 637 else 638 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 639 640 if (restart) 641 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 642 643 return; 644 } 645 646 static void 647 vr_reset(sc) 648 struct vr_softc *sc; 649 { 650 register int i; 651 652 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 653 654 for (i = 0; i < VR_TIMEOUT; i++) { 655 DELAY(10); 656 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 657 break; 658 } 659 if (i == VR_TIMEOUT) { 660 if (sc->vr_revid < REV_ID_VT3065_A) 661 printf("vr%d: reset never completed!\n", sc->vr_unit); 662 else { 663 /* Use newer force reset command */ 664 printf("vr%d: Using force reset command.\n", sc->vr_unit); 665 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 666 } 667 } 668 669 /* Wait a little while for the chip to get its brains in order. */ 670 DELAY(1000); 671 672 return; 673 } 674 675 /* 676 * Probe for a VIA Rhine chip. Check the PCI vendor and device 677 * IDs against our list and return a device name if we find a match. 678 */ 679 static int 680 vr_probe(dev) 681 device_t dev; 682 { 683 struct vr_type *t; 684 685 t = vr_devs; 686 687 while(t->vr_name != NULL) { 688 if ((pci_get_vendor(dev) == t->vr_vid) && 689 (pci_get_device(dev) == t->vr_did)) { 690 device_set_desc(dev, t->vr_name); 691 return(0); 692 } 693 t++; 694 } 695 696 return(ENXIO); 697 } 698 699 /* 700 * Attach the interface. Allocate softc structures, do ifmedia 701 * setup and ethernet/BPF attach. 702 */ 703 static int 704 vr_attach(dev) 705 device_t dev; 706 { 707 int i; 708 u_char eaddr[ETHER_ADDR_LEN]; 709 struct vr_softc *sc; 710 struct ifnet *ifp; 711 int unit, error = 0, rid; 712 713 sc = device_get_softc(dev); 714 unit = device_get_unit(dev); 715 716 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 717 MTX_DEF | MTX_RECURSE); 718 /* 719 * Map control/status registers. 720 */ 721 pci_enable_busmaster(dev); 722 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 723 724 rid = VR_RID; 725 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 726 727 if (sc->vr_res == NULL) { 728 printf("vr%d: couldn't map ports/memory\n", unit); 729 error = ENXIO; 730 goto fail; 731 } 732 733 sc->vr_btag = rman_get_bustag(sc->vr_res); 734 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 735 736 /* Allocate interrupt */ 737 rid = 0; 738 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 739 RF_SHAREABLE | RF_ACTIVE); 740 741 if (sc->vr_irq == NULL) { 742 printf("vr%d: couldn't map interrupt\n", unit); 743 error = ENXIO; 744 goto fail; 745 } 746 747 /* 748 * Windows may put the chip in suspend mode when it 749 * shuts down. Be sure to kick it in the head to wake it 750 * up again. 751 */ 752 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 753 754 /* Reset the adapter. */ 755 vr_reset(sc); 756 757 /* 758 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 759 * initialization and disable AUTOPOLL. 760 */ 761 pci_write_config(dev, VR_PCI_MODE, 762 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 763 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 764 765 /* 766 * Get station address. The way the Rhine chips work, 767 * you're not allowed to directly access the EEPROM once 768 * they've been programmed a special way. Consequently, 769 * we need to read the node address from the PAR0 and PAR1 770 * registers. 771 */ 772 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 773 DELAY(200); 774 for (i = 0; i < ETHER_ADDR_LEN; i++) 775 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 776 777 sc->vr_unit = unit; 778 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 779 780 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 781 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 782 783 if (sc->vr_ldata == NULL) { 784 printf("vr%d: no memory for list buffers!\n", unit); 785 error = ENXIO; 786 goto fail; 787 } 788 789 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 790 791 ifp = &sc->arpcom.ac_if; 792 ifp->if_softc = sc; 793 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 794 ifp->if_mtu = ETHERMTU; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = vr_ioctl; 797 ifp->if_start = vr_start; 798 ifp->if_watchdog = vr_watchdog; 799 ifp->if_init = vr_init; 800 ifp->if_baudrate = 10000000; 801 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 802 #ifdef DEVICE_POLLING 803 ifp->if_capabilities |= IFCAP_POLLING; 804 #endif 805 ifp->if_capenable = ifp->if_capabilities; 806 807 /* 808 * Do MII setup. 809 */ 810 if (mii_phy_probe(dev, &sc->vr_miibus, 811 vr_ifmedia_upd, vr_ifmedia_sts)) { 812 printf("vr%d: MII without any phy!\n", sc->vr_unit); 813 error = ENXIO; 814 goto fail; 815 } 816 817 callout_handle_init(&sc->vr_stat_ch); 818 819 /* 820 * Call MI attach routine. 821 */ 822 ether_ifattach(ifp, eaddr); 823 824 /* Hook interrupt last to avoid having to lock softc */ 825 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 826 vr_intr, sc, &sc->vr_intrhand); 827 828 if (error) { 829 printf("vr%d: couldn't set up irq\n", unit); 830 ether_ifdetach(ifp); 831 goto fail; 832 } 833 834 fail: 835 if (error) 836 vr_detach(dev); 837 838 return(error); 839 } 840 841 /* 842 * Shutdown hardware and free up resources. This can be called any 843 * time after the mutex has been initialized. It is called in both 844 * the error case in attach and the normal detach case so it needs 845 * to be careful about only freeing resources that have actually been 846 * allocated. 847 */ 848 static int 849 vr_detach(dev) 850 device_t dev; 851 { 852 struct vr_softc *sc; 853 struct ifnet *ifp; 854 855 sc = device_get_softc(dev); 856 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 857 VR_LOCK(sc); 858 ifp = &sc->arpcom.ac_if; 859 860 /* These should only be active if attach succeeded */ 861 if (device_is_attached(dev)) { 862 vr_stop(sc); 863 ether_ifdetach(ifp); 864 } 865 if (sc->vr_miibus) 866 device_delete_child(dev, sc->vr_miibus); 867 bus_generic_detach(dev); 868 869 if (sc->vr_intrhand) 870 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 871 if (sc->vr_irq) 872 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 873 if (sc->vr_res) 874 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 875 876 if (sc->vr_ldata) 877 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 878 879 VR_UNLOCK(sc); 880 mtx_destroy(&sc->vr_mtx); 881 882 return(0); 883 } 884 885 /* 886 * Initialize the transmit descriptors. 887 */ 888 static int 889 vr_list_tx_init(sc) 890 struct vr_softc *sc; 891 { 892 struct vr_chain_data *cd; 893 struct vr_list_data *ld; 894 int i; 895 896 cd = &sc->vr_cdata; 897 ld = sc->vr_ldata; 898 for (i = 0; i < VR_TX_LIST_CNT; i++) { 899 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 900 if (i == (VR_TX_LIST_CNT - 1)) 901 cd->vr_tx_chain[i].vr_nextdesc = 902 &cd->vr_tx_chain[0]; 903 else 904 cd->vr_tx_chain[i].vr_nextdesc = 905 &cd->vr_tx_chain[i + 1]; 906 } 907 908 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 909 910 return(0); 911 } 912 913 914 /* 915 * Initialize the RX descriptors and allocate mbufs for them. Note that 916 * we arrange the descriptors in a closed ring, so that the last descriptor 917 * points back to the first. 918 */ 919 static int 920 vr_list_rx_init(sc) 921 struct vr_softc *sc; 922 { 923 struct vr_chain_data *cd; 924 struct vr_list_data *ld; 925 int i; 926 927 cd = &sc->vr_cdata; 928 ld = sc->vr_ldata; 929 930 for (i = 0; i < VR_RX_LIST_CNT; i++) { 931 cd->vr_rx_chain[i].vr_ptr = 932 (struct vr_desc *)&ld->vr_rx_list[i]; 933 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 934 return(ENOBUFS); 935 if (i == (VR_RX_LIST_CNT - 1)) { 936 cd->vr_rx_chain[i].vr_nextdesc = 937 &cd->vr_rx_chain[0]; 938 ld->vr_rx_list[i].vr_next = 939 vtophys(&ld->vr_rx_list[0]); 940 } else { 941 cd->vr_rx_chain[i].vr_nextdesc = 942 &cd->vr_rx_chain[i + 1]; 943 ld->vr_rx_list[i].vr_next = 944 vtophys(&ld->vr_rx_list[i + 1]); 945 } 946 } 947 948 cd->vr_rx_head = &cd->vr_rx_chain[0]; 949 950 return(0); 951 } 952 953 /* 954 * Initialize an RX descriptor and attach an MBUF cluster. 955 * Note: the length fields are only 11 bits wide, which means the 956 * largest size we can specify is 2047. This is important because 957 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 958 * overflow the field and make a mess. 959 */ 960 static int 961 vr_newbuf(sc, c, m) 962 struct vr_softc *sc; 963 struct vr_chain_onefrag *c; 964 struct mbuf *m; 965 { 966 struct mbuf *m_new = NULL; 967 968 if (m == NULL) { 969 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 970 if (m_new == NULL) 971 return(ENOBUFS); 972 973 MCLGET(m_new, M_DONTWAIT); 974 if (!(m_new->m_flags & M_EXT)) { 975 m_freem(m_new); 976 return(ENOBUFS); 977 } 978 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 979 } else { 980 m_new = m; 981 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 982 m_new->m_data = m_new->m_ext.ext_buf; 983 } 984 985 m_adj(m_new, sizeof(u_int64_t)); 986 987 c->vr_mbuf = m_new; 988 c->vr_ptr->vr_status = VR_RXSTAT; 989 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 990 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 991 992 return(0); 993 } 994 995 /* 996 * A frame has been uploaded: pass the resulting mbuf chain up to 997 * the higher level protocols. 998 */ 999 static void 1000 vr_rxeof(sc) 1001 struct vr_softc *sc; 1002 { 1003 struct mbuf *m, *m0; 1004 struct ifnet *ifp; 1005 struct vr_chain_onefrag *cur_rx; 1006 int total_len = 0; 1007 u_int32_t rxstat; 1008 1009 VR_LOCK_ASSERT(sc); 1010 1011 ifp = &sc->arpcom.ac_if; 1012 1013 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1014 VR_RXSTAT_OWN)) { 1015 #ifdef DEVICE_POLLING 1016 if (ifp->if_flags & IFF_POLLING) { 1017 if (sc->rxcycles <= 0) 1018 break; 1019 sc->rxcycles--; 1020 } 1021 #endif /* DEVICE_POLLING */ 1022 m0 = NULL; 1023 cur_rx = sc->vr_cdata.vr_rx_head; 1024 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1025 m = cur_rx->vr_mbuf; 1026 1027 /* 1028 * If an error occurs, update stats, clear the 1029 * status word and leave the mbuf cluster in place: 1030 * it should simply get re-used next time this descriptor 1031 * comes up in the ring. 1032 */ 1033 if (rxstat & VR_RXSTAT_RXERR) { 1034 ifp->if_ierrors++; 1035 printf("vr%d: rx error (%02x):", 1036 sc->vr_unit, rxstat & 0x000000ff); 1037 if (rxstat & VR_RXSTAT_CRCERR) 1038 printf(" crc error"); 1039 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1040 printf(" frame alignment error\n"); 1041 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1042 printf(" FIFO overflow"); 1043 if (rxstat & VR_RXSTAT_GIANT) 1044 printf(" received giant packet"); 1045 if (rxstat & VR_RXSTAT_RUNT) 1046 printf(" received runt packet"); 1047 if (rxstat & VR_RXSTAT_BUSERR) 1048 printf(" system bus error"); 1049 if (rxstat & VR_RXSTAT_BUFFERR) 1050 printf("rx buffer error"); 1051 printf("\n"); 1052 vr_newbuf(sc, cur_rx, m); 1053 continue; 1054 } 1055 1056 /* No errors; receive the packet. */ 1057 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1058 1059 /* 1060 * XXX The VIA Rhine chip includes the CRC with every 1061 * received frame, and there's no way to turn this 1062 * behavior off (at least, I can't find anything in 1063 * the manual that explains how to do it) so we have 1064 * to trim off the CRC manually. 1065 */ 1066 total_len -= ETHER_CRC_LEN; 1067 1068 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1069 NULL); 1070 vr_newbuf(sc, cur_rx, m); 1071 if (m0 == NULL) { 1072 ifp->if_ierrors++; 1073 continue; 1074 } 1075 m = m0; 1076 1077 ifp->if_ipackets++; 1078 VR_UNLOCK(sc); 1079 (*ifp->if_input)(ifp, m); 1080 VR_LOCK(sc); 1081 } 1082 1083 return; 1084 } 1085 1086 static void 1087 vr_rxeoc(sc) 1088 struct vr_softc *sc; 1089 { 1090 struct ifnet *ifp; 1091 int i; 1092 1093 ifp = &sc->arpcom.ac_if; 1094 1095 ifp->if_ierrors++; 1096 1097 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1098 DELAY(10000); 1099 1100 for (i = 0x400; 1101 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1102 i--) 1103 ; /* Wait for receiver to stop */ 1104 1105 if (!i) { 1106 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1107 sc->vr_flags |= VR_F_RESTART; 1108 return; 1109 } 1110 1111 vr_rxeof(sc); 1112 1113 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1114 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1115 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1116 1117 return; 1118 } 1119 1120 /* 1121 * A frame was downloaded to the chip. It's safe for us to clean up 1122 * the list buffers. 1123 */ 1124 1125 static void 1126 vr_txeof(sc) 1127 struct vr_softc *sc; 1128 { 1129 struct vr_chain *cur_tx; 1130 struct ifnet *ifp; 1131 1132 ifp = &sc->arpcom.ac_if; 1133 1134 /* 1135 * Go through our tx list and free mbufs for those 1136 * frames that have been transmitted. 1137 */ 1138 cur_tx = sc->vr_cdata.vr_tx_cons; 1139 while (cur_tx->vr_mbuf != NULL) { 1140 u_int32_t txstat; 1141 int i; 1142 1143 txstat = cur_tx->vr_ptr->vr_status; 1144 1145 if ((txstat & VR_TXSTAT_ABRT) || 1146 (txstat & VR_TXSTAT_UDF)) { 1147 for (i = 0x400; 1148 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1149 i--) 1150 ; /* Wait for chip to shutdown */ 1151 if (!i) { 1152 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1153 sc->vr_flags |= VR_F_RESTART; 1154 break; 1155 } 1156 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1157 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1158 break; 1159 } 1160 1161 if (txstat & VR_TXSTAT_OWN) 1162 break; 1163 1164 if (txstat & VR_TXSTAT_ERRSUM) { 1165 ifp->if_oerrors++; 1166 if (txstat & VR_TXSTAT_DEFER) 1167 ifp->if_collisions++; 1168 if (txstat & VR_TXSTAT_LATECOLL) 1169 ifp->if_collisions++; 1170 } 1171 1172 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1173 1174 ifp->if_opackets++; 1175 m_freem(cur_tx->vr_mbuf); 1176 cur_tx->vr_mbuf = NULL; 1177 ifp->if_flags &= ~IFF_OACTIVE; 1178 1179 cur_tx = cur_tx->vr_nextdesc; 1180 } 1181 sc->vr_cdata.vr_tx_cons = cur_tx; 1182 if (cur_tx->vr_mbuf == NULL) 1183 ifp->if_timer = 0; 1184 } 1185 1186 static void 1187 vr_tick(xsc) 1188 void *xsc; 1189 { 1190 struct vr_softc *sc; 1191 struct mii_data *mii; 1192 1193 sc = xsc; 1194 VR_LOCK(sc); 1195 if (sc->vr_flags & VR_F_RESTART) { 1196 printf("vr%d: restarting\n", sc->vr_unit); 1197 vr_stop(sc); 1198 vr_reset(sc); 1199 vr_init(sc); 1200 sc->vr_flags &= ~VR_F_RESTART; 1201 } 1202 1203 mii = device_get_softc(sc->vr_miibus); 1204 mii_tick(mii); 1205 1206 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1207 1208 VR_UNLOCK(sc); 1209 1210 return; 1211 } 1212 1213 #ifdef DEVICE_POLLING 1214 static poll_handler_t vr_poll; 1215 1216 static void 1217 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1218 { 1219 struct vr_softc *sc = ifp->if_softc; 1220 1221 VR_LOCK(sc); 1222 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1223 ether_poll_deregister(ifp); 1224 cmd = POLL_DEREGISTER; 1225 } 1226 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1227 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1228 goto done; 1229 } 1230 1231 sc->rxcycles = count; 1232 vr_rxeof(sc); 1233 vr_txeof(sc); 1234 if (ifp->if_snd.ifq_head != NULL) 1235 vr_start(ifp); 1236 1237 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1238 u_int16_t status; 1239 1240 status = CSR_READ_2(sc, VR_ISR); 1241 if (status) 1242 CSR_WRITE_2(sc, VR_ISR, status); 1243 1244 if ((status & VR_INTRS) == 0) 1245 goto done; 1246 1247 if (status & VR_ISR_RX_DROPPED) { 1248 printf("vr%d: rx packet lost\n", sc->vr_unit); 1249 ifp->if_ierrors++; 1250 } 1251 1252 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1253 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1254 printf("vr%d: receive error (%04x)", 1255 sc->vr_unit, status); 1256 if (status & VR_ISR_RX_NOBUF) 1257 printf(" no buffers"); 1258 if (status & VR_ISR_RX_OFLOW) 1259 printf(" overflow"); 1260 if (status & VR_ISR_RX_DROPPED) 1261 printf(" packet lost"); 1262 printf("\n"); 1263 vr_rxeoc(sc); 1264 } 1265 1266 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1267 vr_reset(sc); 1268 vr_init(sc); 1269 goto done; 1270 } 1271 1272 if ((status & VR_ISR_UDFI) || 1273 (status & VR_ISR_TX_ABRT2) || 1274 (status & VR_ISR_TX_ABRT)) { 1275 ifp->if_oerrors++; 1276 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1277 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1278 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1279 } 1280 } 1281 } 1282 1283 done: 1284 VR_UNLOCK(sc); 1285 1286 } 1287 #endif /* DEVICE_POLLING */ 1288 1289 static void 1290 vr_intr(arg) 1291 void *arg; 1292 { 1293 struct vr_softc *sc; 1294 struct ifnet *ifp; 1295 u_int16_t status; 1296 1297 sc = arg; 1298 VR_LOCK(sc); 1299 ifp = &sc->arpcom.ac_if; 1300 1301 #ifdef DEVICE_POLLING 1302 if (ifp->if_flags & IFF_POLLING) 1303 goto done; 1304 if ((ifp->if_capenable & IFCAP_POLLING) && 1305 ether_poll_register(vr_poll, ifp)) { /* ok, disable interrupts */ 1306 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1307 vr_poll(ifp, 0, 1); 1308 goto done; 1309 } 1310 #endif /* DEVICE_POLLING */ 1311 1312 /* Supress unwanted interrupts. */ 1313 if (!(ifp->if_flags & IFF_UP)) { 1314 vr_stop(sc); 1315 VR_UNLOCK(sc); 1316 return; 1317 } 1318 1319 /* Disable interrupts. */ 1320 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1321 1322 for (;;) { 1323 1324 status = CSR_READ_2(sc, VR_ISR); 1325 if (status) 1326 CSR_WRITE_2(sc, VR_ISR, status); 1327 1328 if ((status & VR_INTRS) == 0) 1329 break; 1330 1331 if (status & VR_ISR_RX_OK) 1332 vr_rxeof(sc); 1333 1334 if (status & VR_ISR_RX_DROPPED) { 1335 printf("vr%d: rx packet lost\n", sc->vr_unit); 1336 ifp->if_ierrors++; 1337 } 1338 1339 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1340 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1341 printf("vr%d: receive error (%04x)", 1342 sc->vr_unit, status); 1343 if (status & VR_ISR_RX_NOBUF) 1344 printf(" no buffers"); 1345 if (status & VR_ISR_RX_OFLOW) 1346 printf(" overflow"); 1347 if (status & VR_ISR_RX_DROPPED) 1348 printf(" packet lost"); 1349 printf("\n"); 1350 vr_rxeoc(sc); 1351 } 1352 1353 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1354 vr_reset(sc); 1355 vr_init(sc); 1356 break; 1357 } 1358 1359 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1360 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1361 vr_txeof(sc); 1362 if ((status & VR_ISR_UDFI) || 1363 (status & VR_ISR_TX_ABRT2) || 1364 (status & VR_ISR_TX_ABRT)) { 1365 ifp->if_oerrors++; 1366 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1367 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1368 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1369 } 1370 } 1371 } 1372 1373 } 1374 1375 /* Re-enable interrupts. */ 1376 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1377 1378 if (ifp->if_snd.ifq_head != NULL) { 1379 vr_start(ifp); 1380 } 1381 1382 #ifdef DEVICE_POLLING 1383 done: 1384 #endif /* DEVICE_POLLING */ 1385 VR_UNLOCK(sc); 1386 1387 return; 1388 } 1389 1390 /* 1391 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1392 * pointers to the fragment pointers. 1393 */ 1394 static int 1395 vr_encap(sc, c, m_head) 1396 struct vr_softc *sc; 1397 struct vr_chain *c; 1398 struct mbuf *m_head; 1399 { 1400 struct vr_desc *f = NULL; 1401 struct mbuf *m; 1402 1403 /* 1404 * The VIA Rhine wants packet buffers to be longword 1405 * aligned, but very often our mbufs aren't. Rather than 1406 * waste time trying to decide when to copy and when not 1407 * to copy, just do it all the time. 1408 */ 1409 m = m_defrag(m_head, M_DONTWAIT); 1410 if (m == NULL) { 1411 return(1); 1412 } 1413 1414 /* 1415 * The Rhine chip doesn't auto-pad, so we have to make 1416 * sure to pad short frames out to the minimum frame length 1417 * ourselves. 1418 */ 1419 if (m->m_len < VR_MIN_FRAMELEN) { 1420 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1421 m->m_len = m->m_pkthdr.len; 1422 } 1423 1424 c->vr_mbuf = m; 1425 f = c->vr_ptr; 1426 f->vr_data = vtophys(mtod(m, caddr_t)); 1427 f->vr_ctl = m->m_len; 1428 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1429 f->vr_status = 0; 1430 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1431 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1432 1433 return(0); 1434 } 1435 1436 /* 1437 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1438 * to the mbuf data regions directly in the transmit lists. We also save a 1439 * copy of the pointers since the transmit list fragment pointers are 1440 * physical addresses. 1441 */ 1442 1443 static void 1444 vr_start(ifp) 1445 struct ifnet *ifp; 1446 { 1447 struct vr_softc *sc; 1448 struct mbuf *m_head; 1449 struct vr_chain *cur_tx; 1450 1451 if (ifp->if_flags & IFF_OACTIVE) 1452 return; 1453 1454 sc = ifp->if_softc; 1455 1456 VR_LOCK(sc); 1457 1458 cur_tx = sc->vr_cdata.vr_tx_prod; 1459 while (cur_tx->vr_mbuf == NULL) { 1460 IF_DEQUEUE(&ifp->if_snd, m_head); 1461 if (m_head == NULL) 1462 break; 1463 1464 /* Pack the data into the descriptor. */ 1465 if (vr_encap(sc, cur_tx, m_head)) { 1466 /* Rollback, send what we were able to encap. */ 1467 IF_PREPEND(&ifp->if_snd, m_head); 1468 break; 1469 } 1470 1471 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1472 1473 /* 1474 * If there's a BPF listener, bounce a copy of this frame 1475 * to him. 1476 */ 1477 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1478 1479 cur_tx = cur_tx->vr_nextdesc; 1480 } 1481 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1482 sc->vr_cdata.vr_tx_prod = cur_tx; 1483 1484 /* Tell the chip to start transmitting. */ 1485 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1486 1487 /* Set a timeout in case the chip goes out to lunch. */ 1488 ifp->if_timer = 5; 1489 1490 if (cur_tx->vr_mbuf != NULL) 1491 ifp->if_flags |= IFF_OACTIVE; 1492 } 1493 1494 VR_UNLOCK(sc); 1495 1496 return; 1497 } 1498 1499 static void 1500 vr_init(xsc) 1501 void *xsc; 1502 { 1503 struct vr_softc *sc = xsc; 1504 struct ifnet *ifp = &sc->arpcom.ac_if; 1505 struct mii_data *mii; 1506 int i; 1507 1508 VR_LOCK(sc); 1509 1510 mii = device_get_softc(sc->vr_miibus); 1511 1512 /* 1513 * Cancel pending I/O and free all RX/TX buffers. 1514 */ 1515 vr_stop(sc); 1516 vr_reset(sc); 1517 1518 /* 1519 * Set our station address. 1520 */ 1521 for (i = 0; i < ETHER_ADDR_LEN; i++) 1522 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1523 1524 /* Set DMA size */ 1525 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1526 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1527 1528 /* 1529 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1530 * so we must set both. 1531 */ 1532 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1533 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1534 1535 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1536 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1537 1538 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1539 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1540 1541 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1542 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1543 1544 /* Init circular RX list. */ 1545 if (vr_list_rx_init(sc) == ENOBUFS) { 1546 printf("vr%d: initialization failed: no " 1547 "memory for rx buffers\n", sc->vr_unit); 1548 vr_stop(sc); 1549 VR_UNLOCK(sc); 1550 return; 1551 } 1552 1553 /* 1554 * Init tx descriptors. 1555 */ 1556 vr_list_tx_init(sc); 1557 1558 /* If we want promiscuous mode, set the allframes bit. */ 1559 if (ifp->if_flags & IFF_PROMISC) 1560 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1561 else 1562 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1563 1564 /* Set capture broadcast bit to capture broadcast frames. */ 1565 if (ifp->if_flags & IFF_BROADCAST) 1566 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1567 else 1568 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1569 1570 /* 1571 * Program the multicast filter, if necessary. 1572 */ 1573 vr_setmulti(sc); 1574 1575 /* 1576 * Load the address of the RX list. 1577 */ 1578 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1579 1580 /* Enable receiver and transmitter. */ 1581 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1582 VR_CMD_TX_ON|VR_CMD_RX_ON| 1583 VR_CMD_RX_GO); 1584 1585 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1586 1587 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1588 #ifdef DEVICE_POLLING 1589 /* 1590 * Disable interrupts if we are polling. 1591 */ 1592 if (ifp->if_flags & IFF_POLLING) 1593 CSR_WRITE_2(sc, VR_IMR, 0); 1594 else 1595 #endif /* DEVICE_POLLING */ 1596 /* 1597 * Enable interrupts. 1598 */ 1599 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1600 1601 mii_mediachg(mii); 1602 1603 ifp->if_flags |= IFF_RUNNING; 1604 ifp->if_flags &= ~IFF_OACTIVE; 1605 1606 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1607 1608 VR_UNLOCK(sc); 1609 1610 return; 1611 } 1612 1613 /* 1614 * Set media options. 1615 */ 1616 static int 1617 vr_ifmedia_upd(ifp) 1618 struct ifnet *ifp; 1619 { 1620 struct vr_softc *sc; 1621 1622 sc = ifp->if_softc; 1623 1624 if (ifp->if_flags & IFF_UP) 1625 vr_init(sc); 1626 1627 return(0); 1628 } 1629 1630 /* 1631 * Report current media status. 1632 */ 1633 static void 1634 vr_ifmedia_sts(ifp, ifmr) 1635 struct ifnet *ifp; 1636 struct ifmediareq *ifmr; 1637 { 1638 struct vr_softc *sc; 1639 struct mii_data *mii; 1640 1641 sc = ifp->if_softc; 1642 mii = device_get_softc(sc->vr_miibus); 1643 mii_pollstat(mii); 1644 ifmr->ifm_active = mii->mii_media_active; 1645 ifmr->ifm_status = mii->mii_media_status; 1646 1647 return; 1648 } 1649 1650 static int 1651 vr_ioctl(ifp, command, data) 1652 struct ifnet *ifp; 1653 u_long command; 1654 caddr_t data; 1655 { 1656 struct vr_softc *sc = ifp->if_softc; 1657 struct ifreq *ifr = (struct ifreq *) data; 1658 struct mii_data *mii; 1659 int error = 0; 1660 1661 VR_LOCK(sc); 1662 1663 switch(command) { 1664 case SIOCSIFFLAGS: 1665 if (ifp->if_flags & IFF_UP) { 1666 vr_init(sc); 1667 } else { 1668 if (ifp->if_flags & IFF_RUNNING) 1669 vr_stop(sc); 1670 } 1671 error = 0; 1672 break; 1673 case SIOCADDMULTI: 1674 case SIOCDELMULTI: 1675 vr_setmulti(sc); 1676 error = 0; 1677 break; 1678 case SIOCGIFMEDIA: 1679 case SIOCSIFMEDIA: 1680 mii = device_get_softc(sc->vr_miibus); 1681 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1682 break; 1683 case SIOCSIFCAP: 1684 ifp->if_capenable = ifr->ifr_reqcap; 1685 break; 1686 default: 1687 error = ether_ioctl(ifp, command, data); 1688 break; 1689 } 1690 1691 VR_UNLOCK(sc); 1692 1693 return(error); 1694 } 1695 1696 static void 1697 vr_watchdog(ifp) 1698 struct ifnet *ifp; 1699 { 1700 struct vr_softc *sc; 1701 1702 sc = ifp->if_softc; 1703 1704 VR_LOCK(sc); 1705 ifp->if_oerrors++; 1706 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1707 1708 vr_stop(sc); 1709 vr_reset(sc); 1710 vr_init(sc); 1711 1712 if (ifp->if_snd.ifq_head != NULL) 1713 vr_start(ifp); 1714 1715 VR_UNLOCK(sc); 1716 1717 return; 1718 } 1719 1720 /* 1721 * Stop the adapter and free any mbufs allocated to the 1722 * RX and TX lists. 1723 */ 1724 static void 1725 vr_stop(sc) 1726 struct vr_softc *sc; 1727 { 1728 register int i; 1729 struct ifnet *ifp; 1730 1731 VR_LOCK(sc); 1732 1733 ifp = &sc->arpcom.ac_if; 1734 ifp->if_timer = 0; 1735 1736 untimeout(vr_tick, sc, sc->vr_stat_ch); 1737 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1738 #ifdef DEVICE_POLLING 1739 ether_poll_deregister(ifp); 1740 #endif /* DEVICE_POLLING */ 1741 1742 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1743 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1744 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1745 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1746 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1747 1748 /* 1749 * Free data in the RX lists. 1750 */ 1751 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1752 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1753 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1754 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1755 } 1756 } 1757 bzero((char *)&sc->vr_ldata->vr_rx_list, 1758 sizeof(sc->vr_ldata->vr_rx_list)); 1759 1760 /* 1761 * Free the TX list buffers. 1762 */ 1763 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1764 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1765 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1766 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1767 } 1768 } 1769 1770 bzero((char *)&sc->vr_ldata->vr_tx_list, 1771 sizeof(sc->vr_ldata->vr_tx_list)); 1772 1773 VR_UNLOCK(sc); 1774 1775 return; 1776 } 1777 1778 /* 1779 * Stop all chip I/O so that the kernel's probe routines don't 1780 * get confused by errant DMAs when rebooting. 1781 */ 1782 static void 1783 vr_shutdown(dev) 1784 device_t dev; 1785 { 1786 struct vr_softc *sc; 1787 1788 sc = device_get_softc(dev); 1789 1790 vr_stop(sc); 1791 1792 return; 1793 } 1794