1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <dev/pci/pcireg.h> 91 #include <dev/pci/pcivar.h> 92 93 #define VR_USEIOSPACE 94 95 #include <pci/if_vrreg.h> 96 97 MODULE_DEPEND(vr, pci, 1, 1, 1); 98 MODULE_DEPEND(vr, ether, 1, 1, 1); 99 MODULE_DEPEND(vr, miibus, 1, 1, 1); 100 101 /* "controller miibus0" required. See GENERIC if you get errors here. */ 102 #include "miibus_if.h" 103 104 #undef VR_USESWSHIFT 105 106 /* 107 * Various supported device vendors/types and their names. 108 */ 109 static struct vr_type vr_devs[] = { 110 { VIA_VENDORID, VIA_DEVICEID_RHINE, 111 "VIA VT3043 Rhine I 10/100BaseTX" }, 112 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 113 "VIA VT86C100A Rhine II 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 115 "VIA VT6102 Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 117 "VIA VT6105 Rhine III 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 119 "VIA VT6105M Rhine III 10/100BaseTX" }, 120 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 121 "Delta Electronics Rhine II 10/100BaseTX" }, 122 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 123 "Addtron Technology Rhine II 10/100BaseTX" }, 124 { 0, 0, NULL } 125 }; 126 127 static int vr_probe (device_t); 128 static int vr_attach (device_t); 129 static int vr_detach (device_t); 130 131 static int vr_newbuf (struct vr_softc *, 132 struct vr_chain_onefrag *, 133 struct mbuf *); 134 static int vr_encap (struct vr_softc *, struct vr_chain *, 135 struct mbuf * ); 136 137 static void vr_rxeof (struct vr_softc *); 138 static void vr_rxeoc (struct vr_softc *); 139 static void vr_txeof (struct vr_softc *); 140 static void vr_txeoc (struct vr_softc *); 141 static void vr_tick (void *); 142 static void vr_intr (void *); 143 static void vr_start (struct ifnet *); 144 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 145 static void vr_init (void *); 146 static void vr_stop (struct vr_softc *); 147 static void vr_watchdog (struct ifnet *); 148 static void vr_shutdown (device_t); 149 static int vr_ifmedia_upd (struct ifnet *); 150 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152 #ifdef VR_USESWSHIFT 153 static void vr_mii_sync (struct vr_softc *); 154 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 155 #endif 156 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 157 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_miibus_readreg (device_t, int, int); 159 static int vr_miibus_writereg (device_t, int, int, int); 160 static void vr_miibus_statchg (device_t); 161 162 static void vr_setcfg (struct vr_softc *, int); 163 static uint32_t vr_mchash (const uint8_t *); 164 static void vr_setmulti (struct vr_softc *); 165 static void vr_reset (struct vr_softc *); 166 static int vr_list_rx_init (struct vr_softc *); 167 static int vr_list_tx_init (struct vr_softc *); 168 169 #ifdef VR_USEIOSPACE 170 #define VR_RES SYS_RES_IOPORT 171 #define VR_RID VR_PCI_LOIO 172 #else 173 #define VR_RES SYS_RES_MEMORY 174 #define VR_RID VR_PCI_LOMEM 175 #endif 176 177 static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200 }; 201 202 static devclass_t vr_devclass; 203 204 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207 #define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | (x)) 210 211 #define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~(x)) 214 215 #define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | (x)) 218 219 #define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~(x)) 222 223 #define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227 #define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | (x)) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 238 239 #ifdef VR_USESWSHIFT 240 /* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243 static void 244 vr_mii_sync(sc) 245 struct vr_softc *sc; 246 { 247 register int i; 248 249 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 250 251 for (i = 0; i < 32; i++) { 252 SIO_SET(VR_MIICMD_CLK); 253 DELAY(1); 254 SIO_CLR(VR_MIICMD_CLK); 255 DELAY(1); 256 } 257 258 return; 259 } 260 261 /* 262 * Clock a series of bits through the MII. 263 */ 264 static void 265 vr_mii_send(sc, bits, cnt) 266 struct vr_softc *sc; 267 u_int32_t bits; 268 int cnt; 269 { 270 int i; 271 272 SIO_CLR(VR_MIICMD_CLK); 273 274 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 275 if (bits & i) { 276 SIO_SET(VR_MIICMD_DATAIN); 277 } else { 278 SIO_CLR(VR_MIICMD_DATAIN); 279 } 280 DELAY(1); 281 SIO_CLR(VR_MIICMD_CLK); 282 DELAY(1); 283 SIO_SET(VR_MIICMD_CLK); 284 } 285 } 286 #endif 287 288 /* 289 * Read an PHY register through the MII. 290 */ 291 static int 292 vr_mii_readreg(sc, frame) 293 struct vr_softc *sc; 294 struct vr_mii_frame *frame; 295 296 #ifdef VR_USESWSHIFT 297 { 298 int i, ack; 299 300 VR_LOCK(sc); 301 302 /* 303 * Set up frame for RX. 304 */ 305 frame->mii_stdelim = VR_MII_STARTDELIM; 306 frame->mii_opcode = VR_MII_READOP; 307 frame->mii_turnaround = 0; 308 frame->mii_data = 0; 309 310 CSR_WRITE_1(sc, VR_MIICMD, 0); 311 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 312 313 /* 314 * Turn on data xmit. 315 */ 316 SIO_SET(VR_MIICMD_DIR); 317 318 vr_mii_sync(sc); 319 320 /* 321 * Send command/address info. 322 */ 323 vr_mii_send(sc, frame->mii_stdelim, 2); 324 vr_mii_send(sc, frame->mii_opcode, 2); 325 vr_mii_send(sc, frame->mii_phyaddr, 5); 326 vr_mii_send(sc, frame->mii_regaddr, 5); 327 328 /* Idle bit */ 329 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 330 DELAY(1); 331 SIO_SET(VR_MIICMD_CLK); 332 DELAY(1); 333 334 /* Turn off xmit. */ 335 SIO_CLR(VR_MIICMD_DIR); 336 337 /* Check for ack */ 338 SIO_CLR(VR_MIICMD_CLK); 339 DELAY(1); 340 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 344 /* 345 * Now try reading data bits. If the ack failed, we still 346 * need to clock through 16 cycles to keep the PHY(s) in sync. 347 */ 348 if (ack) { 349 for(i = 0; i < 16; i++) { 350 SIO_CLR(VR_MIICMD_CLK); 351 DELAY(1); 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 goto fail; 356 } 357 358 for (i = 0x8000; i; i >>= 1) { 359 SIO_CLR(VR_MIICMD_CLK); 360 DELAY(1); 361 if (!ack) { 362 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 363 frame->mii_data |= i; 364 DELAY(1); 365 } 366 SIO_SET(VR_MIICMD_CLK); 367 DELAY(1); 368 } 369 370 fail: 371 372 SIO_CLR(VR_MIICMD_CLK); 373 DELAY(1); 374 SIO_SET(VR_MIICMD_CLK); 375 DELAY(1); 376 377 VR_UNLOCK(sc); 378 379 if (ack) 380 return(1); 381 return(0); 382 } 383 #else 384 { 385 int s, i; 386 387 s = splimp(); 388 389 /* Set the PHY-adress */ 390 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 391 frame->mii_phyaddr); 392 393 /* Set the register-adress */ 394 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 395 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 396 397 for (i = 0; i < 10000; i++) { 398 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 399 break; 400 DELAY(1); 401 } 402 403 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 404 405 (void)splx(s); 406 407 return(0); 408 } 409 #endif 410 411 412 /* 413 * Write to a PHY register through the MII. 414 */ 415 static int 416 vr_mii_writereg(sc, frame) 417 struct vr_softc *sc; 418 struct vr_mii_frame *frame; 419 420 #ifdef VR_USESWSHIFT 421 { 422 VR_LOCK(sc); 423 424 CSR_WRITE_1(sc, VR_MIICMD, 0); 425 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 426 427 /* 428 * Set up frame for TX. 429 */ 430 431 frame->mii_stdelim = VR_MII_STARTDELIM; 432 frame->mii_opcode = VR_MII_WRITEOP; 433 frame->mii_turnaround = VR_MII_TURNAROUND; 434 435 /* 436 * Turn on data output. 437 */ 438 SIO_SET(VR_MIICMD_DIR); 439 440 vr_mii_sync(sc); 441 442 vr_mii_send(sc, frame->mii_stdelim, 2); 443 vr_mii_send(sc, frame->mii_opcode, 2); 444 vr_mii_send(sc, frame->mii_phyaddr, 5); 445 vr_mii_send(sc, frame->mii_regaddr, 5); 446 vr_mii_send(sc, frame->mii_turnaround, 2); 447 vr_mii_send(sc, frame->mii_data, 16); 448 449 /* Idle bit. */ 450 SIO_SET(VR_MIICMD_CLK); 451 DELAY(1); 452 SIO_CLR(VR_MIICMD_CLK); 453 DELAY(1); 454 455 /* 456 * Turn off xmit. 457 */ 458 SIO_CLR(VR_MIICMD_DIR); 459 460 VR_UNLOCK(sc); 461 462 return(0); 463 } 464 #else 465 { 466 int s, i; 467 468 s = splimp(); 469 470 /* Set the PHY-adress */ 471 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 472 frame->mii_phyaddr); 473 474 /* Set the register-adress and data to write */ 475 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 476 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 477 478 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 479 480 for (i = 0; i < 10000; i++) { 481 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 482 break; 483 DELAY(1); 484 } 485 486 (void)splx(s); 487 488 return(0); 489 } 490 #endif 491 492 static int 493 vr_miibus_readreg(dev, phy, reg) 494 device_t dev; 495 int phy, reg; 496 { 497 struct vr_softc *sc; 498 struct vr_mii_frame frame; 499 500 sc = device_get_softc(dev); 501 502 switch (sc->vr_revid) { 503 case REV_ID_VT6102_APOLLO: 504 if (phy != 1) 505 return 0; 506 default: 507 break; 508 } 509 510 bzero((char *)&frame, sizeof(frame)); 511 512 frame.mii_phyaddr = phy; 513 frame.mii_regaddr = reg; 514 vr_mii_readreg(sc, &frame); 515 516 return(frame.mii_data); 517 } 518 519 static int 520 vr_miibus_writereg(dev, phy, reg, data) 521 device_t dev; 522 u_int16_t phy, reg, data; 523 { 524 struct vr_softc *sc; 525 struct vr_mii_frame frame; 526 527 sc = device_get_softc(dev); 528 529 switch (sc->vr_revid) { 530 case REV_ID_VT6102_APOLLO: 531 if (phy != 1) 532 return 0; 533 default: 534 break; 535 } 536 537 bzero((char *)&frame, sizeof(frame)); 538 539 frame.mii_phyaddr = phy; 540 frame.mii_regaddr = reg; 541 frame.mii_data = data; 542 543 vr_mii_writereg(sc, &frame); 544 545 return(0); 546 } 547 548 static void 549 vr_miibus_statchg(dev) 550 device_t dev; 551 { 552 struct vr_softc *sc; 553 struct mii_data *mii; 554 555 sc = device_get_softc(dev); 556 VR_LOCK(sc); 557 mii = device_get_softc(sc->vr_miibus); 558 vr_setcfg(sc, mii->mii_media_active); 559 VR_UNLOCK(sc); 560 561 return; 562 } 563 564 /* 565 * Calculate CRC of a multicast group address, return the lower 6 bits. 566 */ 567 static u_int32_t 568 vr_mchash(addr) 569 const uint8_t *addr; 570 { 571 uint32_t crc, carry; 572 int idx, bit; 573 uint8_t data; 574 575 /* Compute CRC for the address value. */ 576 crc = 0xFFFFFFFF; /* initial value */ 577 578 for (idx = 0; idx < 6; idx++) { 579 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 580 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 581 crc <<= 1; 582 if (carry) 583 crc = (crc ^ 0x04c11db6) | carry; 584 } 585 } 586 587 /* return the filter bit position */ 588 return((crc >> 26) & 0x0000003F); 589 } 590 591 /* 592 * Program the 64-bit multicast hash filter. 593 */ 594 static void 595 vr_setmulti(sc) 596 struct vr_softc *sc; 597 { 598 struct ifnet *ifp; 599 int h = 0; 600 u_int32_t hashes[2] = { 0, 0 }; 601 struct ifmultiaddr *ifma; 602 u_int8_t rxfilt; 603 int mcnt = 0; 604 605 ifp = &sc->arpcom.ac_if; 606 607 rxfilt = CSR_READ_1(sc, VR_RXCFG); 608 609 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 610 rxfilt |= VR_RXCFG_RX_MULTI; 611 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 612 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 613 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 614 return; 615 } 616 617 /* first, zot all the existing hash bits */ 618 CSR_WRITE_4(sc, VR_MAR0, 0); 619 CSR_WRITE_4(sc, VR_MAR1, 0); 620 621 /* now program new ones */ 622 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 623 if (ifma->ifma_addr->sa_family != AF_LINK) 624 continue; 625 h = vr_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 626 if (h < 32) 627 hashes[0] |= (1 << h); 628 else 629 hashes[1] |= (1 << (h - 32)); 630 mcnt++; 631 } 632 633 if (mcnt) 634 rxfilt |= VR_RXCFG_RX_MULTI; 635 else 636 rxfilt &= ~VR_RXCFG_RX_MULTI; 637 638 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 639 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 640 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 641 642 return; 643 } 644 645 /* 646 * In order to fiddle with the 647 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 648 * first have to put the transmit and/or receive logic in the idle state. 649 */ 650 static void 651 vr_setcfg(sc, media) 652 struct vr_softc *sc; 653 int media; 654 { 655 int restart = 0; 656 657 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 658 restart = 1; 659 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 660 } 661 662 if ((media & IFM_GMASK) == IFM_FDX) 663 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 664 else 665 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 666 667 if (restart) 668 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 669 670 return; 671 } 672 673 static void 674 vr_reset(sc) 675 struct vr_softc *sc; 676 { 677 register int i; 678 679 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 680 681 for (i = 0; i < VR_TIMEOUT; i++) { 682 DELAY(10); 683 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 684 break; 685 } 686 if (i == VR_TIMEOUT) { 687 if (sc->vr_revid < REV_ID_VT3065_A) 688 printf("vr%d: reset never completed!\n", sc->vr_unit); 689 else { 690 /* Use newer force reset command */ 691 printf("vr%d: Using force reset command.\n", sc->vr_unit); 692 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 693 } 694 } 695 696 /* Wait a little while for the chip to get its brains in order. */ 697 DELAY(1000); 698 699 return; 700 } 701 702 /* 703 * Probe for a VIA Rhine chip. Check the PCI vendor and device 704 * IDs against our list and return a device name if we find a match. 705 */ 706 static int 707 vr_probe(dev) 708 device_t dev; 709 { 710 struct vr_type *t; 711 712 t = vr_devs; 713 714 while(t->vr_name != NULL) { 715 if ((pci_get_vendor(dev) == t->vr_vid) && 716 (pci_get_device(dev) == t->vr_did)) { 717 device_set_desc(dev, t->vr_name); 718 return(0); 719 } 720 t++; 721 } 722 723 return(ENXIO); 724 } 725 726 /* 727 * Attach the interface. Allocate softc structures, do ifmedia 728 * setup and ethernet/BPF attach. 729 */ 730 static int 731 vr_attach(dev) 732 device_t dev; 733 { 734 int i; 735 u_char eaddr[ETHER_ADDR_LEN]; 736 struct vr_softc *sc; 737 struct ifnet *ifp; 738 int unit, error = 0, rid; 739 740 sc = device_get_softc(dev); 741 unit = device_get_unit(dev); 742 743 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 744 MTX_DEF | MTX_RECURSE); 745 #ifndef BURN_BRIDGES 746 /* 747 * Handle power management nonsense. 748 */ 749 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 750 u_int32_t iobase, membase, irq; 751 752 /* Save important PCI config data. */ 753 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 754 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 755 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 756 757 /* Reset the power state. */ 758 printf("vr%d: chip is in D%d power mode " 759 "-- setting to D0\n", unit, 760 pci_get_powerstate(dev)); 761 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 762 763 /* Restore PCI config data. */ 764 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 765 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 766 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 767 } 768 #endif 769 /* 770 * Map control/status registers. 771 */ 772 pci_enable_busmaster(dev); 773 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 774 775 rid = VR_RID; 776 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 777 778 if (sc->vr_res == NULL) { 779 printf("vr%d: couldn't map ports/memory\n", unit); 780 error = ENXIO; 781 goto fail; 782 } 783 784 sc->vr_btag = rman_get_bustag(sc->vr_res); 785 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 786 787 /* Allocate interrupt */ 788 rid = 0; 789 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 790 RF_SHAREABLE | RF_ACTIVE); 791 792 if (sc->vr_irq == NULL) { 793 printf("vr%d: couldn't map interrupt\n", unit); 794 error = ENXIO; 795 goto fail; 796 } 797 798 /* 799 * Windows may put the chip in suspend mode when it 800 * shuts down. Be sure to kick it in the head to wake it 801 * up again. 802 */ 803 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 804 805 /* Reset the adapter. */ 806 vr_reset(sc); 807 808 /* 809 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 810 * initialization and disable AUTOPOLL. 811 */ 812 pci_write_config(dev, VR_PCI_MODE, 813 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 814 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 815 816 /* 817 * Get station address. The way the Rhine chips work, 818 * you're not allowed to directly access the EEPROM once 819 * they've been programmed a special way. Consequently, 820 * we need to read the node address from the PAR0 and PAR1 821 * registers. 822 */ 823 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 824 DELAY(200); 825 for (i = 0; i < ETHER_ADDR_LEN; i++) 826 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 827 828 sc->vr_unit = unit; 829 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 830 831 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 832 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 833 834 if (sc->vr_ldata == NULL) { 835 printf("vr%d: no memory for list buffers!\n", unit); 836 error = ENXIO; 837 goto fail; 838 } 839 840 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 841 842 ifp = &sc->arpcom.ac_if; 843 ifp->if_softc = sc; 844 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 845 ifp->if_mtu = ETHERMTU; 846 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 847 ifp->if_ioctl = vr_ioctl; 848 ifp->if_start = vr_start; 849 ifp->if_watchdog = vr_watchdog; 850 ifp->if_init = vr_init; 851 ifp->if_baudrate = 10000000; 852 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 853 854 /* 855 * Do MII setup. 856 */ 857 if (mii_phy_probe(dev, &sc->vr_miibus, 858 vr_ifmedia_upd, vr_ifmedia_sts)) { 859 printf("vr%d: MII without any phy!\n", sc->vr_unit); 860 error = ENXIO; 861 goto fail; 862 } 863 864 callout_handle_init(&sc->vr_stat_ch); 865 866 /* 867 * Call MI attach routine. 868 */ 869 ether_ifattach(ifp, eaddr); 870 871 /* Hook interrupt last to avoid having to lock softc */ 872 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 873 vr_intr, sc, &sc->vr_intrhand); 874 875 if (error) { 876 printf("vr%d: couldn't set up irq\n", unit); 877 ether_ifdetach(ifp); 878 goto fail; 879 } 880 881 fail: 882 if (error) 883 vr_detach(dev); 884 885 return(error); 886 } 887 888 /* 889 * Shutdown hardware and free up resources. This can be called any 890 * time after the mutex has been initialized. It is called in both 891 * the error case in attach and the normal detach case so it needs 892 * to be careful about only freeing resources that have actually been 893 * allocated. 894 */ 895 static int 896 vr_detach(dev) 897 device_t dev; 898 { 899 struct vr_softc *sc; 900 struct ifnet *ifp; 901 902 sc = device_get_softc(dev); 903 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 904 VR_LOCK(sc); 905 ifp = &sc->arpcom.ac_if; 906 907 /* These should only be active if attach succeeded */ 908 if (device_is_attached(dev)) { 909 vr_stop(sc); 910 ether_ifdetach(ifp); 911 } 912 if (sc->vr_miibus) 913 device_delete_child(dev, sc->vr_miibus); 914 bus_generic_detach(dev); 915 916 if (sc->vr_intrhand) 917 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 918 if (sc->vr_irq) 919 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 920 if (sc->vr_res) 921 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 922 923 if (sc->vr_ldata) 924 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 925 926 VR_UNLOCK(sc); 927 mtx_destroy(&sc->vr_mtx); 928 929 return(0); 930 } 931 932 /* 933 * Initialize the transmit descriptors. 934 */ 935 static int 936 vr_list_tx_init(sc) 937 struct vr_softc *sc; 938 { 939 struct vr_chain_data *cd; 940 struct vr_list_data *ld; 941 int i; 942 943 cd = &sc->vr_cdata; 944 ld = sc->vr_ldata; 945 for (i = 0; i < VR_TX_LIST_CNT; i++) { 946 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 947 if (i == (VR_TX_LIST_CNT - 1)) 948 cd->vr_tx_chain[i].vr_nextdesc = 949 &cd->vr_tx_chain[0]; 950 else 951 cd->vr_tx_chain[i].vr_nextdesc = 952 &cd->vr_tx_chain[i + 1]; 953 } 954 955 cd->vr_tx_free = &cd->vr_tx_chain[0]; 956 cd->vr_tx_tail = cd->vr_tx_head = NULL; 957 958 return(0); 959 } 960 961 962 /* 963 * Initialize the RX descriptors and allocate mbufs for them. Note that 964 * we arrange the descriptors in a closed ring, so that the last descriptor 965 * points back to the first. 966 */ 967 static int 968 vr_list_rx_init(sc) 969 struct vr_softc *sc; 970 { 971 struct vr_chain_data *cd; 972 struct vr_list_data *ld; 973 int i; 974 975 cd = &sc->vr_cdata; 976 ld = sc->vr_ldata; 977 978 for (i = 0; i < VR_RX_LIST_CNT; i++) { 979 cd->vr_rx_chain[i].vr_ptr = 980 (struct vr_desc *)&ld->vr_rx_list[i]; 981 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 982 return(ENOBUFS); 983 if (i == (VR_RX_LIST_CNT - 1)) { 984 cd->vr_rx_chain[i].vr_nextdesc = 985 &cd->vr_rx_chain[0]; 986 ld->vr_rx_list[i].vr_next = 987 vtophys(&ld->vr_rx_list[0]); 988 } else { 989 cd->vr_rx_chain[i].vr_nextdesc = 990 &cd->vr_rx_chain[i + 1]; 991 ld->vr_rx_list[i].vr_next = 992 vtophys(&ld->vr_rx_list[i + 1]); 993 } 994 } 995 996 cd->vr_rx_head = &cd->vr_rx_chain[0]; 997 998 return(0); 999 } 1000 1001 /* 1002 * Initialize an RX descriptor and attach an MBUF cluster. 1003 * Note: the length fields are only 11 bits wide, which means the 1004 * largest size we can specify is 2047. This is important because 1005 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1006 * overflow the field and make a mess. 1007 */ 1008 static int 1009 vr_newbuf(sc, c, m) 1010 struct vr_softc *sc; 1011 struct vr_chain_onefrag *c; 1012 struct mbuf *m; 1013 { 1014 struct mbuf *m_new = NULL; 1015 1016 if (m == NULL) { 1017 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1018 if (m_new == NULL) 1019 return(ENOBUFS); 1020 1021 MCLGET(m_new, M_DONTWAIT); 1022 if (!(m_new->m_flags & M_EXT)) { 1023 m_freem(m_new); 1024 return(ENOBUFS); 1025 } 1026 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1027 } else { 1028 m_new = m; 1029 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 1030 m_new->m_data = m_new->m_ext.ext_buf; 1031 } 1032 1033 m_adj(m_new, sizeof(u_int64_t)); 1034 1035 c->vr_mbuf = m_new; 1036 c->vr_ptr->vr_status = VR_RXSTAT; 1037 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 1038 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 1039 1040 return(0); 1041 } 1042 1043 /* 1044 * A frame has been uploaded: pass the resulting mbuf chain up to 1045 * the higher level protocols. 1046 */ 1047 static void 1048 vr_rxeof(sc) 1049 struct vr_softc *sc; 1050 { 1051 struct mbuf *m; 1052 struct ifnet *ifp; 1053 struct vr_chain_onefrag *cur_rx; 1054 int total_len = 0; 1055 u_int32_t rxstat; 1056 1057 VR_LOCK_ASSERT(sc); 1058 1059 ifp = &sc->arpcom.ac_if; 1060 1061 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 1062 VR_RXSTAT_OWN)) { 1063 struct mbuf *m0 = NULL; 1064 1065 cur_rx = sc->vr_cdata.vr_rx_head; 1066 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 1067 m = cur_rx->vr_mbuf; 1068 1069 /* 1070 * If an error occurs, update stats, clear the 1071 * status word and leave the mbuf cluster in place: 1072 * it should simply get re-used next time this descriptor 1073 * comes up in the ring. 1074 */ 1075 if (rxstat & VR_RXSTAT_RXERR) { 1076 ifp->if_ierrors++; 1077 printf("vr%d: rx error (%02x):", 1078 sc->vr_unit, rxstat & 0x000000ff); 1079 if (rxstat & VR_RXSTAT_CRCERR) 1080 printf(" crc error"); 1081 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1082 printf(" frame alignment error\n"); 1083 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1084 printf(" FIFO overflow"); 1085 if (rxstat & VR_RXSTAT_GIANT) 1086 printf(" received giant packet"); 1087 if (rxstat & VR_RXSTAT_RUNT) 1088 printf(" received runt packet"); 1089 if (rxstat & VR_RXSTAT_BUSERR) 1090 printf(" system bus error"); 1091 if (rxstat & VR_RXSTAT_BUFFERR) 1092 printf("rx buffer error"); 1093 printf("\n"); 1094 vr_newbuf(sc, cur_rx, m); 1095 continue; 1096 } 1097 1098 /* No errors; receive the packet. */ 1099 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1100 1101 /* 1102 * XXX The VIA Rhine chip includes the CRC with every 1103 * received frame, and there's no way to turn this 1104 * behavior off (at least, I can't find anything in 1105 * the manual that explains how to do it) so we have 1106 * to trim off the CRC manually. 1107 */ 1108 total_len -= ETHER_CRC_LEN; 1109 1110 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1111 NULL); 1112 vr_newbuf(sc, cur_rx, m); 1113 if (m0 == NULL) { 1114 ifp->if_ierrors++; 1115 continue; 1116 } 1117 m = m0; 1118 1119 ifp->if_ipackets++; 1120 VR_UNLOCK(sc); 1121 (*ifp->if_input)(ifp, m); 1122 VR_LOCK(sc); 1123 } 1124 1125 return; 1126 } 1127 1128 static void 1129 vr_rxeoc(sc) 1130 struct vr_softc *sc; 1131 { 1132 struct ifnet *ifp; 1133 int i; 1134 1135 ifp = &sc->arpcom.ac_if; 1136 1137 ifp->if_ierrors++; 1138 1139 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1140 DELAY(10000); 1141 1142 for (i = 0x400; 1143 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1144 i--) 1145 ; /* Wait for receiver to stop */ 1146 1147 if (!i) { 1148 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1149 sc->vr_flags |= VR_F_RESTART; 1150 return; 1151 } 1152 1153 vr_rxeof(sc); 1154 1155 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1156 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1157 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1158 1159 return; 1160 } 1161 1162 /* 1163 * A frame was downloaded to the chip. It's safe for us to clean up 1164 * the list buffers. 1165 */ 1166 1167 static void 1168 vr_txeof(sc) 1169 struct vr_softc *sc; 1170 { 1171 struct vr_chain *cur_tx; 1172 struct ifnet *ifp; 1173 1174 ifp = &sc->arpcom.ac_if; 1175 1176 /* Reset the timeout timer; if_txeoc will clear it. */ 1177 ifp->if_timer = 5; 1178 1179 /* Sanity check. */ 1180 if (sc->vr_cdata.vr_tx_head == NULL) 1181 return; 1182 1183 /* 1184 * Go through our tx list and free mbufs for those 1185 * frames that have been transmitted. 1186 */ 1187 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1188 u_int32_t txstat; 1189 int i; 1190 1191 cur_tx = sc->vr_cdata.vr_tx_head; 1192 txstat = cur_tx->vr_ptr->vr_status; 1193 1194 if ((txstat & VR_TXSTAT_ABRT) || 1195 (txstat & VR_TXSTAT_UDF)) { 1196 for (i = 0x400; 1197 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1198 i--) 1199 ; /* Wait for chip to shutdown */ 1200 if (!i) { 1201 printf("vr%d: tx shutdown timeout\n", sc->vr_unit); 1202 sc->vr_flags |= VR_F_RESTART; 1203 break; 1204 } 1205 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1206 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1207 break; 1208 } 1209 1210 if (txstat & VR_TXSTAT_OWN) 1211 break; 1212 1213 if (txstat & VR_TXSTAT_ERRSUM) { 1214 ifp->if_oerrors++; 1215 if (txstat & VR_TXSTAT_DEFER) 1216 ifp->if_collisions++; 1217 if (txstat & VR_TXSTAT_LATECOLL) 1218 ifp->if_collisions++; 1219 } 1220 1221 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1222 1223 ifp->if_opackets++; 1224 if (cur_tx->vr_mbuf != NULL) { 1225 m_freem(cur_tx->vr_mbuf); 1226 cur_tx->vr_mbuf = NULL; 1227 } 1228 1229 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1230 sc->vr_cdata.vr_tx_head = NULL; 1231 sc->vr_cdata.vr_tx_tail = NULL; 1232 break; 1233 } 1234 1235 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1236 } 1237 1238 return; 1239 } 1240 1241 /* 1242 * TX 'end of channel' interrupt handler. 1243 */ 1244 static void 1245 vr_txeoc(sc) 1246 struct vr_softc *sc; 1247 { 1248 struct ifnet *ifp; 1249 1250 ifp = &sc->arpcom.ac_if; 1251 1252 if (sc->vr_cdata.vr_tx_head == NULL) { 1253 ifp->if_flags &= ~IFF_OACTIVE; 1254 sc->vr_cdata.vr_tx_tail = NULL; 1255 ifp->if_timer = 0; 1256 } 1257 1258 return; 1259 } 1260 1261 static void 1262 vr_tick(xsc) 1263 void *xsc; 1264 { 1265 struct vr_softc *sc; 1266 struct mii_data *mii; 1267 1268 sc = xsc; 1269 VR_LOCK(sc); 1270 if (sc->vr_flags & VR_F_RESTART) { 1271 printf("vr%d: restarting\n", sc->vr_unit); 1272 vr_stop(sc); 1273 vr_reset(sc); 1274 vr_init(sc); 1275 sc->vr_flags &= ~VR_F_RESTART; 1276 } 1277 1278 mii = device_get_softc(sc->vr_miibus); 1279 mii_tick(mii); 1280 1281 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1282 1283 VR_UNLOCK(sc); 1284 1285 return; 1286 } 1287 1288 static void 1289 vr_intr(arg) 1290 void *arg; 1291 { 1292 struct vr_softc *sc; 1293 struct ifnet *ifp; 1294 u_int16_t status; 1295 1296 sc = arg; 1297 VR_LOCK(sc); 1298 ifp = &sc->arpcom.ac_if; 1299 1300 /* Supress unwanted interrupts. */ 1301 if (!(ifp->if_flags & IFF_UP)) { 1302 vr_stop(sc); 1303 VR_UNLOCK(sc); 1304 return; 1305 } 1306 1307 /* Disable interrupts. */ 1308 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1309 1310 for (;;) { 1311 1312 status = CSR_READ_2(sc, VR_ISR); 1313 if (status) 1314 CSR_WRITE_2(sc, VR_ISR, status); 1315 1316 if ((status & VR_INTRS) == 0) 1317 break; 1318 1319 if (status & VR_ISR_RX_OK) 1320 vr_rxeof(sc); 1321 1322 if (status & VR_ISR_RX_DROPPED) { 1323 printf("vr%d: rx packet lost\n", sc->vr_unit); 1324 ifp->if_ierrors++; 1325 } 1326 1327 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1328 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1329 printf("vr%d: receive error (%04x)", 1330 sc->vr_unit, status); 1331 if (status & VR_ISR_RX_NOBUF) 1332 printf(" no buffers"); 1333 if (status & VR_ISR_RX_OFLOW) 1334 printf(" overflow"); 1335 if (status & VR_ISR_RX_DROPPED) 1336 printf(" packet lost"); 1337 printf("\n"); 1338 vr_rxeoc(sc); 1339 } 1340 1341 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1342 vr_reset(sc); 1343 vr_init(sc); 1344 break; 1345 } 1346 1347 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1348 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1349 vr_txeof(sc); 1350 if ((status & VR_ISR_UDFI) || 1351 (status & VR_ISR_TX_ABRT2) || 1352 (status & VR_ISR_TX_ABRT)) { 1353 ifp->if_oerrors++; 1354 if (sc->vr_cdata.vr_tx_head != NULL) { 1355 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1356 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1357 } 1358 } else 1359 vr_txeoc(sc); 1360 } 1361 1362 } 1363 1364 /* Re-enable interrupts. */ 1365 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1366 1367 if (ifp->if_snd.ifq_head != NULL) { 1368 vr_start(ifp); 1369 } 1370 1371 VR_UNLOCK(sc); 1372 1373 return; 1374 } 1375 1376 /* 1377 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1378 * pointers to the fragment pointers. 1379 */ 1380 static int 1381 vr_encap(sc, c, m_head) 1382 struct vr_softc *sc; 1383 struct vr_chain *c; 1384 struct mbuf *m_head; 1385 { 1386 int frag = 0; 1387 struct vr_desc *f = NULL; 1388 int total_len; 1389 struct mbuf *m; 1390 1391 m = m_head; 1392 total_len = 0; 1393 1394 /* 1395 * The VIA Rhine wants packet buffers to be longword 1396 * aligned, but very often our mbufs aren't. Rather than 1397 * waste time trying to decide when to copy and when not 1398 * to copy, just do it all the time. 1399 */ 1400 if (m != NULL) { 1401 struct mbuf *m_new = NULL; 1402 1403 m_new = m_defrag(m_head, M_DONTWAIT); 1404 if (m_new == NULL) { 1405 return(1); 1406 } 1407 1408 m_head = m_new; 1409 /* 1410 * The Rhine chip doesn't auto-pad, so we have to make 1411 * sure to pad short frames out to the minimum frame length 1412 * ourselves. 1413 */ 1414 if (m_head->m_len < VR_MIN_FRAMELEN) { 1415 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1416 m_new->m_len = m_new->m_pkthdr.len; 1417 } 1418 f = c->vr_ptr; 1419 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1420 f->vr_ctl = total_len = m_new->m_len; 1421 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1422 f->vr_status = 0; 1423 frag = 1; 1424 } 1425 1426 c->vr_mbuf = m_head; 1427 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1428 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1429 1430 return(0); 1431 } 1432 1433 /* 1434 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1435 * to the mbuf data regions directly in the transmit lists. We also save a 1436 * copy of the pointers since the transmit list fragment pointers are 1437 * physical addresses. 1438 */ 1439 1440 static void 1441 vr_start(ifp) 1442 struct ifnet *ifp; 1443 { 1444 struct vr_softc *sc; 1445 struct mbuf *m_head = NULL; 1446 struct vr_chain *cur_tx = NULL, *start_tx, *prev_tx; 1447 1448 sc = ifp->if_softc; 1449 1450 VR_LOCK(sc); 1451 1452 /* 1453 * Check for an available queue slot. If there are none, 1454 * punt. 1455 */ 1456 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1457 VR_UNLOCK(sc); 1458 return; 1459 } 1460 1461 start_tx = sc->vr_cdata.vr_tx_free; 1462 1463 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1464 IF_DEQUEUE(&ifp->if_snd, m_head); 1465 if (m_head == NULL) 1466 break; 1467 1468 /* Pick a descriptor off the free list. */ 1469 prev_tx = cur_tx; 1470 cur_tx = sc->vr_cdata.vr_tx_free; 1471 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1472 1473 /* Pack the data into the descriptor. */ 1474 if (vr_encap(sc, cur_tx, m_head)) { 1475 /* Rollback, send what we were able to encap. */ 1476 IF_PREPEND(&ifp->if_snd, m_head); 1477 sc->vr_cdata.vr_tx_free = cur_tx; 1478 cur_tx = prev_tx; 1479 break; 1480 } 1481 1482 if (cur_tx != start_tx) 1483 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1484 1485 /* 1486 * If there's a BPF listener, bounce a copy of this frame 1487 * to him. 1488 */ 1489 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1490 1491 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1492 } 1493 1494 /* 1495 * If there are no frames queued, bail. 1496 */ 1497 if (cur_tx == NULL) { 1498 VR_UNLOCK(sc); 1499 return; 1500 } 1501 1502 sc->vr_cdata.vr_tx_tail = cur_tx; 1503 1504 if (sc->vr_cdata.vr_tx_head == NULL) 1505 sc->vr_cdata.vr_tx_head = start_tx; 1506 1507 /* Tell the chip to start transmitting. */ 1508 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1509 1510 /* 1511 * Set a timeout in case the chip goes out to lunch. 1512 */ 1513 ifp->if_timer = 5; 1514 VR_UNLOCK(sc); 1515 1516 return; 1517 } 1518 1519 static void 1520 vr_init(xsc) 1521 void *xsc; 1522 { 1523 struct vr_softc *sc = xsc; 1524 struct ifnet *ifp = &sc->arpcom.ac_if; 1525 struct mii_data *mii; 1526 int i; 1527 1528 VR_LOCK(sc); 1529 1530 mii = device_get_softc(sc->vr_miibus); 1531 1532 /* 1533 * Cancel pending I/O and free all RX/TX buffers. 1534 */ 1535 vr_stop(sc); 1536 vr_reset(sc); 1537 1538 /* 1539 * Set our station address. 1540 */ 1541 for (i = 0; i < ETHER_ADDR_LEN; i++) 1542 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1543 1544 /* Set DMA size */ 1545 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1546 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1547 1548 /* 1549 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1550 * so we must set both. 1551 */ 1552 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1553 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1554 1555 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1556 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1557 1558 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1559 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1560 1561 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1562 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1563 1564 /* Init circular RX list. */ 1565 if (vr_list_rx_init(sc) == ENOBUFS) { 1566 printf("vr%d: initialization failed: no " 1567 "memory for rx buffers\n", sc->vr_unit); 1568 vr_stop(sc); 1569 VR_UNLOCK(sc); 1570 return; 1571 } 1572 1573 /* 1574 * Init tx descriptors. 1575 */ 1576 vr_list_tx_init(sc); 1577 1578 /* If we want promiscuous mode, set the allframes bit. */ 1579 if (ifp->if_flags & IFF_PROMISC) 1580 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1581 else 1582 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1583 1584 /* Set capture broadcast bit to capture broadcast frames. */ 1585 if (ifp->if_flags & IFF_BROADCAST) 1586 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1587 else 1588 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1589 1590 /* 1591 * Program the multicast filter, if necessary. 1592 */ 1593 vr_setmulti(sc); 1594 1595 /* 1596 * Load the address of the RX list. 1597 */ 1598 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1599 1600 /* Enable receiver and transmitter. */ 1601 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1602 VR_CMD_TX_ON|VR_CMD_RX_ON| 1603 VR_CMD_RX_GO); 1604 1605 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1606 1607 /* 1608 * Enable interrupts. 1609 */ 1610 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1611 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1612 1613 mii_mediachg(mii); 1614 1615 ifp->if_flags |= IFF_RUNNING; 1616 ifp->if_flags &= ~IFF_OACTIVE; 1617 1618 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1619 1620 VR_UNLOCK(sc); 1621 1622 return; 1623 } 1624 1625 /* 1626 * Set media options. 1627 */ 1628 static int 1629 vr_ifmedia_upd(ifp) 1630 struct ifnet *ifp; 1631 { 1632 struct vr_softc *sc; 1633 1634 sc = ifp->if_softc; 1635 1636 if (ifp->if_flags & IFF_UP) 1637 vr_init(sc); 1638 1639 return(0); 1640 } 1641 1642 /* 1643 * Report current media status. 1644 */ 1645 static void 1646 vr_ifmedia_sts(ifp, ifmr) 1647 struct ifnet *ifp; 1648 struct ifmediareq *ifmr; 1649 { 1650 struct vr_softc *sc; 1651 struct mii_data *mii; 1652 1653 sc = ifp->if_softc; 1654 mii = device_get_softc(sc->vr_miibus); 1655 mii_pollstat(mii); 1656 ifmr->ifm_active = mii->mii_media_active; 1657 ifmr->ifm_status = mii->mii_media_status; 1658 1659 return; 1660 } 1661 1662 static int 1663 vr_ioctl(ifp, command, data) 1664 struct ifnet *ifp; 1665 u_long command; 1666 caddr_t data; 1667 { 1668 struct vr_softc *sc = ifp->if_softc; 1669 struct ifreq *ifr = (struct ifreq *) data; 1670 struct mii_data *mii; 1671 int error = 0; 1672 1673 VR_LOCK(sc); 1674 1675 switch(command) { 1676 case SIOCSIFFLAGS: 1677 if (ifp->if_flags & IFF_UP) { 1678 vr_init(sc); 1679 } else { 1680 if (ifp->if_flags & IFF_RUNNING) 1681 vr_stop(sc); 1682 } 1683 error = 0; 1684 break; 1685 case SIOCADDMULTI: 1686 case SIOCDELMULTI: 1687 vr_setmulti(sc); 1688 error = 0; 1689 break; 1690 case SIOCGIFMEDIA: 1691 case SIOCSIFMEDIA: 1692 mii = device_get_softc(sc->vr_miibus); 1693 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1694 break; 1695 default: 1696 error = ether_ioctl(ifp, command, data); 1697 break; 1698 } 1699 1700 VR_UNLOCK(sc); 1701 1702 return(error); 1703 } 1704 1705 static void 1706 vr_watchdog(ifp) 1707 struct ifnet *ifp; 1708 { 1709 struct vr_softc *sc; 1710 1711 sc = ifp->if_softc; 1712 1713 VR_LOCK(sc); 1714 ifp->if_oerrors++; 1715 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1716 1717 vr_stop(sc); 1718 vr_reset(sc); 1719 vr_init(sc); 1720 1721 if (ifp->if_snd.ifq_head != NULL) 1722 vr_start(ifp); 1723 1724 VR_UNLOCK(sc); 1725 1726 return; 1727 } 1728 1729 /* 1730 * Stop the adapter and free any mbufs allocated to the 1731 * RX and TX lists. 1732 */ 1733 static void 1734 vr_stop(sc) 1735 struct vr_softc *sc; 1736 { 1737 register int i; 1738 struct ifnet *ifp; 1739 1740 VR_LOCK(sc); 1741 1742 ifp = &sc->arpcom.ac_if; 1743 ifp->if_timer = 0; 1744 1745 untimeout(vr_tick, sc, sc->vr_stat_ch); 1746 1747 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1748 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1749 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1750 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1751 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1752 1753 /* 1754 * Free data in the RX lists. 1755 */ 1756 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1757 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1758 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1759 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1760 } 1761 } 1762 bzero((char *)&sc->vr_ldata->vr_rx_list, 1763 sizeof(sc->vr_ldata->vr_rx_list)); 1764 1765 /* 1766 * Free the TX list buffers. 1767 */ 1768 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1769 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1770 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1771 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1772 } 1773 } 1774 1775 bzero((char *)&sc->vr_ldata->vr_tx_list, 1776 sizeof(sc->vr_ldata->vr_tx_list)); 1777 1778 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1779 VR_UNLOCK(sc); 1780 1781 return; 1782 } 1783 1784 /* 1785 * Stop all chip I/O so that the kernel's probe routines don't 1786 * get confused by errant DMAs when rebooting. 1787 */ 1788 static void 1789 vr_shutdown(dev) 1790 device_t dev; 1791 { 1792 struct vr_softc *sc; 1793 1794 sc = device_get_softc(dev); 1795 1796 vr_stop(sc); 1797 1798 return; 1799 } 1800