1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <pci/pcireg.h> 91 #include <pci/pcivar.h> 92 93 #define VR_USEIOSPACE 94 95 #include <pci/if_vrreg.h> 96 97 MODULE_DEPEND(vr, miibus, 1, 1, 1); 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #ifndef lint 103 static const char rcsid[] = 104 "$FreeBSD$"; 105 #endif 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 118 "Delta Electronics Rhine II 10/100BaseTX" }, 119 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 120 "Addtron Technology Rhine II 10/100BaseTX" }, 121 { 0, 0, NULL } 122 }; 123 124 static int vr_probe __P((device_t)); 125 static int vr_attach __P((device_t)); 126 static int vr_detach __P((device_t)); 127 128 static int vr_newbuf __P((struct vr_softc *, 129 struct vr_chain_onefrag *, 130 struct mbuf *)); 131 static int vr_encap __P((struct vr_softc *, struct vr_chain *, 132 struct mbuf * )); 133 134 static void vr_rxeof __P((struct vr_softc *)); 135 static void vr_rxeoc __P((struct vr_softc *)); 136 static void vr_txeof __P((struct vr_softc *)); 137 static void vr_txeoc __P((struct vr_softc *)); 138 static void vr_tick __P((void *)); 139 static void vr_intr __P((void *)); 140 static void vr_start __P((struct ifnet *)); 141 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 142 static void vr_init __P((void *)); 143 static void vr_stop __P((struct vr_softc *)); 144 static void vr_watchdog __P((struct ifnet *)); 145 static void vr_shutdown __P((device_t)); 146 static int vr_ifmedia_upd __P((struct ifnet *)); 147 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 148 149 static void vr_mii_sync __P((struct vr_softc *)); 150 static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 151 static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 152 static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 153 static int vr_miibus_readreg __P((device_t, int, int)); 154 static int vr_miibus_writereg __P((device_t, int, int, int)); 155 static void vr_miibus_statchg __P((device_t)); 156 157 static void vr_setcfg __P((struct vr_softc *, int)); 158 static u_int8_t vr_calchash __P((u_int8_t *)); 159 static void vr_setmulti __P((struct vr_softc *)); 160 static void vr_reset __P((struct vr_softc *)); 161 static int vr_list_rx_init __P((struct vr_softc *)); 162 static int vr_list_tx_init __P((struct vr_softc *)); 163 164 #ifdef VR_USEIOSPACE 165 #define VR_RES SYS_RES_IOPORT 166 #define VR_RID VR_PCI_LOIO 167 #else 168 #define VR_RES SYS_RES_MEMORY 169 #define VR_RID VR_PCI_LOMEM 170 #endif 171 172 static device_method_t vr_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, vr_probe), 175 DEVMETHOD(device_attach, vr_attach), 176 DEVMETHOD(device_detach, vr_detach), 177 DEVMETHOD(device_shutdown, vr_shutdown), 178 179 /* bus interface */ 180 DEVMETHOD(bus_print_child, bus_generic_print_child), 181 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182 183 /* MII interface */ 184 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 185 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 186 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 187 188 { 0, 0 } 189 }; 190 191 static driver_t vr_driver = { 192 "vr", 193 vr_methods, 194 sizeof(struct vr_softc) 195 }; 196 197 static devclass_t vr_devclass; 198 199 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 200 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 201 202 #define VR_SETBIT(sc, reg, x) \ 203 CSR_WRITE_1(sc, reg, \ 204 CSR_READ_1(sc, reg) | x) 205 206 #define VR_CLRBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) & ~x) 209 210 #define VR_SETBIT16(sc, reg, x) \ 211 CSR_WRITE_2(sc, reg, \ 212 CSR_READ_2(sc, reg) | x) 213 214 #define VR_CLRBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) & ~x) 217 218 #define VR_SETBIT32(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, \ 220 CSR_READ_4(sc, reg) | x) 221 222 #define VR_CLRBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) & ~x) 225 226 #define SIO_SET(x) \ 227 CSR_WRITE_1(sc, VR_MIICMD, \ 228 CSR_READ_1(sc, VR_MIICMD) | x) 229 230 #define SIO_CLR(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) & ~x) 233 234 /* 235 * Sync the PHYs by setting data bit and strobing the clock 32 times. 236 */ 237 static void vr_mii_sync(sc) 238 struct vr_softc *sc; 239 { 240 register int i; 241 242 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 243 244 for (i = 0; i < 32; i++) { 245 SIO_SET(VR_MIICMD_CLK); 246 DELAY(1); 247 SIO_CLR(VR_MIICMD_CLK); 248 DELAY(1); 249 } 250 251 return; 252 } 253 254 /* 255 * Clock a series of bits through the MII. 256 */ 257 static void vr_mii_send(sc, bits, cnt) 258 struct vr_softc *sc; 259 u_int32_t bits; 260 int cnt; 261 { 262 int i; 263 264 SIO_CLR(VR_MIICMD_CLK); 265 266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 267 if (bits & i) { 268 SIO_SET(VR_MIICMD_DATAIN); 269 } else { 270 SIO_CLR(VR_MIICMD_DATAIN); 271 } 272 DELAY(1); 273 SIO_CLR(VR_MIICMD_CLK); 274 DELAY(1); 275 SIO_SET(VR_MIICMD_CLK); 276 } 277 } 278 279 /* 280 * Read an PHY register through the MII. 281 */ 282 static int vr_mii_readreg(sc, frame) 283 struct vr_softc *sc; 284 struct vr_mii_frame *frame; 285 286 { 287 int i, ack; 288 289 VR_LOCK(sc); 290 291 /* 292 * Set up frame for RX. 293 */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* 303 * Turn on data xmit. 304 */ 305 SIO_SET(VR_MIICMD_DIR); 306 307 vr_mii_sync(sc); 308 309 /* 310 * Send command/address info. 311 */ 312 vr_mii_send(sc, frame->mii_stdelim, 2); 313 vr_mii_send(sc, frame->mii_opcode, 2); 314 vr_mii_send(sc, frame->mii_phyaddr, 5); 315 vr_mii_send(sc, frame->mii_regaddr, 5); 316 317 /* Idle bit */ 318 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 319 DELAY(1); 320 SIO_SET(VR_MIICMD_CLK); 321 DELAY(1); 322 323 /* Turn off xmit. */ 324 SIO_CLR(VR_MIICMD_DIR); 325 326 /* Check for ack */ 327 SIO_CLR(VR_MIICMD_CLK); 328 DELAY(1); 329 SIO_SET(VR_MIICMD_CLK); 330 DELAY(1); 331 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 332 333 /* 334 * Now try reading data bits. If the ack failed, we still 335 * need to clock through 16 cycles to keep the PHY(s) in sync. 336 */ 337 if (ack) { 338 for(i = 0; i < 16; i++) { 339 SIO_CLR(VR_MIICMD_CLK); 340 DELAY(1); 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 } 344 goto fail; 345 } 346 347 for (i = 0x8000; i; i >>= 1) { 348 SIO_CLR(VR_MIICMD_CLK); 349 DELAY(1); 350 if (!ack) { 351 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 352 frame->mii_data |= i; 353 DELAY(1); 354 } 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 } 358 359 fail: 360 361 SIO_CLR(VR_MIICMD_CLK); 362 DELAY(1); 363 SIO_SET(VR_MIICMD_CLK); 364 DELAY(1); 365 366 VR_UNLOCK(sc); 367 368 if (ack) 369 return(1); 370 return(0); 371 } 372 373 /* 374 * Write to a PHY register through the MII. 375 */ 376 static int vr_mii_writereg(sc, frame) 377 struct vr_softc *sc; 378 struct vr_mii_frame *frame; 379 380 { 381 VR_LOCK(sc); 382 383 CSR_WRITE_1(sc, VR_MIICMD, 0); 384 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 385 386 /* 387 * Set up frame for TX. 388 */ 389 390 frame->mii_stdelim = VR_MII_STARTDELIM; 391 frame->mii_opcode = VR_MII_WRITEOP; 392 frame->mii_turnaround = VR_MII_TURNAROUND; 393 394 /* 395 * Turn on data output. 396 */ 397 SIO_SET(VR_MIICMD_DIR); 398 399 vr_mii_sync(sc); 400 401 vr_mii_send(sc, frame->mii_stdelim, 2); 402 vr_mii_send(sc, frame->mii_opcode, 2); 403 vr_mii_send(sc, frame->mii_phyaddr, 5); 404 vr_mii_send(sc, frame->mii_regaddr, 5); 405 vr_mii_send(sc, frame->mii_turnaround, 2); 406 vr_mii_send(sc, frame->mii_data, 16); 407 408 /* Idle bit. */ 409 SIO_SET(VR_MIICMD_CLK); 410 DELAY(1); 411 SIO_CLR(VR_MIICMD_CLK); 412 DELAY(1); 413 414 /* 415 * Turn off xmit. 416 */ 417 SIO_CLR(VR_MIICMD_DIR); 418 419 VR_UNLOCK(sc); 420 421 return(0); 422 } 423 424 static int vr_miibus_readreg(dev, phy, reg) 425 device_t dev; 426 int phy, reg; 427 { 428 struct vr_softc *sc; 429 struct vr_mii_frame frame; 430 431 sc = device_get_softc(dev); 432 bzero((char *)&frame, sizeof(frame)); 433 434 frame.mii_phyaddr = phy; 435 frame.mii_regaddr = reg; 436 vr_mii_readreg(sc, &frame); 437 438 return(frame.mii_data); 439 } 440 441 static int vr_miibus_writereg(dev, phy, reg, data) 442 device_t dev; 443 u_int16_t phy, reg, data; 444 { 445 struct vr_softc *sc; 446 struct vr_mii_frame frame; 447 448 sc = device_get_softc(dev); 449 bzero((char *)&frame, sizeof(frame)); 450 451 frame.mii_phyaddr = phy; 452 frame.mii_regaddr = reg; 453 frame.mii_data = data; 454 455 vr_mii_writereg(sc, &frame); 456 457 return(0); 458 } 459 460 static void vr_miibus_statchg(dev) 461 device_t dev; 462 { 463 struct vr_softc *sc; 464 struct mii_data *mii; 465 466 sc = device_get_softc(dev); 467 VR_LOCK(sc); 468 mii = device_get_softc(sc->vr_miibus); 469 vr_setcfg(sc, mii->mii_media_active); 470 VR_UNLOCK(sc); 471 472 return; 473 } 474 475 /* 476 * Calculate CRC of a multicast group address, return the lower 6 bits. 477 */ 478 static u_int8_t vr_calchash(addr) 479 u_int8_t *addr; 480 { 481 u_int32_t crc, carry; 482 int i, j; 483 u_int8_t c; 484 485 /* Compute CRC for the address value. */ 486 crc = 0xFFFFFFFF; /* initial value */ 487 488 for (i = 0; i < 6; i++) { 489 c = *(addr + i); 490 for (j = 0; j < 8; j++) { 491 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 492 crc <<= 1; 493 c >>= 1; 494 if (carry) 495 crc = (crc ^ 0x04c11db6) | carry; 496 } 497 } 498 499 /* return the filter bit position */ 500 return((crc >> 26) & 0x0000003F); 501 } 502 503 /* 504 * Program the 64-bit multicast hash filter. 505 */ 506 static void vr_setmulti(sc) 507 struct vr_softc *sc; 508 { 509 struct ifnet *ifp; 510 int h = 0; 511 u_int32_t hashes[2] = { 0, 0 }; 512 struct ifmultiaddr *ifma; 513 u_int8_t rxfilt; 514 int mcnt = 0; 515 516 ifp = &sc->arpcom.ac_if; 517 518 rxfilt = CSR_READ_1(sc, VR_RXCFG); 519 520 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 521 rxfilt |= VR_RXCFG_RX_MULTI; 522 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 523 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 524 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 525 return; 526 } 527 528 /* first, zot all the existing hash bits */ 529 CSR_WRITE_4(sc, VR_MAR0, 0); 530 CSR_WRITE_4(sc, VR_MAR1, 0); 531 532 /* now program new ones */ 533 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 534 if (ifma->ifma_addr->sa_family != AF_LINK) 535 continue; 536 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 537 if (h < 32) 538 hashes[0] |= (1 << h); 539 else 540 hashes[1] |= (1 << (h - 32)); 541 mcnt++; 542 } 543 544 if (mcnt) 545 rxfilt |= VR_RXCFG_RX_MULTI; 546 else 547 rxfilt &= ~VR_RXCFG_RX_MULTI; 548 549 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 550 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 551 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 552 553 return; 554 } 555 556 /* 557 * In order to fiddle with the 558 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 559 * first have to put the transmit and/or receive logic in the idle state. 560 */ 561 static void vr_setcfg(sc, media) 562 struct vr_softc *sc; 563 int media; 564 { 565 int restart = 0; 566 567 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 568 restart = 1; 569 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 570 } 571 572 if ((media & IFM_GMASK) == IFM_FDX) 573 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 574 else 575 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 577 if (restart) 578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 579 580 return; 581 } 582 583 static void vr_reset(sc) 584 struct vr_softc *sc; 585 { 586 register int i; 587 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 589 590 for (i = 0; i < VR_TIMEOUT; i++) { 591 DELAY(10); 592 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 593 break; 594 } 595 if (i == VR_TIMEOUT) 596 printf("vr%d: reset never completed!\n", sc->vr_unit); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600 601 return; 602 } 603 604 /* 605 * Probe for a VIA Rhine chip. Check the PCI vendor and device 606 * IDs against our list and return a device name if we find a match. 607 */ 608 static int vr_probe(dev) 609 device_t dev; 610 { 611 struct vr_type *t; 612 613 t = vr_devs; 614 615 while(t->vr_name != NULL) { 616 if ((pci_get_vendor(dev) == t->vr_vid) && 617 (pci_get_device(dev) == t->vr_did)) { 618 device_set_desc(dev, t->vr_name); 619 return(0); 620 } 621 t++; 622 } 623 624 return(ENXIO); 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 static int vr_attach(dev) 632 device_t dev; 633 { 634 int i; 635 u_char eaddr[ETHER_ADDR_LEN]; 636 u_int32_t command; 637 struct vr_softc *sc; 638 struct ifnet *ifp; 639 int unit, error = 0, rid; 640 641 sc = device_get_softc(dev); 642 unit = device_get_unit(dev); 643 bzero(sc, sizeof(struct vr_softc *)); 644 645 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE); 646 VR_LOCK(sc); 647 648 /* 649 * Handle power management nonsense. 650 */ 651 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 652 u_int32_t iobase, membase, irq; 653 654 /* Save important PCI config data. */ 655 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 656 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 657 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 658 659 /* Reset the power state. */ 660 printf("vr%d: chip is in D%d power mode " 661 "-- setting to D0\n", unit, 662 pci_get_powerstate(dev)); 663 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 664 665 /* Restore PCI config data. */ 666 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 667 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 668 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 669 } 670 671 /* 672 * Map control/status registers. 673 */ 674 pci_enable_busmaster(dev); 675 pci_enable_io(dev, PCIM_CMD_PORTEN); 676 pci_enable_io(dev, PCIM_CMD_MEMEN); 677 command = pci_read_config(dev, PCIR_COMMAND, 4); 678 679 #ifdef VR_USEIOSPACE 680 if (!(command & PCIM_CMD_PORTEN)) { 681 printf("vr%d: failed to enable I/O ports!\n", unit); 682 free(sc, M_DEVBUF); 683 goto fail; 684 } 685 #else 686 if (!(command & PCIM_CMD_MEMEN)) { 687 printf("vr%d: failed to enable memory mapping!\n", unit); 688 goto fail; 689 } 690 #endif 691 692 rid = VR_RID; 693 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 694 0, ~0, 1, RF_ACTIVE); 695 696 if (sc->vr_res == NULL) { 697 printf("vr%d: couldn't map ports/memory\n", unit); 698 error = ENXIO; 699 goto fail; 700 } 701 702 sc->vr_btag = rman_get_bustag(sc->vr_res); 703 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 704 705 /* Allocate interrupt */ 706 rid = 0; 707 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 708 RF_SHAREABLE | RF_ACTIVE); 709 710 if (sc->vr_irq == NULL) { 711 printf("vr%d: couldn't map interrupt\n", unit); 712 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 713 error = ENXIO; 714 goto fail; 715 } 716 717 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 718 vr_intr, sc, &sc->vr_intrhand); 719 720 if (error) { 721 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 722 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 723 printf("vr%d: couldn't set up irq\n", unit); 724 goto fail; 725 } 726 727 /* Reset the adapter. */ 728 vr_reset(sc); 729 730 /* 731 * Get station address. The way the Rhine chips work, 732 * you're not allowed to directly access the EEPROM once 733 * they've been programmed a special way. Consequently, 734 * we need to read the node address from the PAR0 and PAR1 735 * registers. 736 */ 737 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 738 DELAY(200); 739 for (i = 0; i < ETHER_ADDR_LEN; i++) 740 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 741 742 /* 743 * A Rhine chip was detected. Inform the world. 744 */ 745 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 746 747 sc->vr_unit = unit; 748 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 749 750 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 751 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 752 753 if (sc->vr_ldata == NULL) { 754 printf("vr%d: no memory for list buffers!\n", unit); 755 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 756 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 757 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 758 error = ENXIO; 759 goto fail; 760 } 761 762 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 763 764 ifp = &sc->arpcom.ac_if; 765 ifp->if_softc = sc; 766 ifp->if_unit = unit; 767 ifp->if_name = "vr"; 768 ifp->if_mtu = ETHERMTU; 769 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 770 ifp->if_ioctl = vr_ioctl; 771 ifp->if_output = ether_output; 772 ifp->if_start = vr_start; 773 ifp->if_watchdog = vr_watchdog; 774 ifp->if_init = vr_init; 775 ifp->if_baudrate = 10000000; 776 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 777 778 /* 779 * Do MII setup. 780 */ 781 if (mii_phy_probe(dev, &sc->vr_miibus, 782 vr_ifmedia_upd, vr_ifmedia_sts)) { 783 printf("vr%d: MII without any phy!\n", sc->vr_unit); 784 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 785 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 786 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 787 contigfree(sc->vr_ldata, 788 sizeof(struct vr_list_data), M_DEVBUF); 789 error = ENXIO; 790 goto fail; 791 } 792 793 callout_handle_init(&sc->vr_stat_ch); 794 795 /* 796 * Call MI attach routine. 797 */ 798 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 799 VR_UNLOCK(sc); 800 return(0); 801 802 fail: 803 VR_UNLOCK(sc); 804 mtx_destroy(&sc->vr_mtx); 805 806 return(error); 807 } 808 809 static int vr_detach(dev) 810 device_t dev; 811 { 812 struct vr_softc *sc; 813 struct ifnet *ifp; 814 815 sc = device_get_softc(dev); 816 VR_LOCK(sc); 817 ifp = &sc->arpcom.ac_if; 818 819 vr_stop(sc); 820 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 821 822 bus_generic_detach(dev); 823 device_delete_child(dev, sc->vr_miibus); 824 825 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 826 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 827 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 828 829 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 830 831 VR_UNLOCK(sc); 832 mtx_destroy(&sc->vr_mtx); 833 834 return(0); 835 } 836 837 /* 838 * Initialize the transmit descriptors. 839 */ 840 static int vr_list_tx_init(sc) 841 struct vr_softc *sc; 842 { 843 struct vr_chain_data *cd; 844 struct vr_list_data *ld; 845 int i; 846 847 cd = &sc->vr_cdata; 848 ld = sc->vr_ldata; 849 for (i = 0; i < VR_TX_LIST_CNT; i++) { 850 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 851 if (i == (VR_TX_LIST_CNT - 1)) 852 cd->vr_tx_chain[i].vr_nextdesc = 853 &cd->vr_tx_chain[0]; 854 else 855 cd->vr_tx_chain[i].vr_nextdesc = 856 &cd->vr_tx_chain[i + 1]; 857 } 858 859 cd->vr_tx_free = &cd->vr_tx_chain[0]; 860 cd->vr_tx_tail = cd->vr_tx_head = NULL; 861 862 return(0); 863 } 864 865 866 /* 867 * Initialize the RX descriptors and allocate mbufs for them. Note that 868 * we arrange the descriptors in a closed ring, so that the last descriptor 869 * points back to the first. 870 */ 871 static int vr_list_rx_init(sc) 872 struct vr_softc *sc; 873 { 874 struct vr_chain_data *cd; 875 struct vr_list_data *ld; 876 int i; 877 878 cd = &sc->vr_cdata; 879 ld = sc->vr_ldata; 880 881 for (i = 0; i < VR_RX_LIST_CNT; i++) { 882 cd->vr_rx_chain[i].vr_ptr = 883 (struct vr_desc *)&ld->vr_rx_list[i]; 884 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 885 return(ENOBUFS); 886 if (i == (VR_RX_LIST_CNT - 1)) { 887 cd->vr_rx_chain[i].vr_nextdesc = 888 &cd->vr_rx_chain[0]; 889 ld->vr_rx_list[i].vr_next = 890 vtophys(&ld->vr_rx_list[0]); 891 } else { 892 cd->vr_rx_chain[i].vr_nextdesc = 893 &cd->vr_rx_chain[i + 1]; 894 ld->vr_rx_list[i].vr_next = 895 vtophys(&ld->vr_rx_list[i + 1]); 896 } 897 } 898 899 cd->vr_rx_head = &cd->vr_rx_chain[0]; 900 901 return(0); 902 } 903 904 /* 905 * Initialize an RX descriptor and attach an MBUF cluster. 906 * Note: the length fields are only 11 bits wide, which means the 907 * largest size we can specify is 2047. This is important because 908 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 909 * overflow the field and make a mess. 910 */ 911 static int vr_newbuf(sc, c, m) 912 struct vr_softc *sc; 913 struct vr_chain_onefrag *c; 914 struct mbuf *m; 915 { 916 struct mbuf *m_new = NULL; 917 918 if (m == NULL) { 919 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 920 if (m_new == NULL) { 921 printf("vr%d: no memory for rx list " 922 "-- packet dropped!\n", sc->vr_unit); 923 return(ENOBUFS); 924 } 925 926 MCLGET(m_new, M_DONTWAIT); 927 if (!(m_new->m_flags & M_EXT)) { 928 printf("vr%d: no memory for rx list " 929 "-- packet dropped!\n", sc->vr_unit); 930 m_freem(m_new); 931 return(ENOBUFS); 932 } 933 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 934 } else { 935 m_new = m; 936 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 937 m_new->m_data = m_new->m_ext.ext_buf; 938 } 939 940 m_adj(m_new, sizeof(u_int64_t)); 941 942 c->vr_mbuf = m_new; 943 c->vr_ptr->vr_status = VR_RXSTAT; 944 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 945 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 946 947 return(0); 948 } 949 950 /* 951 * A frame has been uploaded: pass the resulting mbuf chain up to 952 * the higher level protocols. 953 */ 954 static void vr_rxeof(sc) 955 struct vr_softc *sc; 956 { 957 struct ether_header *eh; 958 struct mbuf *m; 959 struct ifnet *ifp; 960 struct vr_chain_onefrag *cur_rx; 961 int total_len = 0; 962 u_int32_t rxstat; 963 964 ifp = &sc->arpcom.ac_if; 965 966 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 967 VR_RXSTAT_OWN)) { 968 struct mbuf *m0 = NULL; 969 970 cur_rx = sc->vr_cdata.vr_rx_head; 971 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 972 m = cur_rx->vr_mbuf; 973 974 /* 975 * If an error occurs, update stats, clear the 976 * status word and leave the mbuf cluster in place: 977 * it should simply get re-used next time this descriptor 978 * comes up in the ring. 979 */ 980 if (rxstat & VR_RXSTAT_RXERR) { 981 ifp->if_ierrors++; 982 printf("vr%d: rx error: ", sc->vr_unit); 983 switch(rxstat & 0x000000FF) { 984 case VR_RXSTAT_CRCERR: 985 printf("crc error\n"); 986 break; 987 case VR_RXSTAT_FRAMEALIGNERR: 988 printf("frame alignment error\n"); 989 break; 990 case VR_RXSTAT_FIFOOFLOW: 991 printf("FIFO overflow\n"); 992 break; 993 case VR_RXSTAT_GIANT: 994 printf("received giant packet\n"); 995 break; 996 case VR_RXSTAT_RUNT: 997 printf("received runt packet\n"); 998 break; 999 case VR_RXSTAT_BUSERR: 1000 printf("system bus error\n"); 1001 break; 1002 case VR_RXSTAT_BUFFERR: 1003 printf("rx buffer error\n"); 1004 break; 1005 default: 1006 printf("unknown rx error\n"); 1007 break; 1008 } 1009 vr_newbuf(sc, cur_rx, m); 1010 continue; 1011 } 1012 1013 /* No errors; receive the packet. */ 1014 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1015 1016 /* 1017 * XXX The VIA Rhine chip includes the CRC with every 1018 * received frame, and there's no way to turn this 1019 * behavior off (at least, I can't find anything in 1020 * the manual that explains how to do it) so we have 1021 * to trim off the CRC manually. 1022 */ 1023 total_len -= ETHER_CRC_LEN; 1024 1025 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1026 total_len + ETHER_ALIGN, 0, ifp, NULL); 1027 vr_newbuf(sc, cur_rx, m); 1028 if (m0 == NULL) { 1029 ifp->if_ierrors++; 1030 continue; 1031 } 1032 m_adj(m0, ETHER_ALIGN); 1033 m = m0; 1034 1035 ifp->if_ipackets++; 1036 eh = mtod(m, struct ether_header *); 1037 1038 /* Remove header from mbuf and pass it on. */ 1039 m_adj(m, sizeof(struct ether_header)); 1040 ether_input(ifp, eh, m); 1041 } 1042 1043 return; 1044 } 1045 1046 void vr_rxeoc(sc) 1047 struct vr_softc *sc; 1048 { 1049 1050 vr_rxeof(sc); 1051 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1052 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1053 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1054 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1055 1056 return; 1057 } 1058 1059 /* 1060 * A frame was downloaded to the chip. It's safe for us to clean up 1061 * the list buffers. 1062 */ 1063 1064 static void vr_txeof(sc) 1065 struct vr_softc *sc; 1066 { 1067 struct vr_chain *cur_tx; 1068 struct ifnet *ifp; 1069 1070 ifp = &sc->arpcom.ac_if; 1071 1072 /* Clear the timeout timer. */ 1073 ifp->if_timer = 0; 1074 1075 /* Sanity check. */ 1076 if (sc->vr_cdata.vr_tx_head == NULL) 1077 return; 1078 1079 /* 1080 * Go through our tx list and free mbufs for those 1081 * frames that have been transmitted. 1082 */ 1083 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1084 u_int32_t txstat; 1085 1086 cur_tx = sc->vr_cdata.vr_tx_head; 1087 txstat = cur_tx->vr_ptr->vr_status; 1088 1089 if (txstat & VR_TXSTAT_OWN) 1090 break; 1091 1092 if (txstat & VR_TXSTAT_ERRSUM) { 1093 ifp->if_oerrors++; 1094 if (txstat & VR_TXSTAT_DEFER) 1095 ifp->if_collisions++; 1096 if (txstat & VR_TXSTAT_LATECOLL) 1097 ifp->if_collisions++; 1098 } 1099 1100 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1101 1102 ifp->if_opackets++; 1103 if (cur_tx->vr_mbuf != NULL) { 1104 m_freem(cur_tx->vr_mbuf); 1105 cur_tx->vr_mbuf = NULL; 1106 } 1107 1108 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1109 sc->vr_cdata.vr_tx_head = NULL; 1110 sc->vr_cdata.vr_tx_tail = NULL; 1111 break; 1112 } 1113 1114 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1115 } 1116 1117 return; 1118 } 1119 1120 /* 1121 * TX 'end of channel' interrupt handler. 1122 */ 1123 static void vr_txeoc(sc) 1124 struct vr_softc *sc; 1125 { 1126 struct ifnet *ifp; 1127 1128 ifp = &sc->arpcom.ac_if; 1129 1130 ifp->if_timer = 0; 1131 1132 if (sc->vr_cdata.vr_tx_head == NULL) { 1133 ifp->if_flags &= ~IFF_OACTIVE; 1134 sc->vr_cdata.vr_tx_tail = NULL; 1135 } 1136 1137 return; 1138 } 1139 1140 static void vr_tick(xsc) 1141 void *xsc; 1142 { 1143 struct vr_softc *sc; 1144 struct mii_data *mii; 1145 1146 sc = xsc; 1147 VR_LOCK(sc); 1148 mii = device_get_softc(sc->vr_miibus); 1149 mii_tick(mii); 1150 1151 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1152 1153 VR_UNLOCK(sc); 1154 1155 return; 1156 } 1157 1158 static void vr_intr(arg) 1159 void *arg; 1160 { 1161 struct vr_softc *sc; 1162 struct ifnet *ifp; 1163 u_int16_t status; 1164 1165 sc = arg; 1166 VR_LOCK(sc); 1167 ifp = &sc->arpcom.ac_if; 1168 1169 /* Supress unwanted interrupts. */ 1170 if (!(ifp->if_flags & IFF_UP)) { 1171 vr_stop(sc); 1172 VR_UNLOCK(sc); 1173 return; 1174 } 1175 1176 /* Disable interrupts. */ 1177 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1178 1179 for (;;) { 1180 1181 status = CSR_READ_2(sc, VR_ISR); 1182 if (status) 1183 CSR_WRITE_2(sc, VR_ISR, status); 1184 1185 if ((status & VR_INTRS) == 0) 1186 break; 1187 1188 if (status & VR_ISR_RX_OK) 1189 vr_rxeof(sc); 1190 1191 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1192 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1193 (status & VR_ISR_RX_DROPPED)) { 1194 vr_rxeof(sc); 1195 vr_rxeoc(sc); 1196 } 1197 1198 if (status & VR_ISR_TX_OK) { 1199 vr_txeof(sc); 1200 vr_txeoc(sc); 1201 } 1202 1203 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1204 ifp->if_oerrors++; 1205 vr_txeof(sc); 1206 if (sc->vr_cdata.vr_tx_head != NULL) { 1207 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1208 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1209 } 1210 } 1211 1212 if (status & VR_ISR_BUSERR) { 1213 vr_reset(sc); 1214 vr_init(sc); 1215 } 1216 } 1217 1218 /* Re-enable interrupts. */ 1219 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1220 1221 if (ifp->if_snd.ifq_head != NULL) { 1222 vr_start(ifp); 1223 } 1224 1225 VR_UNLOCK(sc); 1226 1227 return; 1228 } 1229 1230 /* 1231 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1232 * pointers to the fragment pointers. 1233 */ 1234 static int vr_encap(sc, c, m_head) 1235 struct vr_softc *sc; 1236 struct vr_chain *c; 1237 struct mbuf *m_head; 1238 { 1239 int frag = 0; 1240 struct vr_desc *f = NULL; 1241 int total_len; 1242 struct mbuf *m; 1243 1244 m = m_head; 1245 total_len = 0; 1246 1247 /* 1248 * The VIA Rhine wants packet buffers to be longword 1249 * aligned, but very often our mbufs aren't. Rather than 1250 * waste time trying to decide when to copy and when not 1251 * to copy, just do it all the time. 1252 */ 1253 if (m != NULL) { 1254 struct mbuf *m_new = NULL; 1255 1256 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1257 if (m_new == NULL) { 1258 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1259 return(1); 1260 } 1261 if (m_head->m_pkthdr.len > MHLEN) { 1262 MCLGET(m_new, M_DONTWAIT); 1263 if (!(m_new->m_flags & M_EXT)) { 1264 m_freem(m_new); 1265 printf("vr%d: no memory for tx list\n", 1266 sc->vr_unit); 1267 return(1); 1268 } 1269 } 1270 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1271 mtod(m_new, caddr_t)); 1272 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1273 m_freem(m_head); 1274 m_head = m_new; 1275 /* 1276 * The Rhine chip doesn't auto-pad, so we have to make 1277 * sure to pad short frames out to the minimum frame length 1278 * ourselves. 1279 */ 1280 if (m_head->m_len < VR_MIN_FRAMELEN) { 1281 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1282 m_new->m_len = m_new->m_pkthdr.len; 1283 } 1284 f = c->vr_ptr; 1285 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1286 f->vr_ctl = total_len = m_new->m_len; 1287 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1288 f->vr_status = 0; 1289 frag = 1; 1290 } 1291 1292 c->vr_mbuf = m_head; 1293 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1294 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1295 1296 return(0); 1297 } 1298 1299 /* 1300 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1301 * to the mbuf data regions directly in the transmit lists. We also save a 1302 * copy of the pointers since the transmit list fragment pointers are 1303 * physical addresses. 1304 */ 1305 1306 static void vr_start(ifp) 1307 struct ifnet *ifp; 1308 { 1309 struct vr_softc *sc; 1310 struct mbuf *m_head = NULL; 1311 struct vr_chain *cur_tx = NULL, *start_tx; 1312 1313 sc = ifp->if_softc; 1314 1315 VR_LOCK(sc); 1316 if (ifp->if_flags & IFF_OACTIVE) { 1317 VR_UNLOCK(sc); 1318 return; 1319 } 1320 1321 /* 1322 * Check for an available queue slot. If there are none, 1323 * punt. 1324 */ 1325 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1326 ifp->if_flags |= IFF_OACTIVE; 1327 return; 1328 } 1329 1330 start_tx = sc->vr_cdata.vr_tx_free; 1331 1332 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1333 IF_DEQUEUE(&ifp->if_snd, m_head); 1334 if (m_head == NULL) 1335 break; 1336 1337 /* Pick a descriptor off the free list. */ 1338 cur_tx = sc->vr_cdata.vr_tx_free; 1339 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1340 1341 /* Pack the data into the descriptor. */ 1342 if (vr_encap(sc, cur_tx, m_head)) { 1343 IF_PREPEND(&ifp->if_snd, m_head); 1344 ifp->if_flags |= IFF_OACTIVE; 1345 cur_tx = NULL; 1346 break; 1347 } 1348 1349 if (cur_tx != start_tx) 1350 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1351 1352 /* 1353 * If there's a BPF listener, bounce a copy of this frame 1354 * to him. 1355 */ 1356 if (ifp->if_bpf) 1357 bpf_mtap(ifp, cur_tx->vr_mbuf); 1358 1359 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1360 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1361 } 1362 1363 /* 1364 * If there are no frames queued, bail. 1365 */ 1366 if (cur_tx == NULL) { 1367 VR_UNLOCK(sc); 1368 return; 1369 } 1370 1371 sc->vr_cdata.vr_tx_tail = cur_tx; 1372 1373 if (sc->vr_cdata.vr_tx_head == NULL) 1374 sc->vr_cdata.vr_tx_head = start_tx; 1375 1376 /* 1377 * Set a timeout in case the chip goes out to lunch. 1378 */ 1379 ifp->if_timer = 5; 1380 VR_UNLOCK(sc); 1381 1382 return; 1383 } 1384 1385 static void vr_init(xsc) 1386 void *xsc; 1387 { 1388 struct vr_softc *sc = xsc; 1389 struct ifnet *ifp = &sc->arpcom.ac_if; 1390 struct mii_data *mii; 1391 int i; 1392 1393 VR_LOCK(sc); 1394 1395 mii = device_get_softc(sc->vr_miibus); 1396 1397 /* 1398 * Cancel pending I/O and free all RX/TX buffers. 1399 */ 1400 vr_stop(sc); 1401 vr_reset(sc); 1402 1403 /* 1404 * Set our station address. 1405 */ 1406 for (i = 0; i < ETHER_ADDR_LEN; i++) 1407 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1408 1409 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1410 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1411 1412 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1413 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1414 1415 /* Init circular RX list. */ 1416 if (vr_list_rx_init(sc) == ENOBUFS) { 1417 printf("vr%d: initialization failed: no " 1418 "memory for rx buffers\n", sc->vr_unit); 1419 vr_stop(sc); 1420 VR_UNLOCK(sc); 1421 return; 1422 } 1423 1424 /* 1425 * Init tx descriptors. 1426 */ 1427 vr_list_tx_init(sc); 1428 1429 /* If we want promiscuous mode, set the allframes bit. */ 1430 if (ifp->if_flags & IFF_PROMISC) 1431 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1432 else 1433 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1434 1435 /* Set capture broadcast bit to capture broadcast frames. */ 1436 if (ifp->if_flags & IFF_BROADCAST) 1437 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1438 else 1439 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1440 1441 /* 1442 * Program the multicast filter, if necessary. 1443 */ 1444 vr_setmulti(sc); 1445 1446 /* 1447 * Load the address of the RX list. 1448 */ 1449 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1450 1451 /* Enable receiver and transmitter. */ 1452 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1453 VR_CMD_TX_ON|VR_CMD_RX_ON| 1454 VR_CMD_RX_GO); 1455 1456 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1457 1458 /* 1459 * Enable interrupts. 1460 */ 1461 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1462 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1463 1464 mii_mediachg(mii); 1465 1466 ifp->if_flags |= IFF_RUNNING; 1467 ifp->if_flags &= ~IFF_OACTIVE; 1468 1469 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1470 1471 VR_UNLOCK(sc); 1472 1473 return; 1474 } 1475 1476 /* 1477 * Set media options. 1478 */ 1479 static int vr_ifmedia_upd(ifp) 1480 struct ifnet *ifp; 1481 { 1482 struct vr_softc *sc; 1483 1484 sc = ifp->if_softc; 1485 1486 if (ifp->if_flags & IFF_UP) 1487 vr_init(sc); 1488 1489 return(0); 1490 } 1491 1492 /* 1493 * Report current media status. 1494 */ 1495 static void vr_ifmedia_sts(ifp, ifmr) 1496 struct ifnet *ifp; 1497 struct ifmediareq *ifmr; 1498 { 1499 struct vr_softc *sc; 1500 struct mii_data *mii; 1501 1502 sc = ifp->if_softc; 1503 mii = device_get_softc(sc->vr_miibus); 1504 mii_pollstat(mii); 1505 ifmr->ifm_active = mii->mii_media_active; 1506 ifmr->ifm_status = mii->mii_media_status; 1507 1508 return; 1509 } 1510 1511 static int vr_ioctl(ifp, command, data) 1512 struct ifnet *ifp; 1513 u_long command; 1514 caddr_t data; 1515 { 1516 struct vr_softc *sc = ifp->if_softc; 1517 struct ifreq *ifr = (struct ifreq *) data; 1518 struct mii_data *mii; 1519 int error = 0; 1520 1521 VR_LOCK(sc); 1522 1523 switch(command) { 1524 case SIOCSIFADDR: 1525 case SIOCGIFADDR: 1526 case SIOCSIFMTU: 1527 error = ether_ioctl(ifp, command, data); 1528 break; 1529 case SIOCSIFFLAGS: 1530 if (ifp->if_flags & IFF_UP) { 1531 vr_init(sc); 1532 } else { 1533 if (ifp->if_flags & IFF_RUNNING) 1534 vr_stop(sc); 1535 } 1536 error = 0; 1537 break; 1538 case SIOCADDMULTI: 1539 case SIOCDELMULTI: 1540 vr_setmulti(sc); 1541 error = 0; 1542 break; 1543 case SIOCGIFMEDIA: 1544 case SIOCSIFMEDIA: 1545 mii = device_get_softc(sc->vr_miibus); 1546 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1547 break; 1548 default: 1549 error = EINVAL; 1550 break; 1551 } 1552 1553 VR_UNLOCK(sc); 1554 1555 return(error); 1556 } 1557 1558 static void vr_watchdog(ifp) 1559 struct ifnet *ifp; 1560 { 1561 struct vr_softc *sc; 1562 1563 sc = ifp->if_softc; 1564 1565 VR_LOCK(sc); 1566 ifp->if_oerrors++; 1567 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1568 1569 vr_stop(sc); 1570 vr_reset(sc); 1571 vr_init(sc); 1572 1573 if (ifp->if_snd.ifq_head != NULL) 1574 vr_start(ifp); 1575 1576 VR_UNLOCK(sc); 1577 1578 return; 1579 } 1580 1581 /* 1582 * Stop the adapter and free any mbufs allocated to the 1583 * RX and TX lists. 1584 */ 1585 static void vr_stop(sc) 1586 struct vr_softc *sc; 1587 { 1588 register int i; 1589 struct ifnet *ifp; 1590 1591 VR_LOCK(sc); 1592 1593 ifp = &sc->arpcom.ac_if; 1594 ifp->if_timer = 0; 1595 1596 untimeout(vr_tick, sc, sc->vr_stat_ch); 1597 1598 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1599 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1600 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1601 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1602 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1603 1604 /* 1605 * Free data in the RX lists. 1606 */ 1607 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1608 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1609 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1610 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1611 } 1612 } 1613 bzero((char *)&sc->vr_ldata->vr_rx_list, 1614 sizeof(sc->vr_ldata->vr_rx_list)); 1615 1616 /* 1617 * Free the TX list buffers. 1618 */ 1619 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1620 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1621 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1622 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1623 } 1624 } 1625 1626 bzero((char *)&sc->vr_ldata->vr_tx_list, 1627 sizeof(sc->vr_ldata->vr_tx_list)); 1628 1629 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1630 VR_UNLOCK(sc); 1631 1632 return; 1633 } 1634 1635 /* 1636 * Stop all chip I/O so that the kernel's probe routines don't 1637 * get confused by errant DMAs when rebooting. 1638 */ 1639 static void vr_shutdown(dev) 1640 device_t dev; 1641 { 1642 struct vr_softc *sc; 1643 1644 sc = device_get_softc(dev); 1645 1646 vr_stop(sc); 1647 1648 return; 1649 } 1650