1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #ifdef HAVE_KERNEL_OPTION_HEADERS 64 #include "opt_device_polling.h" 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/sockio.h> 70 #include <sys/mbuf.h> 71 #include <sys/malloc.h> 72 #include <sys/kernel.h> 73 #include <sys/module.h> 74 #include <sys/socket.h> 75 76 #include <net/if.h> 77 #include <net/if_arp.h> 78 #include <net/ethernet.h> 79 #include <net/if_dl.h> 80 #include <net/if_media.h> 81 #include <net/if_types.h> 82 83 #include <net/bpf.h> 84 85 #include <vm/vm.h> /* for vtophys */ 86 #include <vm/pmap.h> /* for vtophys */ 87 #include <machine/bus.h> 88 #include <machine/resource.h> 89 #include <sys/bus.h> 90 #include <sys/rman.h> 91 92 #include <dev/mii/mii.h> 93 #include <dev/mii/miivar.h> 94 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 98 #define VR_USEIOSPACE 99 100 #include <pci/if_vrreg.h> 101 102 MODULE_DEPEND(vr, pci, 1, 1, 1); 103 MODULE_DEPEND(vr, ether, 1, 1, 1); 104 MODULE_DEPEND(vr, miibus, 1, 1, 1); 105 106 /* "device miibus" required. See GENERIC if you get errors here. */ 107 #include "miibus_if.h" 108 109 #undef VR_USESWSHIFT 110 111 /* 112 * Various supported device vendors/types and their names. 113 */ 114 static struct vr_type vr_devs[] = { 115 { VIA_VENDORID, VIA_DEVICEID_RHINE, 116 "VIA VT3043 Rhine I 10/100BaseTX" }, 117 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 118 "VIA VT86C100A Rhine II 10/100BaseTX" }, 119 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 120 "VIA VT6102 Rhine II 10/100BaseTX" }, 121 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 122 "VIA VT6105 Rhine III 10/100BaseTX" }, 123 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 124 "VIA VT6105M Rhine III 10/100BaseTX" }, 125 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 126 "Delta Electronics Rhine II 10/100BaseTX" }, 127 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 128 "Addtron Technology Rhine II 10/100BaseTX" }, 129 { 0, 0, NULL } 130 }; 131 132 static int vr_probe(device_t); 133 static int vr_attach(device_t); 134 static int vr_detach(device_t); 135 136 static int vr_newbuf(struct vr_softc *, struct vr_chain_onefrag *, 137 struct mbuf *); 138 static int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf * ); 139 140 static void vr_rxeof(struct vr_softc *); 141 static void vr_rxeoc(struct vr_softc *); 142 static void vr_txeof(struct vr_softc *); 143 static void vr_tick(void *); 144 static void vr_intr(void *); 145 static void vr_start(struct ifnet *); 146 static void vr_start_locked(struct ifnet *); 147 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 148 static void vr_init(void *); 149 static void vr_init_locked(struct vr_softc *); 150 static void vr_stop(struct vr_softc *); 151 static void vr_watchdog(struct ifnet *); 152 static void vr_shutdown(device_t); 153 static int vr_ifmedia_upd(struct ifnet *); 154 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 155 156 #ifdef VR_USESWSHIFT 157 static void vr_mii_sync(struct vr_softc *); 158 static void vr_mii_send(struct vr_softc *, uint32_t, int); 159 #endif 160 static int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *); 161 static int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *); 162 static int vr_miibus_readreg(device_t, uint16_t, uint16_t); 163 static int vr_miibus_writereg(device_t, uint16_t, uint16_t, uint16_t); 164 static void vr_miibus_statchg(device_t); 165 166 static void vr_setcfg(struct vr_softc *, int); 167 static void vr_setmulti(struct vr_softc *); 168 static void vr_reset(struct vr_softc *); 169 static int vr_list_rx_init(struct vr_softc *); 170 static int vr_list_tx_init(struct vr_softc *); 171 172 #ifdef VR_USEIOSPACE 173 #define VR_RES SYS_RES_IOPORT 174 #define VR_RID VR_PCI_LOIO 175 #else 176 #define VR_RES SYS_RES_MEMORY 177 #define VR_RID VR_PCI_LOMEM 178 #endif 179 180 static device_method_t vr_methods[] = { 181 /* Device interface */ 182 DEVMETHOD(device_probe, vr_probe), 183 DEVMETHOD(device_attach, vr_attach), 184 DEVMETHOD(device_detach, vr_detach), 185 DEVMETHOD(device_shutdown, vr_shutdown), 186 187 /* bus interface */ 188 DEVMETHOD(bus_print_child, bus_generic_print_child), 189 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 190 191 /* MII interface */ 192 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 193 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 194 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 195 196 { 0, 0 } 197 }; 198 199 static driver_t vr_driver = { 200 "vr", 201 vr_methods, 202 sizeof(struct vr_softc) 203 }; 204 205 static devclass_t vr_devclass; 206 207 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 208 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 209 210 #define VR_SETBIT(sc, reg, x) \ 211 CSR_WRITE_1(sc, reg, \ 212 CSR_READ_1(sc, reg) | (x)) 213 214 #define VR_CLRBIT(sc, reg, x) \ 215 CSR_WRITE_1(sc, reg, \ 216 CSR_READ_1(sc, reg) & ~(x)) 217 218 #define VR_SETBIT16(sc, reg, x) \ 219 CSR_WRITE_2(sc, reg, \ 220 CSR_READ_2(sc, reg) | (x)) 221 222 #define VR_CLRBIT16(sc, reg, x) \ 223 CSR_WRITE_2(sc, reg, \ 224 CSR_READ_2(sc, reg) & ~(x)) 225 226 #define VR_SETBIT32(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230 #define VR_CLRBIT32(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234 #define SIO_SET(x) \ 235 CSR_WRITE_1(sc, VR_MIICMD, \ 236 CSR_READ_1(sc, VR_MIICMD) | (x)) 237 238 #define SIO_CLR(x) \ 239 CSR_WRITE_1(sc, VR_MIICMD, \ 240 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 241 242 #ifdef VR_USESWSHIFT 243 /* 244 * Sync the PHYs by setting data bit and strobing the clock 32 times. 245 */ 246 static void 247 vr_mii_sync(struct vr_softc *sc) 248 { 249 register int i; 250 251 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 252 253 for (i = 0; i < 32; i++) { 254 SIO_SET(VR_MIICMD_CLK); 255 DELAY(1); 256 SIO_CLR(VR_MIICMD_CLK); 257 DELAY(1); 258 } 259 } 260 261 /* 262 * Clock a series of bits through the MII. 263 */ 264 static void 265 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 266 { 267 int i; 268 269 SIO_CLR(VR_MIICMD_CLK); 270 271 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 272 if (bits & i) { 273 SIO_SET(VR_MIICMD_DATAIN); 274 } else { 275 SIO_CLR(VR_MIICMD_DATAIN); 276 } 277 DELAY(1); 278 SIO_CLR(VR_MIICMD_CLK); 279 DELAY(1); 280 SIO_SET(VR_MIICMD_CLK); 281 } 282 } 283 #endif 284 285 /* 286 * Read an PHY register through the MII. 287 */ 288 static int 289 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 290 #ifdef VR_USESWSHIFT 291 { 292 int i, ack; 293 294 /* Set up frame for RX. */ 295 frame->mii_stdelim = VR_MII_STARTDELIM; 296 frame->mii_opcode = VR_MII_READOP; 297 frame->mii_turnaround = 0; 298 frame->mii_data = 0; 299 300 CSR_WRITE_1(sc, VR_MIICMD, 0); 301 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 302 303 /* Turn on data xmit. */ 304 SIO_SET(VR_MIICMD_DIR); 305 306 vr_mii_sync(sc); 307 308 /* Send command/address info. */ 309 vr_mii_send(sc, frame->mii_stdelim, 2); 310 vr_mii_send(sc, frame->mii_opcode, 2); 311 vr_mii_send(sc, frame->mii_phyaddr, 5); 312 vr_mii_send(sc, frame->mii_regaddr, 5); 313 314 /* Idle bit. */ 315 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 316 DELAY(1); 317 SIO_SET(VR_MIICMD_CLK); 318 DELAY(1); 319 320 /* Turn off xmit. */ 321 SIO_CLR(VR_MIICMD_DIR); 322 323 /* Check for ack */ 324 SIO_CLR(VR_MIICMD_CLK); 325 DELAY(1); 326 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 327 SIO_SET(VR_MIICMD_CLK); 328 DELAY(1); 329 330 /* 331 * Now try reading data bits. If the ack failed, we still 332 * need to clock through 16 cycles to keep the PHY(s) in sync. 333 */ 334 if (ack) { 335 for(i = 0; i < 16; i++) { 336 SIO_CLR(VR_MIICMD_CLK); 337 DELAY(1); 338 SIO_SET(VR_MIICMD_CLK); 339 DELAY(1); 340 } 341 goto fail; 342 } 343 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_CLR(VR_MIICMD_CLK); 346 DELAY(1); 347 if (!ack) { 348 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 349 frame->mii_data |= i; 350 DELAY(1); 351 } 352 SIO_SET(VR_MIICMD_CLK); 353 DELAY(1); 354 } 355 356 fail: 357 SIO_CLR(VR_MIICMD_CLK); 358 DELAY(1); 359 SIO_SET(VR_MIICMD_CLK); 360 DELAY(1); 361 362 if (ack) 363 return (1); 364 return (0); 365 } 366 #else 367 { 368 int i; 369 370 /* Set the PHY address. */ 371 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 372 frame->mii_phyaddr); 373 374 /* Set the register address. */ 375 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 376 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 377 378 for (i = 0; i < 10000; i++) { 379 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 380 break; 381 DELAY(1); 382 } 383 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 384 385 return (0); 386 } 387 #endif 388 389 390 /* 391 * Write to a PHY register through the MII. 392 */ 393 static int 394 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 395 #ifdef VR_USESWSHIFT 396 { 397 CSR_WRITE_1(sc, VR_MIICMD, 0); 398 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 399 400 /* Set up frame for TX. */ 401 frame->mii_stdelim = VR_MII_STARTDELIM; 402 frame->mii_opcode = VR_MII_WRITEOP; 403 frame->mii_turnaround = VR_MII_TURNAROUND; 404 405 /* Turn on data output. */ 406 SIO_SET(VR_MIICMD_DIR); 407 408 vr_mii_sync(sc); 409 410 vr_mii_send(sc, frame->mii_stdelim, 2); 411 vr_mii_send(sc, frame->mii_opcode, 2); 412 vr_mii_send(sc, frame->mii_phyaddr, 5); 413 vr_mii_send(sc, frame->mii_regaddr, 5); 414 vr_mii_send(sc, frame->mii_turnaround, 2); 415 vr_mii_send(sc, frame->mii_data, 16); 416 417 /* Idle bit. */ 418 SIO_SET(VR_MIICMD_CLK); 419 DELAY(1); 420 SIO_CLR(VR_MIICMD_CLK); 421 DELAY(1); 422 423 /* Turn off xmit. */ 424 SIO_CLR(VR_MIICMD_DIR); 425 426 return (0); 427 } 428 #else 429 { 430 int i; 431 432 /* Set the PHY address. */ 433 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 434 frame->mii_phyaddr); 435 436 /* Set the register address and data to write. */ 437 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 438 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 439 440 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 441 442 for (i = 0; i < 10000; i++) { 443 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 444 break; 445 DELAY(1); 446 } 447 448 return (0); 449 } 450 #endif 451 452 static int 453 vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 454 { 455 struct vr_mii_frame frame; 456 struct vr_softc *sc = device_get_softc(dev); 457 458 switch (sc->vr_revid) { 459 case REV_ID_VT6102_APOLLO: 460 if (phy != 1) { 461 frame.mii_data = 0; 462 goto out; 463 } 464 default: 465 break; 466 } 467 468 bzero((char *)&frame, sizeof(frame)); 469 frame.mii_phyaddr = phy; 470 frame.mii_regaddr = reg; 471 vr_mii_readreg(sc, &frame); 472 473 out: 474 return (frame.mii_data); 475 } 476 477 static int 478 vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 479 { 480 struct vr_mii_frame frame; 481 struct vr_softc *sc = device_get_softc(dev); 482 483 switch (sc->vr_revid) { 484 case REV_ID_VT6102_APOLLO: 485 if (phy != 1) 486 return (0); 487 default: 488 break; 489 } 490 491 bzero((char *)&frame, sizeof(frame)); 492 frame.mii_phyaddr = phy; 493 frame.mii_regaddr = reg; 494 frame.mii_data = data; 495 vr_mii_writereg(sc, &frame); 496 497 return (0); 498 } 499 500 static void 501 vr_miibus_statchg(device_t dev) 502 { 503 struct mii_data *mii; 504 struct vr_softc *sc = device_get_softc(dev); 505 506 mii = device_get_softc(sc->vr_miibus); 507 vr_setcfg(sc, mii->mii_media_active); 508 } 509 510 /* 511 * Program the 64-bit multicast hash filter. 512 */ 513 static void 514 vr_setmulti(struct vr_softc *sc) 515 { 516 struct ifnet *ifp = sc->vr_ifp; 517 int h = 0; 518 uint32_t hashes[2] = { 0, 0 }; 519 struct ifmultiaddr *ifma; 520 uint8_t rxfilt; 521 int mcnt = 0; 522 523 VR_LOCK_ASSERT(sc); 524 525 rxfilt = CSR_READ_1(sc, VR_RXCFG); 526 527 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 528 rxfilt |= VR_RXCFG_RX_MULTI; 529 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 530 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 531 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 532 return; 533 } 534 535 /* First, zero out all the existing hash bits. */ 536 CSR_WRITE_4(sc, VR_MAR0, 0); 537 CSR_WRITE_4(sc, VR_MAR1, 0); 538 539 /* Now program new ones. */ 540 IF_ADDR_LOCK(ifp); 541 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 542 if (ifma->ifma_addr->sa_family != AF_LINK) 543 continue; 544 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 545 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 546 if (h < 32) 547 hashes[0] |= (1 << h); 548 else 549 hashes[1] |= (1 << (h - 32)); 550 mcnt++; 551 } 552 IF_ADDR_UNLOCK(ifp); 553 554 if (mcnt) 555 rxfilt |= VR_RXCFG_RX_MULTI; 556 else 557 rxfilt &= ~VR_RXCFG_RX_MULTI; 558 559 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 560 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 561 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 562 } 563 564 /* 565 * In order to fiddle with the 566 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 567 * first have to put the transmit and/or receive logic in the idle state. 568 */ 569 static void 570 vr_setcfg(struct vr_softc *sc, int media) 571 { 572 int restart = 0; 573 574 VR_LOCK_ASSERT(sc); 575 576 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 577 restart = 1; 578 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 579 } 580 581 if ((media & IFM_GMASK) == IFM_FDX) 582 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 583 else 584 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 585 586 if (restart) 587 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 588 } 589 590 static void 591 vr_reset(struct vr_softc *sc) 592 { 593 register int i; 594 595 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 596 597 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 598 599 for (i = 0; i < VR_TIMEOUT; i++) { 600 DELAY(10); 601 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 602 break; 603 } 604 if (i == VR_TIMEOUT) { 605 if (sc->vr_revid < REV_ID_VT3065_A) 606 device_printf(sc->vr_dev, "reset never completed!\n"); 607 else { 608 /* Use newer force reset command */ 609 device_printf(sc->vr_dev, "Using force reset command.\n"); 610 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 611 } 612 } 613 614 /* Wait a little while for the chip to get its brains in order. */ 615 DELAY(1000); 616 } 617 618 /* 619 * Probe for a VIA Rhine chip. Check the PCI vendor and device 620 * IDs against our list and return a device name if we find a match. 621 */ 622 static int 623 vr_probe(device_t dev) 624 { 625 struct vr_type *t = vr_devs; 626 627 while (t->vr_name != NULL) { 628 if ((pci_get_vendor(dev) == t->vr_vid) && 629 (pci_get_device(dev) == t->vr_did)) { 630 device_set_desc(dev, t->vr_name); 631 return (BUS_PROBE_DEFAULT); 632 } 633 t++; 634 } 635 636 return (ENXIO); 637 } 638 639 /* 640 * Attach the interface. Allocate softc structures, do ifmedia 641 * setup and ethernet/BPF attach. 642 */ 643 static int 644 vr_attach(dev) 645 device_t dev; 646 { 647 int i; 648 u_char eaddr[ETHER_ADDR_LEN]; 649 struct vr_softc *sc; 650 struct ifnet *ifp; 651 int unit, error = 0, rid; 652 653 sc = device_get_softc(dev); 654 sc->vr_dev = dev; 655 unit = device_get_unit(dev); 656 657 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 658 MTX_DEF); 659 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 660 661 /* 662 * Map control/status registers. 663 */ 664 pci_enable_busmaster(dev); 665 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 666 667 rid = VR_RID; 668 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 669 670 if (sc->vr_res == NULL) { 671 device_printf(dev, "couldn't map ports/memory\n"); 672 error = ENXIO; 673 goto fail; 674 } 675 676 sc->vr_btag = rman_get_bustag(sc->vr_res); 677 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 678 679 /* Allocate interrupt */ 680 rid = 0; 681 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 682 RF_SHAREABLE | RF_ACTIVE); 683 684 if (sc->vr_irq == NULL) { 685 device_printf(dev, "couldn't map interrupt\n"); 686 error = ENXIO; 687 goto fail; 688 } 689 690 /* Allocate ifnet structure. */ 691 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 692 if (ifp == NULL) { 693 device_printf(dev, "can not if_alloc()\n"); 694 error = ENOSPC; 695 goto fail; 696 } 697 ifp->if_softc = sc; 698 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 699 ifp->if_mtu = ETHERMTU; 700 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 701 ifp->if_ioctl = vr_ioctl; 702 ifp->if_start = vr_start; 703 ifp->if_watchdog = vr_watchdog; 704 ifp->if_init = vr_init; 705 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_LIST_CNT - 1); 706 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 707 IFQ_SET_READY(&ifp->if_snd); 708 ifp->if_capenable = ifp->if_capabilities; 709 #ifdef DEVICE_POLLING 710 ifp->if_capabilities |= IFCAP_POLLING; 711 #endif 712 713 /* 714 * Windows may put the chip in suspend mode when it 715 * shuts down. Be sure to kick it in the head to wake it 716 * up again. 717 */ 718 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 719 720 /* Reset the adapter. */ 721 vr_reset(sc); 722 723 /* 724 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 725 * initialization and disable AUTOPOLL. 726 */ 727 pci_write_config(dev, VR_PCI_MODE, 728 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 729 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 730 731 /* 732 * Get station address. The way the Rhine chips work, 733 * you're not allowed to directly access the EEPROM once 734 * they've been programmed a special way. Consequently, 735 * we need to read the node address from the PAR0 and PAR1 736 * registers. 737 */ 738 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 739 DELAY(200); 740 for (i = 0; i < ETHER_ADDR_LEN; i++) 741 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 742 743 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 744 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 745 746 if (sc->vr_ldata == NULL) { 747 device_printf(dev, "no memory for list buffers!\n"); 748 error = ENXIO; 749 goto fail; 750 } 751 752 /* Do MII setup. */ 753 if (mii_phy_probe(dev, &sc->vr_miibus, 754 vr_ifmedia_upd, vr_ifmedia_sts)) { 755 device_printf(dev, "MII without any phy!\n"); 756 error = ENXIO; 757 goto fail; 758 } 759 760 /* Call MI attach routine. */ 761 ether_ifattach(ifp, eaddr); 762 763 sc->suspended = 0; 764 765 /* Hook interrupt last to avoid having to lock softc */ 766 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 767 NULL, vr_intr, sc, &sc->vr_intrhand); 768 769 if (error) { 770 device_printf(dev, "couldn't set up irq\n"); 771 ether_ifdetach(ifp); 772 goto fail; 773 } 774 775 fail: 776 if (error) 777 vr_detach(dev); 778 779 return (error); 780 } 781 782 /* 783 * Shutdown hardware and free up resources. This can be called any 784 * time after the mutex has been initialized. It is called in both 785 * the error case in attach and the normal detach case so it needs 786 * to be careful about only freeing resources that have actually been 787 * allocated. 788 */ 789 static int 790 vr_detach(device_t dev) 791 { 792 struct vr_softc *sc = device_get_softc(dev); 793 struct ifnet *ifp = sc->vr_ifp; 794 795 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 796 797 #ifdef DEVICE_POLLING 798 if (ifp->if_capenable & IFCAP_POLLING) 799 ether_poll_deregister(ifp); 800 #endif 801 802 /* These should only be active if attach succeeded */ 803 if (device_is_attached(dev)) { 804 VR_LOCK(sc); 805 sc->suspended = 1; 806 vr_stop(sc); 807 VR_UNLOCK(sc); 808 callout_drain(&sc->vr_stat_callout); 809 ether_ifdetach(ifp); 810 } 811 if (sc->vr_miibus) 812 device_delete_child(dev, sc->vr_miibus); 813 bus_generic_detach(dev); 814 815 if (sc->vr_intrhand) 816 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 817 if (sc->vr_irq) 818 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 819 if (sc->vr_res) 820 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 821 822 if (ifp) 823 if_free(ifp); 824 825 if (sc->vr_ldata) 826 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 827 828 mtx_destroy(&sc->vr_mtx); 829 830 return (0); 831 } 832 833 /* 834 * Initialize the transmit descriptors. 835 */ 836 static int 837 vr_list_tx_init(struct vr_softc *sc) 838 { 839 struct vr_chain_data *cd; 840 struct vr_list_data *ld; 841 int i; 842 843 cd = &sc->vr_cdata; 844 ld = sc->vr_ldata; 845 for (i = 0; i < VR_TX_LIST_CNT; i++) { 846 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 847 if (i == (VR_TX_LIST_CNT - 1)) 848 cd->vr_tx_chain[i].vr_nextdesc = 849 &cd->vr_tx_chain[0]; 850 else 851 cd->vr_tx_chain[i].vr_nextdesc = 852 &cd->vr_tx_chain[i + 1]; 853 } 854 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 855 856 return (0); 857 } 858 859 860 /* 861 * Initialize the RX descriptors and allocate mbufs for them. Note that 862 * we arrange the descriptors in a closed ring, so that the last descriptor 863 * points back to the first. 864 */ 865 static int 866 vr_list_rx_init(struct vr_softc *sc) 867 { 868 struct vr_chain_data *cd; 869 struct vr_list_data *ld; 870 int i; 871 872 VR_LOCK_ASSERT(sc); 873 874 cd = &sc->vr_cdata; 875 ld = sc->vr_ldata; 876 877 for (i = 0; i < VR_RX_LIST_CNT; i++) { 878 cd->vr_rx_chain[i].vr_ptr = 879 (struct vr_desc *)&ld->vr_rx_list[i]; 880 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 881 return (ENOBUFS); 882 if (i == (VR_RX_LIST_CNT - 1)) { 883 cd->vr_rx_chain[i].vr_nextdesc = 884 &cd->vr_rx_chain[0]; 885 ld->vr_rx_list[i].vr_next = 886 vtophys(&ld->vr_rx_list[0]); 887 } else { 888 cd->vr_rx_chain[i].vr_nextdesc = 889 &cd->vr_rx_chain[i + 1]; 890 ld->vr_rx_list[i].vr_next = 891 vtophys(&ld->vr_rx_list[i + 1]); 892 } 893 } 894 895 cd->vr_rx_head = &cd->vr_rx_chain[0]; 896 897 return (0); 898 } 899 900 /* 901 * Initialize an RX descriptor and attach an MBUF cluster. 902 * Note: the length fields are only 11 bits wide, which means the 903 * largest size we can specify is 2047. This is important because 904 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 905 * overflow the field and make a mess. 906 */ 907 static int 908 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 909 { 910 struct mbuf *m_new = NULL; 911 912 if (m == NULL) { 913 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 914 if (m_new == NULL) 915 return (ENOBUFS); 916 917 MCLGET(m_new, M_DONTWAIT); 918 if (!(m_new->m_flags & M_EXT)) { 919 m_freem(m_new); 920 return (ENOBUFS); 921 } 922 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 923 } else { 924 m_new = m; 925 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 926 m_new->m_data = m_new->m_ext.ext_buf; 927 } 928 929 m_adj(m_new, sizeof(uint64_t)); 930 931 c->vr_mbuf = m_new; 932 c->vr_ptr->vr_status = VR_RXSTAT; 933 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 934 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 935 936 return (0); 937 } 938 939 /* 940 * A frame has been uploaded: pass the resulting mbuf chain up to 941 * the higher level protocols. 942 */ 943 static void 944 vr_rxeof(struct vr_softc *sc) 945 { 946 struct mbuf *m, *m0; 947 struct ifnet *ifp; 948 struct vr_chain_onefrag *cur_rx; 949 int total_len = 0; 950 uint32_t rxstat; 951 952 VR_LOCK_ASSERT(sc); 953 ifp = sc->vr_ifp; 954 955 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 956 VR_RXSTAT_OWN)) { 957 #ifdef DEVICE_POLLING 958 if (ifp->if_capenable & IFCAP_POLLING) { 959 if (sc->rxcycles <= 0) 960 break; 961 sc->rxcycles--; 962 } 963 #endif 964 m0 = NULL; 965 cur_rx = sc->vr_cdata.vr_rx_head; 966 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 967 m = cur_rx->vr_mbuf; 968 969 /* 970 * If an error occurs, update stats, clear the 971 * status word and leave the mbuf cluster in place: 972 * it should simply get re-used next time this descriptor 973 * comes up in the ring. 974 */ 975 if (rxstat & VR_RXSTAT_RXERR) { 976 ifp->if_ierrors++; 977 device_printf(sc->vr_dev, 978 "rx error (%02x):", rxstat & 0x000000ff); 979 if (rxstat & VR_RXSTAT_CRCERR) 980 printf(" crc error"); 981 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 982 printf(" frame alignment error\n"); 983 if (rxstat & VR_RXSTAT_FIFOOFLOW) 984 printf(" FIFO overflow"); 985 if (rxstat & VR_RXSTAT_GIANT) 986 printf(" received giant packet"); 987 if (rxstat & VR_RXSTAT_RUNT) 988 printf(" received runt packet"); 989 if (rxstat & VR_RXSTAT_BUSERR) 990 printf(" system bus error"); 991 if (rxstat & VR_RXSTAT_BUFFERR) 992 printf("rx buffer error"); 993 printf("\n"); 994 vr_newbuf(sc, cur_rx, m); 995 continue; 996 } 997 998 /* No errors; receive the packet. */ 999 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1000 1001 /* 1002 * XXX The VIA Rhine chip includes the CRC with every 1003 * received frame, and there's no way to turn this 1004 * behavior off (at least, I can't find anything in 1005 * the manual that explains how to do it) so we have 1006 * to trim off the CRC manually. 1007 */ 1008 total_len -= ETHER_CRC_LEN; 1009 1010 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1011 NULL); 1012 vr_newbuf(sc, cur_rx, m); 1013 if (m0 == NULL) { 1014 ifp->if_ierrors++; 1015 continue; 1016 } 1017 m = m0; 1018 1019 ifp->if_ipackets++; 1020 VR_UNLOCK(sc); 1021 (*ifp->if_input)(ifp, m); 1022 VR_LOCK(sc); 1023 } 1024 } 1025 1026 static void 1027 vr_rxeoc(struct vr_softc *sc) 1028 { 1029 struct ifnet *ifp = sc->vr_ifp; 1030 int i; 1031 1032 VR_LOCK_ASSERT(sc); 1033 1034 ifp->if_ierrors++; 1035 1036 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1037 DELAY(10000); 1038 1039 /* Wait for receiver to stop */ 1040 for (i = 0x400; 1041 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1042 i--) { 1043 ; 1044 } 1045 1046 if (!i) { 1047 device_printf(sc->vr_dev, "rx shutdown error!\n"); 1048 sc->vr_flags |= VR_F_RESTART; 1049 return; 1050 } 1051 1052 vr_rxeof(sc); 1053 1054 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1056 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1057 } 1058 1059 /* 1060 * A frame was downloaded to the chip. It's safe for us to clean up 1061 * the list buffers. 1062 */ 1063 static void 1064 vr_txeof(struct vr_softc *sc) 1065 { 1066 struct vr_chain *cur_tx; 1067 struct ifnet *ifp = sc->vr_ifp; 1068 1069 VR_LOCK_ASSERT(sc); 1070 1071 /* 1072 * Go through our tx list and free mbufs for those 1073 * frames that have been transmitted. 1074 */ 1075 cur_tx = sc->vr_cdata.vr_tx_cons; 1076 while (cur_tx->vr_mbuf != NULL) { 1077 uint32_t txstat; 1078 int i; 1079 1080 txstat = cur_tx->vr_ptr->vr_status; 1081 1082 if ((txstat & VR_TXSTAT_ABRT) || 1083 (txstat & VR_TXSTAT_UDF)) { 1084 for (i = 0x400; 1085 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1086 i--) 1087 ; /* Wait for chip to shutdown */ 1088 if (!i) { 1089 device_printf(sc->vr_dev, "tx shutdown timeout\n"); 1090 sc->vr_flags |= VR_F_RESTART; 1091 break; 1092 } 1093 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1094 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1095 break; 1096 } 1097 1098 if (txstat & VR_TXSTAT_OWN) 1099 break; 1100 1101 if (txstat & VR_TXSTAT_ERRSUM) { 1102 ifp->if_oerrors++; 1103 if (txstat & VR_TXSTAT_DEFER) 1104 ifp->if_collisions++; 1105 if (txstat & VR_TXSTAT_LATECOLL) 1106 ifp->if_collisions++; 1107 } 1108 1109 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1110 1111 ifp->if_opackets++; 1112 m_freem(cur_tx->vr_mbuf); 1113 cur_tx->vr_mbuf = NULL; 1114 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1115 1116 cur_tx = cur_tx->vr_nextdesc; 1117 } 1118 sc->vr_cdata.vr_tx_cons = cur_tx; 1119 if (cur_tx->vr_mbuf == NULL) 1120 ifp->if_timer = 0; 1121 } 1122 1123 static void 1124 vr_tick(void *xsc) 1125 { 1126 struct vr_softc *sc = xsc; 1127 struct mii_data *mii; 1128 1129 VR_LOCK_ASSERT(sc); 1130 1131 if (sc->vr_flags & VR_F_RESTART) { 1132 device_printf(sc->vr_dev, "restarting\n"); 1133 vr_stop(sc); 1134 vr_reset(sc); 1135 vr_init_locked(sc); 1136 sc->vr_flags &= ~VR_F_RESTART; 1137 } 1138 1139 mii = device_get_softc(sc->vr_miibus); 1140 mii_tick(mii); 1141 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1142 } 1143 1144 #ifdef DEVICE_POLLING 1145 static poll_handler_t vr_poll; 1146 static poll_handler_t vr_poll_locked; 1147 1148 static void 1149 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1150 { 1151 struct vr_softc *sc = ifp->if_softc; 1152 1153 VR_LOCK(sc); 1154 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1155 vr_poll_locked(ifp, cmd, count); 1156 VR_UNLOCK(sc); 1157 } 1158 1159 static void 1160 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1161 { 1162 struct vr_softc *sc = ifp->if_softc; 1163 1164 VR_LOCK_ASSERT(sc); 1165 1166 sc->rxcycles = count; 1167 vr_rxeof(sc); 1168 vr_txeof(sc); 1169 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1170 vr_start_locked(ifp); 1171 1172 if (cmd == POLL_AND_CHECK_STATUS) { 1173 uint16_t status; 1174 1175 /* Also check status register. */ 1176 status = CSR_READ_2(sc, VR_ISR); 1177 if (status) 1178 CSR_WRITE_2(sc, VR_ISR, status); 1179 1180 if ((status & VR_INTRS) == 0) 1181 return; 1182 1183 if (status & VR_ISR_RX_DROPPED) { 1184 if_printf(ifp, "rx packet lost\n"); 1185 ifp->if_ierrors++; 1186 } 1187 1188 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1189 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1190 if_printf(ifp, "receive error (%04x)", status); 1191 if (status & VR_ISR_RX_NOBUF) 1192 printf(" no buffers"); 1193 if (status & VR_ISR_RX_OFLOW) 1194 printf(" overflow"); 1195 if (status & VR_ISR_RX_DROPPED) 1196 printf(" packet lost"); 1197 printf("\n"); 1198 vr_rxeoc(sc); 1199 } 1200 1201 if ((status & VR_ISR_BUSERR) || 1202 (status & VR_ISR_TX_UNDERRUN)) { 1203 vr_reset(sc); 1204 vr_init_locked(sc); 1205 return; 1206 } 1207 1208 if ((status & VR_ISR_UDFI) || 1209 (status & VR_ISR_TX_ABRT2) || 1210 (status & VR_ISR_TX_ABRT)) { 1211 ifp->if_oerrors++; 1212 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1213 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1214 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1215 } 1216 } 1217 } 1218 } 1219 #endif /* DEVICE_POLLING */ 1220 1221 static void 1222 vr_intr(void *arg) 1223 { 1224 struct vr_softc *sc = arg; 1225 struct ifnet *ifp = sc->vr_ifp; 1226 uint16_t status; 1227 1228 VR_LOCK(sc); 1229 1230 if (sc->suspended) { 1231 /* 1232 * Forcibly disable interrupts. 1233 * XXX: Mobile VIA based platforms may need 1234 * interrupt re-enable on resume. 1235 */ 1236 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1237 goto done_locked; 1238 } 1239 1240 #ifdef DEVICE_POLLING 1241 if (ifp->if_capenable & IFCAP_POLLING) 1242 goto done_locked; 1243 #endif 1244 1245 /* Suppress unwanted interrupts. */ 1246 if (!(ifp->if_flags & IFF_UP)) { 1247 vr_stop(sc); 1248 goto done_locked; 1249 } 1250 1251 /* Disable interrupts. */ 1252 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1253 1254 for (;;) { 1255 status = CSR_READ_2(sc, VR_ISR); 1256 if (status) 1257 CSR_WRITE_2(sc, VR_ISR, status); 1258 1259 if ((status & VR_INTRS) == 0) 1260 break; 1261 1262 if (status & VR_ISR_RX_OK) 1263 vr_rxeof(sc); 1264 1265 if (status & VR_ISR_RX_DROPPED) { 1266 device_printf(sc->vr_dev, "rx packet lost\n"); 1267 ifp->if_ierrors++; 1268 } 1269 1270 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1271 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1272 device_printf(sc->vr_dev, "receive error (%04x)", status); 1273 if (status & VR_ISR_RX_NOBUF) 1274 printf(" no buffers"); 1275 if (status & VR_ISR_RX_OFLOW) 1276 printf(" overflow"); 1277 if (status & VR_ISR_RX_DROPPED) 1278 printf(" packet lost"); 1279 printf("\n"); 1280 vr_rxeoc(sc); 1281 } 1282 1283 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1284 vr_reset(sc); 1285 vr_init_locked(sc); 1286 break; 1287 } 1288 1289 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1290 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1291 vr_txeof(sc); 1292 if ((status & VR_ISR_UDFI) || 1293 (status & VR_ISR_TX_ABRT2) || 1294 (status & VR_ISR_TX_ABRT)) { 1295 ifp->if_oerrors++; 1296 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1297 VR_SETBIT16(sc, VR_COMMAND, 1298 VR_CMD_TX_ON); 1299 VR_SETBIT16(sc, VR_COMMAND, 1300 VR_CMD_TX_GO); 1301 } 1302 } 1303 } 1304 } 1305 1306 /* Re-enable interrupts. */ 1307 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1308 1309 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1310 vr_start_locked(ifp); 1311 1312 done_locked: 1313 VR_UNLOCK(sc); 1314 } 1315 1316 /* 1317 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1318 * pointers to the fragment pointers. 1319 */ 1320 static int 1321 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1322 { 1323 struct vr_desc *f = NULL; 1324 struct mbuf *m; 1325 1326 VR_LOCK_ASSERT(sc); 1327 /* 1328 * The VIA Rhine wants packet buffers to be longword 1329 * aligned, but very often our mbufs aren't. Rather than 1330 * waste time trying to decide when to copy and when not 1331 * to copy, just do it all the time. 1332 */ 1333 m = m_defrag(m_head, M_DONTWAIT); 1334 if (m == NULL) 1335 return (1); 1336 1337 /* 1338 * The Rhine chip doesn't auto-pad, so we have to make 1339 * sure to pad short frames out to the minimum frame length 1340 * ourselves. 1341 */ 1342 if (m->m_len < VR_MIN_FRAMELEN) { 1343 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1344 m->m_len = m->m_pkthdr.len; 1345 } 1346 1347 c->vr_mbuf = m; 1348 f = c->vr_ptr; 1349 f->vr_data = vtophys(mtod(m, caddr_t)); 1350 f->vr_ctl = m->m_len; 1351 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1352 f->vr_status = 0; 1353 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1354 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1355 1356 return (0); 1357 } 1358 1359 /* 1360 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1361 * to the mbuf data regions directly in the transmit lists. We also save a 1362 * copy of the pointers since the transmit list fragment pointers are 1363 * physical addresses. 1364 */ 1365 1366 static void 1367 vr_start(struct ifnet *ifp) 1368 { 1369 struct vr_softc *sc = ifp->if_softc; 1370 1371 VR_LOCK(sc); 1372 vr_start_locked(ifp); 1373 VR_UNLOCK(sc); 1374 } 1375 1376 static void 1377 vr_start_locked(struct ifnet *ifp) 1378 { 1379 struct vr_softc *sc = ifp->if_softc; 1380 struct mbuf *m_head; 1381 struct vr_chain *cur_tx; 1382 1383 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1384 return; 1385 1386 cur_tx = sc->vr_cdata.vr_tx_prod; 1387 while (cur_tx->vr_mbuf == NULL) { 1388 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1389 if (m_head == NULL) 1390 break; 1391 1392 /* Pack the data into the descriptor. */ 1393 if (vr_encap(sc, cur_tx, m_head)) { 1394 /* Rollback, send what we were able to encap. */ 1395 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1396 break; 1397 } 1398 1399 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1400 1401 /* 1402 * If there's a BPF listener, bounce a copy of this frame 1403 * to him. 1404 */ 1405 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1406 1407 cur_tx = cur_tx->vr_nextdesc; 1408 } 1409 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1410 sc->vr_cdata.vr_tx_prod = cur_tx; 1411 1412 /* Tell the chip to start transmitting. */ 1413 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1414 1415 /* Set a timeout in case the chip goes out to lunch. */ 1416 ifp->if_timer = 5; 1417 1418 if (cur_tx->vr_mbuf != NULL) 1419 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1420 } 1421 } 1422 1423 static void 1424 vr_init(void *xsc) 1425 { 1426 struct vr_softc *sc = xsc; 1427 1428 VR_LOCK(sc); 1429 vr_init_locked(sc); 1430 VR_UNLOCK(sc); 1431 } 1432 1433 static void 1434 vr_init_locked(struct vr_softc *sc) 1435 { 1436 struct ifnet *ifp = sc->vr_ifp; 1437 struct mii_data *mii; 1438 int i; 1439 1440 VR_LOCK_ASSERT(sc); 1441 1442 mii = device_get_softc(sc->vr_miibus); 1443 1444 /* Cancel pending I/O and free all RX/TX buffers. */ 1445 vr_stop(sc); 1446 vr_reset(sc); 1447 1448 /* Set our station address. */ 1449 for (i = 0; i < ETHER_ADDR_LEN; i++) 1450 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 1451 1452 /* Set DMA size. */ 1453 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1454 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1455 1456 /* 1457 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1458 * so we must set both. 1459 */ 1460 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1461 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1462 1463 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1464 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1465 1466 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1467 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1468 1469 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1470 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1471 1472 /* Init circular RX list. */ 1473 if (vr_list_rx_init(sc) == ENOBUFS) { 1474 device_printf(sc->vr_dev, 1475 "initialization failed: no memory for rx buffers\n"); 1476 vr_stop(sc); 1477 return; 1478 } 1479 1480 /* Init tx descriptors. */ 1481 vr_list_tx_init(sc); 1482 1483 /* If we want promiscuous mode, set the allframes bit. */ 1484 if (ifp->if_flags & IFF_PROMISC) 1485 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1486 else 1487 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1488 1489 /* Set capture broadcast bit to capture broadcast frames. */ 1490 if (ifp->if_flags & IFF_BROADCAST) 1491 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1492 else 1493 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1494 1495 /* 1496 * Program the multicast filter, if necessary. 1497 */ 1498 vr_setmulti(sc); 1499 1500 /* 1501 * Load the address of the RX list. 1502 */ 1503 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1504 1505 /* Enable receiver and transmitter. */ 1506 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1507 VR_CMD_TX_ON|VR_CMD_RX_ON| 1508 VR_CMD_RX_GO); 1509 1510 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1511 1512 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1513 #ifdef DEVICE_POLLING 1514 /* 1515 * Disable interrupts if we are polling. 1516 */ 1517 if (ifp->if_capenable & IFCAP_POLLING) 1518 CSR_WRITE_2(sc, VR_IMR, 0); 1519 else 1520 #endif 1521 /* 1522 * Enable interrupts. 1523 */ 1524 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1525 1526 mii_mediachg(mii); 1527 1528 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1529 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1530 1531 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1532 } 1533 1534 /* 1535 * Set media options. 1536 */ 1537 static int 1538 vr_ifmedia_upd(struct ifnet *ifp) 1539 { 1540 struct vr_softc *sc = ifp->if_softc; 1541 1542 if (ifp->if_flags & IFF_UP) 1543 vr_init(sc); 1544 1545 return (0); 1546 } 1547 1548 /* 1549 * Report current media status. 1550 */ 1551 static void 1552 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1553 { 1554 struct vr_softc *sc = ifp->if_softc; 1555 struct mii_data *mii; 1556 1557 mii = device_get_softc(sc->vr_miibus); 1558 VR_LOCK(sc); 1559 mii_pollstat(mii); 1560 VR_UNLOCK(sc); 1561 ifmr->ifm_active = mii->mii_media_active; 1562 ifmr->ifm_status = mii->mii_media_status; 1563 } 1564 1565 static int 1566 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1567 { 1568 struct vr_softc *sc = ifp->if_softc; 1569 struct ifreq *ifr = (struct ifreq *) data; 1570 struct mii_data *mii; 1571 int error = 0; 1572 1573 switch (command) { 1574 case SIOCSIFFLAGS: 1575 VR_LOCK(sc); 1576 if (ifp->if_flags & IFF_UP) { 1577 vr_init_locked(sc); 1578 } else { 1579 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1580 vr_stop(sc); 1581 } 1582 VR_UNLOCK(sc); 1583 error = 0; 1584 break; 1585 case SIOCADDMULTI: 1586 case SIOCDELMULTI: 1587 VR_LOCK(sc); 1588 vr_setmulti(sc); 1589 VR_UNLOCK(sc); 1590 error = 0; 1591 break; 1592 case SIOCGIFMEDIA: 1593 case SIOCSIFMEDIA: 1594 mii = device_get_softc(sc->vr_miibus); 1595 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1596 break; 1597 case SIOCSIFCAP: 1598 #ifdef DEVICE_POLLING 1599 if (ifr->ifr_reqcap & IFCAP_POLLING && 1600 !(ifp->if_capenable & IFCAP_POLLING)) { 1601 error = ether_poll_register(vr_poll, ifp); 1602 if (error) 1603 return(error); 1604 VR_LOCK(sc); 1605 /* Disable interrupts */ 1606 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1607 ifp->if_capenable |= IFCAP_POLLING; 1608 VR_UNLOCK(sc); 1609 return (error); 1610 1611 } 1612 if (!(ifr->ifr_reqcap & IFCAP_POLLING) && 1613 ifp->if_capenable & IFCAP_POLLING) { 1614 error = ether_poll_deregister(ifp); 1615 /* Enable interrupts. */ 1616 VR_LOCK(sc); 1617 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1618 ifp->if_capenable &= ~IFCAP_POLLING; 1619 VR_UNLOCK(sc); 1620 return (error); 1621 } 1622 #endif /* DEVICE_POLLING */ 1623 break; 1624 default: 1625 error = ether_ioctl(ifp, command, data); 1626 break; 1627 } 1628 1629 return (error); 1630 } 1631 1632 static void 1633 vr_watchdog(struct ifnet *ifp) 1634 { 1635 struct vr_softc *sc = ifp->if_softc; 1636 1637 VR_LOCK(sc); 1638 1639 ifp->if_oerrors++; 1640 if_printf(ifp, "watchdog timeout\n"); 1641 1642 vr_stop(sc); 1643 vr_reset(sc); 1644 vr_init_locked(sc); 1645 1646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1647 vr_start_locked(ifp); 1648 1649 VR_UNLOCK(sc); 1650 } 1651 1652 /* 1653 * Stop the adapter and free any mbufs allocated to the 1654 * RX and TX lists. 1655 */ 1656 static void 1657 vr_stop(struct vr_softc *sc) 1658 { 1659 register int i; 1660 struct ifnet *ifp; 1661 1662 VR_LOCK_ASSERT(sc); 1663 1664 ifp = sc->vr_ifp; 1665 ifp->if_timer = 0; 1666 1667 callout_stop(&sc->vr_stat_callout); 1668 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1669 1670 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1671 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1672 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1673 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1674 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1675 1676 /* 1677 * Free data in the RX lists. 1678 */ 1679 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1680 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1681 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1682 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1683 } 1684 } 1685 bzero((char *)&sc->vr_ldata->vr_rx_list, 1686 sizeof(sc->vr_ldata->vr_rx_list)); 1687 1688 /* 1689 * Free the TX list buffers. 1690 */ 1691 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1692 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1693 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1694 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1695 } 1696 } 1697 bzero((char *)&sc->vr_ldata->vr_tx_list, 1698 sizeof(sc->vr_ldata->vr_tx_list)); 1699 } 1700 1701 /* 1702 * Stop all chip I/O so that the kernel's probe routines don't 1703 * get confused by errant DMAs when rebooting. 1704 */ 1705 static void 1706 vr_shutdown(device_t dev) 1707 { 1708 1709 vr_detach(dev); 1710 } 1711