1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/bus_pio.h> 81 #include <machine/bus_memio.h> 82 #include <machine/bus.h> 83 #include <machine/resource.h> 84 #include <sys/bus.h> 85 #include <sys/rman.h> 86 87 #include <dev/mii/mii.h> 88 #include <dev/mii/miivar.h> 89 90 #include <pci/pcireg.h> 91 #include <pci/pcivar.h> 92 93 #define VR_USEIOSPACE 94 95 #include <pci/if_vrreg.h> 96 97 MODULE_DEPEND(vr, miibus, 1, 1, 1); 98 99 /* "controller miibus0" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 #ifndef lint 103 static const char rcsid[] = 104 "$FreeBSD$"; 105 #endif 106 107 /* 108 * Various supported device vendors/types and their names. 109 */ 110 static struct vr_type vr_devs[] = { 111 { VIA_VENDORID, VIA_DEVICEID_RHINE, 112 "VIA VT3043 Rhine I 10/100BaseTX" }, 113 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 114 "VIA VT86C100A Rhine II 10/100BaseTX" }, 115 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 116 "VIA VT6102 Rhine II 10/100BaseTX" }, 117 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 118 "Delta Electronics Rhine II 10/100BaseTX" }, 119 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 120 "Addtron Technology Rhine II 10/100BaseTX" }, 121 { 0, 0, NULL } 122 }; 123 124 static int vr_probe (device_t); 125 static int vr_attach (device_t); 126 static int vr_detach (device_t); 127 128 static int vr_newbuf (struct vr_softc *, 129 struct vr_chain_onefrag *, 130 struct mbuf *); 131 static int vr_encap (struct vr_softc *, struct vr_chain *, 132 struct mbuf * ); 133 134 static void vr_rxeof (struct vr_softc *); 135 static void vr_rxeoc (struct vr_softc *); 136 static void vr_txeof (struct vr_softc *); 137 static void vr_txeoc (struct vr_softc *); 138 static void vr_tick (void *); 139 static void vr_intr (void *); 140 static void vr_start (struct ifnet *); 141 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 142 static void vr_init (void *); 143 static void vr_stop (struct vr_softc *); 144 static void vr_watchdog (struct ifnet *); 145 static void vr_shutdown (device_t); 146 static int vr_ifmedia_upd (struct ifnet *); 147 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 149 static void vr_mii_sync (struct vr_softc *); 150 static void vr_mii_send (struct vr_softc *, u_int32_t, int); 151 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 152 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 153 static int vr_miibus_readreg (device_t, int, int); 154 static int vr_miibus_writereg (device_t, int, int, int); 155 static void vr_miibus_statchg (device_t); 156 157 static void vr_setcfg (struct vr_softc *, int); 158 static u_int8_t vr_calchash (u_int8_t *); 159 static void vr_setmulti (struct vr_softc *); 160 static void vr_reset (struct vr_softc *); 161 static int vr_list_rx_init (struct vr_softc *); 162 static int vr_list_tx_init (struct vr_softc *); 163 164 #ifdef VR_USEIOSPACE 165 #define VR_RES SYS_RES_IOPORT 166 #define VR_RID VR_PCI_LOIO 167 #else 168 #define VR_RES SYS_RES_MEMORY 169 #define VR_RID VR_PCI_LOMEM 170 #endif 171 172 static device_method_t vr_methods[] = { 173 /* Device interface */ 174 DEVMETHOD(device_probe, vr_probe), 175 DEVMETHOD(device_attach, vr_attach), 176 DEVMETHOD(device_detach, vr_detach), 177 DEVMETHOD(device_shutdown, vr_shutdown), 178 179 /* bus interface */ 180 DEVMETHOD(bus_print_child, bus_generic_print_child), 181 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 182 183 /* MII interface */ 184 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 185 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 186 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 187 188 { 0, 0 } 189 }; 190 191 static driver_t vr_driver = { 192 "vr", 193 vr_methods, 194 sizeof(struct vr_softc) 195 }; 196 197 static devclass_t vr_devclass; 198 199 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 200 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 201 202 #define VR_SETBIT(sc, reg, x) \ 203 CSR_WRITE_1(sc, reg, \ 204 CSR_READ_1(sc, reg) | x) 205 206 #define VR_CLRBIT(sc, reg, x) \ 207 CSR_WRITE_1(sc, reg, \ 208 CSR_READ_1(sc, reg) & ~x) 209 210 #define VR_SETBIT16(sc, reg, x) \ 211 CSR_WRITE_2(sc, reg, \ 212 CSR_READ_2(sc, reg) | x) 213 214 #define VR_CLRBIT16(sc, reg, x) \ 215 CSR_WRITE_2(sc, reg, \ 216 CSR_READ_2(sc, reg) & ~x) 217 218 #define VR_SETBIT32(sc, reg, x) \ 219 CSR_WRITE_4(sc, reg, \ 220 CSR_READ_4(sc, reg) | x) 221 222 #define VR_CLRBIT32(sc, reg, x) \ 223 CSR_WRITE_4(sc, reg, \ 224 CSR_READ_4(sc, reg) & ~x) 225 226 #define SIO_SET(x) \ 227 CSR_WRITE_1(sc, VR_MIICMD, \ 228 CSR_READ_1(sc, VR_MIICMD) | x) 229 230 #define SIO_CLR(x) \ 231 CSR_WRITE_1(sc, VR_MIICMD, \ 232 CSR_READ_1(sc, VR_MIICMD) & ~x) 233 234 /* 235 * Sync the PHYs by setting data bit and strobing the clock 32 times. 236 */ 237 static void vr_mii_sync(sc) 238 struct vr_softc *sc; 239 { 240 register int i; 241 242 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 243 244 for (i = 0; i < 32; i++) { 245 SIO_SET(VR_MIICMD_CLK); 246 DELAY(1); 247 SIO_CLR(VR_MIICMD_CLK); 248 DELAY(1); 249 } 250 251 return; 252 } 253 254 /* 255 * Clock a series of bits through the MII. 256 */ 257 static void vr_mii_send(sc, bits, cnt) 258 struct vr_softc *sc; 259 u_int32_t bits; 260 int cnt; 261 { 262 int i; 263 264 SIO_CLR(VR_MIICMD_CLK); 265 266 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 267 if (bits & i) { 268 SIO_SET(VR_MIICMD_DATAIN); 269 } else { 270 SIO_CLR(VR_MIICMD_DATAIN); 271 } 272 DELAY(1); 273 SIO_CLR(VR_MIICMD_CLK); 274 DELAY(1); 275 SIO_SET(VR_MIICMD_CLK); 276 } 277 } 278 279 /* 280 * Read an PHY register through the MII. 281 */ 282 static int vr_mii_readreg(sc, frame) 283 struct vr_softc *sc; 284 struct vr_mii_frame *frame; 285 286 { 287 int i, ack; 288 289 VR_LOCK(sc); 290 291 /* 292 * Set up frame for RX. 293 */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* 303 * Turn on data xmit. 304 */ 305 SIO_SET(VR_MIICMD_DIR); 306 307 vr_mii_sync(sc); 308 309 /* 310 * Send command/address info. 311 */ 312 vr_mii_send(sc, frame->mii_stdelim, 2); 313 vr_mii_send(sc, frame->mii_opcode, 2); 314 vr_mii_send(sc, frame->mii_phyaddr, 5); 315 vr_mii_send(sc, frame->mii_regaddr, 5); 316 317 /* Idle bit */ 318 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 319 DELAY(1); 320 SIO_SET(VR_MIICMD_CLK); 321 DELAY(1); 322 323 /* Turn off xmit. */ 324 SIO_CLR(VR_MIICMD_DIR); 325 326 /* Check for ack */ 327 SIO_CLR(VR_MIICMD_CLK); 328 DELAY(1); 329 SIO_SET(VR_MIICMD_CLK); 330 DELAY(1); 331 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 332 333 /* 334 * Now try reading data bits. If the ack failed, we still 335 * need to clock through 16 cycles to keep the PHY(s) in sync. 336 */ 337 if (ack) { 338 for(i = 0; i < 16; i++) { 339 SIO_CLR(VR_MIICMD_CLK); 340 DELAY(1); 341 SIO_SET(VR_MIICMD_CLK); 342 DELAY(1); 343 } 344 goto fail; 345 } 346 347 for (i = 0x8000; i; i >>= 1) { 348 SIO_CLR(VR_MIICMD_CLK); 349 DELAY(1); 350 if (!ack) { 351 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 352 frame->mii_data |= i; 353 DELAY(1); 354 } 355 SIO_SET(VR_MIICMD_CLK); 356 DELAY(1); 357 } 358 359 fail: 360 361 SIO_CLR(VR_MIICMD_CLK); 362 DELAY(1); 363 SIO_SET(VR_MIICMD_CLK); 364 DELAY(1); 365 366 VR_UNLOCK(sc); 367 368 if (ack) 369 return(1); 370 return(0); 371 } 372 373 /* 374 * Write to a PHY register through the MII. 375 */ 376 static int vr_mii_writereg(sc, frame) 377 struct vr_softc *sc; 378 struct vr_mii_frame *frame; 379 380 { 381 VR_LOCK(sc); 382 383 CSR_WRITE_1(sc, VR_MIICMD, 0); 384 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 385 386 /* 387 * Set up frame for TX. 388 */ 389 390 frame->mii_stdelim = VR_MII_STARTDELIM; 391 frame->mii_opcode = VR_MII_WRITEOP; 392 frame->mii_turnaround = VR_MII_TURNAROUND; 393 394 /* 395 * Turn on data output. 396 */ 397 SIO_SET(VR_MIICMD_DIR); 398 399 vr_mii_sync(sc); 400 401 vr_mii_send(sc, frame->mii_stdelim, 2); 402 vr_mii_send(sc, frame->mii_opcode, 2); 403 vr_mii_send(sc, frame->mii_phyaddr, 5); 404 vr_mii_send(sc, frame->mii_regaddr, 5); 405 vr_mii_send(sc, frame->mii_turnaround, 2); 406 vr_mii_send(sc, frame->mii_data, 16); 407 408 /* Idle bit. */ 409 SIO_SET(VR_MIICMD_CLK); 410 DELAY(1); 411 SIO_CLR(VR_MIICMD_CLK); 412 DELAY(1); 413 414 /* 415 * Turn off xmit. 416 */ 417 SIO_CLR(VR_MIICMD_DIR); 418 419 VR_UNLOCK(sc); 420 421 return(0); 422 } 423 424 static int vr_miibus_readreg(dev, phy, reg) 425 device_t dev; 426 int phy, reg; 427 { 428 struct vr_softc *sc; 429 struct vr_mii_frame frame; 430 431 sc = device_get_softc(dev); 432 bzero((char *)&frame, sizeof(frame)); 433 434 frame.mii_phyaddr = phy; 435 frame.mii_regaddr = reg; 436 vr_mii_readreg(sc, &frame); 437 438 return(frame.mii_data); 439 } 440 441 static int vr_miibus_writereg(dev, phy, reg, data) 442 device_t dev; 443 u_int16_t phy, reg, data; 444 { 445 struct vr_softc *sc; 446 struct vr_mii_frame frame; 447 448 sc = device_get_softc(dev); 449 bzero((char *)&frame, sizeof(frame)); 450 451 frame.mii_phyaddr = phy; 452 frame.mii_regaddr = reg; 453 frame.mii_data = data; 454 455 vr_mii_writereg(sc, &frame); 456 457 return(0); 458 } 459 460 static void vr_miibus_statchg(dev) 461 device_t dev; 462 { 463 struct vr_softc *sc; 464 struct mii_data *mii; 465 466 sc = device_get_softc(dev); 467 VR_LOCK(sc); 468 mii = device_get_softc(sc->vr_miibus); 469 vr_setcfg(sc, mii->mii_media_active); 470 VR_UNLOCK(sc); 471 472 return; 473 } 474 475 /* 476 * Calculate CRC of a multicast group address, return the lower 6 bits. 477 */ 478 static u_int8_t vr_calchash(addr) 479 u_int8_t *addr; 480 { 481 u_int32_t crc, carry; 482 int i, j; 483 u_int8_t c; 484 485 /* Compute CRC for the address value. */ 486 crc = 0xFFFFFFFF; /* initial value */ 487 488 for (i = 0; i < 6; i++) { 489 c = *(addr + i); 490 for (j = 0; j < 8; j++) { 491 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 492 crc <<= 1; 493 c >>= 1; 494 if (carry) 495 crc = (crc ^ 0x04c11db6) | carry; 496 } 497 } 498 499 /* return the filter bit position */ 500 return((crc >> 26) & 0x0000003F); 501 } 502 503 /* 504 * Program the 64-bit multicast hash filter. 505 */ 506 static void vr_setmulti(sc) 507 struct vr_softc *sc; 508 { 509 struct ifnet *ifp; 510 int h = 0; 511 u_int32_t hashes[2] = { 0, 0 }; 512 struct ifmultiaddr *ifma; 513 u_int8_t rxfilt; 514 int mcnt = 0; 515 516 ifp = &sc->arpcom.ac_if; 517 518 rxfilt = CSR_READ_1(sc, VR_RXCFG); 519 520 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 521 rxfilt |= VR_RXCFG_RX_MULTI; 522 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 523 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 524 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 525 return; 526 } 527 528 /* first, zot all the existing hash bits */ 529 CSR_WRITE_4(sc, VR_MAR0, 0); 530 CSR_WRITE_4(sc, VR_MAR1, 0); 531 532 /* now program new ones */ 533 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 534 if (ifma->ifma_addr->sa_family != AF_LINK) 535 continue; 536 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 537 if (h < 32) 538 hashes[0] |= (1 << h); 539 else 540 hashes[1] |= (1 << (h - 32)); 541 mcnt++; 542 } 543 544 if (mcnt) 545 rxfilt |= VR_RXCFG_RX_MULTI; 546 else 547 rxfilt &= ~VR_RXCFG_RX_MULTI; 548 549 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 550 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 551 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 552 553 return; 554 } 555 556 /* 557 * In order to fiddle with the 558 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 559 * first have to put the transmit and/or receive logic in the idle state. 560 */ 561 static void vr_setcfg(sc, media) 562 struct vr_softc *sc; 563 int media; 564 { 565 int restart = 0; 566 567 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 568 restart = 1; 569 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 570 } 571 572 if ((media & IFM_GMASK) == IFM_FDX) 573 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 574 else 575 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 577 if (restart) 578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 579 580 return; 581 } 582 583 static void vr_reset(sc) 584 struct vr_softc *sc; 585 { 586 register int i; 587 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 589 590 for (i = 0; i < VR_TIMEOUT; i++) { 591 DELAY(10); 592 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 593 break; 594 } 595 if (i == VR_TIMEOUT) 596 printf("vr%d: reset never completed!\n", sc->vr_unit); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600 601 return; 602 } 603 604 /* 605 * Probe for a VIA Rhine chip. Check the PCI vendor and device 606 * IDs against our list and return a device name if we find a match. 607 */ 608 static int vr_probe(dev) 609 device_t dev; 610 { 611 struct vr_type *t; 612 613 t = vr_devs; 614 615 while(t->vr_name != NULL) { 616 if ((pci_get_vendor(dev) == t->vr_vid) && 617 (pci_get_device(dev) == t->vr_did)) { 618 device_set_desc(dev, t->vr_name); 619 return(0); 620 } 621 t++; 622 } 623 624 return(ENXIO); 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 static int vr_attach(dev) 632 device_t dev; 633 { 634 int i; 635 u_char eaddr[ETHER_ADDR_LEN]; 636 u_int32_t command; 637 struct vr_softc *sc; 638 struct ifnet *ifp; 639 int unit, error = 0, rid; 640 641 sc = device_get_softc(dev); 642 unit = device_get_unit(dev); 643 bzero(sc, sizeof(struct vr_softc *)); 644 645 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 646 MTX_DEF | MTX_RECURSE); 647 VR_LOCK(sc); 648 649 /* 650 * Handle power management nonsense. 651 */ 652 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 653 u_int32_t iobase, membase, irq; 654 655 /* Save important PCI config data. */ 656 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 657 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 658 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 659 660 /* Reset the power state. */ 661 printf("vr%d: chip is in D%d power mode " 662 "-- setting to D0\n", unit, 663 pci_get_powerstate(dev)); 664 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 665 666 /* Restore PCI config data. */ 667 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 668 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 669 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 670 } 671 672 /* 673 * Map control/status registers. 674 */ 675 pci_enable_busmaster(dev); 676 pci_enable_io(dev, SYS_RES_IOPORT); 677 pci_enable_io(dev, SYS_RES_MEMORY); 678 command = pci_read_config(dev, PCIR_COMMAND, 4); 679 680 #ifdef VR_USEIOSPACE 681 if (!(command & PCIM_CMD_PORTEN)) { 682 printf("vr%d: failed to enable I/O ports!\n", unit); 683 free(sc, M_DEVBUF); 684 goto fail; 685 } 686 #else 687 if (!(command & PCIM_CMD_MEMEN)) { 688 printf("vr%d: failed to enable memory mapping!\n", unit); 689 goto fail; 690 } 691 #endif 692 693 rid = VR_RID; 694 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 695 0, ~0, 1, RF_ACTIVE); 696 697 if (sc->vr_res == NULL) { 698 printf("vr%d: couldn't map ports/memory\n", unit); 699 error = ENXIO; 700 goto fail; 701 } 702 703 sc->vr_btag = rman_get_bustag(sc->vr_res); 704 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 705 706 /* Allocate interrupt */ 707 rid = 0; 708 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 709 RF_SHAREABLE | RF_ACTIVE); 710 711 if (sc->vr_irq == NULL) { 712 printf("vr%d: couldn't map interrupt\n", unit); 713 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 714 error = ENXIO; 715 goto fail; 716 } 717 718 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 719 vr_intr, sc, &sc->vr_intrhand); 720 721 if (error) { 722 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 723 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 724 printf("vr%d: couldn't set up irq\n", unit); 725 goto fail; 726 } 727 728 /* 729 * Windows may put the chip in suspend mode when it 730 * shuts down. Be sure to kick it in the head to wake it 731 * up again. 732 */ 733 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 734 735 /* Reset the adapter. */ 736 vr_reset(sc); 737 738 /* 739 * Get station address. The way the Rhine chips work, 740 * you're not allowed to directly access the EEPROM once 741 * they've been programmed a special way. Consequently, 742 * we need to read the node address from the PAR0 and PAR1 743 * registers. 744 */ 745 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 746 DELAY(200); 747 for (i = 0; i < ETHER_ADDR_LEN; i++) 748 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 749 750 /* 751 * A Rhine chip was detected. Inform the world. 752 */ 753 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 754 755 sc->vr_unit = unit; 756 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 757 758 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 759 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 760 761 if (sc->vr_ldata == NULL) { 762 printf("vr%d: no memory for list buffers!\n", unit); 763 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 764 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 765 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 766 error = ENXIO; 767 goto fail; 768 } 769 770 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 771 772 ifp = &sc->arpcom.ac_if; 773 ifp->if_softc = sc; 774 ifp->if_unit = unit; 775 ifp->if_name = "vr"; 776 ifp->if_mtu = ETHERMTU; 777 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 778 ifp->if_ioctl = vr_ioctl; 779 ifp->if_output = ether_output; 780 ifp->if_start = vr_start; 781 ifp->if_watchdog = vr_watchdog; 782 ifp->if_init = vr_init; 783 ifp->if_baudrate = 10000000; 784 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 785 786 /* 787 * Do MII setup. 788 */ 789 if (mii_phy_probe(dev, &sc->vr_miibus, 790 vr_ifmedia_upd, vr_ifmedia_sts)) { 791 printf("vr%d: MII without any phy!\n", sc->vr_unit); 792 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 793 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 794 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 795 contigfree(sc->vr_ldata, 796 sizeof(struct vr_list_data), M_DEVBUF); 797 error = ENXIO; 798 goto fail; 799 } 800 801 callout_handle_init(&sc->vr_stat_ch); 802 803 /* 804 * Call MI attach routine. 805 */ 806 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 807 VR_UNLOCK(sc); 808 return(0); 809 810 fail: 811 VR_UNLOCK(sc); 812 mtx_destroy(&sc->vr_mtx); 813 814 return(error); 815 } 816 817 static int vr_detach(dev) 818 device_t dev; 819 { 820 struct vr_softc *sc; 821 struct ifnet *ifp; 822 823 sc = device_get_softc(dev); 824 VR_LOCK(sc); 825 ifp = &sc->arpcom.ac_if; 826 827 vr_stop(sc); 828 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 829 830 bus_generic_detach(dev); 831 device_delete_child(dev, sc->vr_miibus); 832 833 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 834 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 835 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 836 837 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 838 839 VR_UNLOCK(sc); 840 mtx_destroy(&sc->vr_mtx); 841 842 return(0); 843 } 844 845 /* 846 * Initialize the transmit descriptors. 847 */ 848 static int vr_list_tx_init(sc) 849 struct vr_softc *sc; 850 { 851 struct vr_chain_data *cd; 852 struct vr_list_data *ld; 853 int i; 854 855 cd = &sc->vr_cdata; 856 ld = sc->vr_ldata; 857 for (i = 0; i < VR_TX_LIST_CNT; i++) { 858 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 859 if (i == (VR_TX_LIST_CNT - 1)) 860 cd->vr_tx_chain[i].vr_nextdesc = 861 &cd->vr_tx_chain[0]; 862 else 863 cd->vr_tx_chain[i].vr_nextdesc = 864 &cd->vr_tx_chain[i + 1]; 865 } 866 867 cd->vr_tx_free = &cd->vr_tx_chain[0]; 868 cd->vr_tx_tail = cd->vr_tx_head = NULL; 869 870 return(0); 871 } 872 873 874 /* 875 * Initialize the RX descriptors and allocate mbufs for them. Note that 876 * we arrange the descriptors in a closed ring, so that the last descriptor 877 * points back to the first. 878 */ 879 static int vr_list_rx_init(sc) 880 struct vr_softc *sc; 881 { 882 struct vr_chain_data *cd; 883 struct vr_list_data *ld; 884 int i; 885 886 cd = &sc->vr_cdata; 887 ld = sc->vr_ldata; 888 889 for (i = 0; i < VR_RX_LIST_CNT; i++) { 890 cd->vr_rx_chain[i].vr_ptr = 891 (struct vr_desc *)&ld->vr_rx_list[i]; 892 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 893 return(ENOBUFS); 894 if (i == (VR_RX_LIST_CNT - 1)) { 895 cd->vr_rx_chain[i].vr_nextdesc = 896 &cd->vr_rx_chain[0]; 897 ld->vr_rx_list[i].vr_next = 898 vtophys(&ld->vr_rx_list[0]); 899 } else { 900 cd->vr_rx_chain[i].vr_nextdesc = 901 &cd->vr_rx_chain[i + 1]; 902 ld->vr_rx_list[i].vr_next = 903 vtophys(&ld->vr_rx_list[i + 1]); 904 } 905 } 906 907 cd->vr_rx_head = &cd->vr_rx_chain[0]; 908 909 return(0); 910 } 911 912 /* 913 * Initialize an RX descriptor and attach an MBUF cluster. 914 * Note: the length fields are only 11 bits wide, which means the 915 * largest size we can specify is 2047. This is important because 916 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 917 * overflow the field and make a mess. 918 */ 919 static int vr_newbuf(sc, c, m) 920 struct vr_softc *sc; 921 struct vr_chain_onefrag *c; 922 struct mbuf *m; 923 { 924 struct mbuf *m_new = NULL; 925 926 if (m == NULL) { 927 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 928 if (m_new == NULL) 929 return(ENOBUFS); 930 931 MCLGET(m_new, M_DONTWAIT); 932 if (!(m_new->m_flags & M_EXT)) { 933 m_freem(m_new); 934 return(ENOBUFS); 935 } 936 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 937 } else { 938 m_new = m; 939 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 940 m_new->m_data = m_new->m_ext.ext_buf; 941 } 942 943 m_adj(m_new, sizeof(u_int64_t)); 944 945 c->vr_mbuf = m_new; 946 c->vr_ptr->vr_status = VR_RXSTAT; 947 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 948 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 949 950 return(0); 951 } 952 953 /* 954 * A frame has been uploaded: pass the resulting mbuf chain up to 955 * the higher level protocols. 956 */ 957 static void vr_rxeof(sc) 958 struct vr_softc *sc; 959 { 960 struct ether_header *eh; 961 struct mbuf *m; 962 struct ifnet *ifp; 963 struct vr_chain_onefrag *cur_rx; 964 int total_len = 0; 965 u_int32_t rxstat; 966 967 ifp = &sc->arpcom.ac_if; 968 969 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 970 VR_RXSTAT_OWN)) { 971 struct mbuf *m0 = NULL; 972 973 cur_rx = sc->vr_cdata.vr_rx_head; 974 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 975 m = cur_rx->vr_mbuf; 976 977 /* 978 * If an error occurs, update stats, clear the 979 * status word and leave the mbuf cluster in place: 980 * it should simply get re-used next time this descriptor 981 * comes up in the ring. 982 */ 983 if (rxstat & VR_RXSTAT_RXERR) { 984 ifp->if_ierrors++; 985 printf("vr%d: rx error: ", sc->vr_unit); 986 switch(rxstat & 0x000000FF) { 987 case VR_RXSTAT_CRCERR: 988 printf("crc error\n"); 989 break; 990 case VR_RXSTAT_FRAMEALIGNERR: 991 printf("frame alignment error\n"); 992 break; 993 case VR_RXSTAT_FIFOOFLOW: 994 printf("FIFO overflow\n"); 995 break; 996 case VR_RXSTAT_GIANT: 997 printf("received giant packet\n"); 998 break; 999 case VR_RXSTAT_RUNT: 1000 printf("received runt packet\n"); 1001 break; 1002 case VR_RXSTAT_BUSERR: 1003 printf("system bus error\n"); 1004 break; 1005 case VR_RXSTAT_BUFFERR: 1006 printf("rx buffer error\n"); 1007 break; 1008 default: 1009 printf("unknown rx error\n"); 1010 break; 1011 } 1012 vr_newbuf(sc, cur_rx, m); 1013 continue; 1014 } 1015 1016 /* No errors; receive the packet. */ 1017 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1018 1019 /* 1020 * XXX The VIA Rhine chip includes the CRC with every 1021 * received frame, and there's no way to turn this 1022 * behavior off (at least, I can't find anything in 1023 * the manual that explains how to do it) so we have 1024 * to trim off the CRC manually. 1025 */ 1026 total_len -= ETHER_CRC_LEN; 1027 1028 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1029 NULL); 1030 vr_newbuf(sc, cur_rx, m); 1031 if (m0 == NULL) { 1032 ifp->if_ierrors++; 1033 continue; 1034 } 1035 m = m0; 1036 1037 ifp->if_ipackets++; 1038 eh = mtod(m, struct ether_header *); 1039 1040 /* Remove header from mbuf and pass it on. */ 1041 m_adj(m, sizeof(struct ether_header)); 1042 ether_input(ifp, eh, m); 1043 } 1044 1045 return; 1046 } 1047 1048 void vr_rxeoc(sc) 1049 struct vr_softc *sc; 1050 { 1051 1052 vr_rxeof(sc); 1053 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1054 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1055 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1056 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1057 1058 return; 1059 } 1060 1061 /* 1062 * A frame was downloaded to the chip. It's safe for us to clean up 1063 * the list buffers. 1064 */ 1065 1066 static void vr_txeof(sc) 1067 struct vr_softc *sc; 1068 { 1069 struct vr_chain *cur_tx; 1070 struct ifnet *ifp; 1071 1072 ifp = &sc->arpcom.ac_if; 1073 1074 /* Reset the timeout timer; if_txeoc will clear it. */ 1075 ifp->if_timer = 5; 1076 1077 /* Sanity check. */ 1078 if (sc->vr_cdata.vr_tx_head == NULL) 1079 return; 1080 1081 /* 1082 * Go through our tx list and free mbufs for those 1083 * frames that have been transmitted. 1084 */ 1085 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1086 u_int32_t txstat; 1087 1088 cur_tx = sc->vr_cdata.vr_tx_head; 1089 txstat = cur_tx->vr_ptr->vr_status; 1090 1091 if ((txstat & VR_TXSTAT_ABRT) || 1092 (txstat & VR_TXSTAT_UDF)) { 1093 while (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON) 1094 ; /* Wait for chip to shutdown */ 1095 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1096 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1097 break; 1098 } 1099 1100 if (txstat & VR_TXSTAT_OWN) 1101 break; 1102 1103 if (txstat & VR_TXSTAT_ERRSUM) { 1104 ifp->if_oerrors++; 1105 if (txstat & VR_TXSTAT_DEFER) 1106 ifp->if_collisions++; 1107 if (txstat & VR_TXSTAT_LATECOLL) 1108 ifp->if_collisions++; 1109 } 1110 1111 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1112 1113 ifp->if_opackets++; 1114 if (cur_tx->vr_mbuf != NULL) { 1115 m_freem(cur_tx->vr_mbuf); 1116 cur_tx->vr_mbuf = NULL; 1117 } 1118 1119 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1120 sc->vr_cdata.vr_tx_head = NULL; 1121 sc->vr_cdata.vr_tx_tail = NULL; 1122 break; 1123 } 1124 1125 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1126 } 1127 1128 return; 1129 } 1130 1131 /* 1132 * TX 'end of channel' interrupt handler. 1133 */ 1134 static void vr_txeoc(sc) 1135 struct vr_softc *sc; 1136 { 1137 struct ifnet *ifp; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 1141 if (sc->vr_cdata.vr_tx_head == NULL) { 1142 ifp->if_flags &= ~IFF_OACTIVE; 1143 sc->vr_cdata.vr_tx_tail = NULL; 1144 ifp->if_timer = 0; 1145 } 1146 1147 return; 1148 } 1149 1150 static void vr_tick(xsc) 1151 void *xsc; 1152 { 1153 struct vr_softc *sc; 1154 struct mii_data *mii; 1155 1156 sc = xsc; 1157 VR_LOCK(sc); 1158 mii = device_get_softc(sc->vr_miibus); 1159 mii_tick(mii); 1160 1161 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1162 1163 VR_UNLOCK(sc); 1164 1165 return; 1166 } 1167 1168 static void vr_intr(arg) 1169 void *arg; 1170 { 1171 struct vr_softc *sc; 1172 struct ifnet *ifp; 1173 u_int16_t status; 1174 1175 sc = arg; 1176 VR_LOCK(sc); 1177 ifp = &sc->arpcom.ac_if; 1178 1179 /* Supress unwanted interrupts. */ 1180 if (!(ifp->if_flags & IFF_UP)) { 1181 vr_stop(sc); 1182 VR_UNLOCK(sc); 1183 return; 1184 } 1185 1186 /* Disable interrupts. */ 1187 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1188 1189 for (;;) { 1190 1191 status = CSR_READ_2(sc, VR_ISR); 1192 if (status) 1193 CSR_WRITE_2(sc, VR_ISR, status); 1194 1195 if ((status & VR_INTRS) == 0) 1196 break; 1197 1198 if (status & VR_ISR_RX_OK) 1199 vr_rxeof(sc); 1200 1201 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1202 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1203 (status & VR_ISR_RX_DROPPED)) { 1204 vr_rxeof(sc); 1205 vr_rxeoc(sc); 1206 } 1207 1208 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1209 vr_reset(sc); 1210 vr_init(sc); 1211 break; 1212 } 1213 1214 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1215 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1216 vr_txeof(sc); 1217 if ((status & VR_ISR_UDFI) || 1218 (status & VR_ISR_TX_ABRT2) || 1219 (status & VR_ISR_TX_ABRT)) { 1220 ifp->if_oerrors++; 1221 if (sc->vr_cdata.vr_tx_head != NULL) { 1222 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1223 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1224 } 1225 } else 1226 vr_txeoc(sc); 1227 } 1228 1229 } 1230 1231 /* Re-enable interrupts. */ 1232 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1233 1234 if (ifp->if_snd.ifq_head != NULL) { 1235 vr_start(ifp); 1236 } 1237 1238 VR_UNLOCK(sc); 1239 1240 return; 1241 } 1242 1243 /* 1244 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1245 * pointers to the fragment pointers. 1246 */ 1247 static int vr_encap(sc, c, m_head) 1248 struct vr_softc *sc; 1249 struct vr_chain *c; 1250 struct mbuf *m_head; 1251 { 1252 int frag = 0; 1253 struct vr_desc *f = NULL; 1254 int total_len; 1255 struct mbuf *m; 1256 1257 m = m_head; 1258 total_len = 0; 1259 1260 /* 1261 * The VIA Rhine wants packet buffers to be longword 1262 * aligned, but very often our mbufs aren't. Rather than 1263 * waste time trying to decide when to copy and when not 1264 * to copy, just do it all the time. 1265 */ 1266 if (m != NULL) { 1267 struct mbuf *m_new = NULL; 1268 1269 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1270 if (m_new == NULL) { 1271 printf("vr%d: no memory for tx list\n", sc->vr_unit); 1272 return(1); 1273 } 1274 if (m_head->m_pkthdr.len > MHLEN) { 1275 MCLGET(m_new, M_DONTWAIT); 1276 if (!(m_new->m_flags & M_EXT)) { 1277 m_freem(m_new); 1278 printf("vr%d: no memory for tx list\n", 1279 sc->vr_unit); 1280 return(1); 1281 } 1282 } 1283 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1284 mtod(m_new, caddr_t)); 1285 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1286 m_freem(m_head); 1287 m_head = m_new; 1288 /* 1289 * The Rhine chip doesn't auto-pad, so we have to make 1290 * sure to pad short frames out to the minimum frame length 1291 * ourselves. 1292 */ 1293 if (m_head->m_len < VR_MIN_FRAMELEN) { 1294 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1295 m_new->m_len = m_new->m_pkthdr.len; 1296 } 1297 f = c->vr_ptr; 1298 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1299 f->vr_ctl = total_len = m_new->m_len; 1300 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1301 f->vr_status = 0; 1302 frag = 1; 1303 } 1304 1305 c->vr_mbuf = m_head; 1306 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1307 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1308 1309 return(0); 1310 } 1311 1312 /* 1313 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1314 * to the mbuf data regions directly in the transmit lists. We also save a 1315 * copy of the pointers since the transmit list fragment pointers are 1316 * physical addresses. 1317 */ 1318 1319 static void vr_start(ifp) 1320 struct ifnet *ifp; 1321 { 1322 struct vr_softc *sc; 1323 struct mbuf *m_head = NULL; 1324 struct vr_chain *cur_tx = NULL, *start_tx; 1325 1326 sc = ifp->if_softc; 1327 1328 VR_LOCK(sc); 1329 if (ifp->if_flags & IFF_OACTIVE) { 1330 VR_UNLOCK(sc); 1331 return; 1332 } 1333 1334 /* 1335 * Check for an available queue slot. If there are none, 1336 * punt. 1337 */ 1338 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1339 ifp->if_flags |= IFF_OACTIVE; 1340 return; 1341 } 1342 1343 start_tx = sc->vr_cdata.vr_tx_free; 1344 1345 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1346 IF_DEQUEUE(&ifp->if_snd, m_head); 1347 if (m_head == NULL) 1348 break; 1349 1350 /* Pick a descriptor off the free list. */ 1351 cur_tx = sc->vr_cdata.vr_tx_free; 1352 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1353 1354 /* Pack the data into the descriptor. */ 1355 if (vr_encap(sc, cur_tx, m_head)) { 1356 IF_PREPEND(&ifp->if_snd, m_head); 1357 ifp->if_flags |= IFF_OACTIVE; 1358 cur_tx = NULL; 1359 break; 1360 } 1361 1362 if (cur_tx != start_tx) 1363 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1364 1365 /* 1366 * If there's a BPF listener, bounce a copy of this frame 1367 * to him. 1368 */ 1369 if (ifp->if_bpf) 1370 bpf_mtap(ifp, cur_tx->vr_mbuf); 1371 1372 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1373 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1374 } 1375 1376 /* 1377 * If there are no frames queued, bail. 1378 */ 1379 if (cur_tx == NULL) { 1380 VR_UNLOCK(sc); 1381 return; 1382 } 1383 1384 sc->vr_cdata.vr_tx_tail = cur_tx; 1385 1386 if (sc->vr_cdata.vr_tx_head == NULL) 1387 sc->vr_cdata.vr_tx_head = start_tx; 1388 1389 /* 1390 * Set a timeout in case the chip goes out to lunch. 1391 */ 1392 ifp->if_timer = 5; 1393 VR_UNLOCK(sc); 1394 1395 return; 1396 } 1397 1398 static void vr_init(xsc) 1399 void *xsc; 1400 { 1401 struct vr_softc *sc = xsc; 1402 struct ifnet *ifp = &sc->arpcom.ac_if; 1403 struct mii_data *mii; 1404 int i; 1405 1406 VR_LOCK(sc); 1407 1408 mii = device_get_softc(sc->vr_miibus); 1409 1410 /* 1411 * Cancel pending I/O and free all RX/TX buffers. 1412 */ 1413 vr_stop(sc); 1414 vr_reset(sc); 1415 1416 /* 1417 * Set our station address. 1418 */ 1419 for (i = 0; i < ETHER_ADDR_LEN; i++) 1420 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1421 1422 /* Set DMA size */ 1423 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1424 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1425 1426 /* 1427 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1428 * so we must set both. 1429 */ 1430 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1431 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESHSTORENFWD); 1432 1433 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1434 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1435 1436 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1437 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1438 1439 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1440 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1441 1442 /* Init circular RX list. */ 1443 if (vr_list_rx_init(sc) == ENOBUFS) { 1444 printf("vr%d: initialization failed: no " 1445 "memory for rx buffers\n", sc->vr_unit); 1446 vr_stop(sc); 1447 VR_UNLOCK(sc); 1448 return; 1449 } 1450 1451 /* 1452 * Init tx descriptors. 1453 */ 1454 vr_list_tx_init(sc); 1455 1456 /* If we want promiscuous mode, set the allframes bit. */ 1457 if (ifp->if_flags & IFF_PROMISC) 1458 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1459 else 1460 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1461 1462 /* Set capture broadcast bit to capture broadcast frames. */ 1463 if (ifp->if_flags & IFF_BROADCAST) 1464 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1465 else 1466 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1467 1468 /* 1469 * Program the multicast filter, if necessary. 1470 */ 1471 vr_setmulti(sc); 1472 1473 /* 1474 * Load the address of the RX list. 1475 */ 1476 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1477 1478 /* Enable receiver and transmitter. */ 1479 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1480 VR_CMD_TX_ON|VR_CMD_RX_ON| 1481 VR_CMD_RX_GO); 1482 1483 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1484 1485 /* 1486 * Enable interrupts. 1487 */ 1488 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1489 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1490 1491 mii_mediachg(mii); 1492 1493 ifp->if_flags |= IFF_RUNNING; 1494 ifp->if_flags &= ~IFF_OACTIVE; 1495 1496 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1497 1498 VR_UNLOCK(sc); 1499 1500 return; 1501 } 1502 1503 /* 1504 * Set media options. 1505 */ 1506 static int vr_ifmedia_upd(ifp) 1507 struct ifnet *ifp; 1508 { 1509 struct vr_softc *sc; 1510 1511 sc = ifp->if_softc; 1512 1513 if (ifp->if_flags & IFF_UP) 1514 vr_init(sc); 1515 1516 return(0); 1517 } 1518 1519 /* 1520 * Report current media status. 1521 */ 1522 static void vr_ifmedia_sts(ifp, ifmr) 1523 struct ifnet *ifp; 1524 struct ifmediareq *ifmr; 1525 { 1526 struct vr_softc *sc; 1527 struct mii_data *mii; 1528 1529 sc = ifp->if_softc; 1530 mii = device_get_softc(sc->vr_miibus); 1531 mii_pollstat(mii); 1532 ifmr->ifm_active = mii->mii_media_active; 1533 ifmr->ifm_status = mii->mii_media_status; 1534 1535 return; 1536 } 1537 1538 static int vr_ioctl(ifp, command, data) 1539 struct ifnet *ifp; 1540 u_long command; 1541 caddr_t data; 1542 { 1543 struct vr_softc *sc = ifp->if_softc; 1544 struct ifreq *ifr = (struct ifreq *) data; 1545 struct mii_data *mii; 1546 int error = 0; 1547 1548 VR_LOCK(sc); 1549 1550 switch(command) { 1551 case SIOCSIFADDR: 1552 case SIOCGIFADDR: 1553 case SIOCSIFMTU: 1554 error = ether_ioctl(ifp, command, data); 1555 break; 1556 case SIOCSIFFLAGS: 1557 if (ifp->if_flags & IFF_UP) { 1558 vr_init(sc); 1559 } else { 1560 if (ifp->if_flags & IFF_RUNNING) 1561 vr_stop(sc); 1562 } 1563 error = 0; 1564 break; 1565 case SIOCADDMULTI: 1566 case SIOCDELMULTI: 1567 vr_setmulti(sc); 1568 error = 0; 1569 break; 1570 case SIOCGIFMEDIA: 1571 case SIOCSIFMEDIA: 1572 mii = device_get_softc(sc->vr_miibus); 1573 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1574 break; 1575 default: 1576 error = EINVAL; 1577 break; 1578 } 1579 1580 VR_UNLOCK(sc); 1581 1582 return(error); 1583 } 1584 1585 static void vr_watchdog(ifp) 1586 struct ifnet *ifp; 1587 { 1588 struct vr_softc *sc; 1589 1590 sc = ifp->if_softc; 1591 1592 VR_LOCK(sc); 1593 ifp->if_oerrors++; 1594 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1595 1596 vr_stop(sc); 1597 vr_reset(sc); 1598 vr_init(sc); 1599 1600 if (ifp->if_snd.ifq_head != NULL) 1601 vr_start(ifp); 1602 1603 VR_UNLOCK(sc); 1604 1605 return; 1606 } 1607 1608 /* 1609 * Stop the adapter and free any mbufs allocated to the 1610 * RX and TX lists. 1611 */ 1612 static void vr_stop(sc) 1613 struct vr_softc *sc; 1614 { 1615 register int i; 1616 struct ifnet *ifp; 1617 1618 VR_LOCK(sc); 1619 1620 ifp = &sc->arpcom.ac_if; 1621 ifp->if_timer = 0; 1622 1623 untimeout(vr_tick, sc, sc->vr_stat_ch); 1624 1625 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1626 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1627 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1628 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1629 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1630 1631 /* 1632 * Free data in the RX lists. 1633 */ 1634 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1635 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1636 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1637 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1638 } 1639 } 1640 bzero((char *)&sc->vr_ldata->vr_rx_list, 1641 sizeof(sc->vr_ldata->vr_rx_list)); 1642 1643 /* 1644 * Free the TX list buffers. 1645 */ 1646 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1647 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1648 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1649 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1650 } 1651 } 1652 1653 bzero((char *)&sc->vr_ldata->vr_tx_list, 1654 sizeof(sc->vr_ldata->vr_tx_list)); 1655 1656 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1657 VR_UNLOCK(sc); 1658 1659 return; 1660 } 1661 1662 /* 1663 * Stop all chip I/O so that the kernel's probe routines don't 1664 * get confused by errant DMAs when rebooting. 1665 */ 1666 static void vr_shutdown(dev) 1667 device_t dev; 1668 { 1669 struct vr_softc *sc; 1670 1671 sc = device_get_softc(dev); 1672 1673 vr_stop(sc); 1674 1675 return; 1676 } 1677