1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #ifdef HAVE_KERNEL_OPTION_HEADERS 64 #include "opt_device_polling.h" 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <sys/endian.h> 71 #include <sys/kernel.h> 72 #include <sys/malloc.h> 73 #include <sys/mbuf.h> 74 #include <sys/module.h> 75 #include <sys/rman.h> 76 #include <sys/socket.h> 77 #include <sys/sockio.h> 78 #include <sys/sysctl.h> 79 #include <sys/taskqueue.h> 80 81 #include <net/bpf.h> 82 #include <net/if.h> 83 #include <net/ethernet.h> 84 #include <net/if_dl.h> 85 #include <net/if_media.h> 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #include <machine/bus.h> 96 97 #include <dev/vr/if_vrreg.h> 98 99 /* "device miibus" required. See GENERIC if you get errors here. */ 100 #include "miibus_if.h" 101 102 MODULE_DEPEND(vr, pci, 1, 1, 1); 103 MODULE_DEPEND(vr, ether, 1, 1, 1); 104 MODULE_DEPEND(vr, miibus, 1, 1, 1); 105 106 /* Define to show Rx/Tx error status. */ 107 #undef VR_SHOW_ERRORS 108 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 109 110 /* 111 * Various supported device vendors/types, their names & quirks. 112 */ 113 #define VR_Q_NEEDALIGN (1<<0) 114 #define VR_Q_CSUM (1<<1) 115 #define VR_Q_CAM (1<<2) 116 117 static const struct vr_type { 118 u_int16_t vr_vid; 119 u_int16_t vr_did; 120 int vr_quirks; 121 const char *vr_name; 122 } const vr_devs[] = { 123 { VIA_VENDORID, VIA_DEVICEID_RHINE, 124 VR_Q_NEEDALIGN, 125 "VIA VT3043 Rhine I 10/100BaseTX" }, 126 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 127 VR_Q_NEEDALIGN, 128 "VIA VT86C100A Rhine II 10/100BaseTX" }, 129 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 130 0, 131 "VIA VT6102 Rhine II 10/100BaseTX" }, 132 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 133 0, 134 "VIA VT6105 Rhine III 10/100BaseTX" }, 135 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 136 VR_Q_CSUM, 137 "VIA VT6105M Rhine III 10/100BaseTX" }, 138 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 139 VR_Q_NEEDALIGN, 140 "Delta Electronics Rhine II 10/100BaseTX" }, 141 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 142 VR_Q_NEEDALIGN, 143 "Addtron Technology Rhine II 10/100BaseTX" }, 144 { 0, 0, 0, NULL } 145 }; 146 147 static int vr_probe(device_t); 148 static int vr_attach(device_t); 149 static int vr_detach(device_t); 150 static int vr_shutdown(device_t); 151 static int vr_suspend(device_t); 152 static int vr_resume(device_t); 153 154 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 155 static int vr_dma_alloc(struct vr_softc *); 156 static void vr_dma_free(struct vr_softc *); 157 static __inline void vr_discard_rxbuf(struct vr_rxdesc *); 158 static int vr_newbuf(struct vr_softc *, int); 159 160 #ifndef __NO_STRICT_ALIGNMENT 161 static __inline void vr_fixup_rx(struct mbuf *); 162 #endif 163 static int vr_rxeof(struct vr_softc *); 164 static void vr_txeof(struct vr_softc *); 165 static void vr_tick(void *); 166 static int vr_error(struct vr_softc *, uint16_t); 167 static void vr_tx_underrun(struct vr_softc *); 168 static void vr_intr(void *); 169 static void vr_start(struct ifnet *); 170 static void vr_start_locked(struct ifnet *); 171 static int vr_encap(struct vr_softc *, struct mbuf **); 172 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 173 static void vr_init(void *); 174 static void vr_init_locked(struct vr_softc *); 175 static void vr_tx_start(struct vr_softc *); 176 static void vr_rx_start(struct vr_softc *); 177 static int vr_tx_stop(struct vr_softc *); 178 static int vr_rx_stop(struct vr_softc *); 179 static void vr_stop(struct vr_softc *); 180 static void vr_watchdog(struct vr_softc *); 181 static int vr_ifmedia_upd(struct ifnet *); 182 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 183 184 static int vr_miibus_readreg(device_t, int, int); 185 static int vr_miibus_writereg(device_t, int, int, int); 186 static void vr_miibus_statchg(device_t); 187 188 static void vr_cam_mask(struct vr_softc *, uint32_t, int); 189 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 190 static void vr_set_filter(struct vr_softc *); 191 static void vr_reset(const struct vr_softc *); 192 static int vr_tx_ring_init(struct vr_softc *); 193 static int vr_rx_ring_init(struct vr_softc *); 194 static void vr_setwol(struct vr_softc *); 195 static void vr_clrwol(struct vr_softc *); 196 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 197 198 static const struct vr_tx_threshold_table { 199 int tx_cfg; 200 int bcr_cfg; 201 int value; 202 } const vr_tx_threshold_tables[] = { 203 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 204 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 205 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 206 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 207 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 208 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 209 }; 210 211 static device_method_t vr_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_probe, vr_probe), 214 DEVMETHOD(device_attach, vr_attach), 215 DEVMETHOD(device_detach, vr_detach), 216 DEVMETHOD(device_shutdown, vr_shutdown), 217 DEVMETHOD(device_suspend, vr_suspend), 218 DEVMETHOD(device_resume, vr_resume), 219 220 /* MII interface */ 221 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 222 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 223 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 224 225 DEVMETHOD_END 226 }; 227 228 static driver_t vr_driver = { 229 "vr", 230 vr_methods, 231 sizeof(struct vr_softc) 232 }; 233 234 static devclass_t vr_devclass; 235 236 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 237 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 238 239 static int 240 vr_miibus_readreg(device_t dev, int phy, int reg) 241 { 242 struct vr_softc *sc; 243 int i; 244 245 sc = device_get_softc(dev); 246 247 /* Set the register address. */ 248 CSR_WRITE_1(sc, VR_MIIADDR, reg); 249 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 250 251 for (i = 0; i < VR_MII_TIMEOUT; i++) { 252 DELAY(1); 253 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 254 break; 255 } 256 if (i == VR_MII_TIMEOUT) 257 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 258 259 return (CSR_READ_2(sc, VR_MIIDATA)); 260 } 261 262 static int 263 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 264 { 265 struct vr_softc *sc; 266 int i; 267 268 sc = device_get_softc(dev); 269 270 /* Set the register address and data to write. */ 271 CSR_WRITE_1(sc, VR_MIIADDR, reg); 272 CSR_WRITE_2(sc, VR_MIIDATA, data); 273 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 274 275 for (i = 0; i < VR_MII_TIMEOUT; i++) { 276 DELAY(1); 277 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 278 break; 279 } 280 if (i == VR_MII_TIMEOUT) 281 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 282 reg); 283 284 return (0); 285 } 286 287 /* 288 * In order to fiddle with the 289 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 290 * first have to put the transmit and/or receive logic in the idle state. 291 */ 292 static void 293 vr_miibus_statchg(device_t dev) 294 { 295 struct vr_softc *sc; 296 struct mii_data *mii; 297 struct ifnet *ifp; 298 int lfdx, mfdx; 299 uint8_t cr0, cr1, fc; 300 301 sc = device_get_softc(dev); 302 mii = device_get_softc(sc->vr_miibus); 303 ifp = sc->vr_ifp; 304 if (mii == NULL || ifp == NULL || 305 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 306 return; 307 308 sc->vr_link = 0; 309 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 310 (IFM_ACTIVE | IFM_AVALID)) { 311 switch (IFM_SUBTYPE(mii->mii_media_active)) { 312 case IFM_10_T: 313 case IFM_100_TX: 314 sc->vr_link = 1; 315 break; 316 default: 317 break; 318 } 319 } 320 321 if (sc->vr_link != 0) { 322 cr0 = CSR_READ_1(sc, VR_CR0); 323 cr1 = CSR_READ_1(sc, VR_CR1); 324 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 325 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 326 if (mfdx != lfdx) { 327 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 328 if (vr_tx_stop(sc) != 0 || 329 vr_rx_stop(sc) != 0) { 330 device_printf(sc->vr_dev, 331 "%s: Tx/Rx shutdown error -- " 332 "resetting\n", __func__); 333 sc->vr_flags |= VR_F_RESTART; 334 VR_UNLOCK(sc); 335 return; 336 } 337 } 338 if (lfdx) 339 cr1 |= VR_CR1_FULLDUPLEX; 340 else 341 cr1 &= ~VR_CR1_FULLDUPLEX; 342 CSR_WRITE_1(sc, VR_CR1, cr1); 343 } 344 fc = 0; 345 #ifdef notyet 346 /* Configure flow-control. */ 347 if (sc->vr_revid >= REV_ID_VT6105_A0) { 348 fc = CSR_READ_1(sc, VR_FLOWCR1); 349 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 350 if ((IFM_OPTIONS(mii->mii_media_active) & 351 IFM_ETH_RXPAUSE) != 0) 352 fc |= VR_FLOWCR1_RXPAUSE; 353 if ((IFM_OPTIONS(mii->mii_media_active) & 354 IFM_ETH_TXPAUSE) != 0) 355 fc |= VR_FLOWCR1_TXPAUSE; 356 CSR_WRITE_1(sc, VR_FLOWCR1, fc); 357 } else if (sc->vr_revid >= REV_ID_VT6102_A) { 358 /* No Tx puase capability available for Rhine II. */ 359 fc = CSR_READ_1(sc, VR_MISC_CR0); 360 fc &= ~VR_MISCCR0_RXPAUSE; 361 if ((IFM_OPTIONS(mii->mii_media_active) & 362 IFM_ETH_RXPAUSE) != 0) 363 fc |= VR_MISCCR0_RXPAUSE; 364 CSR_WRITE_1(sc, VR_MISC_CR0, fc); 365 } 366 #endif 367 vr_rx_start(sc); 368 vr_tx_start(sc); 369 } else { 370 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 371 device_printf(sc->vr_dev, 372 "%s: Tx/Rx shutdown error -- resetting\n", 373 __func__); 374 sc->vr_flags |= VR_F_RESTART; 375 } 376 } 377 } 378 379 380 static void 381 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 382 { 383 384 if (type == VR_MCAST_CAM) 385 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 386 else 387 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 388 CSR_WRITE_4(sc, VR_CAMMASK, mask); 389 CSR_WRITE_1(sc, VR_CAMCTL, 0); 390 } 391 392 static int 393 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 394 { 395 int i; 396 397 if (type == VR_MCAST_CAM) { 398 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 399 return (EINVAL); 400 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 401 } else 402 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 403 404 /* Set CAM entry address. */ 405 CSR_WRITE_1(sc, VR_CAMADDR, idx); 406 /* Set CAM entry data. */ 407 if (type == VR_MCAST_CAM) { 408 for (i = 0; i < ETHER_ADDR_LEN; i++) 409 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 410 } else { 411 CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 412 CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 413 } 414 DELAY(10); 415 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 416 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 417 for (i = 0; i < VR_TIMEOUT; i++) { 418 DELAY(1); 419 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 420 break; 421 } 422 423 if (i == VR_TIMEOUT) 424 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 425 __func__); 426 CSR_WRITE_1(sc, VR_CAMCTL, 0); 427 428 return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 429 } 430 431 /* 432 * Program the 64-bit multicast hash filter. 433 */ 434 static void 435 vr_set_filter(struct vr_softc *sc) 436 { 437 struct ifnet *ifp; 438 int h; 439 uint32_t hashes[2] = { 0, 0 }; 440 struct ifmultiaddr *ifma; 441 uint8_t rxfilt; 442 int error, mcnt; 443 uint32_t cam_mask; 444 445 VR_LOCK_ASSERT(sc); 446 447 ifp = sc->vr_ifp; 448 rxfilt = CSR_READ_1(sc, VR_RXCFG); 449 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 450 VR_RXCFG_RX_MULTI); 451 if (ifp->if_flags & IFF_BROADCAST) 452 rxfilt |= VR_RXCFG_RX_BROAD; 453 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 454 rxfilt |= VR_RXCFG_RX_MULTI; 455 if (ifp->if_flags & IFF_PROMISC) 456 rxfilt |= VR_RXCFG_RX_PROMISC; 457 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 458 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 459 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 460 return; 461 } 462 463 /* Now program new ones. */ 464 error = 0; 465 mcnt = 0; 466 if_maddr_rlock(ifp); 467 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 468 /* 469 * For hardwares that have CAM capability, use 470 * 32 entries multicast perfect filter. 471 */ 472 cam_mask = 0; 473 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 474 if (ifma->ifma_addr->sa_family != AF_LINK) 475 continue; 476 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 477 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 478 if (error != 0) { 479 cam_mask = 0; 480 break; 481 } 482 cam_mask |= 1 << mcnt; 483 mcnt++; 484 } 485 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 486 } 487 488 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 489 /* 490 * If there are too many multicast addresses or 491 * setting multicast CAM filter failed, use hash 492 * table based filtering. 493 */ 494 mcnt = 0; 495 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 496 if (ifma->ifma_addr->sa_family != AF_LINK) 497 continue; 498 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 499 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 500 if (h < 32) 501 hashes[0] |= (1 << h); 502 else 503 hashes[1] |= (1 << (h - 32)); 504 mcnt++; 505 } 506 } 507 if_maddr_runlock(ifp); 508 509 if (mcnt > 0) 510 rxfilt |= VR_RXCFG_RX_MULTI; 511 512 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 513 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 514 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 515 } 516 517 static void 518 vr_reset(const struct vr_softc *sc) 519 { 520 int i; 521 522 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 523 524 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 525 if (sc->vr_revid < REV_ID_VT6102_A) { 526 /* VT86C100A needs more delay after reset. */ 527 DELAY(100); 528 } 529 for (i = 0; i < VR_TIMEOUT; i++) { 530 DELAY(10); 531 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 532 break; 533 } 534 if (i == VR_TIMEOUT) { 535 if (sc->vr_revid < REV_ID_VT6102_A) 536 device_printf(sc->vr_dev, "reset never completed!\n"); 537 else { 538 /* Use newer force reset command. */ 539 device_printf(sc->vr_dev, 540 "Using force reset command.\n"); 541 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 542 /* 543 * Wait a little while for the chip to get its brains 544 * in order. 545 */ 546 DELAY(2000); 547 } 548 } 549 550 } 551 552 /* 553 * Probe for a VIA Rhine chip. Check the PCI vendor and device 554 * IDs against our list and return a match or NULL 555 */ 556 static const struct vr_type * 557 vr_match(device_t dev) 558 { 559 const struct vr_type *t = vr_devs; 560 561 for (t = vr_devs; t->vr_name != NULL; t++) 562 if ((pci_get_vendor(dev) == t->vr_vid) && 563 (pci_get_device(dev) == t->vr_did)) 564 return (t); 565 return (NULL); 566 } 567 568 /* 569 * Probe for a VIA Rhine chip. Check the PCI vendor and device 570 * IDs against our list and return a device name if we find a match. 571 */ 572 static int 573 vr_probe(device_t dev) 574 { 575 const struct vr_type *t; 576 577 t = vr_match(dev); 578 if (t != NULL) { 579 device_set_desc(dev, t->vr_name); 580 return (BUS_PROBE_DEFAULT); 581 } 582 return (ENXIO); 583 } 584 585 /* 586 * Attach the interface. Allocate softc structures, do ifmedia 587 * setup and ethernet/BPF attach. 588 */ 589 static int 590 vr_attach(device_t dev) 591 { 592 struct vr_softc *sc; 593 struct ifnet *ifp; 594 const struct vr_type *t; 595 uint8_t eaddr[ETHER_ADDR_LEN]; 596 int error, rid; 597 int i, phy, pmc; 598 599 sc = device_get_softc(dev); 600 sc->vr_dev = dev; 601 t = vr_match(dev); 602 KASSERT(t != NULL, ("Lost if_vr device match")); 603 sc->vr_quirks = t->vr_quirks; 604 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 605 606 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 607 MTX_DEF); 608 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 609 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 610 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 611 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 612 vr_sysctl_stats, "I", "Statistics"); 613 614 error = 0; 615 616 /* 617 * Map control/status registers. 618 */ 619 pci_enable_busmaster(dev); 620 sc->vr_revid = pci_get_revid(dev); 621 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 622 623 sc->vr_res_id = PCIR_BAR(0); 624 sc->vr_res_type = SYS_RES_IOPORT; 625 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 626 &sc->vr_res_id, RF_ACTIVE); 627 if (sc->vr_res == NULL) { 628 device_printf(dev, "couldn't map ports\n"); 629 error = ENXIO; 630 goto fail; 631 } 632 633 /* Allocate interrupt. */ 634 rid = 0; 635 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 636 RF_SHAREABLE | RF_ACTIVE); 637 638 if (sc->vr_irq == NULL) { 639 device_printf(dev, "couldn't map interrupt\n"); 640 error = ENXIO; 641 goto fail; 642 } 643 644 /* Allocate ifnet structure. */ 645 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 646 if (ifp == NULL) { 647 device_printf(dev, "couldn't allocate ifnet structure\n"); 648 error = ENOSPC; 649 goto fail; 650 } 651 ifp->if_softc = sc; 652 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 653 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 654 ifp->if_ioctl = vr_ioctl; 655 ifp->if_start = vr_start; 656 ifp->if_init = vr_init; 657 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 658 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 659 IFQ_SET_READY(&ifp->if_snd); 660 661 /* Configure Tx FIFO threshold. */ 662 sc->vr_txthresh = VR_TXTHRESH_MIN; 663 if (sc->vr_revid < REV_ID_VT6105_A0) { 664 /* 665 * Use store and forward mode for Rhine I/II. 666 * Otherwise they produce a lot of Tx underruns and 667 * it would take a while to get working FIFO threshold 668 * value. 669 */ 670 sc->vr_txthresh = VR_TXTHRESH_MAX; 671 } 672 if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 673 ifp->if_hwassist = VR_CSUM_FEATURES; 674 ifp->if_capabilities |= IFCAP_HWCSUM; 675 /* 676 * To update checksum field the hardware may need to 677 * store entire frames into FIFO before transmitting. 678 */ 679 sc->vr_txthresh = VR_TXTHRESH_MAX; 680 } 681 682 if (sc->vr_revid >= REV_ID_VT6102_A && 683 pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 684 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 685 686 /* Rhine supports oversized VLAN frame. */ 687 ifp->if_capabilities |= IFCAP_VLAN_MTU; 688 ifp->if_capenable = ifp->if_capabilities; 689 #ifdef DEVICE_POLLING 690 ifp->if_capabilities |= IFCAP_POLLING; 691 #endif 692 693 /* 694 * Windows may put the chip in suspend mode when it 695 * shuts down. Be sure to kick it in the head to wake it 696 * up again. 697 */ 698 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 699 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 700 701 /* 702 * Get station address. The way the Rhine chips work, 703 * you're not allowed to directly access the EEPROM once 704 * they've been programmed a special way. Consequently, 705 * we need to read the node address from the PAR0 and PAR1 706 * registers. 707 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 708 * VR_CFGC and VR_CFGD such that memory mapped IO configured 709 * by driver is reset to default state. 710 */ 711 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 712 for (i = VR_TIMEOUT; i > 0; i--) { 713 DELAY(1); 714 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 715 break; 716 } 717 if (i == 0) 718 device_printf(dev, "Reloading EEPROM timeout!\n"); 719 for (i = 0; i < ETHER_ADDR_LEN; i++) 720 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 721 722 /* Reset the adapter. */ 723 vr_reset(sc); 724 /* Ack intr & disable further interrupts. */ 725 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 726 CSR_WRITE_2(sc, VR_IMR, 0); 727 if (sc->vr_revid >= REV_ID_VT6102_A) 728 CSR_WRITE_2(sc, VR_MII_IMR, 0); 729 730 if (sc->vr_revid < REV_ID_VT6102_A) { 731 pci_write_config(dev, VR_PCI_MODE2, 732 pci_read_config(dev, VR_PCI_MODE2, 1) | 733 VR_MODE2_MODE10T, 1); 734 } else { 735 /* Report error instead of retrying forever. */ 736 pci_write_config(dev, VR_PCI_MODE2, 737 pci_read_config(dev, VR_PCI_MODE2, 1) | 738 VR_MODE2_PCEROPT, 1); 739 /* Detect MII coding error. */ 740 pci_write_config(dev, VR_PCI_MODE3, 741 pci_read_config(dev, VR_PCI_MODE3, 1) | 742 VR_MODE3_MIION, 1); 743 if (sc->vr_revid >= REV_ID_VT6105_LOM && 744 sc->vr_revid < REV_ID_VT6105M_A0) 745 pci_write_config(dev, VR_PCI_MODE2, 746 pci_read_config(dev, VR_PCI_MODE2, 1) | 747 VR_MODE2_MODE10T, 1); 748 /* Enable Memory-Read-Multiple. */ 749 if (sc->vr_revid >= REV_ID_VT6107_A1 && 750 sc->vr_revid < REV_ID_VT6105M_A0) 751 pci_write_config(dev, VR_PCI_MODE2, 752 pci_read_config(dev, VR_PCI_MODE2, 1) | 753 VR_MODE2_MRDPL, 1); 754 } 755 /* Disable MII AUTOPOLL. */ 756 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 757 758 if (vr_dma_alloc(sc) != 0) { 759 error = ENXIO; 760 goto fail; 761 } 762 763 /* Do MII setup. */ 764 if (sc->vr_revid >= REV_ID_VT6105_A0) 765 phy = 1; 766 else 767 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 768 error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 769 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0); 770 if (error != 0) { 771 device_printf(dev, "attaching PHYs failed\n"); 772 goto fail; 773 } 774 775 /* Call MI attach routine. */ 776 ether_ifattach(ifp, eaddr); 777 /* 778 * Tell the upper layer(s) we support long frames. 779 * Must appear after the call to ether_ifattach() because 780 * ether_ifattach() sets ifi_hdrlen to the default value. 781 */ 782 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 783 784 /* Hook interrupt last to avoid having to lock softc. */ 785 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 786 NULL, vr_intr, sc, &sc->vr_intrhand); 787 788 if (error) { 789 device_printf(dev, "couldn't set up irq\n"); 790 ether_ifdetach(ifp); 791 goto fail; 792 } 793 794 fail: 795 if (error) 796 vr_detach(dev); 797 798 return (error); 799 } 800 801 /* 802 * Shutdown hardware and free up resources. This can be called any 803 * time after the mutex has been initialized. It is called in both 804 * the error case in attach and the normal detach case so it needs 805 * to be careful about only freeing resources that have actually been 806 * allocated. 807 */ 808 static int 809 vr_detach(device_t dev) 810 { 811 struct vr_softc *sc = device_get_softc(dev); 812 struct ifnet *ifp = sc->vr_ifp; 813 814 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 815 816 #ifdef DEVICE_POLLING 817 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 818 ether_poll_deregister(ifp); 819 #endif 820 821 /* These should only be active if attach succeeded. */ 822 if (device_is_attached(dev)) { 823 VR_LOCK(sc); 824 sc->vr_detach = 1; 825 vr_stop(sc); 826 VR_UNLOCK(sc); 827 callout_drain(&sc->vr_stat_callout); 828 ether_ifdetach(ifp); 829 } 830 if (sc->vr_miibus) 831 device_delete_child(dev, sc->vr_miibus); 832 bus_generic_detach(dev); 833 834 if (sc->vr_intrhand) 835 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 836 if (sc->vr_irq) 837 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 838 if (sc->vr_res) 839 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 840 sc->vr_res); 841 842 if (ifp) 843 if_free(ifp); 844 845 vr_dma_free(sc); 846 847 mtx_destroy(&sc->vr_mtx); 848 849 return (0); 850 } 851 852 struct vr_dmamap_arg { 853 bus_addr_t vr_busaddr; 854 }; 855 856 static void 857 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 858 { 859 struct vr_dmamap_arg *ctx; 860 861 if (error != 0) 862 return; 863 ctx = arg; 864 ctx->vr_busaddr = segs[0].ds_addr; 865 } 866 867 static int 868 vr_dma_alloc(struct vr_softc *sc) 869 { 870 struct vr_dmamap_arg ctx; 871 struct vr_txdesc *txd; 872 struct vr_rxdesc *rxd; 873 bus_size_t tx_alignment; 874 int error, i; 875 876 /* Create parent DMA tag. */ 877 error = bus_dma_tag_create( 878 bus_get_dma_tag(sc->vr_dev), /* parent */ 879 1, 0, /* alignment, boundary */ 880 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 881 BUS_SPACE_MAXADDR, /* highaddr */ 882 NULL, NULL, /* filter, filterarg */ 883 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 884 0, /* nsegments */ 885 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 886 0, /* flags */ 887 NULL, NULL, /* lockfunc, lockarg */ 888 &sc->vr_cdata.vr_parent_tag); 889 if (error != 0) { 890 device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 891 goto fail; 892 } 893 /* Create tag for Tx ring. */ 894 error = bus_dma_tag_create( 895 sc->vr_cdata.vr_parent_tag, /* parent */ 896 VR_RING_ALIGN, 0, /* alignment, boundary */ 897 BUS_SPACE_MAXADDR, /* lowaddr */ 898 BUS_SPACE_MAXADDR, /* highaddr */ 899 NULL, NULL, /* filter, filterarg */ 900 VR_TX_RING_SIZE, /* maxsize */ 901 1, /* nsegments */ 902 VR_TX_RING_SIZE, /* maxsegsize */ 903 0, /* flags */ 904 NULL, NULL, /* lockfunc, lockarg */ 905 &sc->vr_cdata.vr_tx_ring_tag); 906 if (error != 0) { 907 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 908 goto fail; 909 } 910 911 /* Create tag for Rx ring. */ 912 error = bus_dma_tag_create( 913 sc->vr_cdata.vr_parent_tag, /* parent */ 914 VR_RING_ALIGN, 0, /* alignment, boundary */ 915 BUS_SPACE_MAXADDR, /* lowaddr */ 916 BUS_SPACE_MAXADDR, /* highaddr */ 917 NULL, NULL, /* filter, filterarg */ 918 VR_RX_RING_SIZE, /* maxsize */ 919 1, /* nsegments */ 920 VR_RX_RING_SIZE, /* maxsegsize */ 921 0, /* flags */ 922 NULL, NULL, /* lockfunc, lockarg */ 923 &sc->vr_cdata.vr_rx_ring_tag); 924 if (error != 0) { 925 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 926 goto fail; 927 } 928 929 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 930 tx_alignment = sizeof(uint32_t); 931 else 932 tx_alignment = 1; 933 /* Create tag for Tx buffers. */ 934 error = bus_dma_tag_create( 935 sc->vr_cdata.vr_parent_tag, /* parent */ 936 tx_alignment, 0, /* alignment, boundary */ 937 BUS_SPACE_MAXADDR, /* lowaddr */ 938 BUS_SPACE_MAXADDR, /* highaddr */ 939 NULL, NULL, /* filter, filterarg */ 940 MCLBYTES * VR_MAXFRAGS, /* maxsize */ 941 VR_MAXFRAGS, /* nsegments */ 942 MCLBYTES, /* maxsegsize */ 943 0, /* flags */ 944 NULL, NULL, /* lockfunc, lockarg */ 945 &sc->vr_cdata.vr_tx_tag); 946 if (error != 0) { 947 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 948 goto fail; 949 } 950 951 /* Create tag for Rx buffers. */ 952 error = bus_dma_tag_create( 953 sc->vr_cdata.vr_parent_tag, /* parent */ 954 VR_RX_ALIGN, 0, /* alignment, boundary */ 955 BUS_SPACE_MAXADDR, /* lowaddr */ 956 BUS_SPACE_MAXADDR, /* highaddr */ 957 NULL, NULL, /* filter, filterarg */ 958 MCLBYTES, /* maxsize */ 959 1, /* nsegments */ 960 MCLBYTES, /* maxsegsize */ 961 0, /* flags */ 962 NULL, NULL, /* lockfunc, lockarg */ 963 &sc->vr_cdata.vr_rx_tag); 964 if (error != 0) { 965 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 966 goto fail; 967 } 968 969 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 970 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 971 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 972 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 973 if (error != 0) { 974 device_printf(sc->vr_dev, 975 "failed to allocate DMA'able memory for Tx ring\n"); 976 goto fail; 977 } 978 979 ctx.vr_busaddr = 0; 980 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 981 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 982 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 983 if (error != 0 || ctx.vr_busaddr == 0) { 984 device_printf(sc->vr_dev, 985 "failed to load DMA'able memory for Tx ring\n"); 986 goto fail; 987 } 988 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 989 990 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 991 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 992 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 993 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 994 if (error != 0) { 995 device_printf(sc->vr_dev, 996 "failed to allocate DMA'able memory for Rx ring\n"); 997 goto fail; 998 } 999 1000 ctx.vr_busaddr = 0; 1001 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1002 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1003 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1004 if (error != 0 || ctx.vr_busaddr == 0) { 1005 device_printf(sc->vr_dev, 1006 "failed to load DMA'able memory for Rx ring\n"); 1007 goto fail; 1008 } 1009 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1010 1011 /* Create DMA maps for Tx buffers. */ 1012 for (i = 0; i < VR_TX_RING_CNT; i++) { 1013 txd = &sc->vr_cdata.vr_txdesc[i]; 1014 txd->tx_m = NULL; 1015 txd->tx_dmamap = NULL; 1016 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1017 &txd->tx_dmamap); 1018 if (error != 0) { 1019 device_printf(sc->vr_dev, 1020 "failed to create Tx dmamap\n"); 1021 goto fail; 1022 } 1023 } 1024 /* Create DMA maps for Rx buffers. */ 1025 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1026 &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1027 device_printf(sc->vr_dev, 1028 "failed to create spare Rx dmamap\n"); 1029 goto fail; 1030 } 1031 for (i = 0; i < VR_RX_RING_CNT; i++) { 1032 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1033 rxd->rx_m = NULL; 1034 rxd->rx_dmamap = NULL; 1035 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1036 &rxd->rx_dmamap); 1037 if (error != 0) { 1038 device_printf(sc->vr_dev, 1039 "failed to create Rx dmamap\n"); 1040 goto fail; 1041 } 1042 } 1043 1044 fail: 1045 return (error); 1046 } 1047 1048 static void 1049 vr_dma_free(struct vr_softc *sc) 1050 { 1051 struct vr_txdesc *txd; 1052 struct vr_rxdesc *rxd; 1053 int i; 1054 1055 /* Tx ring. */ 1056 if (sc->vr_cdata.vr_tx_ring_tag) { 1057 if (sc->vr_cdata.vr_tx_ring_map) 1058 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1059 sc->vr_cdata.vr_tx_ring_map); 1060 if (sc->vr_cdata.vr_tx_ring_map && 1061 sc->vr_rdata.vr_tx_ring) 1062 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1063 sc->vr_rdata.vr_tx_ring, 1064 sc->vr_cdata.vr_tx_ring_map); 1065 sc->vr_rdata.vr_tx_ring = NULL; 1066 sc->vr_cdata.vr_tx_ring_map = NULL; 1067 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1068 sc->vr_cdata.vr_tx_ring_tag = NULL; 1069 } 1070 /* Rx ring. */ 1071 if (sc->vr_cdata.vr_rx_ring_tag) { 1072 if (sc->vr_cdata.vr_rx_ring_map) 1073 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1074 sc->vr_cdata.vr_rx_ring_map); 1075 if (sc->vr_cdata.vr_rx_ring_map && 1076 sc->vr_rdata.vr_rx_ring) 1077 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1078 sc->vr_rdata.vr_rx_ring, 1079 sc->vr_cdata.vr_rx_ring_map); 1080 sc->vr_rdata.vr_rx_ring = NULL; 1081 sc->vr_cdata.vr_rx_ring_map = NULL; 1082 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1083 sc->vr_cdata.vr_rx_ring_tag = NULL; 1084 } 1085 /* Tx buffers. */ 1086 if (sc->vr_cdata.vr_tx_tag) { 1087 for (i = 0; i < VR_TX_RING_CNT; i++) { 1088 txd = &sc->vr_cdata.vr_txdesc[i]; 1089 if (txd->tx_dmamap) { 1090 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1091 txd->tx_dmamap); 1092 txd->tx_dmamap = NULL; 1093 } 1094 } 1095 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1096 sc->vr_cdata.vr_tx_tag = NULL; 1097 } 1098 /* Rx buffers. */ 1099 if (sc->vr_cdata.vr_rx_tag) { 1100 for (i = 0; i < VR_RX_RING_CNT; i++) { 1101 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1102 if (rxd->rx_dmamap) { 1103 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1104 rxd->rx_dmamap); 1105 rxd->rx_dmamap = NULL; 1106 } 1107 } 1108 if (sc->vr_cdata.vr_rx_sparemap) { 1109 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1110 sc->vr_cdata.vr_rx_sparemap); 1111 sc->vr_cdata.vr_rx_sparemap = 0; 1112 } 1113 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1114 sc->vr_cdata.vr_rx_tag = NULL; 1115 } 1116 1117 if (sc->vr_cdata.vr_parent_tag) { 1118 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1119 sc->vr_cdata.vr_parent_tag = NULL; 1120 } 1121 } 1122 1123 /* 1124 * Initialize the transmit descriptors. 1125 */ 1126 static int 1127 vr_tx_ring_init(struct vr_softc *sc) 1128 { 1129 struct vr_ring_data *rd; 1130 struct vr_txdesc *txd; 1131 bus_addr_t addr; 1132 int i; 1133 1134 sc->vr_cdata.vr_tx_prod = 0; 1135 sc->vr_cdata.vr_tx_cons = 0; 1136 sc->vr_cdata.vr_tx_cnt = 0; 1137 sc->vr_cdata.vr_tx_pkts = 0; 1138 1139 rd = &sc->vr_rdata; 1140 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1141 for (i = 0; i < VR_TX_RING_CNT; i++) { 1142 if (i == VR_TX_RING_CNT - 1) 1143 addr = VR_TX_RING_ADDR(sc, 0); 1144 else 1145 addr = VR_TX_RING_ADDR(sc, i + 1); 1146 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1147 txd = &sc->vr_cdata.vr_txdesc[i]; 1148 txd->tx_m = NULL; 1149 } 1150 1151 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1152 sc->vr_cdata.vr_tx_ring_map, 1153 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1154 1155 return (0); 1156 } 1157 1158 /* 1159 * Initialize the RX descriptors and allocate mbufs for them. Note that 1160 * we arrange the descriptors in a closed ring, so that the last descriptor 1161 * points back to the first. 1162 */ 1163 static int 1164 vr_rx_ring_init(struct vr_softc *sc) 1165 { 1166 struct vr_ring_data *rd; 1167 struct vr_rxdesc *rxd; 1168 bus_addr_t addr; 1169 int i; 1170 1171 sc->vr_cdata.vr_rx_cons = 0; 1172 1173 rd = &sc->vr_rdata; 1174 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1175 for (i = 0; i < VR_RX_RING_CNT; i++) { 1176 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1177 rxd->rx_m = NULL; 1178 rxd->desc = &rd->vr_rx_ring[i]; 1179 if (i == VR_RX_RING_CNT - 1) 1180 addr = VR_RX_RING_ADDR(sc, 0); 1181 else 1182 addr = VR_RX_RING_ADDR(sc, i + 1); 1183 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1184 if (vr_newbuf(sc, i) != 0) 1185 return (ENOBUFS); 1186 } 1187 1188 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1189 sc->vr_cdata.vr_rx_ring_map, 1190 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1191 1192 return (0); 1193 } 1194 1195 static __inline void 1196 vr_discard_rxbuf(struct vr_rxdesc *rxd) 1197 { 1198 struct vr_desc *desc; 1199 1200 desc = rxd->desc; 1201 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1202 desc->vr_status = htole32(VR_RXSTAT_OWN); 1203 } 1204 1205 /* 1206 * Initialize an RX descriptor and attach an MBUF cluster. 1207 * Note: the length fields are only 11 bits wide, which means the 1208 * largest size we can specify is 2047. This is important because 1209 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1210 * overflow the field and make a mess. 1211 */ 1212 static int 1213 vr_newbuf(struct vr_softc *sc, int idx) 1214 { 1215 struct vr_desc *desc; 1216 struct vr_rxdesc *rxd; 1217 struct mbuf *m; 1218 bus_dma_segment_t segs[1]; 1219 bus_dmamap_t map; 1220 int nsegs; 1221 1222 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1223 if (m == NULL) 1224 return (ENOBUFS); 1225 m->m_len = m->m_pkthdr.len = MCLBYTES; 1226 m_adj(m, sizeof(uint64_t)); 1227 1228 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1229 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1230 m_freem(m); 1231 return (ENOBUFS); 1232 } 1233 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1234 1235 rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1236 if (rxd->rx_m != NULL) { 1237 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1238 BUS_DMASYNC_POSTREAD); 1239 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1240 } 1241 map = rxd->rx_dmamap; 1242 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1243 sc->vr_cdata.vr_rx_sparemap = map; 1244 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1245 BUS_DMASYNC_PREREAD); 1246 rxd->rx_m = m; 1247 desc = rxd->desc; 1248 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1249 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1250 desc->vr_status = htole32(VR_RXSTAT_OWN); 1251 1252 return (0); 1253 } 1254 1255 #ifndef __NO_STRICT_ALIGNMENT 1256 static __inline void 1257 vr_fixup_rx(struct mbuf *m) 1258 { 1259 uint16_t *src, *dst; 1260 int i; 1261 1262 src = mtod(m, uint16_t *); 1263 dst = src - 1; 1264 1265 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1266 *dst++ = *src++; 1267 1268 m->m_data -= ETHER_ALIGN; 1269 } 1270 #endif 1271 1272 /* 1273 * A frame has been uploaded: pass the resulting mbuf chain up to 1274 * the higher level protocols. 1275 */ 1276 static int 1277 vr_rxeof(struct vr_softc *sc) 1278 { 1279 struct vr_rxdesc *rxd; 1280 struct mbuf *m; 1281 struct ifnet *ifp; 1282 struct vr_desc *cur_rx; 1283 int cons, prog, total_len, rx_npkts; 1284 uint32_t rxstat, rxctl; 1285 1286 VR_LOCK_ASSERT(sc); 1287 ifp = sc->vr_ifp; 1288 cons = sc->vr_cdata.vr_rx_cons; 1289 rx_npkts = 0; 1290 1291 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1292 sc->vr_cdata.vr_rx_ring_map, 1293 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1294 1295 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1296 #ifdef DEVICE_POLLING 1297 if (ifp->if_capenable & IFCAP_POLLING) { 1298 if (sc->rxcycles <= 0) 1299 break; 1300 sc->rxcycles--; 1301 } 1302 #endif 1303 cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1304 rxstat = le32toh(cur_rx->vr_status); 1305 rxctl = le32toh(cur_rx->vr_ctl); 1306 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1307 break; 1308 1309 prog++; 1310 rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1311 m = rxd->rx_m; 1312 1313 /* 1314 * If an error occurs, update stats, clear the 1315 * status word and leave the mbuf cluster in place: 1316 * it should simply get re-used next time this descriptor 1317 * comes up in the ring. 1318 * We don't support SG in Rx path yet, so discard 1319 * partial frame. 1320 */ 1321 if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1322 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1323 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 1324 ifp->if_ierrors++; 1325 sc->vr_stat.rx_errors++; 1326 if (rxstat & VR_RXSTAT_CRCERR) 1327 sc->vr_stat.rx_crc_errors++; 1328 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1329 sc->vr_stat.rx_alignment++; 1330 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1331 sc->vr_stat.rx_fifo_overflows++; 1332 if (rxstat & VR_RXSTAT_GIANT) 1333 sc->vr_stat.rx_giants++; 1334 if (rxstat & VR_RXSTAT_RUNT) 1335 sc->vr_stat.rx_runts++; 1336 if (rxstat & VR_RXSTAT_BUFFERR) 1337 sc->vr_stat.rx_no_buffers++; 1338 #ifdef VR_SHOW_ERRORS 1339 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1340 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1341 #endif 1342 vr_discard_rxbuf(rxd); 1343 continue; 1344 } 1345 1346 if (vr_newbuf(sc, cons) != 0) { 1347 ifp->if_iqdrops++; 1348 sc->vr_stat.rx_errors++; 1349 sc->vr_stat.rx_no_mbufs++; 1350 vr_discard_rxbuf(rxd); 1351 continue; 1352 } 1353 1354 /* 1355 * XXX The VIA Rhine chip includes the CRC with every 1356 * received frame, and there's no way to turn this 1357 * behavior off (at least, I can't find anything in 1358 * the manual that explains how to do it) so we have 1359 * to trim off the CRC manually. 1360 */ 1361 total_len = VR_RXBYTES(rxstat); 1362 total_len -= ETHER_CRC_LEN; 1363 m->m_pkthdr.len = m->m_len = total_len; 1364 #ifndef __NO_STRICT_ALIGNMENT 1365 /* 1366 * RX buffers must be 32-bit aligned. 1367 * Ignore the alignment problems on the non-strict alignment 1368 * platform. The performance hit incurred due to unaligned 1369 * accesses is much smaller than the hit produced by forcing 1370 * buffer copies all the time. 1371 */ 1372 vr_fixup_rx(m); 1373 #endif 1374 m->m_pkthdr.rcvif = ifp; 1375 ifp->if_ipackets++; 1376 sc->vr_stat.rx_ok++; 1377 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1378 (rxstat & VR_RXSTAT_FRAG) == 0 && 1379 (rxctl & VR_RXCTL_IP) != 0) { 1380 /* Checksum is valid for non-fragmented IP packets. */ 1381 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1382 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1383 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1384 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1385 m->m_pkthdr.csum_flags |= 1386 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1387 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1388 m->m_pkthdr.csum_data = 0xffff; 1389 } 1390 } 1391 } 1392 VR_UNLOCK(sc); 1393 (*ifp->if_input)(ifp, m); 1394 VR_LOCK(sc); 1395 rx_npkts++; 1396 } 1397 1398 if (prog > 0) { 1399 sc->vr_cdata.vr_rx_cons = cons; 1400 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1401 sc->vr_cdata.vr_rx_ring_map, 1402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1403 } 1404 return (rx_npkts); 1405 } 1406 1407 /* 1408 * A frame was downloaded to the chip. It's safe for us to clean up 1409 * the list buffers. 1410 */ 1411 static void 1412 vr_txeof(struct vr_softc *sc) 1413 { 1414 struct vr_txdesc *txd; 1415 struct vr_desc *cur_tx; 1416 struct ifnet *ifp; 1417 uint32_t txctl, txstat; 1418 int cons, prod; 1419 1420 VR_LOCK_ASSERT(sc); 1421 1422 cons = sc->vr_cdata.vr_tx_cons; 1423 prod = sc->vr_cdata.vr_tx_prod; 1424 if (cons == prod) 1425 return; 1426 1427 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1428 sc->vr_cdata.vr_tx_ring_map, 1429 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1430 1431 ifp = sc->vr_ifp; 1432 /* 1433 * Go through our tx list and free mbufs for those 1434 * frames that have been transmitted. 1435 */ 1436 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1437 cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1438 txctl = le32toh(cur_tx->vr_ctl); 1439 txstat = le32toh(cur_tx->vr_status); 1440 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1441 break; 1442 1443 sc->vr_cdata.vr_tx_cnt--; 1444 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1445 /* Only the first descriptor in the chain is valid. */ 1446 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1447 continue; 1448 1449 txd = &sc->vr_cdata.vr_txdesc[cons]; 1450 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1451 __func__)); 1452 1453 if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1454 ifp->if_oerrors++; 1455 sc->vr_stat.tx_errors++; 1456 if ((txstat & VR_TXSTAT_ABRT) != 0) { 1457 /* Give up and restart Tx. */ 1458 sc->vr_stat.tx_abort++; 1459 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1460 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1461 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1462 txd->tx_dmamap); 1463 m_freem(txd->tx_m); 1464 txd->tx_m = NULL; 1465 VR_INC(cons, VR_TX_RING_CNT); 1466 sc->vr_cdata.vr_tx_cons = cons; 1467 if (vr_tx_stop(sc) != 0) { 1468 device_printf(sc->vr_dev, 1469 "%s: Tx shutdown error -- " 1470 "resetting\n", __func__); 1471 sc->vr_flags |= VR_F_RESTART; 1472 return; 1473 } 1474 vr_tx_start(sc); 1475 break; 1476 } 1477 if ((sc->vr_revid < REV_ID_VT3071_A && 1478 (txstat & VR_TXSTAT_UNDERRUN)) || 1479 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1480 sc->vr_stat.tx_underrun++; 1481 /* Retry and restart Tx. */ 1482 sc->vr_cdata.vr_tx_cnt++; 1483 sc->vr_cdata.vr_tx_cons = cons; 1484 cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1485 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1486 sc->vr_cdata.vr_tx_ring_map, 1487 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1488 vr_tx_underrun(sc); 1489 return; 1490 } 1491 if ((txstat & VR_TXSTAT_DEFER) != 0) { 1492 ifp->if_collisions++; 1493 sc->vr_stat.tx_collisions++; 1494 } 1495 if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 1496 ifp->if_collisions++; 1497 sc->vr_stat.tx_late_collisions++; 1498 } 1499 } else { 1500 sc->vr_stat.tx_ok++; 1501 ifp->if_opackets++; 1502 } 1503 1504 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1505 BUS_DMASYNC_POSTWRITE); 1506 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1507 if (sc->vr_revid < REV_ID_VT3071_A) { 1508 ifp->if_collisions += 1509 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1510 sc->vr_stat.tx_collisions += 1511 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1512 } else { 1513 ifp->if_collisions += (txstat & 0x0f); 1514 sc->vr_stat.tx_collisions += (txstat & 0x0f); 1515 } 1516 m_freem(txd->tx_m); 1517 txd->tx_m = NULL; 1518 } 1519 1520 sc->vr_cdata.vr_tx_cons = cons; 1521 if (sc->vr_cdata.vr_tx_cnt == 0) 1522 sc->vr_watchdog_timer = 0; 1523 } 1524 1525 static void 1526 vr_tick(void *xsc) 1527 { 1528 struct vr_softc *sc; 1529 struct mii_data *mii; 1530 1531 sc = (struct vr_softc *)xsc; 1532 1533 VR_LOCK_ASSERT(sc); 1534 1535 if ((sc->vr_flags & VR_F_RESTART) != 0) { 1536 device_printf(sc->vr_dev, "restarting\n"); 1537 sc->vr_stat.num_restart++; 1538 sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1539 vr_init_locked(sc); 1540 sc->vr_flags &= ~VR_F_RESTART; 1541 } 1542 1543 mii = device_get_softc(sc->vr_miibus); 1544 mii_tick(mii); 1545 if (sc->vr_link == 0) 1546 vr_miibus_statchg(sc->vr_dev); 1547 vr_watchdog(sc); 1548 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1549 } 1550 1551 #ifdef DEVICE_POLLING 1552 static poll_handler_t vr_poll; 1553 static poll_handler_t vr_poll_locked; 1554 1555 static int 1556 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1557 { 1558 struct vr_softc *sc; 1559 int rx_npkts; 1560 1561 sc = ifp->if_softc; 1562 rx_npkts = 0; 1563 1564 VR_LOCK(sc); 1565 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1566 rx_npkts = vr_poll_locked(ifp, cmd, count); 1567 VR_UNLOCK(sc); 1568 return (rx_npkts); 1569 } 1570 1571 static int 1572 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1573 { 1574 struct vr_softc *sc; 1575 int rx_npkts; 1576 1577 sc = ifp->if_softc; 1578 1579 VR_LOCK_ASSERT(sc); 1580 1581 sc->rxcycles = count; 1582 rx_npkts = vr_rxeof(sc); 1583 vr_txeof(sc); 1584 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1585 vr_start_locked(ifp); 1586 1587 if (cmd == POLL_AND_CHECK_STATUS) { 1588 uint16_t status; 1589 1590 /* Also check status register. */ 1591 status = CSR_READ_2(sc, VR_ISR); 1592 if (status) 1593 CSR_WRITE_2(sc, VR_ISR, status); 1594 1595 if ((status & VR_INTRS) == 0) 1596 return (rx_npkts); 1597 1598 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1599 VR_ISR_STATSOFLOW)) != 0) { 1600 if (vr_error(sc, status) != 0) 1601 return (rx_npkts); 1602 } 1603 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1604 #ifdef VR_SHOW_ERRORS 1605 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1606 __func__, status, VR_ISR_ERR_BITS); 1607 #endif 1608 vr_rx_start(sc); 1609 } 1610 } 1611 return (rx_npkts); 1612 } 1613 #endif /* DEVICE_POLLING */ 1614 1615 /* Back off the transmit threshold. */ 1616 static void 1617 vr_tx_underrun(struct vr_softc *sc) 1618 { 1619 int thresh; 1620 1621 device_printf(sc->vr_dev, "Tx underrun -- "); 1622 if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1623 thresh = sc->vr_txthresh; 1624 sc->vr_txthresh++; 1625 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1626 sc->vr_txthresh = VR_TXTHRESH_MAX; 1627 printf("using store and forward mode\n"); 1628 } else 1629 printf("increasing Tx threshold(%d -> %d)\n", 1630 vr_tx_threshold_tables[thresh].value, 1631 vr_tx_threshold_tables[thresh + 1].value); 1632 } else 1633 printf("\n"); 1634 sc->vr_stat.tx_underrun++; 1635 if (vr_tx_stop(sc) != 0) { 1636 device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1637 "resetting\n", __func__); 1638 sc->vr_flags |= VR_F_RESTART; 1639 return; 1640 } 1641 vr_tx_start(sc); 1642 } 1643 1644 static void 1645 vr_intr(void *arg) 1646 { 1647 struct vr_softc *sc; 1648 struct ifnet *ifp; 1649 uint16_t status; 1650 1651 sc = (struct vr_softc *)arg; 1652 1653 VR_LOCK(sc); 1654 1655 if (sc->vr_suspended != 0) 1656 goto done_locked; 1657 1658 status = CSR_READ_2(sc, VR_ISR); 1659 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1660 goto done_locked; 1661 1662 ifp = sc->vr_ifp; 1663 #ifdef DEVICE_POLLING 1664 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1665 goto done_locked; 1666 #endif 1667 1668 /* Suppress unwanted interrupts. */ 1669 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1670 (sc->vr_flags & VR_F_RESTART) != 0) { 1671 CSR_WRITE_2(sc, VR_IMR, 0); 1672 CSR_WRITE_2(sc, VR_ISR, status); 1673 goto done_locked; 1674 } 1675 1676 /* Disable interrupts. */ 1677 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1678 1679 for (; (status & VR_INTRS) != 0;) { 1680 CSR_WRITE_2(sc, VR_ISR, status); 1681 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1682 VR_ISR_STATSOFLOW)) != 0) { 1683 if (vr_error(sc, status) != 0) { 1684 VR_UNLOCK(sc); 1685 return; 1686 } 1687 } 1688 vr_rxeof(sc); 1689 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1690 #ifdef VR_SHOW_ERRORS 1691 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1692 __func__, status, VR_ISR_ERR_BITS); 1693 #endif 1694 /* Restart Rx if RxDMA SM was stopped. */ 1695 vr_rx_start(sc); 1696 } 1697 vr_txeof(sc); 1698 status = CSR_READ_2(sc, VR_ISR); 1699 } 1700 1701 /* Re-enable interrupts. */ 1702 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1703 1704 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1705 vr_start_locked(ifp); 1706 1707 done_locked: 1708 VR_UNLOCK(sc); 1709 } 1710 1711 static int 1712 vr_error(struct vr_softc *sc, uint16_t status) 1713 { 1714 uint16_t pcis; 1715 1716 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1717 if ((status & VR_ISR_BUSERR) != 0) { 1718 status &= ~VR_ISR_BUSERR; 1719 sc->vr_stat.bus_errors++; 1720 /* Disable further interrupts. */ 1721 CSR_WRITE_2(sc, VR_IMR, 0); 1722 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1723 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1724 "resetting\n", pcis); 1725 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1726 sc->vr_flags |= VR_F_RESTART; 1727 return (EAGAIN); 1728 } 1729 if ((status & VR_ISR_LINKSTAT2) != 0) { 1730 /* Link state change, duplex changes etc. */ 1731 status &= ~VR_ISR_LINKSTAT2; 1732 } 1733 if ((status & VR_ISR_STATSOFLOW) != 0) { 1734 status &= ~VR_ISR_STATSOFLOW; 1735 if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1736 /* Update MIB counters. */ 1737 } 1738 } 1739 1740 if (status != 0) 1741 device_printf(sc->vr_dev, 1742 "unhandled interrupt, status = 0x%04x\n", status); 1743 return (0); 1744 } 1745 1746 /* 1747 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1748 * pointers to the fragment pointers. 1749 */ 1750 static int 1751 vr_encap(struct vr_softc *sc, struct mbuf **m_head) 1752 { 1753 struct vr_txdesc *txd; 1754 struct vr_desc *desc; 1755 struct mbuf *m; 1756 bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1757 uint32_t csum_flags, txctl; 1758 int error, i, nsegs, prod, si; 1759 int padlen; 1760 1761 VR_LOCK_ASSERT(sc); 1762 1763 M_ASSERTPKTHDR((*m_head)); 1764 1765 /* 1766 * Some VIA Rhine wants packet buffers to be longword 1767 * aligned, but very often our mbufs aren't. Rather than 1768 * waste time trying to decide when to copy and when not 1769 * to copy, just do it all the time. 1770 */ 1771 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1772 m = m_defrag(*m_head, M_DONTWAIT); 1773 if (m == NULL) { 1774 m_freem(*m_head); 1775 *m_head = NULL; 1776 return (ENOBUFS); 1777 } 1778 *m_head = m; 1779 } 1780 1781 /* 1782 * The Rhine chip doesn't auto-pad, so we have to make 1783 * sure to pad short frames out to the minimum frame length 1784 * ourselves. 1785 */ 1786 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1787 m = *m_head; 1788 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1789 if (M_WRITABLE(m) == 0) { 1790 /* Get a writable copy. */ 1791 m = m_dup(*m_head, M_DONTWAIT); 1792 m_freem(*m_head); 1793 if (m == NULL) { 1794 *m_head = NULL; 1795 return (ENOBUFS); 1796 } 1797 *m_head = m; 1798 } 1799 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1800 m = m_defrag(m, M_DONTWAIT); 1801 if (m == NULL) { 1802 m_freem(*m_head); 1803 *m_head = NULL; 1804 return (ENOBUFS); 1805 } 1806 } 1807 /* 1808 * Manually pad short frames, and zero the pad space 1809 * to avoid leaking data. 1810 */ 1811 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1812 m->m_pkthdr.len += padlen; 1813 m->m_len = m->m_pkthdr.len; 1814 *m_head = m; 1815 } 1816 1817 prod = sc->vr_cdata.vr_tx_prod; 1818 txd = &sc->vr_cdata.vr_txdesc[prod]; 1819 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1820 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1821 if (error == EFBIG) { 1822 m = m_collapse(*m_head, M_DONTWAIT, VR_MAXFRAGS); 1823 if (m == NULL) { 1824 m_freem(*m_head); 1825 *m_head = NULL; 1826 return (ENOBUFS); 1827 } 1828 *m_head = m; 1829 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1830 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1831 if (error != 0) { 1832 m_freem(*m_head); 1833 *m_head = NULL; 1834 return (error); 1835 } 1836 } else if (error != 0) 1837 return (error); 1838 if (nsegs == 0) { 1839 m_freem(*m_head); 1840 *m_head = NULL; 1841 return (EIO); 1842 } 1843 1844 /* Check number of available descriptors. */ 1845 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1846 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1847 return (ENOBUFS); 1848 } 1849 1850 txd->tx_m = *m_head; 1851 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1852 BUS_DMASYNC_PREWRITE); 1853 1854 /* Set checksum offload. */ 1855 csum_flags = 0; 1856 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1857 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1858 csum_flags |= VR_TXCTL_IPCSUM; 1859 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1860 csum_flags |= VR_TXCTL_TCPCSUM; 1861 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1862 csum_flags |= VR_TXCTL_UDPCSUM; 1863 } 1864 1865 /* 1866 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1867 * is required for all descriptors regardless of single or 1868 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1869 * the first descriptor for a multi-fragmented frames. Without 1870 * that VIA Rhine chip generates Tx underrun interrupts and can't 1871 * send any frames. 1872 */ 1873 si = prod; 1874 for (i = 0; i < nsegs; i++) { 1875 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1876 desc->vr_status = 0; 1877 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1878 if (i == 0) 1879 txctl |= VR_TXCTL_FIRSTFRAG; 1880 desc->vr_ctl = htole32(txctl); 1881 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1882 sc->vr_cdata.vr_tx_cnt++; 1883 VR_INC(prod, VR_TX_RING_CNT); 1884 } 1885 /* Update producer index. */ 1886 sc->vr_cdata.vr_tx_prod = prod; 1887 1888 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1889 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1890 1891 /* 1892 * Set EOP on the last desciptor and reuqest Tx completion 1893 * interrupt for every VR_TX_INTR_THRESH-th frames. 1894 */ 1895 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1896 if (sc->vr_cdata.vr_tx_pkts == 0) 1897 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1898 else 1899 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1900 1901 /* Lastly turn the first descriptor ownership to hardware. */ 1902 desc = &sc->vr_rdata.vr_tx_ring[si]; 1903 desc->vr_status |= htole32(VR_TXSTAT_OWN); 1904 1905 /* Sync descriptors. */ 1906 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1907 sc->vr_cdata.vr_tx_ring_map, 1908 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1909 1910 return (0); 1911 } 1912 1913 static void 1914 vr_start(struct ifnet *ifp) 1915 { 1916 struct vr_softc *sc; 1917 1918 sc = ifp->if_softc; 1919 VR_LOCK(sc); 1920 vr_start_locked(ifp); 1921 VR_UNLOCK(sc); 1922 } 1923 1924 static void 1925 vr_start_locked(struct ifnet *ifp) 1926 { 1927 struct vr_softc *sc; 1928 struct mbuf *m_head; 1929 int enq; 1930 1931 sc = ifp->if_softc; 1932 1933 VR_LOCK_ASSERT(sc); 1934 1935 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1936 IFF_DRV_RUNNING || sc->vr_link == 0) 1937 return; 1938 1939 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1940 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1941 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1942 if (m_head == NULL) 1943 break; 1944 /* 1945 * Pack the data into the transmit ring. If we 1946 * don't have room, set the OACTIVE flag and wait 1947 * for the NIC to drain the ring. 1948 */ 1949 if (vr_encap(sc, &m_head)) { 1950 if (m_head == NULL) 1951 break; 1952 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1953 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1954 break; 1955 } 1956 1957 enq++; 1958 /* 1959 * If there's a BPF listener, bounce a copy of this frame 1960 * to him. 1961 */ 1962 ETHER_BPF_MTAP(ifp, m_head); 1963 } 1964 1965 if (enq > 0) { 1966 /* Tell the chip to start transmitting. */ 1967 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 1968 /* Set a timeout in case the chip goes out to lunch. */ 1969 sc->vr_watchdog_timer = 5; 1970 } 1971 } 1972 1973 static void 1974 vr_init(void *xsc) 1975 { 1976 struct vr_softc *sc; 1977 1978 sc = (struct vr_softc *)xsc; 1979 VR_LOCK(sc); 1980 vr_init_locked(sc); 1981 VR_UNLOCK(sc); 1982 } 1983 1984 static void 1985 vr_init_locked(struct vr_softc *sc) 1986 { 1987 struct ifnet *ifp; 1988 struct mii_data *mii; 1989 bus_addr_t addr; 1990 int i; 1991 1992 VR_LOCK_ASSERT(sc); 1993 1994 ifp = sc->vr_ifp; 1995 mii = device_get_softc(sc->vr_miibus); 1996 1997 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1998 return; 1999 2000 /* Cancel pending I/O and free all RX/TX buffers. */ 2001 vr_stop(sc); 2002 vr_reset(sc); 2003 2004 /* Set our station address. */ 2005 for (i = 0; i < ETHER_ADDR_LEN; i++) 2006 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2007 2008 /* Set DMA size. */ 2009 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2010 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 2011 2012 /* 2013 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2014 * so we must set both. 2015 */ 2016 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2017 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2018 2019 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2020 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2021 2022 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2023 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 2024 2025 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2026 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 2027 2028 /* Init circular RX list. */ 2029 if (vr_rx_ring_init(sc) != 0) { 2030 device_printf(sc->vr_dev, 2031 "initialization failed: no memory for rx buffers\n"); 2032 vr_stop(sc); 2033 return; 2034 } 2035 2036 /* Init tx descriptors. */ 2037 vr_tx_ring_init(sc); 2038 2039 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2040 uint8_t vcam[2] = { 0, 0 }; 2041 2042 /* Disable VLAN hardware tag insertion/stripping. */ 2043 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2044 /* Disable VLAN hardware filtering. */ 2045 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2046 /* Disable all CAM entries. */ 2047 vr_cam_mask(sc, VR_MCAST_CAM, 0); 2048 vr_cam_mask(sc, VR_VLAN_CAM, 0); 2049 /* Enable the first VLAN CAM. */ 2050 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2051 vr_cam_mask(sc, VR_VLAN_CAM, 1); 2052 } 2053 2054 /* 2055 * Set up receive filter. 2056 */ 2057 vr_set_filter(sc); 2058 2059 /* 2060 * Load the address of the RX ring. 2061 */ 2062 addr = VR_RX_RING_ADDR(sc, 0); 2063 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2064 /* 2065 * Load the address of the TX ring. 2066 */ 2067 addr = VR_TX_RING_ADDR(sc, 0); 2068 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2069 /* Default : full-duplex, no Tx poll. */ 2070 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 2071 2072 /* Set flow-control parameters for Rhine III. */ 2073 if (sc->vr_revid >= REV_ID_VT6105_A0) { 2074 /* Rx buffer count available for incoming packet. */ 2075 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT); 2076 /* 2077 * Tx pause low threshold : 16 free receive buffers 2078 * Tx pause XON high threshold : 48 free receive buffers 2079 */ 2080 CSR_WRITE_1(sc, VR_FLOWCR1, 2081 VR_FLOWCR1_TXLO16 | VR_FLOWCR1_TXHI48 | VR_FLOWCR1_XONXOFF); 2082 /* Set Tx pause timer. */ 2083 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2084 } 2085 2086 /* Enable receiver and transmitter. */ 2087 CSR_WRITE_1(sc, VR_CR0, 2088 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 2089 2090 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2091 #ifdef DEVICE_POLLING 2092 /* 2093 * Disable interrupts if we are polling. 2094 */ 2095 if (ifp->if_capenable & IFCAP_POLLING) 2096 CSR_WRITE_2(sc, VR_IMR, 0); 2097 else 2098 #endif 2099 /* 2100 * Enable interrupts and disable MII intrs. 2101 */ 2102 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2103 if (sc->vr_revid > REV_ID_VT6102_A) 2104 CSR_WRITE_2(sc, VR_MII_IMR, 0); 2105 2106 sc->vr_link = 0; 2107 mii_mediachg(mii); 2108 2109 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2110 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2111 2112 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 2113 } 2114 2115 /* 2116 * Set media options. 2117 */ 2118 static int 2119 vr_ifmedia_upd(struct ifnet *ifp) 2120 { 2121 struct vr_softc *sc; 2122 struct mii_data *mii; 2123 struct mii_softc *miisc; 2124 int error; 2125 2126 sc = ifp->if_softc; 2127 VR_LOCK(sc); 2128 mii = device_get_softc(sc->vr_miibus); 2129 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2130 PHY_RESET(miisc); 2131 error = mii_mediachg(mii); 2132 VR_UNLOCK(sc); 2133 2134 return (error); 2135 } 2136 2137 /* 2138 * Report current media status. 2139 */ 2140 static void 2141 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2142 { 2143 struct vr_softc *sc; 2144 struct mii_data *mii; 2145 2146 sc = ifp->if_softc; 2147 mii = device_get_softc(sc->vr_miibus); 2148 VR_LOCK(sc); 2149 if ((ifp->if_flags & IFF_UP) == 0) { 2150 VR_UNLOCK(sc); 2151 return; 2152 } 2153 mii_pollstat(mii); 2154 ifmr->ifm_active = mii->mii_media_active; 2155 ifmr->ifm_status = mii->mii_media_status; 2156 VR_UNLOCK(sc); 2157 } 2158 2159 static int 2160 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2161 { 2162 struct vr_softc *sc; 2163 struct ifreq *ifr; 2164 struct mii_data *mii; 2165 int error, mask; 2166 2167 sc = ifp->if_softc; 2168 ifr = (struct ifreq *)data; 2169 error = 0; 2170 2171 switch (command) { 2172 case SIOCSIFFLAGS: 2173 VR_LOCK(sc); 2174 if (ifp->if_flags & IFF_UP) { 2175 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2176 if ((ifp->if_flags ^ sc->vr_if_flags) & 2177 (IFF_PROMISC | IFF_ALLMULTI)) 2178 vr_set_filter(sc); 2179 } else { 2180 if (sc->vr_detach == 0) 2181 vr_init_locked(sc); 2182 } 2183 } else { 2184 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2185 vr_stop(sc); 2186 } 2187 sc->vr_if_flags = ifp->if_flags; 2188 VR_UNLOCK(sc); 2189 break; 2190 case SIOCADDMULTI: 2191 case SIOCDELMULTI: 2192 VR_LOCK(sc); 2193 vr_set_filter(sc); 2194 VR_UNLOCK(sc); 2195 break; 2196 case SIOCGIFMEDIA: 2197 case SIOCSIFMEDIA: 2198 mii = device_get_softc(sc->vr_miibus); 2199 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2200 break; 2201 case SIOCSIFCAP: 2202 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2203 #ifdef DEVICE_POLLING 2204 if (mask & IFCAP_POLLING) { 2205 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2206 error = ether_poll_register(vr_poll, ifp); 2207 if (error != 0) 2208 break; 2209 VR_LOCK(sc); 2210 /* Disable interrupts. */ 2211 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2212 ifp->if_capenable |= IFCAP_POLLING; 2213 VR_UNLOCK(sc); 2214 } else { 2215 error = ether_poll_deregister(ifp); 2216 /* Enable interrupts. */ 2217 VR_LOCK(sc); 2218 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2219 ifp->if_capenable &= ~IFCAP_POLLING; 2220 VR_UNLOCK(sc); 2221 } 2222 } 2223 #endif /* DEVICE_POLLING */ 2224 if ((mask & IFCAP_TXCSUM) != 0 && 2225 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2226 ifp->if_capenable ^= IFCAP_TXCSUM; 2227 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2228 ifp->if_hwassist |= VR_CSUM_FEATURES; 2229 else 2230 ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2231 } 2232 if ((mask & IFCAP_RXCSUM) != 0 && 2233 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2234 ifp->if_capenable ^= IFCAP_RXCSUM; 2235 if ((mask & IFCAP_WOL_UCAST) != 0 && 2236 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2237 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2238 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2239 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2240 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2241 break; 2242 default: 2243 error = ether_ioctl(ifp, command, data); 2244 break; 2245 } 2246 2247 return (error); 2248 } 2249 2250 static void 2251 vr_watchdog(struct vr_softc *sc) 2252 { 2253 struct ifnet *ifp; 2254 2255 VR_LOCK_ASSERT(sc); 2256 2257 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2258 return; 2259 2260 ifp = sc->vr_ifp; 2261 /* 2262 * Reclaim first as we don't request interrupt for every packets. 2263 */ 2264 vr_txeof(sc); 2265 if (sc->vr_cdata.vr_tx_cnt == 0) 2266 return; 2267 2268 if (sc->vr_link == 0) { 2269 if (bootverbose) 2270 if_printf(sc->vr_ifp, "watchdog timeout " 2271 "(missed link)\n"); 2272 ifp->if_oerrors++; 2273 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2274 vr_init_locked(sc); 2275 return; 2276 } 2277 2278 ifp->if_oerrors++; 2279 if_printf(ifp, "watchdog timeout\n"); 2280 2281 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2282 vr_init_locked(sc); 2283 2284 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2285 vr_start_locked(ifp); 2286 } 2287 2288 static void 2289 vr_tx_start(struct vr_softc *sc) 2290 { 2291 bus_addr_t addr; 2292 uint8_t cmd; 2293 2294 cmd = CSR_READ_1(sc, VR_CR0); 2295 if ((cmd & VR_CR0_TX_ON) == 0) { 2296 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2297 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2298 cmd |= VR_CR0_TX_ON; 2299 CSR_WRITE_1(sc, VR_CR0, cmd); 2300 } 2301 if (sc->vr_cdata.vr_tx_cnt != 0) { 2302 sc->vr_watchdog_timer = 5; 2303 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2304 } 2305 } 2306 2307 static void 2308 vr_rx_start(struct vr_softc *sc) 2309 { 2310 bus_addr_t addr; 2311 uint8_t cmd; 2312 2313 cmd = CSR_READ_1(sc, VR_CR0); 2314 if ((cmd & VR_CR0_RX_ON) == 0) { 2315 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2316 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2317 cmd |= VR_CR0_RX_ON; 2318 CSR_WRITE_1(sc, VR_CR0, cmd); 2319 } 2320 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2321 } 2322 2323 static int 2324 vr_tx_stop(struct vr_softc *sc) 2325 { 2326 int i; 2327 uint8_t cmd; 2328 2329 cmd = CSR_READ_1(sc, VR_CR0); 2330 if ((cmd & VR_CR0_TX_ON) != 0) { 2331 cmd &= ~VR_CR0_TX_ON; 2332 CSR_WRITE_1(sc, VR_CR0, cmd); 2333 for (i = VR_TIMEOUT; i > 0; i--) { 2334 DELAY(5); 2335 cmd = CSR_READ_1(sc, VR_CR0); 2336 if ((cmd & VR_CR0_TX_ON) == 0) 2337 break; 2338 } 2339 if (i == 0) 2340 return (ETIMEDOUT); 2341 } 2342 return (0); 2343 } 2344 2345 static int 2346 vr_rx_stop(struct vr_softc *sc) 2347 { 2348 int i; 2349 uint8_t cmd; 2350 2351 cmd = CSR_READ_1(sc, VR_CR0); 2352 if ((cmd & VR_CR0_RX_ON) != 0) { 2353 cmd &= ~VR_CR0_RX_ON; 2354 CSR_WRITE_1(sc, VR_CR0, cmd); 2355 for (i = VR_TIMEOUT; i > 0; i--) { 2356 DELAY(5); 2357 cmd = CSR_READ_1(sc, VR_CR0); 2358 if ((cmd & VR_CR0_RX_ON) == 0) 2359 break; 2360 } 2361 if (i == 0) 2362 return (ETIMEDOUT); 2363 } 2364 return (0); 2365 } 2366 2367 /* 2368 * Stop the adapter and free any mbufs allocated to the 2369 * RX and TX lists. 2370 */ 2371 static void 2372 vr_stop(struct vr_softc *sc) 2373 { 2374 struct vr_txdesc *txd; 2375 struct vr_rxdesc *rxd; 2376 struct ifnet *ifp; 2377 int i; 2378 2379 VR_LOCK_ASSERT(sc); 2380 2381 ifp = sc->vr_ifp; 2382 sc->vr_watchdog_timer = 0; 2383 2384 callout_stop(&sc->vr_stat_callout); 2385 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2386 2387 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2388 if (vr_rx_stop(sc) != 0) 2389 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2390 if (vr_tx_stop(sc) != 0) 2391 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2392 /* Clear pending interrupts. */ 2393 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2394 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2395 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 2396 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 2397 2398 /* 2399 * Free RX and TX mbufs still in the queues. 2400 */ 2401 for (i = 0; i < VR_RX_RING_CNT; i++) { 2402 rxd = &sc->vr_cdata.vr_rxdesc[i]; 2403 if (rxd->rx_m != NULL) { 2404 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2405 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2406 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2407 rxd->rx_dmamap); 2408 m_freem(rxd->rx_m); 2409 rxd->rx_m = NULL; 2410 } 2411 } 2412 for (i = 0; i < VR_TX_RING_CNT; i++) { 2413 txd = &sc->vr_cdata.vr_txdesc[i]; 2414 if (txd->tx_m != NULL) { 2415 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2416 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2417 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2418 txd->tx_dmamap); 2419 m_freem(txd->tx_m); 2420 txd->tx_m = NULL; 2421 } 2422 } 2423 } 2424 2425 /* 2426 * Stop all chip I/O so that the kernel's probe routines don't 2427 * get confused by errant DMAs when rebooting. 2428 */ 2429 static int 2430 vr_shutdown(device_t dev) 2431 { 2432 2433 return (vr_suspend(dev)); 2434 } 2435 2436 static int 2437 vr_suspend(device_t dev) 2438 { 2439 struct vr_softc *sc; 2440 2441 sc = device_get_softc(dev); 2442 2443 VR_LOCK(sc); 2444 vr_stop(sc); 2445 vr_setwol(sc); 2446 sc->vr_suspended = 1; 2447 VR_UNLOCK(sc); 2448 2449 return (0); 2450 } 2451 2452 static int 2453 vr_resume(device_t dev) 2454 { 2455 struct vr_softc *sc; 2456 struct ifnet *ifp; 2457 2458 sc = device_get_softc(dev); 2459 2460 VR_LOCK(sc); 2461 ifp = sc->vr_ifp; 2462 vr_clrwol(sc); 2463 vr_reset(sc); 2464 if (ifp->if_flags & IFF_UP) 2465 vr_init_locked(sc); 2466 2467 sc->vr_suspended = 0; 2468 VR_UNLOCK(sc); 2469 2470 return (0); 2471 } 2472 2473 static void 2474 vr_setwol(struct vr_softc *sc) 2475 { 2476 struct ifnet *ifp; 2477 int pmc; 2478 uint16_t pmstat; 2479 uint8_t v; 2480 2481 VR_LOCK_ASSERT(sc); 2482 2483 if (sc->vr_revid < REV_ID_VT6102_A || 2484 pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2485 return; 2486 2487 ifp = sc->vr_ifp; 2488 2489 /* Clear WOL configuration. */ 2490 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2491 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2492 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2493 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2494 if (sc->vr_revid > REV_ID_VT6105_B0) { 2495 /* Newer Rhine III supports two additional patterns. */ 2496 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2497 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2498 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2499 } 2500 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2501 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2502 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2503 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2504 /* 2505 * It seems that multicast wakeup frames require programming pattern 2506 * registers and valid CRC as well as pattern mask for each pattern. 2507 * While it's possible to setup such a pattern it would complicate 2508 * WOL configuration so ignore multicast wakeup frames. 2509 */ 2510 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2511 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2512 v = CSR_READ_1(sc, VR_STICKHW); 2513 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2514 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2515 } 2516 2517 /* Put hardware into sleep. */ 2518 v = CSR_READ_1(sc, VR_STICKHW); 2519 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2520 CSR_WRITE_1(sc, VR_STICKHW, v); 2521 2522 /* Request PME if WOL is requested. */ 2523 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2524 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2525 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2526 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2527 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2528 } 2529 2530 static void 2531 vr_clrwol(struct vr_softc *sc) 2532 { 2533 uint8_t v; 2534 2535 VR_LOCK_ASSERT(sc); 2536 2537 if (sc->vr_revid < REV_ID_VT6102_A) 2538 return; 2539 2540 /* Take hardware out of sleep. */ 2541 v = CSR_READ_1(sc, VR_STICKHW); 2542 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2543 CSR_WRITE_1(sc, VR_STICKHW, v); 2544 2545 /* Clear WOL configuration as WOL may interfere normal operation. */ 2546 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2547 CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2548 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2549 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2550 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2551 if (sc->vr_revid > REV_ID_VT6105_B0) { 2552 /* Newer Rhine III supports two additional patterns. */ 2553 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2554 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2555 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2556 } 2557 } 2558 2559 static int 2560 vr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2561 { 2562 struct vr_softc *sc; 2563 struct vr_statistics *stat; 2564 int error; 2565 int result; 2566 2567 result = -1; 2568 error = sysctl_handle_int(oidp, &result, 0, req); 2569 2570 if (error != 0 || req->newptr == NULL) 2571 return (error); 2572 2573 if (result == 1) { 2574 sc = (struct vr_softc *)arg1; 2575 stat = &sc->vr_stat; 2576 2577 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2578 printf("Outbound good frames : %ju\n", 2579 (uintmax_t)stat->tx_ok); 2580 printf("Inbound good frames : %ju\n", 2581 (uintmax_t)stat->rx_ok); 2582 printf("Outbound errors : %u\n", stat->tx_errors); 2583 printf("Inbound errors : %u\n", stat->rx_errors); 2584 printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2585 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2586 printf("Inbound FIFO overflows : %d\n", 2587 stat->rx_fifo_overflows); 2588 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2589 printf("Inbound frame alignment errors : %u\n", 2590 stat->rx_alignment); 2591 printf("Inbound giant frames : %u\n", stat->rx_giants); 2592 printf("Inbound runt frames : %u\n", stat->rx_runts); 2593 printf("Outbound aborted with excessive collisions : %u\n", 2594 stat->tx_abort); 2595 printf("Outbound collisions : %u\n", stat->tx_collisions); 2596 printf("Outbound late collisions : %u\n", 2597 stat->tx_late_collisions); 2598 printf("Outbound underrun : %u\n", stat->tx_underrun); 2599 printf("PCI bus errors : %u\n", stat->bus_errors); 2600 printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2601 stat->num_restart); 2602 } 2603 2604 return (error); 2605 } 2606