1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/module.h> 70 #include <sys/socket.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/bpf.h> 79 80 #include <vm/vm.h> /* for vtophys */ 81 #include <vm/pmap.h> /* for vtophys */ 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #define VR_USEIOSPACE 96 97 #include <pci/if_vrreg.h> 98 99 MODULE_DEPEND(vr, pci, 1, 1, 1); 100 MODULE_DEPEND(vr, ether, 1, 1, 1); 101 MODULE_DEPEND(vr, miibus, 1, 1, 1); 102 103 /* "controller miibus0" required. See GENERIC if you get errors here. */ 104 #include "miibus_if.h" 105 106 #undef VR_USESWSHIFT 107 108 /* 109 * Various supported device vendors/types and their names. 110 */ 111 static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117 "VIA VT6102 Rhine II 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 119 "VIA VT6105 Rhine III 10/100BaseTX" }, 120 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 121 "VIA VT6105M Rhine III 10/100BaseTX" }, 122 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 123 "Delta Electronics Rhine II 10/100BaseTX" }, 124 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 125 "Addtron Technology Rhine II 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int vr_probe (device_t); 130 static int vr_attach (device_t); 131 static int vr_detach (device_t); 132 133 static int vr_newbuf (struct vr_softc *, 134 struct vr_chain_onefrag *, 135 struct mbuf *); 136 static int vr_encap (struct vr_softc *, struct vr_chain *, 137 struct mbuf * ); 138 139 static void vr_rxeof (struct vr_softc *); 140 static void vr_rxeoc (struct vr_softc *); 141 static void vr_txeof (struct vr_softc *); 142 static void vr_tick (void *); 143 static void vr_intr (void *); 144 static void vr_start (struct ifnet *); 145 static void vr_start_locked (struct ifnet *); 146 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 147 static void vr_init (void *); 148 static void vr_init_locked (struct vr_softc *); 149 static void vr_stop (struct vr_softc *); 150 static void vr_watchdog (struct ifnet *); 151 static void vr_shutdown (device_t); 152 static int vr_ifmedia_upd (struct ifnet *); 153 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 154 155 #ifdef VR_USESWSHIFT 156 static void vr_mii_sync (struct vr_softc *); 157 static void vr_mii_send (struct vr_softc *, uint32_t, int); 158 #endif 159 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 160 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 161 static int vr_miibus_readreg (device_t, uint16_t, uint16_t); 162 static int vr_miibus_writereg (device_t, uint16_t, uint16_t, uint16_t); 163 static void vr_miibus_statchg (device_t); 164 165 static void vr_setcfg (struct vr_softc *, int); 166 static void vr_setmulti (struct vr_softc *); 167 static void vr_reset (struct vr_softc *); 168 static int vr_list_rx_init (struct vr_softc *); 169 static int vr_list_tx_init (struct vr_softc *); 170 171 #ifdef VR_USEIOSPACE 172 #define VR_RES SYS_RES_IOPORT 173 #define VR_RID VR_PCI_LOIO 174 #else 175 #define VR_RES SYS_RES_MEMORY 176 #define VR_RID VR_PCI_LOMEM 177 #endif 178 179 static device_method_t vr_methods[] = { 180 /* Device interface */ 181 DEVMETHOD(device_probe, vr_probe), 182 DEVMETHOD(device_attach, vr_attach), 183 DEVMETHOD(device_detach, vr_detach), 184 DEVMETHOD(device_shutdown, vr_shutdown), 185 186 /* bus interface */ 187 DEVMETHOD(bus_print_child, bus_generic_print_child), 188 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 189 190 /* MII interface */ 191 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 192 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 193 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 194 195 { 0, 0 } 196 }; 197 198 static driver_t vr_driver = { 199 "vr", 200 vr_methods, 201 sizeof(struct vr_softc) 202 }; 203 204 static devclass_t vr_devclass; 205 206 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 207 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 208 209 #define VR_SETBIT(sc, reg, x) \ 210 CSR_WRITE_1(sc, reg, \ 211 CSR_READ_1(sc, reg) | (x)) 212 213 #define VR_CLRBIT(sc, reg, x) \ 214 CSR_WRITE_1(sc, reg, \ 215 CSR_READ_1(sc, reg) & ~(x)) 216 217 #define VR_SETBIT16(sc, reg, x) \ 218 CSR_WRITE_2(sc, reg, \ 219 CSR_READ_2(sc, reg) | (x)) 220 221 #define VR_CLRBIT16(sc, reg, x) \ 222 CSR_WRITE_2(sc, reg, \ 223 CSR_READ_2(sc, reg) & ~(x)) 224 225 #define VR_SETBIT32(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229 #define VR_CLRBIT32(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233 #define SIO_SET(x) \ 234 CSR_WRITE_1(sc, VR_MIICMD, \ 235 CSR_READ_1(sc, VR_MIICMD) | (x)) 236 237 #define SIO_CLR(x) \ 238 CSR_WRITE_1(sc, VR_MIICMD, \ 239 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 240 241 #ifdef VR_USESWSHIFT 242 /* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245 static void 246 vr_mii_sync(struct vr_softc *sc) 247 { 248 register int i; 249 250 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 251 252 for (i = 0; i < 32; i++) { 253 SIO_SET(VR_MIICMD_CLK); 254 DELAY(1); 255 SIO_CLR(VR_MIICMD_CLK); 256 DELAY(1); 257 } 258 } 259 260 /* 261 * Clock a series of bits through the MII. 262 */ 263 static void 264 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 265 { 266 int i; 267 268 SIO_CLR(VR_MIICMD_CLK); 269 270 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 271 if (bits & i) { 272 SIO_SET(VR_MIICMD_DATAIN); 273 } else { 274 SIO_CLR(VR_MIICMD_DATAIN); 275 } 276 DELAY(1); 277 SIO_CLR(VR_MIICMD_CLK); 278 DELAY(1); 279 SIO_SET(VR_MIICMD_CLK); 280 } 281 } 282 #endif 283 284 /* 285 * Read an PHY register through the MII. 286 */ 287 static int 288 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 289 #ifdef VR_USESWSHIFT 290 { 291 int i, ack; 292 293 /* Set up frame for RX. */ 294 frame->mii_stdelim = VR_MII_STARTDELIM; 295 frame->mii_opcode = VR_MII_READOP; 296 frame->mii_turnaround = 0; 297 frame->mii_data = 0; 298 299 CSR_WRITE_1(sc, VR_MIICMD, 0); 300 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 301 302 /* Turn on data xmit. */ 303 SIO_SET(VR_MIICMD_DIR); 304 305 vr_mii_sync(sc); 306 307 /* Send command/address info. */ 308 vr_mii_send(sc, frame->mii_stdelim, 2); 309 vr_mii_send(sc, frame->mii_opcode, 2); 310 vr_mii_send(sc, frame->mii_phyaddr, 5); 311 vr_mii_send(sc, frame->mii_regaddr, 5); 312 313 /* Idle bit. */ 314 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 315 DELAY(1); 316 SIO_SET(VR_MIICMD_CLK); 317 DELAY(1); 318 319 /* Turn off xmit. */ 320 SIO_CLR(VR_MIICMD_DIR); 321 322 /* Check for ack */ 323 SIO_CLR(VR_MIICMD_CLK); 324 DELAY(1); 325 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 326 SIO_SET(VR_MIICMD_CLK); 327 DELAY(1); 328 329 /* 330 * Now try reading data bits. If the ack failed, we still 331 * need to clock through 16 cycles to keep the PHY(s) in sync. 332 */ 333 if (ack) { 334 for(i = 0; i < 16; i++) { 335 SIO_CLR(VR_MIICMD_CLK); 336 DELAY(1); 337 SIO_SET(VR_MIICMD_CLK); 338 DELAY(1); 339 } 340 goto fail; 341 } 342 343 for (i = 0x8000; i; i >>= 1) { 344 SIO_CLR(VR_MIICMD_CLK); 345 DELAY(1); 346 if (!ack) { 347 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 348 frame->mii_data |= i; 349 DELAY(1); 350 } 351 SIO_SET(VR_MIICMD_CLK); 352 DELAY(1); 353 } 354 355 fail: 356 SIO_CLR(VR_MIICMD_CLK); 357 DELAY(1); 358 SIO_SET(VR_MIICMD_CLK); 359 DELAY(1); 360 361 if (ack) 362 return (1); 363 return (0); 364 } 365 #else 366 { 367 int i; 368 369 /* Set the PHY address. */ 370 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 371 frame->mii_phyaddr); 372 373 /* Set the register address. */ 374 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 375 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 376 377 for (i = 0; i < 10000; i++) { 378 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 379 break; 380 DELAY(1); 381 } 382 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 383 384 return (0); 385 } 386 #endif 387 388 389 /* 390 * Write to a PHY register through the MII. 391 */ 392 static int 393 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 394 #ifdef VR_USESWSHIFT 395 { 396 CSR_WRITE_1(sc, VR_MIICMD, 0); 397 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 398 399 /* Set up frame for TX. */ 400 frame->mii_stdelim = VR_MII_STARTDELIM; 401 frame->mii_opcode = VR_MII_WRITEOP; 402 frame->mii_turnaround = VR_MII_TURNAROUND; 403 404 /* Turn on data output. */ 405 SIO_SET(VR_MIICMD_DIR); 406 407 vr_mii_sync(sc); 408 409 vr_mii_send(sc, frame->mii_stdelim, 2); 410 vr_mii_send(sc, frame->mii_opcode, 2); 411 vr_mii_send(sc, frame->mii_phyaddr, 5); 412 vr_mii_send(sc, frame->mii_regaddr, 5); 413 vr_mii_send(sc, frame->mii_turnaround, 2); 414 vr_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 SIO_SET(VR_MIICMD_CLK); 418 DELAY(1); 419 SIO_CLR(VR_MIICMD_CLK); 420 DELAY(1); 421 422 /* Turn off xmit. */ 423 SIO_CLR(VR_MIICMD_DIR); 424 425 return (0); 426 } 427 #else 428 { 429 int i; 430 431 /* Set the PHY address. */ 432 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 433 frame->mii_phyaddr); 434 435 /* Set the register address and data to write. */ 436 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 437 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 438 439 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 440 441 for (i = 0; i < 10000; i++) { 442 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 443 break; 444 DELAY(1); 445 } 446 447 return (0); 448 } 449 #endif 450 451 static int 452 vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 453 { 454 struct vr_mii_frame frame; 455 struct vr_softc *sc = device_get_softc(dev); 456 457 switch (sc->vr_revid) { 458 case REV_ID_VT6102_APOLLO: 459 if (phy != 1) { 460 frame.mii_data = 0; 461 goto out; 462 } 463 default: 464 break; 465 } 466 467 bzero((char *)&frame, sizeof(frame)); 468 frame.mii_phyaddr = phy; 469 frame.mii_regaddr = reg; 470 vr_mii_readreg(sc, &frame); 471 472 out: 473 return (frame.mii_data); 474 } 475 476 static int 477 vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 478 { 479 struct vr_mii_frame frame; 480 struct vr_softc *sc = device_get_softc(dev); 481 482 switch (sc->vr_revid) { 483 case REV_ID_VT6102_APOLLO: 484 if (phy != 1) 485 return (0); 486 default: 487 break; 488 } 489 490 bzero((char *)&frame, sizeof(frame)); 491 frame.mii_phyaddr = phy; 492 frame.mii_regaddr = reg; 493 frame.mii_data = data; 494 vr_mii_writereg(sc, &frame); 495 496 return (0); 497 } 498 499 static void 500 vr_miibus_statchg(device_t dev) 501 { 502 struct mii_data *mii; 503 struct vr_softc *sc = device_get_softc(dev); 504 505 mii = device_get_softc(sc->vr_miibus); 506 vr_setcfg(sc, mii->mii_media_active); 507 } 508 509 /* 510 * Program the 64-bit multicast hash filter. 511 */ 512 static void 513 vr_setmulti(struct vr_softc *sc) 514 { 515 struct ifnet *ifp = &sc->arpcom.ac_if; 516 int h = 0; 517 uint32_t hashes[2] = { 0, 0 }; 518 struct ifmultiaddr *ifma; 519 uint8_t rxfilt; 520 int mcnt = 0; 521 522 VR_LOCK_ASSERT(sc); 523 524 rxfilt = CSR_READ_1(sc, VR_RXCFG); 525 526 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 527 rxfilt |= VR_RXCFG_RX_MULTI; 528 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 529 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 530 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 531 return; 532 } 533 534 /* First, zero out all the existing hash bits. */ 535 CSR_WRITE_4(sc, VR_MAR0, 0); 536 CSR_WRITE_4(sc, VR_MAR1, 0); 537 538 /* Now program new ones. */ 539 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 540 if (ifma->ifma_addr->sa_family != AF_LINK) 541 continue; 542 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 543 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 544 if (h < 32) 545 hashes[0] |= (1 << h); 546 else 547 hashes[1] |= (1 << (h - 32)); 548 mcnt++; 549 } 550 551 if (mcnt) 552 rxfilt |= VR_RXCFG_RX_MULTI; 553 else 554 rxfilt &= ~VR_RXCFG_RX_MULTI; 555 556 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 557 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 558 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 559 } 560 561 /* 562 * In order to fiddle with the 563 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 564 * first have to put the transmit and/or receive logic in the idle state. 565 */ 566 static void 567 vr_setcfg(struct vr_softc *sc, int media) 568 { 569 int restart = 0; 570 571 VR_LOCK_ASSERT(sc); 572 573 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 574 restart = 1; 575 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 576 } 577 578 if ((media & IFM_GMASK) == IFM_FDX) 579 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 580 else 581 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 582 583 if (restart) 584 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 585 } 586 587 static void 588 vr_reset(struct vr_softc *sc) 589 { 590 register int i; 591 592 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during detach w/o lock. */ 593 594 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 595 596 for (i = 0; i < VR_TIMEOUT; i++) { 597 DELAY(10); 598 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 599 break; 600 } 601 if (i == VR_TIMEOUT) { 602 if (sc->vr_revid < REV_ID_VT3065_A) 603 printf("vr%d: reset never completed!\n", sc->vr_unit); 604 else { 605 /* Use newer force reset command */ 606 printf("vr%d: Using force reset command.\n", 607 sc->vr_unit); 608 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 609 } 610 } 611 612 /* Wait a little while for the chip to get its brains in order. */ 613 DELAY(1000); 614 } 615 616 /* 617 * Probe for a VIA Rhine chip. Check the PCI vendor and device 618 * IDs against our list and return a device name if we find a match. 619 */ 620 static int 621 vr_probe(device_t dev) 622 { 623 struct vr_type *t = vr_devs; 624 625 while (t->vr_name != NULL) { 626 if ((pci_get_vendor(dev) == t->vr_vid) && 627 (pci_get_device(dev) == t->vr_did)) { 628 device_set_desc(dev, t->vr_name); 629 return (0); 630 } 631 t++; 632 } 633 634 return (ENXIO); 635 } 636 637 /* 638 * Attach the interface. Allocate softc structures, do ifmedia 639 * setup and ethernet/BPF attach. 640 */ 641 static int 642 vr_attach(dev) 643 device_t dev; 644 { 645 int i; 646 u_char eaddr[ETHER_ADDR_LEN]; 647 struct vr_softc *sc; 648 struct ifnet *ifp; 649 int unit, error = 0, rid; 650 651 sc = device_get_softc(dev); 652 unit = device_get_unit(dev); 653 654 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 655 MTX_DEF); 656 /* 657 * Map control/status registers. 658 */ 659 pci_enable_busmaster(dev); 660 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 661 662 rid = VR_RID; 663 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 664 665 if (sc->vr_res == NULL) { 666 printf("vr%d: couldn't map ports/memory\n", unit); 667 error = ENXIO; 668 goto fail; 669 } 670 671 sc->vr_btag = rman_get_bustag(sc->vr_res); 672 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 673 674 /* Allocate interrupt */ 675 rid = 0; 676 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 677 RF_SHAREABLE | RF_ACTIVE); 678 679 if (sc->vr_irq == NULL) { 680 printf("vr%d: couldn't map interrupt\n", unit); 681 error = ENXIO; 682 goto fail; 683 } 684 685 /* 686 * Windows may put the chip in suspend mode when it 687 * shuts down. Be sure to kick it in the head to wake it 688 * up again. 689 */ 690 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 691 692 /* Reset the adapter. */ 693 vr_reset(sc); 694 695 /* 696 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 697 * initialization and disable AUTOPOLL. 698 */ 699 pci_write_config(dev, VR_PCI_MODE, 700 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 701 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 702 703 /* 704 * Get station address. The way the Rhine chips work, 705 * you're not allowed to directly access the EEPROM once 706 * they've been programmed a special way. Consequently, 707 * we need to read the node address from the PAR0 and PAR1 708 * registers. 709 */ 710 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 711 DELAY(200); 712 for (i = 0; i < ETHER_ADDR_LEN; i++) 713 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 714 715 sc->vr_unit = unit; 716 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 717 718 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 719 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 720 721 if (sc->vr_ldata == NULL) { 722 printf("vr%d: no memory for list buffers!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 727 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 728 729 ifp = &sc->arpcom.ac_if; 730 ifp->if_softc = sc; 731 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 732 ifp->if_mtu = ETHERMTU; 733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 734 ifp->if_ioctl = vr_ioctl; 735 ifp->if_start = vr_start; 736 ifp->if_watchdog = vr_watchdog; 737 ifp->if_init = vr_init; 738 ifp->if_baudrate = 10000000; 739 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 740 #ifdef DEVICE_POLLING 741 ifp->if_capabilities |= IFCAP_POLLING; 742 #endif 743 ifp->if_capenable = ifp->if_capabilities; 744 745 /* Do MII setup. */ 746 if (mii_phy_probe(dev, &sc->vr_miibus, 747 vr_ifmedia_upd, vr_ifmedia_sts)) { 748 printf("vr%d: MII without any phy!\n", sc->vr_unit); 749 error = ENXIO; 750 goto fail; 751 } 752 753 callout_handle_init(&sc->vr_stat_ch); 754 755 /* Call MI attach routine. */ 756 ether_ifattach(ifp, eaddr); 757 758 sc->suspended = 0; 759 760 /* Hook interrupt last to avoid having to lock softc */ 761 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 762 vr_intr, sc, &sc->vr_intrhand); 763 764 if (error) { 765 printf("vr%d: couldn't set up irq\n", unit); 766 ether_ifdetach(ifp); 767 goto fail; 768 } 769 770 fail: 771 if (error) 772 vr_detach(dev); 773 774 return (error); 775 } 776 777 /* 778 * Shutdown hardware and free up resources. This can be called any 779 * time after the mutex has been initialized. It is called in both 780 * the error case in attach and the normal detach case so it needs 781 * to be careful about only freeing resources that have actually been 782 * allocated. 783 */ 784 static int 785 vr_detach(device_t dev) 786 { 787 struct vr_softc *sc = device_get_softc(dev); 788 struct ifnet *ifp = &sc->arpcom.ac_if; 789 790 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 791 792 VR_LOCK(sc); 793 794 sc->suspended = 1; 795 796 /* These should only be active if attach succeeded */ 797 if (device_is_attached(dev)) { 798 vr_stop(sc); 799 ether_ifdetach(ifp); 800 } 801 if (sc->vr_miibus) 802 device_delete_child(dev, sc->vr_miibus); 803 bus_generic_detach(dev); 804 805 if (sc->vr_intrhand) 806 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 807 if (sc->vr_irq) 808 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 809 if (sc->vr_res) 810 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 811 812 if (sc->vr_ldata) 813 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 814 815 VR_UNLOCK(sc); 816 mtx_destroy(&sc->vr_mtx); 817 818 return (0); 819 } 820 821 /* 822 * Initialize the transmit descriptors. 823 */ 824 static int 825 vr_list_tx_init(struct vr_softc *sc) 826 { 827 struct vr_chain_data *cd; 828 struct vr_list_data *ld; 829 int i; 830 831 cd = &sc->vr_cdata; 832 ld = sc->vr_ldata; 833 for (i = 0; i < VR_TX_LIST_CNT; i++) { 834 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 835 if (i == (VR_TX_LIST_CNT - 1)) 836 cd->vr_tx_chain[i].vr_nextdesc = 837 &cd->vr_tx_chain[0]; 838 else 839 cd->vr_tx_chain[i].vr_nextdesc = 840 &cd->vr_tx_chain[i + 1]; 841 } 842 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 843 844 return (0); 845 } 846 847 848 /* 849 * Initialize the RX descriptors and allocate mbufs for them. Note that 850 * we arrange the descriptors in a closed ring, so that the last descriptor 851 * points back to the first. 852 */ 853 static int 854 vr_list_rx_init(struct vr_softc *sc) 855 { 856 struct vr_chain_data *cd; 857 struct vr_list_data *ld; 858 int i; 859 860 VR_LOCK_ASSERT(sc); 861 862 cd = &sc->vr_cdata; 863 ld = sc->vr_ldata; 864 865 for (i = 0; i < VR_RX_LIST_CNT; i++) { 866 cd->vr_rx_chain[i].vr_ptr = 867 (struct vr_desc *)&ld->vr_rx_list[i]; 868 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 869 return (ENOBUFS); 870 if (i == (VR_RX_LIST_CNT - 1)) { 871 cd->vr_rx_chain[i].vr_nextdesc = 872 &cd->vr_rx_chain[0]; 873 ld->vr_rx_list[i].vr_next = 874 vtophys(&ld->vr_rx_list[0]); 875 } else { 876 cd->vr_rx_chain[i].vr_nextdesc = 877 &cd->vr_rx_chain[i + 1]; 878 ld->vr_rx_list[i].vr_next = 879 vtophys(&ld->vr_rx_list[i + 1]); 880 } 881 } 882 883 cd->vr_rx_head = &cd->vr_rx_chain[0]; 884 885 return (0); 886 } 887 888 /* 889 * Initialize an RX descriptor and attach an MBUF cluster. 890 * Note: the length fields are only 11 bits wide, which means the 891 * largest size we can specify is 2047. This is important because 892 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 893 * overflow the field and make a mess. 894 */ 895 static int 896 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 897 { 898 struct mbuf *m_new = NULL; 899 900 if (m == NULL) { 901 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 902 if (m_new == NULL) 903 return (ENOBUFS); 904 905 MCLGET(m_new, M_DONTWAIT); 906 if (!(m_new->m_flags & M_EXT)) { 907 m_freem(m_new); 908 return (ENOBUFS); 909 } 910 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 911 } else { 912 m_new = m; 913 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 914 m_new->m_data = m_new->m_ext.ext_buf; 915 } 916 917 m_adj(m_new, sizeof(uint64_t)); 918 919 c->vr_mbuf = m_new; 920 c->vr_ptr->vr_status = VR_RXSTAT; 921 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 922 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 923 924 return (0); 925 } 926 927 /* 928 * A frame has been uploaded: pass the resulting mbuf chain up to 929 * the higher level protocols. 930 */ 931 static void 932 vr_rxeof(struct vr_softc *sc) 933 { 934 struct mbuf *m, *m0; 935 struct ifnet *ifp; 936 struct vr_chain_onefrag *cur_rx; 937 int total_len = 0; 938 uint32_t rxstat; 939 940 VR_LOCK_ASSERT(sc); 941 ifp = &sc->arpcom.ac_if; 942 943 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 944 VR_RXSTAT_OWN)) { 945 #ifdef DEVICE_POLLING 946 if (ifp->if_flags & IFF_POLLING) { 947 if (sc->rxcycles <= 0) 948 break; 949 sc->rxcycles--; 950 } 951 #endif /* DEVICE_POLLING */ 952 m0 = NULL; 953 cur_rx = sc->vr_cdata.vr_rx_head; 954 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 955 m = cur_rx->vr_mbuf; 956 957 /* 958 * If an error occurs, update stats, clear the 959 * status word and leave the mbuf cluster in place: 960 * it should simply get re-used next time this descriptor 961 * comes up in the ring. 962 */ 963 if (rxstat & VR_RXSTAT_RXERR) { 964 ifp->if_ierrors++; 965 printf("vr%d: rx error (%02x):", sc->vr_unit, 966 rxstat & 0x000000ff); 967 if (rxstat & VR_RXSTAT_CRCERR) 968 printf(" crc error"); 969 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 970 printf(" frame alignment error\n"); 971 if (rxstat & VR_RXSTAT_FIFOOFLOW) 972 printf(" FIFO overflow"); 973 if (rxstat & VR_RXSTAT_GIANT) 974 printf(" received giant packet"); 975 if (rxstat & VR_RXSTAT_RUNT) 976 printf(" received runt packet"); 977 if (rxstat & VR_RXSTAT_BUSERR) 978 printf(" system bus error"); 979 if (rxstat & VR_RXSTAT_BUFFERR) 980 printf("rx buffer error"); 981 printf("\n"); 982 vr_newbuf(sc, cur_rx, m); 983 continue; 984 } 985 986 /* No errors; receive the packet. */ 987 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 988 989 /* 990 * XXX The VIA Rhine chip includes the CRC with every 991 * received frame, and there's no way to turn this 992 * behavior off (at least, I can't find anything in 993 * the manual that explains how to do it) so we have 994 * to trim off the CRC manually. 995 */ 996 total_len -= ETHER_CRC_LEN; 997 998 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 999 NULL); 1000 vr_newbuf(sc, cur_rx, m); 1001 if (m0 == NULL) { 1002 ifp->if_ierrors++; 1003 continue; 1004 } 1005 m = m0; 1006 1007 ifp->if_ipackets++; 1008 VR_UNLOCK(sc); 1009 (*ifp->if_input)(ifp, m); 1010 VR_LOCK(sc); 1011 } 1012 } 1013 1014 static void 1015 vr_rxeoc(struct vr_softc *sc) 1016 { 1017 struct ifnet *ifp = &sc->arpcom.ac_if; 1018 int i; 1019 1020 VR_LOCK_ASSERT(sc); 1021 1022 ifp->if_ierrors++; 1023 1024 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1025 DELAY(10000); 1026 1027 /* Wait for receiver to stop */ 1028 for (i = 0x400; 1029 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1030 i--) { 1031 ; 1032 } 1033 1034 if (!i) { 1035 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1036 sc->vr_flags |= VR_F_RESTART; 1037 return; 1038 } 1039 1040 vr_rxeof(sc); 1041 1042 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1043 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1044 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1045 } 1046 1047 /* 1048 * A frame was downloaded to the chip. It's safe for us to clean up 1049 * the list buffers. 1050 */ 1051 static void 1052 vr_txeof(struct vr_softc *sc) 1053 { 1054 struct vr_chain *cur_tx; 1055 struct ifnet *ifp = &sc->arpcom.ac_if; 1056 1057 VR_LOCK_ASSERT(sc); 1058 1059 /* 1060 * Go through our tx list and free mbufs for those 1061 * frames that have been transmitted. 1062 */ 1063 cur_tx = sc->vr_cdata.vr_tx_cons; 1064 while (cur_tx->vr_mbuf != NULL) { 1065 uint32_t txstat; 1066 int i; 1067 1068 txstat = cur_tx->vr_ptr->vr_status; 1069 1070 if ((txstat & VR_TXSTAT_ABRT) || 1071 (txstat & VR_TXSTAT_UDF)) { 1072 for (i = 0x400; 1073 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1074 i--) 1075 ; /* Wait for chip to shutdown */ 1076 if (!i) { 1077 printf("vr%d: tx shutdown timeout\n", 1078 sc->vr_unit); 1079 sc->vr_flags |= VR_F_RESTART; 1080 break; 1081 } 1082 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1083 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1084 break; 1085 } 1086 1087 if (txstat & VR_TXSTAT_OWN) 1088 break; 1089 1090 if (txstat & VR_TXSTAT_ERRSUM) { 1091 ifp->if_oerrors++; 1092 if (txstat & VR_TXSTAT_DEFER) 1093 ifp->if_collisions++; 1094 if (txstat & VR_TXSTAT_LATECOLL) 1095 ifp->if_collisions++; 1096 } 1097 1098 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1099 1100 ifp->if_opackets++; 1101 m_freem(cur_tx->vr_mbuf); 1102 cur_tx->vr_mbuf = NULL; 1103 ifp->if_flags &= ~IFF_OACTIVE; 1104 1105 cur_tx = cur_tx->vr_nextdesc; 1106 } 1107 sc->vr_cdata.vr_tx_cons = cur_tx; 1108 if (cur_tx->vr_mbuf == NULL) 1109 ifp->if_timer = 0; 1110 } 1111 1112 static void 1113 vr_tick(void *xsc) 1114 { 1115 struct vr_softc *sc = xsc; 1116 struct mii_data *mii; 1117 1118 VR_LOCK(sc); 1119 1120 if (sc->vr_flags & VR_F_RESTART) { 1121 printf("vr%d: restarting\n", sc->vr_unit); 1122 vr_stop(sc); 1123 vr_reset(sc); 1124 vr_init_locked(sc); 1125 sc->vr_flags &= ~VR_F_RESTART; 1126 } 1127 1128 mii = device_get_softc(sc->vr_miibus); 1129 mii_tick(mii); 1130 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1131 1132 VR_UNLOCK(sc); 1133 } 1134 1135 #ifdef DEVICE_POLLING 1136 static poll_handler_t vr_poll; 1137 static poll_handler_t vr_poll_locked; 1138 1139 static void 1140 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1141 { 1142 struct vr_softc *sc = ifp->if_softc; 1143 1144 VR_LOCK(sc); 1145 vr_poll_locked(ifp, cmd, count); 1146 VR_UNLOCK(sc); 1147 } 1148 1149 static void 1150 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1151 { 1152 struct vr_softc *sc = ifp->if_softc; 1153 1154 VR_LOCK_ASSERT(sc); 1155 1156 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1157 ether_poll_deregister(ifp); 1158 cmd = POLL_DEREGISTER; 1159 } 1160 1161 if (cmd == POLL_DEREGISTER) { 1162 /* Final call, enable interrupts. */ 1163 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1164 return; 1165 } 1166 1167 sc->rxcycles = count; 1168 vr_rxeof(sc); 1169 vr_txeof(sc); 1170 if (ifp->if_snd.ifq_head != NULL) 1171 vr_start_locked(ifp); 1172 1173 if (cmd == POLL_AND_CHECK_STATUS) { 1174 uint16_t status; 1175 1176 /* Also check status register. */ 1177 status = CSR_READ_2(sc, VR_ISR); 1178 if (status) 1179 CSR_WRITE_2(sc, VR_ISR, status); 1180 1181 if ((status & VR_INTRS) == 0) 1182 return; 1183 1184 if (status & VR_ISR_RX_DROPPED) { 1185 printf("vr%d: rx packet lost\n", sc->vr_unit); 1186 ifp->if_ierrors++; 1187 } 1188 1189 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1190 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1191 printf("vr%d: receive error (%04x)", 1192 sc->vr_unit, status); 1193 if (status & VR_ISR_RX_NOBUF) 1194 printf(" no buffers"); 1195 if (status & VR_ISR_RX_OFLOW) 1196 printf(" overflow"); 1197 if (status & VR_ISR_RX_DROPPED) 1198 printf(" packet lost"); 1199 printf("\n"); 1200 vr_rxeoc(sc); 1201 } 1202 1203 if ((status & VR_ISR_BUSERR) || 1204 (status & VR_ISR_TX_UNDERRUN)) { 1205 vr_reset(sc); 1206 vr_init_locked(sc); 1207 return; 1208 } 1209 1210 if ((status & VR_ISR_UDFI) || 1211 (status & VR_ISR_TX_ABRT2) || 1212 (status & VR_ISR_TX_ABRT)) { 1213 ifp->if_oerrors++; 1214 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1215 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1216 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1217 } 1218 } 1219 } 1220 } 1221 #endif /* DEVICE_POLLING */ 1222 1223 static void 1224 vr_intr(void *arg) 1225 { 1226 struct vr_softc *sc = arg; 1227 struct ifnet *ifp = &sc->arpcom.ac_if; 1228 uint16_t status; 1229 1230 VR_LOCK(sc); 1231 1232 if (sc->suspended) 1233 goto done_locked; 1234 1235 #ifdef DEVICE_POLLING 1236 if (ifp->if_flags & IFF_POLLING) 1237 goto done_locked; 1238 1239 if ((ifp->if_capenable & IFCAP_POLLING) && 1240 ether_poll_register(vr_poll, ifp)) { 1241 /* OK, disable interrupts. */ 1242 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1243 vr_poll_locked(ifp, 0, 1); 1244 goto done_locked; 1245 } 1246 #endif /* DEVICE_POLLING */ 1247 1248 /* Suppress unwanted interrupts. */ 1249 if (!(ifp->if_flags & IFF_UP)) { 1250 vr_stop(sc); 1251 goto done_locked; 1252 } 1253 1254 /* Disable interrupts. */ 1255 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1256 1257 for (;;) { 1258 status = CSR_READ_2(sc, VR_ISR); 1259 if (status) 1260 CSR_WRITE_2(sc, VR_ISR, status); 1261 1262 if ((status & VR_INTRS) == 0) 1263 break; 1264 1265 if (status & VR_ISR_RX_OK) 1266 vr_rxeof(sc); 1267 1268 if (status & VR_ISR_RX_DROPPED) { 1269 printf("vr%d: rx packet lost\n", sc->vr_unit); 1270 ifp->if_ierrors++; 1271 } 1272 1273 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1274 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1275 printf("vr%d: receive error (%04x)", 1276 sc->vr_unit, status); 1277 if (status & VR_ISR_RX_NOBUF) 1278 printf(" no buffers"); 1279 if (status & VR_ISR_RX_OFLOW) 1280 printf(" overflow"); 1281 if (status & VR_ISR_RX_DROPPED) 1282 printf(" packet lost"); 1283 printf("\n"); 1284 vr_rxeoc(sc); 1285 } 1286 1287 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1288 vr_reset(sc); 1289 vr_init_locked(sc); 1290 break; 1291 } 1292 1293 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1294 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1295 vr_txeof(sc); 1296 if ((status & VR_ISR_UDFI) || 1297 (status & VR_ISR_TX_ABRT2) || 1298 (status & VR_ISR_TX_ABRT)) { 1299 ifp->if_oerrors++; 1300 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1301 VR_SETBIT16(sc, VR_COMMAND, 1302 VR_CMD_TX_ON); 1303 VR_SETBIT16(sc, VR_COMMAND, 1304 VR_CMD_TX_GO); 1305 } 1306 } 1307 } 1308 } 1309 1310 /* Re-enable interrupts. */ 1311 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1312 1313 if (_IF_QLEN(&ifp->if_snd) != 0) 1314 vr_start_locked(ifp); 1315 1316 done_locked: 1317 VR_UNLOCK(sc); 1318 } 1319 1320 /* 1321 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1322 * pointers to the fragment pointers. 1323 */ 1324 static int 1325 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1326 { 1327 struct vr_desc *f = NULL; 1328 struct mbuf *m; 1329 1330 VR_LOCK_ASSERT(sc); 1331 /* 1332 * The VIA Rhine wants packet buffers to be longword 1333 * aligned, but very often our mbufs aren't. Rather than 1334 * waste time trying to decide when to copy and when not 1335 * to copy, just do it all the time. 1336 */ 1337 m = m_defrag(m_head, M_DONTWAIT); 1338 if (m == NULL) 1339 return (1); 1340 1341 /* 1342 * The Rhine chip doesn't auto-pad, so we have to make 1343 * sure to pad short frames out to the minimum frame length 1344 * ourselves. 1345 */ 1346 if (m->m_len < VR_MIN_FRAMELEN) { 1347 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1348 m->m_len = m->m_pkthdr.len; 1349 } 1350 1351 c->vr_mbuf = m; 1352 f = c->vr_ptr; 1353 f->vr_data = vtophys(mtod(m, caddr_t)); 1354 f->vr_ctl = m->m_len; 1355 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1356 f->vr_status = 0; 1357 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1358 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1359 1360 return (0); 1361 } 1362 1363 /* 1364 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1365 * to the mbuf data regions directly in the transmit lists. We also save a 1366 * copy of the pointers since the transmit list fragment pointers are 1367 * physical addresses. 1368 */ 1369 1370 static void 1371 vr_start(struct ifnet *ifp) 1372 { 1373 struct vr_softc *sc = ifp->if_softc; 1374 1375 VR_LOCK(sc); 1376 vr_start_locked(ifp); 1377 VR_UNLOCK(sc); 1378 } 1379 1380 static void 1381 vr_start_locked(struct ifnet *ifp) 1382 { 1383 struct vr_softc *sc = ifp->if_softc; 1384 struct mbuf *m_head; 1385 struct vr_chain *cur_tx; 1386 1387 if (ifp->if_flags & IFF_OACTIVE) 1388 return; 1389 1390 cur_tx = sc->vr_cdata.vr_tx_prod; 1391 while (cur_tx->vr_mbuf == NULL) { 1392 IF_DEQUEUE(&ifp->if_snd, m_head); 1393 if (m_head == NULL) 1394 break; 1395 1396 /* Pack the data into the descriptor. */ 1397 if (vr_encap(sc, cur_tx, m_head)) { 1398 /* Rollback, send what we were able to encap. */ 1399 IF_PREPEND(&ifp->if_snd, m_head); 1400 break; 1401 } 1402 1403 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1404 1405 /* 1406 * If there's a BPF listener, bounce a copy of this frame 1407 * to him. 1408 */ 1409 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1410 1411 cur_tx = cur_tx->vr_nextdesc; 1412 } 1413 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1414 sc->vr_cdata.vr_tx_prod = cur_tx; 1415 1416 /* Tell the chip to start transmitting. */ 1417 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1418 1419 /* Set a timeout in case the chip goes out to lunch. */ 1420 ifp->if_timer = 5; 1421 1422 if (cur_tx->vr_mbuf != NULL) 1423 ifp->if_flags |= IFF_OACTIVE; 1424 } 1425 } 1426 1427 static void 1428 vr_init(void *xsc) 1429 { 1430 struct vr_softc *sc = xsc; 1431 1432 VR_LOCK(sc); 1433 vr_init_locked(sc); 1434 VR_UNLOCK(sc); 1435 } 1436 1437 static void 1438 vr_init_locked(struct vr_softc *sc) 1439 { 1440 struct ifnet *ifp = &sc->arpcom.ac_if; 1441 struct mii_data *mii; 1442 int i; 1443 1444 VR_LOCK_ASSERT(sc); 1445 1446 mii = device_get_softc(sc->vr_miibus); 1447 1448 /* Cancel pending I/O and free all RX/TX buffers. */ 1449 vr_stop(sc); 1450 vr_reset(sc); 1451 1452 /* Set our station address. */ 1453 for (i = 0; i < ETHER_ADDR_LEN; i++) 1454 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1455 1456 /* Set DMA size. */ 1457 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1458 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1459 1460 /* 1461 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1462 * so we must set both. 1463 */ 1464 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1465 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1466 1467 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1468 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1469 1470 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1471 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1472 1473 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1474 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1475 1476 /* Init circular RX list. */ 1477 if (vr_list_rx_init(sc) == ENOBUFS) { 1478 printf( 1479 "vr%d: initialization failed: no memory for rx buffers\n", sc->vr_unit); 1480 vr_stop(sc); 1481 return; 1482 } 1483 1484 /* Init tx descriptors. */ 1485 vr_list_tx_init(sc); 1486 1487 /* If we want promiscuous mode, set the allframes bit. */ 1488 if (ifp->if_flags & IFF_PROMISC) 1489 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1490 else 1491 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1492 1493 /* Set capture broadcast bit to capture broadcast frames. */ 1494 if (ifp->if_flags & IFF_BROADCAST) 1495 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1496 else 1497 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1498 1499 /* 1500 * Program the multicast filter, if necessary. 1501 */ 1502 vr_setmulti(sc); 1503 1504 /* 1505 * Load the address of the RX list. 1506 */ 1507 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1508 1509 /* Enable receiver and transmitter. */ 1510 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1511 VR_CMD_TX_ON|VR_CMD_RX_ON| 1512 VR_CMD_RX_GO); 1513 1514 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1515 1516 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1517 #ifdef DEVICE_POLLING 1518 /* 1519 * Disable interrupts if we are polling. 1520 */ 1521 if (ifp->if_flags & IFF_POLLING) 1522 CSR_WRITE_2(sc, VR_IMR, 0); 1523 else 1524 #endif /* DEVICE_POLLING */ 1525 /* 1526 * Enable interrupts. 1527 */ 1528 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1529 1530 mii_mediachg(mii); 1531 1532 ifp->if_flags |= IFF_RUNNING; 1533 ifp->if_flags &= ~IFF_OACTIVE; 1534 1535 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1536 } 1537 1538 /* 1539 * Set media options. 1540 */ 1541 static int 1542 vr_ifmedia_upd(struct ifnet *ifp) 1543 { 1544 struct vr_softc *sc = ifp->if_softc; 1545 1546 if (ifp->if_flags & IFF_UP) 1547 vr_init(sc); 1548 1549 return (0); 1550 } 1551 1552 /* 1553 * Report current media status. 1554 */ 1555 static void 1556 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1557 { 1558 struct vr_softc *sc = ifp->if_softc; 1559 struct mii_data *mii; 1560 1561 mii = device_get_softc(sc->vr_miibus); 1562 mii_pollstat(mii); 1563 ifmr->ifm_active = mii->mii_media_active; 1564 ifmr->ifm_status = mii->mii_media_status; 1565 } 1566 1567 static int 1568 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1569 { 1570 struct vr_softc *sc = ifp->if_softc; 1571 struct ifreq *ifr = (struct ifreq *) data; 1572 struct mii_data *mii; 1573 int error = 0; 1574 1575 switch (command) { 1576 case SIOCSIFFLAGS: 1577 VR_LOCK(sc); 1578 if (ifp->if_flags & IFF_UP) { 1579 vr_init_locked(sc); 1580 } else { 1581 if (ifp->if_flags & IFF_RUNNING) 1582 vr_stop(sc); 1583 } 1584 VR_UNLOCK(sc); 1585 error = 0; 1586 break; 1587 case SIOCADDMULTI: 1588 case SIOCDELMULTI: 1589 VR_LOCK(sc); 1590 vr_setmulti(sc); 1591 VR_UNLOCK(sc); 1592 error = 0; 1593 break; 1594 case SIOCGIFMEDIA: 1595 case SIOCSIFMEDIA: 1596 mii = device_get_softc(sc->vr_miibus); 1597 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1598 break; 1599 case SIOCSIFCAP: 1600 ifp->if_capenable = ifr->ifr_reqcap; 1601 break; 1602 default: 1603 error = ether_ioctl(ifp, command, data); 1604 break; 1605 } 1606 1607 return (error); 1608 } 1609 1610 static void 1611 vr_watchdog(struct ifnet *ifp) 1612 { 1613 struct vr_softc *sc = ifp->if_softc; 1614 1615 VR_LOCK(sc); 1616 1617 ifp->if_oerrors++; 1618 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1619 1620 vr_stop(sc); 1621 vr_reset(sc); 1622 vr_init_locked(sc); 1623 1624 if (ifp->if_snd.ifq_head != NULL) 1625 vr_start_locked(ifp); 1626 1627 VR_UNLOCK(sc); 1628 } 1629 1630 /* 1631 * Stop the adapter and free any mbufs allocated to the 1632 * RX and TX lists. 1633 */ 1634 static void 1635 vr_stop(struct vr_softc *sc) 1636 { 1637 register int i; 1638 struct ifnet *ifp; 1639 1640 VR_LOCK_ASSERT(sc); 1641 1642 ifp = &sc->arpcom.ac_if; 1643 ifp->if_timer = 0; 1644 1645 untimeout(vr_tick, sc, sc->vr_stat_ch); 1646 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1647 #ifdef DEVICE_POLLING 1648 ether_poll_deregister(ifp); 1649 #endif /* DEVICE_POLLING */ 1650 1651 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1652 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1653 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1654 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1655 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1656 1657 /* 1658 * Free data in the RX lists. 1659 */ 1660 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1661 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1662 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1663 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1664 } 1665 } 1666 bzero((char *)&sc->vr_ldata->vr_rx_list, 1667 sizeof(sc->vr_ldata->vr_rx_list)); 1668 1669 /* 1670 * Free the TX list buffers. 1671 */ 1672 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1673 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1674 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1675 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1676 } 1677 } 1678 bzero((char *)&sc->vr_ldata->vr_tx_list, 1679 sizeof(sc->vr_ldata->vr_tx_list)); 1680 } 1681 1682 /* 1683 * Stop all chip I/O so that the kernel's probe routines don't 1684 * get confused by errant DMAs when rebooting. 1685 */ 1686 static void 1687 vr_shutdown(device_t dev) 1688 { 1689 struct vr_softc *sc = device_get_softc(dev); 1690 1691 VR_LOCK(sc); 1692 vr_stop(sc); 1693 VR_UNLOCK(sc); 1694 } 1695