1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * VIA Rhine fast ethernet PCI NIC driver 37 * 38 * Supports various network adapters based on the VIA Rhine 39 * and Rhine II PCI controllers, including the D-Link DFE530TX. 40 * Datasheets are available at http://www.via.com.tw. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47 /* 48 * The VIA Rhine controllers are similar in some respects to the 49 * the DEC tulip chips, except less complicated. The controller 50 * uses an MII bus and an external physical layer interface. The 51 * receiver has a one entry perfect filter and a 64-bit hash table 52 * multicast filter. Transmit and receive descriptors are similar 53 * to the tulip. 54 * 55 * The Rhine has a serious flaw in its transmit DMA mechanism: 56 * transmit buffers must be longword aligned. Unfortunately, 57 * FreeBSD doesn't guarantee that mbufs will be filled in starting 58 * at longword boundaries, so we have to do a buffer copy before 59 * transmission. 60 */ 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/sockio.h> 65 #include <sys/mbuf.h> 66 #include <sys/malloc.h> 67 #include <sys/kernel.h> 68 #include <sys/socket.h> 69 70 #include <net/if.h> 71 #include <net/if_arp.h> 72 #include <net/ethernet.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 76 #include <net/bpf.h> 77 78 #include <vm/vm.h> /* for vtophys */ 79 #include <vm/pmap.h> /* for vtophys */ 80 #include <machine/clock.h> /* for DELAY */ 81 #include <machine/bus_pio.h> 82 #include <machine/bus_memio.h> 83 #include <machine/bus.h> 84 #include <machine/resource.h> 85 #include <sys/bus.h> 86 #include <sys/rman.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <pci/pcireg.h> 92 #include <pci/pcivar.h> 93 94 #define VR_USEIOSPACE 95 96 #include <pci/if_vrreg.h> 97 98 MODULE_DEPEND(vr, miibus, 1, 1, 1); 99 100 /* "controller miibus0" required. See GENERIC if you get errors here. */ 101 #include "miibus_if.h" 102 103 #ifndef lint 104 static const char rcsid[] = 105 "$FreeBSD$"; 106 #endif 107 108 /* 109 * Various supported device vendors/types and their names. 110 */ 111 static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 117 "Delta Electronics Rhine II 10/100BaseTX" }, 118 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 119 "Addtron Technology Rhine II 10/100BaseTX" }, 120 { 0, 0, NULL } 121 }; 122 123 static int vr_probe __P((device_t)); 124 static int vr_attach __P((device_t)); 125 static int vr_detach __P((device_t)); 126 127 static int vr_newbuf __P((struct vr_softc *, 128 struct vr_chain_onefrag *, 129 struct mbuf *)); 130 static int vr_encap __P((struct vr_softc *, struct vr_chain *, 131 struct mbuf * )); 132 133 static void vr_rxeof __P((struct vr_softc *)); 134 static void vr_rxeoc __P((struct vr_softc *)); 135 static void vr_txeof __P((struct vr_softc *)); 136 static void vr_txeoc __P((struct vr_softc *)); 137 static void vr_tick __P((void *)); 138 static void vr_intr __P((void *)); 139 static void vr_start __P((struct ifnet *)); 140 static int vr_ioctl __P((struct ifnet *, u_long, caddr_t)); 141 static void vr_init __P((void *)); 142 static void vr_stop __P((struct vr_softc *)); 143 static void vr_watchdog __P((struct ifnet *)); 144 static void vr_shutdown __P((device_t)); 145 static int vr_ifmedia_upd __P((struct ifnet *)); 146 static void vr_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 147 148 static void vr_mii_sync __P((struct vr_softc *)); 149 static void vr_mii_send __P((struct vr_softc *, u_int32_t, int)); 150 static int vr_mii_readreg __P((struct vr_softc *, struct vr_mii_frame *)); 151 static int vr_mii_writereg __P((struct vr_softc *, struct vr_mii_frame *)); 152 static int vr_miibus_readreg __P((device_t, int, int)); 153 static int vr_miibus_writereg __P((device_t, int, int, int)); 154 static void vr_miibus_statchg __P((device_t)); 155 156 static void vr_setcfg __P((struct vr_softc *, int)); 157 static u_int8_t vr_calchash __P((u_int8_t *)); 158 static void vr_setmulti __P((struct vr_softc *)); 159 static void vr_reset __P((struct vr_softc *)); 160 static int vr_list_rx_init __P((struct vr_softc *)); 161 static int vr_list_tx_init __P((struct vr_softc *)); 162 163 #ifdef VR_USEIOSPACE 164 #define VR_RES SYS_RES_IOPORT 165 #define VR_RID VR_PCI_LOIO 166 #else 167 #define VR_RES SYS_RES_MEMORY 168 #define VR_RID VR_PCI_LOMEM 169 #endif 170 171 static device_method_t vr_methods[] = { 172 /* Device interface */ 173 DEVMETHOD(device_probe, vr_probe), 174 DEVMETHOD(device_attach, vr_attach), 175 DEVMETHOD(device_detach, vr_detach), 176 DEVMETHOD(device_shutdown, vr_shutdown), 177 178 /* bus interface */ 179 DEVMETHOD(bus_print_child, bus_generic_print_child), 180 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 181 182 /* MII interface */ 183 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 184 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 185 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 186 187 { 0, 0 } 188 }; 189 190 static driver_t vr_driver = { 191 "vr", 192 vr_methods, 193 sizeof(struct vr_softc) 194 }; 195 196 static devclass_t vr_devclass; 197 198 DRIVER_MODULE(if_vr, pci, vr_driver, vr_devclass, 0, 0); 199 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 200 201 #define VR_SETBIT(sc, reg, x) \ 202 CSR_WRITE_1(sc, reg, \ 203 CSR_READ_1(sc, reg) | x) 204 205 #define VR_CLRBIT(sc, reg, x) \ 206 CSR_WRITE_1(sc, reg, \ 207 CSR_READ_1(sc, reg) & ~x) 208 209 #define VR_SETBIT16(sc, reg, x) \ 210 CSR_WRITE_2(sc, reg, \ 211 CSR_READ_2(sc, reg) | x) 212 213 #define VR_CLRBIT16(sc, reg, x) \ 214 CSR_WRITE_2(sc, reg, \ 215 CSR_READ_2(sc, reg) & ~x) 216 217 #define VR_SETBIT32(sc, reg, x) \ 218 CSR_WRITE_4(sc, reg, \ 219 CSR_READ_4(sc, reg) | x) 220 221 #define VR_CLRBIT32(sc, reg, x) \ 222 CSR_WRITE_4(sc, reg, \ 223 CSR_READ_4(sc, reg) & ~x) 224 225 #define SIO_SET(x) \ 226 CSR_WRITE_1(sc, VR_MIICMD, \ 227 CSR_READ_1(sc, VR_MIICMD) | x) 228 229 #define SIO_CLR(x) \ 230 CSR_WRITE_1(sc, VR_MIICMD, \ 231 CSR_READ_1(sc, VR_MIICMD) & ~x) 232 233 /* 234 * Sync the PHYs by setting data bit and strobing the clock 32 times. 235 */ 236 static void vr_mii_sync(sc) 237 struct vr_softc *sc; 238 { 239 register int i; 240 241 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 242 243 for (i = 0; i < 32; i++) { 244 SIO_SET(VR_MIICMD_CLK); 245 DELAY(1); 246 SIO_CLR(VR_MIICMD_CLK); 247 DELAY(1); 248 } 249 250 return; 251 } 252 253 /* 254 * Clock a series of bits through the MII. 255 */ 256 static void vr_mii_send(sc, bits, cnt) 257 struct vr_softc *sc; 258 u_int32_t bits; 259 int cnt; 260 { 261 int i; 262 263 SIO_CLR(VR_MIICMD_CLK); 264 265 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 266 if (bits & i) { 267 SIO_SET(VR_MIICMD_DATAIN); 268 } else { 269 SIO_CLR(VR_MIICMD_DATAIN); 270 } 271 DELAY(1); 272 SIO_CLR(VR_MIICMD_CLK); 273 DELAY(1); 274 SIO_SET(VR_MIICMD_CLK); 275 } 276 } 277 278 /* 279 * Read an PHY register through the MII. 280 */ 281 static int vr_mii_readreg(sc, frame) 282 struct vr_softc *sc; 283 struct vr_mii_frame *frame; 284 285 { 286 int i, ack, s; 287 288 s = splimp(); 289 290 /* 291 * Set up frame for RX. 292 */ 293 frame->mii_stdelim = VR_MII_STARTDELIM; 294 frame->mii_opcode = VR_MII_READOP; 295 frame->mii_turnaround = 0; 296 frame->mii_data = 0; 297 298 CSR_WRITE_1(sc, VR_MIICMD, 0); 299 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 300 301 /* 302 * Turn on data xmit. 303 */ 304 SIO_SET(VR_MIICMD_DIR); 305 306 vr_mii_sync(sc); 307 308 /* 309 * Send command/address info. 310 */ 311 vr_mii_send(sc, frame->mii_stdelim, 2); 312 vr_mii_send(sc, frame->mii_opcode, 2); 313 vr_mii_send(sc, frame->mii_phyaddr, 5); 314 vr_mii_send(sc, frame->mii_regaddr, 5); 315 316 /* Idle bit */ 317 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 318 DELAY(1); 319 SIO_SET(VR_MIICMD_CLK); 320 DELAY(1); 321 322 /* Turn off xmit. */ 323 SIO_CLR(VR_MIICMD_DIR); 324 325 /* Check for ack */ 326 SIO_CLR(VR_MIICMD_CLK); 327 DELAY(1); 328 SIO_SET(VR_MIICMD_CLK); 329 DELAY(1); 330 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 331 332 /* 333 * Now try reading data bits. If the ack failed, we still 334 * need to clock through 16 cycles to keep the PHY(s) in sync. 335 */ 336 if (ack) { 337 for(i = 0; i < 16; i++) { 338 SIO_CLR(VR_MIICMD_CLK); 339 DELAY(1); 340 SIO_SET(VR_MIICMD_CLK); 341 DELAY(1); 342 } 343 goto fail; 344 } 345 346 for (i = 0x8000; i; i >>= 1) { 347 SIO_CLR(VR_MIICMD_CLK); 348 DELAY(1); 349 if (!ack) { 350 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 351 frame->mii_data |= i; 352 DELAY(1); 353 } 354 SIO_SET(VR_MIICMD_CLK); 355 DELAY(1); 356 } 357 358 fail: 359 360 SIO_CLR(VR_MIICMD_CLK); 361 DELAY(1); 362 SIO_SET(VR_MIICMD_CLK); 363 DELAY(1); 364 365 splx(s); 366 367 if (ack) 368 return(1); 369 return(0); 370 } 371 372 /* 373 * Write to a PHY register through the MII. 374 */ 375 static int vr_mii_writereg(sc, frame) 376 struct vr_softc *sc; 377 struct vr_mii_frame *frame; 378 379 { 380 int s; 381 382 s = splimp(); 383 384 CSR_WRITE_1(sc, VR_MIICMD, 0); 385 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 386 387 /* 388 * Set up frame for TX. 389 */ 390 391 frame->mii_stdelim = VR_MII_STARTDELIM; 392 frame->mii_opcode = VR_MII_WRITEOP; 393 frame->mii_turnaround = VR_MII_TURNAROUND; 394 395 /* 396 * Turn on data output. 397 */ 398 SIO_SET(VR_MIICMD_DIR); 399 400 vr_mii_sync(sc); 401 402 vr_mii_send(sc, frame->mii_stdelim, 2); 403 vr_mii_send(sc, frame->mii_opcode, 2); 404 vr_mii_send(sc, frame->mii_phyaddr, 5); 405 vr_mii_send(sc, frame->mii_regaddr, 5); 406 vr_mii_send(sc, frame->mii_turnaround, 2); 407 vr_mii_send(sc, frame->mii_data, 16); 408 409 /* Idle bit. */ 410 SIO_SET(VR_MIICMD_CLK); 411 DELAY(1); 412 SIO_CLR(VR_MIICMD_CLK); 413 DELAY(1); 414 415 /* 416 * Turn off xmit. 417 */ 418 SIO_CLR(VR_MIICMD_DIR); 419 420 splx(s); 421 422 return(0); 423 } 424 425 static int vr_miibus_readreg(dev, phy, reg) 426 device_t dev; 427 int phy, reg; 428 { 429 struct vr_softc *sc; 430 struct vr_mii_frame frame; 431 432 sc = device_get_softc(dev); 433 bzero((char *)&frame, sizeof(frame)); 434 435 frame.mii_phyaddr = phy; 436 frame.mii_regaddr = reg; 437 vr_mii_readreg(sc, &frame); 438 439 return(frame.mii_data); 440 } 441 442 static int vr_miibus_writereg(dev, phy, reg, data) 443 device_t dev; 444 u_int16_t phy, reg, data; 445 { 446 struct vr_softc *sc; 447 struct vr_mii_frame frame; 448 449 sc = device_get_softc(dev); 450 bzero((char *)&frame, sizeof(frame)); 451 452 frame.mii_phyaddr = phy; 453 frame.mii_regaddr = reg; 454 frame.mii_data = data; 455 456 vr_mii_writereg(sc, &frame); 457 458 return(0); 459 } 460 461 static void vr_miibus_statchg(dev) 462 device_t dev; 463 { 464 struct vr_softc *sc; 465 struct mii_data *mii; 466 467 sc = device_get_softc(dev); 468 mii = device_get_softc(sc->vr_miibus); 469 vr_setcfg(sc, mii->mii_media_active); 470 471 return; 472 } 473 474 /* 475 * Calculate CRC of a multicast group address, return the lower 6 bits. 476 */ 477 static u_int8_t vr_calchash(addr) 478 u_int8_t *addr; 479 { 480 u_int32_t crc, carry; 481 int i, j; 482 u_int8_t c; 483 484 /* Compute CRC for the address value. */ 485 crc = 0xFFFFFFFF; /* initial value */ 486 487 for (i = 0; i < 6; i++) { 488 c = *(addr + i); 489 for (j = 0; j < 8; j++) { 490 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 491 crc <<= 1; 492 c >>= 1; 493 if (carry) 494 crc = (crc ^ 0x04c11db6) | carry; 495 } 496 } 497 498 /* return the filter bit position */ 499 return((crc >> 26) & 0x0000003F); 500 } 501 502 /* 503 * Program the 64-bit multicast hash filter. 504 */ 505 static void vr_setmulti(sc) 506 struct vr_softc *sc; 507 { 508 struct ifnet *ifp; 509 int h = 0; 510 u_int32_t hashes[2] = { 0, 0 }; 511 struct ifmultiaddr *ifma; 512 u_int8_t rxfilt; 513 int mcnt = 0; 514 515 ifp = &sc->arpcom.ac_if; 516 517 rxfilt = CSR_READ_1(sc, VR_RXCFG); 518 519 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 520 rxfilt |= VR_RXCFG_RX_MULTI; 521 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 522 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 523 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 524 return; 525 } 526 527 /* first, zot all the existing hash bits */ 528 CSR_WRITE_4(sc, VR_MAR0, 0); 529 CSR_WRITE_4(sc, VR_MAR1, 0); 530 531 /* now program new ones */ 532 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 533 ifma = ifma->ifma_link.le_next) { 534 if (ifma->ifma_addr->sa_family != AF_LINK) 535 continue; 536 h = vr_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 537 if (h < 32) 538 hashes[0] |= (1 << h); 539 else 540 hashes[1] |= (1 << (h - 32)); 541 mcnt++; 542 } 543 544 if (mcnt) 545 rxfilt |= VR_RXCFG_RX_MULTI; 546 else 547 rxfilt &= ~VR_RXCFG_RX_MULTI; 548 549 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 550 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 551 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 552 553 return; 554 } 555 556 /* 557 * In order to fiddle with the 558 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 559 * first have to put the transmit and/or receive logic in the idle state. 560 */ 561 static void vr_setcfg(sc, media) 562 struct vr_softc *sc; 563 int media; 564 { 565 int restart = 0; 566 567 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 568 restart = 1; 569 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 570 } 571 572 if ((media & IFM_GMASK) == IFM_FDX) 573 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 574 else 575 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 576 577 if (restart) 578 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 579 580 return; 581 } 582 583 static void vr_reset(sc) 584 struct vr_softc *sc; 585 { 586 register int i; 587 588 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 589 590 for (i = 0; i < VR_TIMEOUT; i++) { 591 DELAY(10); 592 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 593 break; 594 } 595 if (i == VR_TIMEOUT) 596 printf("vr%d: reset never completed!\n", sc->vr_unit); 597 598 /* Wait a little while for the chip to get its brains in order. */ 599 DELAY(1000); 600 601 return; 602 } 603 604 /* 605 * Probe for a VIA Rhine chip. Check the PCI vendor and device 606 * IDs against our list and return a device name if we find a match. 607 */ 608 static int vr_probe(dev) 609 device_t dev; 610 { 611 struct vr_type *t; 612 613 t = vr_devs; 614 615 while(t->vr_name != NULL) { 616 if ((pci_get_vendor(dev) == t->vr_vid) && 617 (pci_get_device(dev) == t->vr_did)) { 618 device_set_desc(dev, t->vr_name); 619 return(0); 620 } 621 t++; 622 } 623 624 return(ENXIO); 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 static int vr_attach(dev) 632 device_t dev; 633 { 634 int i, s; 635 u_char eaddr[ETHER_ADDR_LEN]; 636 u_int32_t command; 637 struct vr_softc *sc; 638 struct ifnet *ifp; 639 int unit, error = 0, rid; 640 641 s = splimp(); 642 643 sc = device_get_softc(dev); 644 unit = device_get_unit(dev); 645 bzero(sc, sizeof(struct vr_softc *)); 646 647 /* 648 * Handle power management nonsense. 649 */ 650 651 command = pci_read_config(dev, VR_PCI_CAPID, 4) & 0x000000FF; 652 if (command == 0x01) { 653 654 command = pci_read_config(dev, VR_PCI_PWRMGMTCTRL, 4); 655 if (command & VR_PSTATE_MASK) { 656 u_int32_t iobase, membase, irq; 657 658 /* Save important PCI config data. */ 659 iobase = pci_read_config(dev, VR_PCI_LOIO, 4); 660 membase = pci_read_config(dev, VR_PCI_LOMEM, 4); 661 irq = pci_read_config(dev, VR_PCI_INTLINE, 4); 662 663 /* Reset the power state. */ 664 printf("vr%d: chip is in D%d power mode " 665 "-- setting to D0\n", unit, command & VR_PSTATE_MASK); 666 command &= 0xFFFFFFFC; 667 pci_write_config(dev, VR_PCI_PWRMGMTCTRL, command, 4); 668 669 /* Restore PCI config data. */ 670 pci_write_config(dev, VR_PCI_LOIO, iobase, 4); 671 pci_write_config(dev, VR_PCI_LOMEM, membase, 4); 672 pci_write_config(dev, VR_PCI_INTLINE, irq, 4); 673 } 674 } 675 676 /* 677 * Map control/status registers. 678 */ 679 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 680 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 681 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 682 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 683 684 #ifdef VR_USEIOSPACE 685 if (!(command & PCIM_CMD_PORTEN)) { 686 printf("vr%d: failed to enable I/O ports!\n", unit); 687 free(sc, M_DEVBUF); 688 goto fail; 689 } 690 #else 691 if (!(command & PCIM_CMD_MEMEN)) { 692 printf("vr%d: failed to enable memory mapping!\n", unit); 693 goto fail; 694 } 695 #endif 696 697 rid = VR_RID; 698 sc->vr_res = bus_alloc_resource(dev, VR_RES, &rid, 699 0, ~0, 1, RF_ACTIVE); 700 701 if (sc->vr_res == NULL) { 702 printf("vr%d: couldn't map ports/memory\n", unit); 703 error = ENXIO; 704 goto fail; 705 } 706 707 sc->vr_btag = rman_get_bustag(sc->vr_res); 708 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 709 710 /* Allocate interrupt */ 711 rid = 0; 712 sc->vr_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 713 RF_SHAREABLE | RF_ACTIVE); 714 715 if (sc->vr_irq == NULL) { 716 printf("vr%d: couldn't map interrupt\n", unit); 717 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 718 error = ENXIO; 719 goto fail; 720 } 721 722 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET, 723 vr_intr, sc, &sc->vr_intrhand); 724 725 if (error) { 726 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 727 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 728 printf("vr%d: couldn't set up irq\n", unit); 729 goto fail; 730 } 731 732 /* Reset the adapter. */ 733 vr_reset(sc); 734 735 /* 736 * Get station address. The way the Rhine chips work, 737 * you're not allowed to directly access the EEPROM once 738 * they've been programmed a special way. Consequently, 739 * we need to read the node address from the PAR0 and PAR1 740 * registers. 741 */ 742 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 743 DELAY(200); 744 for (i = 0; i < ETHER_ADDR_LEN; i++) 745 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 746 747 /* 748 * A Rhine chip was detected. Inform the world. 749 */ 750 printf("vr%d: Ethernet address: %6D\n", unit, eaddr, ":"); 751 752 sc->vr_unit = unit; 753 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 754 755 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 756 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 757 758 if (sc->vr_ldata == NULL) { 759 printf("vr%d: no memory for list buffers!\n", unit); 760 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 761 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 762 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 763 error = ENXIO; 764 goto fail; 765 } 766 767 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 768 769 ifp = &sc->arpcom.ac_if; 770 ifp->if_softc = sc; 771 ifp->if_unit = unit; 772 ifp->if_name = "vr"; 773 ifp->if_mtu = ETHERMTU; 774 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 775 ifp->if_ioctl = vr_ioctl; 776 ifp->if_output = ether_output; 777 ifp->if_start = vr_start; 778 ifp->if_watchdog = vr_watchdog; 779 ifp->if_init = vr_init; 780 ifp->if_baudrate = 10000000; 781 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 782 783 /* 784 * Do MII setup. 785 */ 786 if (mii_phy_probe(dev, &sc->vr_miibus, 787 vr_ifmedia_upd, vr_ifmedia_sts)) { 788 printf("vr%d: MII without any phy!\n", sc->vr_unit); 789 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 790 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 791 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 792 contigfree(sc->vr_ldata, 793 sizeof(struct vr_list_data), M_DEVBUF); 794 error = ENXIO; 795 goto fail; 796 } 797 798 callout_handle_init(&sc->vr_stat_ch); 799 800 /* 801 * Call MI attach routines. 802 */ 803 if_attach(ifp); 804 ether_ifattach(ifp); 805 806 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 807 808 fail: 809 splx(s); 810 return(error); 811 } 812 813 static int vr_detach(dev) 814 device_t dev; 815 { 816 struct vr_softc *sc; 817 struct ifnet *ifp; 818 int s; 819 820 s = splimp(); 821 822 sc = device_get_softc(dev); 823 ifp = &sc->arpcom.ac_if; 824 825 vr_stop(sc); 826 if_detach(ifp); 827 828 bus_generic_detach(dev); 829 device_delete_child(dev, sc->vr_miibus); 830 831 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 832 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 833 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 834 835 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 836 837 splx(s); 838 839 return(0); 840 } 841 842 /* 843 * Initialize the transmit descriptors. 844 */ 845 static int vr_list_tx_init(sc) 846 struct vr_softc *sc; 847 { 848 struct vr_chain_data *cd; 849 struct vr_list_data *ld; 850 int i; 851 852 cd = &sc->vr_cdata; 853 ld = sc->vr_ldata; 854 for (i = 0; i < VR_TX_LIST_CNT; i++) { 855 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 856 if (i == (VR_TX_LIST_CNT - 1)) 857 cd->vr_tx_chain[i].vr_nextdesc = 858 &cd->vr_tx_chain[0]; 859 else 860 cd->vr_tx_chain[i].vr_nextdesc = 861 &cd->vr_tx_chain[i + 1]; 862 } 863 864 cd->vr_tx_free = &cd->vr_tx_chain[0]; 865 cd->vr_tx_tail = cd->vr_tx_head = NULL; 866 867 return(0); 868 } 869 870 871 /* 872 * Initialize the RX descriptors and allocate mbufs for them. Note that 873 * we arrange the descriptors in a closed ring, so that the last descriptor 874 * points back to the first. 875 */ 876 static int vr_list_rx_init(sc) 877 struct vr_softc *sc; 878 { 879 struct vr_chain_data *cd; 880 struct vr_list_data *ld; 881 int i; 882 883 cd = &sc->vr_cdata; 884 ld = sc->vr_ldata; 885 886 for (i = 0; i < VR_RX_LIST_CNT; i++) { 887 cd->vr_rx_chain[i].vr_ptr = 888 (struct vr_desc *)&ld->vr_rx_list[i]; 889 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 890 return(ENOBUFS); 891 if (i == (VR_RX_LIST_CNT - 1)) { 892 cd->vr_rx_chain[i].vr_nextdesc = 893 &cd->vr_rx_chain[0]; 894 ld->vr_rx_list[i].vr_next = 895 vtophys(&ld->vr_rx_list[0]); 896 } else { 897 cd->vr_rx_chain[i].vr_nextdesc = 898 &cd->vr_rx_chain[i + 1]; 899 ld->vr_rx_list[i].vr_next = 900 vtophys(&ld->vr_rx_list[i + 1]); 901 } 902 } 903 904 cd->vr_rx_head = &cd->vr_rx_chain[0]; 905 906 return(0); 907 } 908 909 /* 910 * Initialize an RX descriptor and attach an MBUF cluster. 911 * Note: the length fields are only 11 bits wide, which means the 912 * largest size we can specify is 2047. This is important because 913 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 914 * overflow the field and make a mess. 915 */ 916 static int vr_newbuf(sc, c, m) 917 struct vr_softc *sc; 918 struct vr_chain_onefrag *c; 919 struct mbuf *m; 920 { 921 struct mbuf *m_new = NULL; 922 923 if (m == NULL) { 924 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 925 if (m_new == NULL) { 926 printf("vr%d: no memory for rx list " 927 "-- packet dropped!\n", sc->vr_unit); 928 return(ENOBUFS); 929 } 930 931 MCLGET(m_new, M_DONTWAIT); 932 if (!(m_new->m_flags & M_EXT)) { 933 printf("vr%d: no memory for rx list " 934 "-- packet dropped!\n", sc->vr_unit); 935 m_freem(m_new); 936 return(ENOBUFS); 937 } 938 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 939 } else { 940 m_new = m; 941 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 942 m_new->m_data = m_new->m_ext.ext_buf; 943 } 944 945 m_adj(m_new, sizeof(u_int64_t)); 946 947 c->vr_mbuf = m_new; 948 c->vr_ptr->vr_status = VR_RXSTAT; 949 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 950 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 951 952 return(0); 953 } 954 955 /* 956 * A frame has been uploaded: pass the resulting mbuf chain up to 957 * the higher level protocols. 958 */ 959 static void vr_rxeof(sc) 960 struct vr_softc *sc; 961 { 962 struct ether_header *eh; 963 struct mbuf *m; 964 struct ifnet *ifp; 965 struct vr_chain_onefrag *cur_rx; 966 int total_len = 0; 967 u_int32_t rxstat; 968 969 ifp = &sc->arpcom.ac_if; 970 971 while(!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 972 VR_RXSTAT_OWN)) { 973 struct mbuf *m0 = NULL; 974 975 cur_rx = sc->vr_cdata.vr_rx_head; 976 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 977 m = cur_rx->vr_mbuf; 978 979 /* 980 * If an error occurs, update stats, clear the 981 * status word and leave the mbuf cluster in place: 982 * it should simply get re-used next time this descriptor 983 * comes up in the ring. 984 */ 985 if (rxstat & VR_RXSTAT_RXERR) { 986 ifp->if_ierrors++; 987 printf("vr%d: rx error: ", sc->vr_unit); 988 switch(rxstat & 0x000000FF) { 989 case VR_RXSTAT_CRCERR: 990 printf("crc error\n"); 991 break; 992 case VR_RXSTAT_FRAMEALIGNERR: 993 printf("frame alignment error\n"); 994 break; 995 case VR_RXSTAT_FIFOOFLOW: 996 printf("FIFO overflow\n"); 997 break; 998 case VR_RXSTAT_GIANT: 999 printf("received giant packet\n"); 1000 break; 1001 case VR_RXSTAT_RUNT: 1002 printf("received runt packet\n"); 1003 break; 1004 case VR_RXSTAT_BUSERR: 1005 printf("system bus error\n"); 1006 break; 1007 case VR_RXSTAT_BUFFERR: 1008 printf("rx buffer error\n"); 1009 break; 1010 default: 1011 printf("unknown rx error\n"); 1012 break; 1013 } 1014 vr_newbuf(sc, cur_rx, m); 1015 continue; 1016 } 1017 1018 /* No errors; receive the packet. */ 1019 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 1020 1021 /* 1022 * XXX The VIA Rhine chip includes the CRC with every 1023 * received frame, and there's no way to turn this 1024 * behavior off (at least, I can't find anything in 1025 * the manual that explains how to do it) so we have 1026 * to trim off the CRC manually. 1027 */ 1028 total_len -= ETHER_CRC_LEN; 1029 1030 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1031 total_len + ETHER_ALIGN, 0, ifp, NULL); 1032 vr_newbuf(sc, cur_rx, m); 1033 if (m0 == NULL) { 1034 ifp->if_ierrors++; 1035 continue; 1036 } 1037 m_adj(m0, ETHER_ALIGN); 1038 m = m0; 1039 1040 ifp->if_ipackets++; 1041 eh = mtod(m, struct ether_header *); 1042 1043 /* Remove header from mbuf and pass it on. */ 1044 m_adj(m, sizeof(struct ether_header)); 1045 ether_input(ifp, eh, m); 1046 } 1047 1048 return; 1049 } 1050 1051 void vr_rxeoc(sc) 1052 struct vr_softc *sc; 1053 { 1054 1055 vr_rxeof(sc); 1056 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1057 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1058 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1059 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1060 1061 return; 1062 } 1063 1064 /* 1065 * A frame was downloaded to the chip. It's safe for us to clean up 1066 * the list buffers. 1067 */ 1068 1069 static void vr_txeof(sc) 1070 struct vr_softc *sc; 1071 { 1072 struct vr_chain *cur_tx; 1073 struct ifnet *ifp; 1074 1075 ifp = &sc->arpcom.ac_if; 1076 1077 /* Clear the timeout timer. */ 1078 ifp->if_timer = 0; 1079 1080 /* Sanity check. */ 1081 if (sc->vr_cdata.vr_tx_head == NULL) 1082 return; 1083 1084 /* 1085 * Go through our tx list and free mbufs for those 1086 * frames that have been transmitted. 1087 */ 1088 while(sc->vr_cdata.vr_tx_head->vr_mbuf != NULL) { 1089 u_int32_t txstat; 1090 1091 cur_tx = sc->vr_cdata.vr_tx_head; 1092 txstat = cur_tx->vr_ptr->vr_status; 1093 1094 if (txstat & VR_TXSTAT_OWN) 1095 break; 1096 1097 if (txstat & VR_TXSTAT_ERRSUM) { 1098 ifp->if_oerrors++; 1099 if (txstat & VR_TXSTAT_DEFER) 1100 ifp->if_collisions++; 1101 if (txstat & VR_TXSTAT_LATECOLL) 1102 ifp->if_collisions++; 1103 } 1104 1105 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1106 1107 ifp->if_opackets++; 1108 if (cur_tx->vr_mbuf != NULL) { 1109 m_freem(cur_tx->vr_mbuf); 1110 cur_tx->vr_mbuf = NULL; 1111 } 1112 1113 if (sc->vr_cdata.vr_tx_head == sc->vr_cdata.vr_tx_tail) { 1114 sc->vr_cdata.vr_tx_head = NULL; 1115 sc->vr_cdata.vr_tx_tail = NULL; 1116 break; 1117 } 1118 1119 sc->vr_cdata.vr_tx_head = cur_tx->vr_nextdesc; 1120 } 1121 1122 return; 1123 } 1124 1125 /* 1126 * TX 'end of channel' interrupt handler. 1127 */ 1128 static void vr_txeoc(sc) 1129 struct vr_softc *sc; 1130 { 1131 struct ifnet *ifp; 1132 1133 ifp = &sc->arpcom.ac_if; 1134 1135 ifp->if_timer = 0; 1136 1137 if (sc->vr_cdata.vr_tx_head == NULL) { 1138 ifp->if_flags &= ~IFF_OACTIVE; 1139 sc->vr_cdata.vr_tx_tail = NULL; 1140 } 1141 1142 return; 1143 } 1144 1145 static void vr_tick(xsc) 1146 void *xsc; 1147 { 1148 struct vr_softc *sc; 1149 struct mii_data *mii; 1150 int s; 1151 1152 s = splimp(); 1153 1154 sc = xsc; 1155 mii = device_get_softc(sc->vr_miibus); 1156 mii_tick(mii); 1157 1158 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1159 1160 splx(s); 1161 1162 return; 1163 } 1164 1165 static void vr_intr(arg) 1166 void *arg; 1167 { 1168 struct vr_softc *sc; 1169 struct ifnet *ifp; 1170 u_int16_t status; 1171 1172 sc = arg; 1173 ifp = &sc->arpcom.ac_if; 1174 1175 /* Supress unwanted interrupts. */ 1176 if (!(ifp->if_flags & IFF_UP)) { 1177 vr_stop(sc); 1178 return; 1179 } 1180 1181 /* Disable interrupts. */ 1182 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1183 1184 for (;;) { 1185 1186 status = CSR_READ_2(sc, VR_ISR); 1187 if (status) 1188 CSR_WRITE_2(sc, VR_ISR, status); 1189 1190 if ((status & VR_INTRS) == 0) 1191 break; 1192 1193 if (status & VR_ISR_RX_OK) 1194 vr_rxeof(sc); 1195 1196 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1197 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW) || 1198 (status & VR_ISR_RX_DROPPED)) { 1199 vr_rxeof(sc); 1200 vr_rxeoc(sc); 1201 } 1202 1203 if (status & VR_ISR_TX_OK) { 1204 vr_txeof(sc); 1205 vr_txeoc(sc); 1206 } 1207 1208 if ((status & VR_ISR_TX_UNDERRUN)||(status & VR_ISR_TX_ABRT)){ 1209 ifp->if_oerrors++; 1210 vr_txeof(sc); 1211 if (sc->vr_cdata.vr_tx_head != NULL) { 1212 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1213 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1214 } 1215 } 1216 1217 if (status & VR_ISR_BUSERR) { 1218 vr_reset(sc); 1219 vr_init(sc); 1220 } 1221 } 1222 1223 /* Re-enable interrupts. */ 1224 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1225 1226 if (ifp->if_snd.ifq_head != NULL) { 1227 vr_start(ifp); 1228 } 1229 1230 return; 1231 } 1232 1233 /* 1234 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1235 * pointers to the fragment pointers. 1236 */ 1237 static int vr_encap(sc, c, m_head) 1238 struct vr_softc *sc; 1239 struct vr_chain *c; 1240 struct mbuf *m_head; 1241 { 1242 int frag = 0; 1243 struct vr_desc *f = NULL; 1244 int total_len; 1245 struct mbuf *m; 1246 1247 m = m_head; 1248 total_len = 0; 1249 1250 /* 1251 * The VIA Rhine wants packet buffers to be longword 1252 * aligned, but very often our mbufs aren't. Rather than 1253 * waste time trying to decide when to copy and when not 1254 * to copy, just do it all the time. 1255 */ 1256 if (m != NULL) { 1257 struct mbuf *m_new = NULL; 1258 1259 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1260 if (m_new == NULL) { 1261 printf("vr%d: no memory for tx list", sc->vr_unit); 1262 return(1); 1263 } 1264 if (m_head->m_pkthdr.len > MHLEN) { 1265 MCLGET(m_new, M_DONTWAIT); 1266 if (!(m_new->m_flags & M_EXT)) { 1267 m_freem(m_new); 1268 printf("vr%d: no memory for tx list", 1269 sc->vr_unit); 1270 return(1); 1271 } 1272 } 1273 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1274 mtod(m_new, caddr_t)); 1275 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1276 m_freem(m_head); 1277 m_head = m_new; 1278 /* 1279 * The Rhine chip doesn't auto-pad, so we have to make 1280 * sure to pad short frames out to the minimum frame length 1281 * ourselves. 1282 */ 1283 if (m_head->m_len < VR_MIN_FRAMELEN) { 1284 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len; 1285 m_new->m_len = m_new->m_pkthdr.len; 1286 } 1287 f = c->vr_ptr; 1288 f->vr_data = vtophys(mtod(m_new, caddr_t)); 1289 f->vr_ctl = total_len = m_new->m_len; 1290 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1291 f->vr_status = 0; 1292 frag = 1; 1293 } 1294 1295 c->vr_mbuf = m_head; 1296 c->vr_ptr->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1297 c->vr_ptr->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1298 1299 return(0); 1300 } 1301 1302 /* 1303 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1304 * to the mbuf data regions directly in the transmit lists. We also save a 1305 * copy of the pointers since the transmit list fragment pointers are 1306 * physical addresses. 1307 */ 1308 1309 static void vr_start(ifp) 1310 struct ifnet *ifp; 1311 { 1312 struct vr_softc *sc; 1313 struct mbuf *m_head = NULL; 1314 struct vr_chain *cur_tx = NULL, *start_tx; 1315 1316 sc = ifp->if_softc; 1317 1318 if (ifp->if_flags & IFF_OACTIVE) 1319 return; 1320 1321 /* 1322 * Check for an available queue slot. If there are none, 1323 * punt. 1324 */ 1325 if (sc->vr_cdata.vr_tx_free->vr_mbuf != NULL) { 1326 ifp->if_flags |= IFF_OACTIVE; 1327 return; 1328 } 1329 1330 start_tx = sc->vr_cdata.vr_tx_free; 1331 1332 while(sc->vr_cdata.vr_tx_free->vr_mbuf == NULL) { 1333 IF_DEQUEUE(&ifp->if_snd, m_head); 1334 if (m_head == NULL) 1335 break; 1336 1337 /* Pick a descriptor off the free list. */ 1338 cur_tx = sc->vr_cdata.vr_tx_free; 1339 sc->vr_cdata.vr_tx_free = cur_tx->vr_nextdesc; 1340 1341 /* Pack the data into the descriptor. */ 1342 vr_encap(sc, cur_tx, m_head); 1343 1344 if (cur_tx != start_tx) 1345 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1346 1347 /* 1348 * If there's a BPF listener, bounce a copy of this frame 1349 * to him. 1350 */ 1351 if (ifp->if_bpf) 1352 bpf_mtap(ifp, cur_tx->vr_mbuf); 1353 1354 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1355 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO); 1356 } 1357 1358 /* 1359 * If there are no frames queued, bail. 1360 */ 1361 if (cur_tx == NULL) 1362 return; 1363 1364 sc->vr_cdata.vr_tx_tail = cur_tx; 1365 1366 if (sc->vr_cdata.vr_tx_head == NULL) 1367 sc->vr_cdata.vr_tx_head = start_tx; 1368 1369 /* 1370 * Set a timeout in case the chip goes out to lunch. 1371 */ 1372 ifp->if_timer = 5; 1373 1374 return; 1375 } 1376 1377 static void vr_init(xsc) 1378 void *xsc; 1379 { 1380 struct vr_softc *sc = xsc; 1381 struct ifnet *ifp = &sc->arpcom.ac_if; 1382 struct mii_data *mii; 1383 int s; 1384 1385 s = splimp(); 1386 1387 mii = device_get_softc(sc->vr_miibus); 1388 1389 /* 1390 * Cancel pending I/O and free all RX/TX buffers. 1391 */ 1392 vr_stop(sc); 1393 vr_reset(sc); 1394 1395 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1396 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_STORENFWD); 1397 1398 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1399 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1400 1401 /* Init circular RX list. */ 1402 if (vr_list_rx_init(sc) == ENOBUFS) { 1403 printf("vr%d: initialization failed: no " 1404 "memory for rx buffers\n", sc->vr_unit); 1405 vr_stop(sc); 1406 (void)splx(s); 1407 return; 1408 } 1409 1410 /* 1411 * Init tx descriptors. 1412 */ 1413 vr_list_tx_init(sc); 1414 1415 /* If we want promiscuous mode, set the allframes bit. */ 1416 if (ifp->if_flags & IFF_PROMISC) 1417 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1418 else 1419 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1420 1421 /* Set capture broadcast bit to capture broadcast frames. */ 1422 if (ifp->if_flags & IFF_BROADCAST) 1423 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1424 else 1425 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1426 1427 /* 1428 * Program the multicast filter, if necessary. 1429 */ 1430 vr_setmulti(sc); 1431 1432 /* 1433 * Load the address of the RX list. 1434 */ 1435 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1436 1437 /* Enable receiver and transmitter. */ 1438 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1439 VR_CMD_TX_ON|VR_CMD_RX_ON| 1440 VR_CMD_RX_GO); 1441 1442 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1443 1444 /* 1445 * Enable interrupts. 1446 */ 1447 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1448 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1449 1450 mii_mediachg(mii); 1451 1452 ifp->if_flags |= IFF_RUNNING; 1453 ifp->if_flags &= ~IFF_OACTIVE; 1454 1455 (void)splx(s); 1456 1457 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1458 1459 return; 1460 } 1461 1462 /* 1463 * Set media options. 1464 */ 1465 static int vr_ifmedia_upd(ifp) 1466 struct ifnet *ifp; 1467 { 1468 struct vr_softc *sc; 1469 1470 sc = ifp->if_softc; 1471 1472 if (ifp->if_flags & IFF_UP) 1473 vr_init(sc); 1474 1475 return(0); 1476 } 1477 1478 /* 1479 * Report current media status. 1480 */ 1481 static void vr_ifmedia_sts(ifp, ifmr) 1482 struct ifnet *ifp; 1483 struct ifmediareq *ifmr; 1484 { 1485 struct vr_softc *sc; 1486 struct mii_data *mii; 1487 1488 sc = ifp->if_softc; 1489 mii = device_get_softc(sc->vr_miibus); 1490 mii_pollstat(mii); 1491 ifmr->ifm_active = mii->mii_media_active; 1492 ifmr->ifm_status = mii->mii_media_status; 1493 1494 return; 1495 } 1496 1497 static int vr_ioctl(ifp, command, data) 1498 struct ifnet *ifp; 1499 u_long command; 1500 caddr_t data; 1501 { 1502 struct vr_softc *sc = ifp->if_softc; 1503 struct ifreq *ifr = (struct ifreq *) data; 1504 struct mii_data *mii; 1505 int s, error = 0; 1506 1507 s = splimp(); 1508 1509 switch(command) { 1510 case SIOCSIFADDR: 1511 case SIOCGIFADDR: 1512 case SIOCSIFMTU: 1513 error = ether_ioctl(ifp, command, data); 1514 break; 1515 case SIOCSIFFLAGS: 1516 if (ifp->if_flags & IFF_UP) { 1517 vr_init(sc); 1518 } else { 1519 if (ifp->if_flags & IFF_RUNNING) 1520 vr_stop(sc); 1521 } 1522 error = 0; 1523 break; 1524 case SIOCADDMULTI: 1525 case SIOCDELMULTI: 1526 vr_setmulti(sc); 1527 error = 0; 1528 break; 1529 case SIOCGIFMEDIA: 1530 case SIOCSIFMEDIA: 1531 mii = device_get_softc(sc->vr_miibus); 1532 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1533 break; 1534 default: 1535 error = EINVAL; 1536 break; 1537 } 1538 1539 (void)splx(s); 1540 1541 return(error); 1542 } 1543 1544 static void vr_watchdog(ifp) 1545 struct ifnet *ifp; 1546 { 1547 struct vr_softc *sc; 1548 1549 sc = ifp->if_softc; 1550 1551 ifp->if_oerrors++; 1552 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1553 1554 vr_stop(sc); 1555 vr_reset(sc); 1556 vr_init(sc); 1557 1558 if (ifp->if_snd.ifq_head != NULL) 1559 vr_start(ifp); 1560 1561 return; 1562 } 1563 1564 /* 1565 * Stop the adapter and free any mbufs allocated to the 1566 * RX and TX lists. 1567 */ 1568 static void vr_stop(sc) 1569 struct vr_softc *sc; 1570 { 1571 register int i; 1572 struct ifnet *ifp; 1573 1574 ifp = &sc->arpcom.ac_if; 1575 ifp->if_timer = 0; 1576 1577 untimeout(vr_tick, sc, sc->vr_stat_ch); 1578 1579 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1580 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1581 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1582 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1583 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1584 1585 /* 1586 * Free data in the RX lists. 1587 */ 1588 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1589 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1590 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1591 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1592 } 1593 } 1594 bzero((char *)&sc->vr_ldata->vr_rx_list, 1595 sizeof(sc->vr_ldata->vr_rx_list)); 1596 1597 /* 1598 * Free the TX list buffers. 1599 */ 1600 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1601 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1602 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1603 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1604 } 1605 } 1606 1607 bzero((char *)&sc->vr_ldata->vr_tx_list, 1608 sizeof(sc->vr_ldata->vr_tx_list)); 1609 1610 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1611 1612 return; 1613 } 1614 1615 /* 1616 * Stop all chip I/O so that the kernel's probe routines don't 1617 * get confused by errant DMAs when rebooting. 1618 */ 1619 static void vr_shutdown(dev) 1620 device_t dev; 1621 { 1622 struct vr_softc *sc; 1623 1624 sc = device_get_softc(dev); 1625 1626 vr_stop(sc); 1627 1628 return; 1629 } 1630