1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * Some Rhine chips has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #ifdef HAVE_KERNEL_OPTION_HEADERS 64 #include "opt_device_polling.h" 65 #endif 66 67 #include <sys/param.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <sys/endian.h> 71 #include <sys/kernel.h> 72 #include <sys/malloc.h> 73 #include <sys/mbuf.h> 74 #include <sys/module.h> 75 #include <sys/rman.h> 76 #include <sys/socket.h> 77 #include <sys/sockio.h> 78 #include <sys/sysctl.h> 79 #include <sys/taskqueue.h> 80 81 #include <net/bpf.h> 82 #include <net/if.h> 83 #include <net/if_var.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 #include <net/if_types.h> 88 #include <net/if_vlan_var.h> 89 90 #include <dev/mii/mii.h> 91 #include <dev/mii/miivar.h> 92 93 #include <dev/pci/pcireg.h> 94 #include <dev/pci/pcivar.h> 95 96 #include <machine/bus.h> 97 98 #include <dev/vr/if_vrreg.h> 99 100 /* "device miibus" required. See GENERIC if you get errors here. */ 101 #include "miibus_if.h" 102 103 MODULE_DEPEND(vr, pci, 1, 1, 1); 104 MODULE_DEPEND(vr, ether, 1, 1, 1); 105 MODULE_DEPEND(vr, miibus, 1, 1, 1); 106 107 /* Define to show Rx/Tx error status. */ 108 #undef VR_SHOW_ERRORS 109 #define VR_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 110 111 /* 112 * Various supported device vendors/types, their names & quirks. 113 */ 114 #define VR_Q_NEEDALIGN (1<<0) 115 #define VR_Q_CSUM (1<<1) 116 #define VR_Q_CAM (1<<2) 117 118 static const struct vr_type { 119 u_int16_t vr_vid; 120 u_int16_t vr_did; 121 int vr_quirks; 122 const char *vr_name; 123 } vr_devs[] = { 124 { VIA_VENDORID, VIA_DEVICEID_RHINE, 125 VR_Q_NEEDALIGN, 126 "VIA VT3043 Rhine I 10/100BaseTX" }, 127 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 128 VR_Q_NEEDALIGN, 129 "VIA VT86C100A Rhine II 10/100BaseTX" }, 130 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 131 0, 132 "VIA VT6102 Rhine II 10/100BaseTX" }, 133 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 134 0, 135 "VIA VT6105 Rhine III 10/100BaseTX" }, 136 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 137 VR_Q_CSUM, 138 "VIA VT6105M Rhine III 10/100BaseTX" }, 139 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 140 VR_Q_NEEDALIGN, 141 "Delta Electronics Rhine II 10/100BaseTX" }, 142 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 143 VR_Q_NEEDALIGN, 144 "Addtron Technology Rhine II 10/100BaseTX" }, 145 { 0, 0, 0, NULL } 146 }; 147 148 static int vr_probe(device_t); 149 static int vr_attach(device_t); 150 static int vr_detach(device_t); 151 static int vr_shutdown(device_t); 152 static int vr_suspend(device_t); 153 static int vr_resume(device_t); 154 155 static void vr_dmamap_cb(void *, bus_dma_segment_t *, int, int); 156 static int vr_dma_alloc(struct vr_softc *); 157 static void vr_dma_free(struct vr_softc *); 158 static __inline void vr_discard_rxbuf(struct vr_rxdesc *); 159 static int vr_newbuf(struct vr_softc *, int); 160 161 #ifndef __NO_STRICT_ALIGNMENT 162 static __inline void vr_fixup_rx(struct mbuf *); 163 #endif 164 static int vr_rxeof(struct vr_softc *); 165 static void vr_txeof(struct vr_softc *); 166 static void vr_tick(void *); 167 static int vr_error(struct vr_softc *, uint16_t); 168 static void vr_tx_underrun(struct vr_softc *); 169 static int vr_intr(void *); 170 static void vr_int_task(void *, int); 171 static void vr_start(struct ifnet *); 172 static void vr_start_locked(struct ifnet *); 173 static int vr_encap(struct vr_softc *, struct mbuf **); 174 static int vr_ioctl(struct ifnet *, u_long, caddr_t); 175 static void vr_init(void *); 176 static void vr_init_locked(struct vr_softc *); 177 static void vr_tx_start(struct vr_softc *); 178 static void vr_rx_start(struct vr_softc *); 179 static int vr_tx_stop(struct vr_softc *); 180 static int vr_rx_stop(struct vr_softc *); 181 static void vr_stop(struct vr_softc *); 182 static void vr_watchdog(struct vr_softc *); 183 static int vr_ifmedia_upd(struct ifnet *); 184 static void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *); 185 186 static int vr_miibus_readreg(device_t, int, int); 187 static int vr_miibus_writereg(device_t, int, int, int); 188 static void vr_miibus_statchg(device_t); 189 190 static void vr_cam_mask(struct vr_softc *, uint32_t, int); 191 static int vr_cam_data(struct vr_softc *, int, int, uint8_t *); 192 static void vr_set_filter(struct vr_softc *); 193 static void vr_reset(const struct vr_softc *); 194 static int vr_tx_ring_init(struct vr_softc *); 195 static int vr_rx_ring_init(struct vr_softc *); 196 static void vr_setwol(struct vr_softc *); 197 static void vr_clrwol(struct vr_softc *); 198 static int vr_sysctl_stats(SYSCTL_HANDLER_ARGS); 199 200 static const struct vr_tx_threshold_table { 201 int tx_cfg; 202 int bcr_cfg; 203 int value; 204 } vr_tx_threshold_tables[] = { 205 { VR_TXTHRESH_64BYTES, VR_BCR1_TXTHRESH64BYTES, 64 }, 206 { VR_TXTHRESH_128BYTES, VR_BCR1_TXTHRESH128BYTES, 128 }, 207 { VR_TXTHRESH_256BYTES, VR_BCR1_TXTHRESH256BYTES, 256 }, 208 { VR_TXTHRESH_512BYTES, VR_BCR1_TXTHRESH512BYTES, 512 }, 209 { VR_TXTHRESH_1024BYTES, VR_BCR1_TXTHRESH1024BYTES, 1024 }, 210 { VR_TXTHRESH_STORENFWD, VR_BCR1_TXTHRESHSTORENFWD, 2048 } 211 }; 212 213 static device_method_t vr_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_probe, vr_probe), 216 DEVMETHOD(device_attach, vr_attach), 217 DEVMETHOD(device_detach, vr_detach), 218 DEVMETHOD(device_shutdown, vr_shutdown), 219 DEVMETHOD(device_suspend, vr_suspend), 220 DEVMETHOD(device_resume, vr_resume), 221 222 /* MII interface */ 223 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 224 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 225 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 226 227 DEVMETHOD_END 228 }; 229 230 static driver_t vr_driver = { 231 "vr", 232 vr_methods, 233 sizeof(struct vr_softc) 234 }; 235 236 static devclass_t vr_devclass; 237 238 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 239 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 240 241 static int 242 vr_miibus_readreg(device_t dev, int phy, int reg) 243 { 244 struct vr_softc *sc; 245 int i; 246 247 sc = device_get_softc(dev); 248 249 /* Set the register address. */ 250 CSR_WRITE_1(sc, VR_MIIADDR, reg); 251 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 252 253 for (i = 0; i < VR_MII_TIMEOUT; i++) { 254 DELAY(1); 255 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 256 break; 257 } 258 if (i == VR_MII_TIMEOUT) 259 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg); 260 261 return (CSR_READ_2(sc, VR_MIIDATA)); 262 } 263 264 static int 265 vr_miibus_writereg(device_t dev, int phy, int reg, int data) 266 { 267 struct vr_softc *sc; 268 int i; 269 270 sc = device_get_softc(dev); 271 272 /* Set the register address and data to write. */ 273 CSR_WRITE_1(sc, VR_MIIADDR, reg); 274 CSR_WRITE_2(sc, VR_MIIDATA, data); 275 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 276 277 for (i = 0; i < VR_MII_TIMEOUT; i++) { 278 DELAY(1); 279 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 280 break; 281 } 282 if (i == VR_MII_TIMEOUT) 283 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy, 284 reg); 285 286 return (0); 287 } 288 289 /* 290 * In order to fiddle with the 291 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 292 * first have to put the transmit and/or receive logic in the idle state. 293 */ 294 static void 295 vr_miibus_statchg(device_t dev) 296 { 297 struct vr_softc *sc; 298 struct mii_data *mii; 299 struct ifnet *ifp; 300 int lfdx, mfdx; 301 uint8_t cr0, cr1, fc; 302 303 sc = device_get_softc(dev); 304 mii = device_get_softc(sc->vr_miibus); 305 ifp = sc->vr_ifp; 306 if (mii == NULL || ifp == NULL || 307 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 308 return; 309 310 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 311 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 312 (IFM_ACTIVE | IFM_AVALID)) { 313 switch (IFM_SUBTYPE(mii->mii_media_active)) { 314 case IFM_10_T: 315 case IFM_100_TX: 316 sc->vr_flags |= VR_F_LINK; 317 break; 318 default: 319 break; 320 } 321 } 322 323 if ((sc->vr_flags & VR_F_LINK) != 0) { 324 cr0 = CSR_READ_1(sc, VR_CR0); 325 cr1 = CSR_READ_1(sc, VR_CR1); 326 mfdx = (cr1 & VR_CR1_FULLDUPLEX) != 0; 327 lfdx = (IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0; 328 if (mfdx != lfdx) { 329 if ((cr0 & (VR_CR0_TX_ON | VR_CR0_RX_ON)) != 0) { 330 if (vr_tx_stop(sc) != 0 || 331 vr_rx_stop(sc) != 0) { 332 device_printf(sc->vr_dev, 333 "%s: Tx/Rx shutdown error -- " 334 "resetting\n", __func__); 335 sc->vr_flags |= VR_F_RESTART; 336 VR_UNLOCK(sc); 337 return; 338 } 339 } 340 if (lfdx) 341 cr1 |= VR_CR1_FULLDUPLEX; 342 else 343 cr1 &= ~VR_CR1_FULLDUPLEX; 344 CSR_WRITE_1(sc, VR_CR1, cr1); 345 } 346 fc = 0; 347 /* Configure flow-control. */ 348 if (sc->vr_revid >= REV_ID_VT6105_A0) { 349 fc = CSR_READ_1(sc, VR_FLOWCR1); 350 fc &= ~(VR_FLOWCR1_TXPAUSE | VR_FLOWCR1_RXPAUSE); 351 if ((IFM_OPTIONS(mii->mii_media_active) & 352 IFM_ETH_RXPAUSE) != 0) 353 fc |= VR_FLOWCR1_RXPAUSE; 354 if ((IFM_OPTIONS(mii->mii_media_active) & 355 IFM_ETH_TXPAUSE) != 0) { 356 fc |= VR_FLOWCR1_TXPAUSE; 357 sc->vr_flags |= VR_F_TXPAUSE; 358 } 359 CSR_WRITE_1(sc, VR_FLOWCR1, fc); 360 } else if (sc->vr_revid >= REV_ID_VT6102_A) { 361 /* No Tx puase capability available for Rhine II. */ 362 fc = CSR_READ_1(sc, VR_MISC_CR0); 363 fc &= ~VR_MISCCR0_RXPAUSE; 364 if ((IFM_OPTIONS(mii->mii_media_active) & 365 IFM_ETH_RXPAUSE) != 0) 366 fc |= VR_MISCCR0_RXPAUSE; 367 CSR_WRITE_1(sc, VR_MISC_CR0, fc); 368 } 369 vr_rx_start(sc); 370 vr_tx_start(sc); 371 } else { 372 if (vr_tx_stop(sc) != 0 || vr_rx_stop(sc) != 0) { 373 device_printf(sc->vr_dev, 374 "%s: Tx/Rx shutdown error -- resetting\n", 375 __func__); 376 sc->vr_flags |= VR_F_RESTART; 377 } 378 } 379 } 380 381 382 static void 383 vr_cam_mask(struct vr_softc *sc, uint32_t mask, int type) 384 { 385 386 if (type == VR_MCAST_CAM) 387 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 388 else 389 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 390 CSR_WRITE_4(sc, VR_CAMMASK, mask); 391 CSR_WRITE_1(sc, VR_CAMCTL, 0); 392 } 393 394 static int 395 vr_cam_data(struct vr_softc *sc, int type, int idx, uint8_t *mac) 396 { 397 int i; 398 399 if (type == VR_MCAST_CAM) { 400 if (idx < 0 || idx >= VR_CAM_MCAST_CNT || mac == NULL) 401 return (EINVAL); 402 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); 403 } else 404 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); 405 406 /* Set CAM entry address. */ 407 CSR_WRITE_1(sc, VR_CAMADDR, idx); 408 /* Set CAM entry data. */ 409 if (type == VR_MCAST_CAM) { 410 for (i = 0; i < ETHER_ADDR_LEN; i++) 411 CSR_WRITE_1(sc, VR_MCAM0 + i, mac[i]); 412 } else { 413 CSR_WRITE_1(sc, VR_VCAM0, mac[0]); 414 CSR_WRITE_1(sc, VR_VCAM1, mac[1]); 415 } 416 DELAY(10); 417 /* Write CAM and wait for self-clear of VR_CAMCTL_WRITE bit. */ 418 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_WRITE); 419 for (i = 0; i < VR_TIMEOUT; i++) { 420 DELAY(1); 421 if ((CSR_READ_1(sc, VR_CAMCTL) & VR_CAMCTL_WRITE) == 0) 422 break; 423 } 424 425 if (i == VR_TIMEOUT) 426 device_printf(sc->vr_dev, "%s: setting CAM filter timeout!\n", 427 __func__); 428 CSR_WRITE_1(sc, VR_CAMCTL, 0); 429 430 return (i == VR_TIMEOUT ? ETIMEDOUT : 0); 431 } 432 433 /* 434 * Program the 64-bit multicast hash filter. 435 */ 436 static void 437 vr_set_filter(struct vr_softc *sc) 438 { 439 struct ifnet *ifp; 440 int h; 441 uint32_t hashes[2] = { 0, 0 }; 442 struct ifmultiaddr *ifma; 443 uint8_t rxfilt; 444 int error, mcnt; 445 uint32_t cam_mask; 446 447 VR_LOCK_ASSERT(sc); 448 449 ifp = sc->vr_ifp; 450 rxfilt = CSR_READ_1(sc, VR_RXCFG); 451 rxfilt &= ~(VR_RXCFG_RX_PROMISC | VR_RXCFG_RX_BROAD | 452 VR_RXCFG_RX_MULTI); 453 if (ifp->if_flags & IFF_BROADCAST) 454 rxfilt |= VR_RXCFG_RX_BROAD; 455 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 456 rxfilt |= VR_RXCFG_RX_MULTI; 457 if (ifp->if_flags & IFF_PROMISC) 458 rxfilt |= VR_RXCFG_RX_PROMISC; 459 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 460 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 461 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 462 return; 463 } 464 465 /* Now program new ones. */ 466 error = 0; 467 mcnt = 0; 468 if_maddr_rlock(ifp); 469 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 470 /* 471 * For hardwares that have CAM capability, use 472 * 32 entries multicast perfect filter. 473 */ 474 cam_mask = 0; 475 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 476 if (ifma->ifma_addr->sa_family != AF_LINK) 477 continue; 478 error = vr_cam_data(sc, VR_MCAST_CAM, mcnt, 479 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 480 if (error != 0) { 481 cam_mask = 0; 482 break; 483 } 484 cam_mask |= 1 << mcnt; 485 mcnt++; 486 } 487 vr_cam_mask(sc, VR_MCAST_CAM, cam_mask); 488 } 489 490 if ((sc->vr_quirks & VR_Q_CAM) == 0 || error != 0) { 491 /* 492 * If there are too many multicast addresses or 493 * setting multicast CAM filter failed, use hash 494 * table based filtering. 495 */ 496 mcnt = 0; 497 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 498 if (ifma->ifma_addr->sa_family != AF_LINK) 499 continue; 500 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 501 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 502 if (h < 32) 503 hashes[0] |= (1 << h); 504 else 505 hashes[1] |= (1 << (h - 32)); 506 mcnt++; 507 } 508 } 509 if_maddr_runlock(ifp); 510 511 if (mcnt > 0) 512 rxfilt |= VR_RXCFG_RX_MULTI; 513 514 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 515 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 516 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 517 } 518 519 static void 520 vr_reset(const struct vr_softc *sc) 521 { 522 int i; 523 524 /*VR_LOCK_ASSERT(sc);*/ /* XXX: Called during attach w/o lock. */ 525 526 CSR_WRITE_1(sc, VR_CR1, VR_CR1_RESET); 527 if (sc->vr_revid < REV_ID_VT6102_A) { 528 /* VT86C100A needs more delay after reset. */ 529 DELAY(100); 530 } 531 for (i = 0; i < VR_TIMEOUT; i++) { 532 DELAY(10); 533 if (!(CSR_READ_1(sc, VR_CR1) & VR_CR1_RESET)) 534 break; 535 } 536 if (i == VR_TIMEOUT) { 537 if (sc->vr_revid < REV_ID_VT6102_A) 538 device_printf(sc->vr_dev, "reset never completed!\n"); 539 else { 540 /* Use newer force reset command. */ 541 device_printf(sc->vr_dev, 542 "Using force reset command.\n"); 543 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 544 /* 545 * Wait a little while for the chip to get its brains 546 * in order. 547 */ 548 DELAY(2000); 549 } 550 } 551 552 } 553 554 /* 555 * Probe for a VIA Rhine chip. Check the PCI vendor and device 556 * IDs against our list and return a match or NULL 557 */ 558 static const struct vr_type * 559 vr_match(device_t dev) 560 { 561 const struct vr_type *t = vr_devs; 562 563 for (t = vr_devs; t->vr_name != NULL; t++) 564 if ((pci_get_vendor(dev) == t->vr_vid) && 565 (pci_get_device(dev) == t->vr_did)) 566 return (t); 567 return (NULL); 568 } 569 570 /* 571 * Probe for a VIA Rhine chip. Check the PCI vendor and device 572 * IDs against our list and return a device name if we find a match. 573 */ 574 static int 575 vr_probe(device_t dev) 576 { 577 const struct vr_type *t; 578 579 t = vr_match(dev); 580 if (t != NULL) { 581 device_set_desc(dev, t->vr_name); 582 return (BUS_PROBE_DEFAULT); 583 } 584 return (ENXIO); 585 } 586 587 /* 588 * Attach the interface. Allocate softc structures, do ifmedia 589 * setup and ethernet/BPF attach. 590 */ 591 static int 592 vr_attach(device_t dev) 593 { 594 struct vr_softc *sc; 595 struct ifnet *ifp; 596 const struct vr_type *t; 597 uint8_t eaddr[ETHER_ADDR_LEN]; 598 int error, rid; 599 int i, phy, pmc; 600 601 sc = device_get_softc(dev); 602 sc->vr_dev = dev; 603 t = vr_match(dev); 604 KASSERT(t != NULL, ("Lost if_vr device match")); 605 sc->vr_quirks = t->vr_quirks; 606 device_printf(dev, "Quirks: 0x%x\n", sc->vr_quirks); 607 608 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 609 MTX_DEF); 610 callout_init_mtx(&sc->vr_stat_callout, &sc->vr_mtx, 0); 611 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 612 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 613 OID_AUTO, "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 614 vr_sysctl_stats, "I", "Statistics"); 615 616 error = 0; 617 618 /* 619 * Map control/status registers. 620 */ 621 pci_enable_busmaster(dev); 622 sc->vr_revid = pci_get_revid(dev); 623 device_printf(dev, "Revision: 0x%x\n", sc->vr_revid); 624 625 sc->vr_res_id = PCIR_BAR(0); 626 sc->vr_res_type = SYS_RES_IOPORT; 627 sc->vr_res = bus_alloc_resource_any(dev, sc->vr_res_type, 628 &sc->vr_res_id, RF_ACTIVE); 629 if (sc->vr_res == NULL) { 630 device_printf(dev, "couldn't map ports\n"); 631 error = ENXIO; 632 goto fail; 633 } 634 635 /* Allocate interrupt. */ 636 rid = 0; 637 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 638 RF_SHAREABLE | RF_ACTIVE); 639 640 if (sc->vr_irq == NULL) { 641 device_printf(dev, "couldn't map interrupt\n"); 642 error = ENXIO; 643 goto fail; 644 } 645 646 /* Allocate ifnet structure. */ 647 ifp = sc->vr_ifp = if_alloc(IFT_ETHER); 648 if (ifp == NULL) { 649 device_printf(dev, "couldn't allocate ifnet structure\n"); 650 error = ENOSPC; 651 goto fail; 652 } 653 ifp->if_softc = sc; 654 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 656 ifp->if_ioctl = vr_ioctl; 657 ifp->if_start = vr_start; 658 ifp->if_init = vr_init; 659 IFQ_SET_MAXLEN(&ifp->if_snd, VR_TX_RING_CNT - 1); 660 ifp->if_snd.ifq_maxlen = VR_TX_RING_CNT - 1; 661 IFQ_SET_READY(&ifp->if_snd); 662 663 TASK_INIT(&sc->vr_inttask, 0, vr_int_task, sc); 664 665 /* Configure Tx FIFO threshold. */ 666 sc->vr_txthresh = VR_TXTHRESH_MIN; 667 if (sc->vr_revid < REV_ID_VT6105_A0) { 668 /* 669 * Use store and forward mode for Rhine I/II. 670 * Otherwise they produce a lot of Tx underruns and 671 * it would take a while to get working FIFO threshold 672 * value. 673 */ 674 sc->vr_txthresh = VR_TXTHRESH_MAX; 675 } 676 if ((sc->vr_quirks & VR_Q_CSUM) != 0) { 677 ifp->if_hwassist = VR_CSUM_FEATURES; 678 ifp->if_capabilities |= IFCAP_HWCSUM; 679 /* 680 * To update checksum field the hardware may need to 681 * store entire frames into FIFO before transmitting. 682 */ 683 sc->vr_txthresh = VR_TXTHRESH_MAX; 684 } 685 686 if (sc->vr_revid >= REV_ID_VT6102_A && 687 pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 688 ifp->if_capabilities |= IFCAP_WOL_UCAST | IFCAP_WOL_MAGIC; 689 690 /* Rhine supports oversized VLAN frame. */ 691 ifp->if_capabilities |= IFCAP_VLAN_MTU; 692 ifp->if_capenable = ifp->if_capabilities; 693 #ifdef DEVICE_POLLING 694 ifp->if_capabilities |= IFCAP_POLLING; 695 #endif 696 697 /* 698 * Windows may put the chip in suspend mode when it 699 * shuts down. Be sure to kick it in the head to wake it 700 * up again. 701 */ 702 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) 703 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 704 705 /* 706 * Get station address. The way the Rhine chips work, 707 * you're not allowed to directly access the EEPROM once 708 * they've been programmed a special way. Consequently, 709 * we need to read the node address from the PAR0 and PAR1 710 * registers. 711 * Reloading EEPROM also overwrites VR_CFGA, VR_CFGB, 712 * VR_CFGC and VR_CFGD such that memory mapped IO configured 713 * by driver is reset to default state. 714 */ 715 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 716 for (i = VR_TIMEOUT; i > 0; i--) { 717 DELAY(1); 718 if ((CSR_READ_1(sc, VR_EECSR) & VR_EECSR_LOAD) == 0) 719 break; 720 } 721 if (i == 0) 722 device_printf(dev, "Reloading EEPROM timeout!\n"); 723 for (i = 0; i < ETHER_ADDR_LEN; i++) 724 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 725 726 /* Reset the adapter. */ 727 vr_reset(sc); 728 /* Ack intr & disable further interrupts. */ 729 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 730 CSR_WRITE_2(sc, VR_IMR, 0); 731 if (sc->vr_revid >= REV_ID_VT6102_A) 732 CSR_WRITE_2(sc, VR_MII_IMR, 0); 733 734 if (sc->vr_revid < REV_ID_VT6102_A) { 735 pci_write_config(dev, VR_PCI_MODE2, 736 pci_read_config(dev, VR_PCI_MODE2, 1) | 737 VR_MODE2_MODE10T, 1); 738 } else { 739 /* Report error instead of retrying forever. */ 740 pci_write_config(dev, VR_PCI_MODE2, 741 pci_read_config(dev, VR_PCI_MODE2, 1) | 742 VR_MODE2_PCEROPT, 1); 743 /* Detect MII coding error. */ 744 pci_write_config(dev, VR_PCI_MODE3, 745 pci_read_config(dev, VR_PCI_MODE3, 1) | 746 VR_MODE3_MIION, 1); 747 if (sc->vr_revid >= REV_ID_VT6105_LOM && 748 sc->vr_revid < REV_ID_VT6105M_A0) 749 pci_write_config(dev, VR_PCI_MODE2, 750 pci_read_config(dev, VR_PCI_MODE2, 1) | 751 VR_MODE2_MODE10T, 1); 752 /* Enable Memory-Read-Multiple. */ 753 if (sc->vr_revid >= REV_ID_VT6107_A1 && 754 sc->vr_revid < REV_ID_VT6105M_A0) 755 pci_write_config(dev, VR_PCI_MODE2, 756 pci_read_config(dev, VR_PCI_MODE2, 1) | 757 VR_MODE2_MRDPL, 1); 758 } 759 /* Disable MII AUTOPOLL. */ 760 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 761 762 if (vr_dma_alloc(sc) != 0) { 763 error = ENXIO; 764 goto fail; 765 } 766 767 /* Do MII setup. */ 768 if (sc->vr_revid >= REV_ID_VT6105_A0) 769 phy = 1; 770 else 771 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK; 772 error = mii_attach(dev, &sc->vr_miibus, ifp, vr_ifmedia_upd, 773 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 774 sc->vr_revid >= REV_ID_VT6102_A ? MIIF_DOPAUSE : 0); 775 if (error != 0) { 776 device_printf(dev, "attaching PHYs failed\n"); 777 goto fail; 778 } 779 780 /* Call MI attach routine. */ 781 ether_ifattach(ifp, eaddr); 782 /* 783 * Tell the upper layer(s) we support long frames. 784 * Must appear after the call to ether_ifattach() because 785 * ether_ifattach() sets ifi_hdrlen to the default value. 786 */ 787 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 788 789 /* Hook interrupt last to avoid having to lock softc. */ 790 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 791 vr_intr, NULL, sc, &sc->vr_intrhand); 792 793 if (error) { 794 device_printf(dev, "couldn't set up irq\n"); 795 ether_ifdetach(ifp); 796 goto fail; 797 } 798 799 fail: 800 if (error) 801 vr_detach(dev); 802 803 return (error); 804 } 805 806 /* 807 * Shutdown hardware and free up resources. This can be called any 808 * time after the mutex has been initialized. It is called in both 809 * the error case in attach and the normal detach case so it needs 810 * to be careful about only freeing resources that have actually been 811 * allocated. 812 */ 813 static int 814 vr_detach(device_t dev) 815 { 816 struct vr_softc *sc = device_get_softc(dev); 817 struct ifnet *ifp = sc->vr_ifp; 818 819 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 820 821 #ifdef DEVICE_POLLING 822 if (ifp != NULL && ifp->if_capenable & IFCAP_POLLING) 823 ether_poll_deregister(ifp); 824 #endif 825 826 /* These should only be active if attach succeeded. */ 827 if (device_is_attached(dev)) { 828 VR_LOCK(sc); 829 sc->vr_flags |= VR_F_DETACHED; 830 vr_stop(sc); 831 VR_UNLOCK(sc); 832 callout_drain(&sc->vr_stat_callout); 833 taskqueue_drain(taskqueue_fast, &sc->vr_inttask); 834 ether_ifdetach(ifp); 835 } 836 if (sc->vr_miibus) 837 device_delete_child(dev, sc->vr_miibus); 838 bus_generic_detach(dev); 839 840 if (sc->vr_intrhand) 841 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 842 if (sc->vr_irq) 843 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 844 if (sc->vr_res) 845 bus_release_resource(dev, sc->vr_res_type, sc->vr_res_id, 846 sc->vr_res); 847 848 if (ifp) 849 if_free(ifp); 850 851 vr_dma_free(sc); 852 853 mtx_destroy(&sc->vr_mtx); 854 855 return (0); 856 } 857 858 struct vr_dmamap_arg { 859 bus_addr_t vr_busaddr; 860 }; 861 862 static void 863 vr_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 864 { 865 struct vr_dmamap_arg *ctx; 866 867 if (error != 0) 868 return; 869 ctx = arg; 870 ctx->vr_busaddr = segs[0].ds_addr; 871 } 872 873 static int 874 vr_dma_alloc(struct vr_softc *sc) 875 { 876 struct vr_dmamap_arg ctx; 877 struct vr_txdesc *txd; 878 struct vr_rxdesc *rxd; 879 bus_size_t tx_alignment; 880 int error, i; 881 882 /* Create parent DMA tag. */ 883 error = bus_dma_tag_create( 884 bus_get_dma_tag(sc->vr_dev), /* parent */ 885 1, 0, /* alignment, boundary */ 886 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 887 BUS_SPACE_MAXADDR, /* highaddr */ 888 NULL, NULL, /* filter, filterarg */ 889 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 890 0, /* nsegments */ 891 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 892 0, /* flags */ 893 NULL, NULL, /* lockfunc, lockarg */ 894 &sc->vr_cdata.vr_parent_tag); 895 if (error != 0) { 896 device_printf(sc->vr_dev, "failed to create parent DMA tag\n"); 897 goto fail; 898 } 899 /* Create tag for Tx ring. */ 900 error = bus_dma_tag_create( 901 sc->vr_cdata.vr_parent_tag, /* parent */ 902 VR_RING_ALIGN, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 VR_TX_RING_SIZE, /* maxsize */ 907 1, /* nsegments */ 908 VR_TX_RING_SIZE, /* maxsegsize */ 909 0, /* flags */ 910 NULL, NULL, /* lockfunc, lockarg */ 911 &sc->vr_cdata.vr_tx_ring_tag); 912 if (error != 0) { 913 device_printf(sc->vr_dev, "failed to create Tx ring DMA tag\n"); 914 goto fail; 915 } 916 917 /* Create tag for Rx ring. */ 918 error = bus_dma_tag_create( 919 sc->vr_cdata.vr_parent_tag, /* parent */ 920 VR_RING_ALIGN, 0, /* alignment, boundary */ 921 BUS_SPACE_MAXADDR, /* lowaddr */ 922 BUS_SPACE_MAXADDR, /* highaddr */ 923 NULL, NULL, /* filter, filterarg */ 924 VR_RX_RING_SIZE, /* maxsize */ 925 1, /* nsegments */ 926 VR_RX_RING_SIZE, /* maxsegsize */ 927 0, /* flags */ 928 NULL, NULL, /* lockfunc, lockarg */ 929 &sc->vr_cdata.vr_rx_ring_tag); 930 if (error != 0) { 931 device_printf(sc->vr_dev, "failed to create Rx ring DMA tag\n"); 932 goto fail; 933 } 934 935 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) 936 tx_alignment = sizeof(uint32_t); 937 else 938 tx_alignment = 1; 939 /* Create tag for Tx buffers. */ 940 error = bus_dma_tag_create( 941 sc->vr_cdata.vr_parent_tag, /* parent */ 942 tx_alignment, 0, /* alignment, boundary */ 943 BUS_SPACE_MAXADDR, /* lowaddr */ 944 BUS_SPACE_MAXADDR, /* highaddr */ 945 NULL, NULL, /* filter, filterarg */ 946 MCLBYTES * VR_MAXFRAGS, /* maxsize */ 947 VR_MAXFRAGS, /* nsegments */ 948 MCLBYTES, /* maxsegsize */ 949 0, /* flags */ 950 NULL, NULL, /* lockfunc, lockarg */ 951 &sc->vr_cdata.vr_tx_tag); 952 if (error != 0) { 953 device_printf(sc->vr_dev, "failed to create Tx DMA tag\n"); 954 goto fail; 955 } 956 957 /* Create tag for Rx buffers. */ 958 error = bus_dma_tag_create( 959 sc->vr_cdata.vr_parent_tag, /* parent */ 960 VR_RX_ALIGN, 0, /* alignment, boundary */ 961 BUS_SPACE_MAXADDR, /* lowaddr */ 962 BUS_SPACE_MAXADDR, /* highaddr */ 963 NULL, NULL, /* filter, filterarg */ 964 MCLBYTES, /* maxsize */ 965 1, /* nsegments */ 966 MCLBYTES, /* maxsegsize */ 967 0, /* flags */ 968 NULL, NULL, /* lockfunc, lockarg */ 969 &sc->vr_cdata.vr_rx_tag); 970 if (error != 0) { 971 device_printf(sc->vr_dev, "failed to create Rx DMA tag\n"); 972 goto fail; 973 } 974 975 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 976 error = bus_dmamem_alloc(sc->vr_cdata.vr_tx_ring_tag, 977 (void **)&sc->vr_rdata.vr_tx_ring, BUS_DMA_WAITOK | 978 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_tx_ring_map); 979 if (error != 0) { 980 device_printf(sc->vr_dev, 981 "failed to allocate DMA'able memory for Tx ring\n"); 982 goto fail; 983 } 984 985 ctx.vr_busaddr = 0; 986 error = bus_dmamap_load(sc->vr_cdata.vr_tx_ring_tag, 987 sc->vr_cdata.vr_tx_ring_map, sc->vr_rdata.vr_tx_ring, 988 VR_TX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 989 if (error != 0 || ctx.vr_busaddr == 0) { 990 device_printf(sc->vr_dev, 991 "failed to load DMA'able memory for Tx ring\n"); 992 goto fail; 993 } 994 sc->vr_rdata.vr_tx_ring_paddr = ctx.vr_busaddr; 995 996 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 997 error = bus_dmamem_alloc(sc->vr_cdata.vr_rx_ring_tag, 998 (void **)&sc->vr_rdata.vr_rx_ring, BUS_DMA_WAITOK | 999 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->vr_cdata.vr_rx_ring_map); 1000 if (error != 0) { 1001 device_printf(sc->vr_dev, 1002 "failed to allocate DMA'able memory for Rx ring\n"); 1003 goto fail; 1004 } 1005 1006 ctx.vr_busaddr = 0; 1007 error = bus_dmamap_load(sc->vr_cdata.vr_rx_ring_tag, 1008 sc->vr_cdata.vr_rx_ring_map, sc->vr_rdata.vr_rx_ring, 1009 VR_RX_RING_SIZE, vr_dmamap_cb, &ctx, 0); 1010 if (error != 0 || ctx.vr_busaddr == 0) { 1011 device_printf(sc->vr_dev, 1012 "failed to load DMA'able memory for Rx ring\n"); 1013 goto fail; 1014 } 1015 sc->vr_rdata.vr_rx_ring_paddr = ctx.vr_busaddr; 1016 1017 /* Create DMA maps for Tx buffers. */ 1018 for (i = 0; i < VR_TX_RING_CNT; i++) { 1019 txd = &sc->vr_cdata.vr_txdesc[i]; 1020 txd->tx_m = NULL; 1021 txd->tx_dmamap = NULL; 1022 error = bus_dmamap_create(sc->vr_cdata.vr_tx_tag, 0, 1023 &txd->tx_dmamap); 1024 if (error != 0) { 1025 device_printf(sc->vr_dev, 1026 "failed to create Tx dmamap\n"); 1027 goto fail; 1028 } 1029 } 1030 /* Create DMA maps for Rx buffers. */ 1031 if ((error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1032 &sc->vr_cdata.vr_rx_sparemap)) != 0) { 1033 device_printf(sc->vr_dev, 1034 "failed to create spare Rx dmamap\n"); 1035 goto fail; 1036 } 1037 for (i = 0; i < VR_RX_RING_CNT; i++) { 1038 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1039 rxd->rx_m = NULL; 1040 rxd->rx_dmamap = NULL; 1041 error = bus_dmamap_create(sc->vr_cdata.vr_rx_tag, 0, 1042 &rxd->rx_dmamap); 1043 if (error != 0) { 1044 device_printf(sc->vr_dev, 1045 "failed to create Rx dmamap\n"); 1046 goto fail; 1047 } 1048 } 1049 1050 fail: 1051 return (error); 1052 } 1053 1054 static void 1055 vr_dma_free(struct vr_softc *sc) 1056 { 1057 struct vr_txdesc *txd; 1058 struct vr_rxdesc *rxd; 1059 int i; 1060 1061 /* Tx ring. */ 1062 if (sc->vr_cdata.vr_tx_ring_tag) { 1063 if (sc->vr_cdata.vr_tx_ring_map) 1064 bus_dmamap_unload(sc->vr_cdata.vr_tx_ring_tag, 1065 sc->vr_cdata.vr_tx_ring_map); 1066 if (sc->vr_cdata.vr_tx_ring_map && 1067 sc->vr_rdata.vr_tx_ring) 1068 bus_dmamem_free(sc->vr_cdata.vr_tx_ring_tag, 1069 sc->vr_rdata.vr_tx_ring, 1070 sc->vr_cdata.vr_tx_ring_map); 1071 sc->vr_rdata.vr_tx_ring = NULL; 1072 sc->vr_cdata.vr_tx_ring_map = NULL; 1073 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_ring_tag); 1074 sc->vr_cdata.vr_tx_ring_tag = NULL; 1075 } 1076 /* Rx ring. */ 1077 if (sc->vr_cdata.vr_rx_ring_tag) { 1078 if (sc->vr_cdata.vr_rx_ring_map) 1079 bus_dmamap_unload(sc->vr_cdata.vr_rx_ring_tag, 1080 sc->vr_cdata.vr_rx_ring_map); 1081 if (sc->vr_cdata.vr_rx_ring_map && 1082 sc->vr_rdata.vr_rx_ring) 1083 bus_dmamem_free(sc->vr_cdata.vr_rx_ring_tag, 1084 sc->vr_rdata.vr_rx_ring, 1085 sc->vr_cdata.vr_rx_ring_map); 1086 sc->vr_rdata.vr_rx_ring = NULL; 1087 sc->vr_cdata.vr_rx_ring_map = NULL; 1088 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_ring_tag); 1089 sc->vr_cdata.vr_rx_ring_tag = NULL; 1090 } 1091 /* Tx buffers. */ 1092 if (sc->vr_cdata.vr_tx_tag) { 1093 for (i = 0; i < VR_TX_RING_CNT; i++) { 1094 txd = &sc->vr_cdata.vr_txdesc[i]; 1095 if (txd->tx_dmamap) { 1096 bus_dmamap_destroy(sc->vr_cdata.vr_tx_tag, 1097 txd->tx_dmamap); 1098 txd->tx_dmamap = NULL; 1099 } 1100 } 1101 bus_dma_tag_destroy(sc->vr_cdata.vr_tx_tag); 1102 sc->vr_cdata.vr_tx_tag = NULL; 1103 } 1104 /* Rx buffers. */ 1105 if (sc->vr_cdata.vr_rx_tag) { 1106 for (i = 0; i < VR_RX_RING_CNT; i++) { 1107 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1108 if (rxd->rx_dmamap) { 1109 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1110 rxd->rx_dmamap); 1111 rxd->rx_dmamap = NULL; 1112 } 1113 } 1114 if (sc->vr_cdata.vr_rx_sparemap) { 1115 bus_dmamap_destroy(sc->vr_cdata.vr_rx_tag, 1116 sc->vr_cdata.vr_rx_sparemap); 1117 sc->vr_cdata.vr_rx_sparemap = 0; 1118 } 1119 bus_dma_tag_destroy(sc->vr_cdata.vr_rx_tag); 1120 sc->vr_cdata.vr_rx_tag = NULL; 1121 } 1122 1123 if (sc->vr_cdata.vr_parent_tag) { 1124 bus_dma_tag_destroy(sc->vr_cdata.vr_parent_tag); 1125 sc->vr_cdata.vr_parent_tag = NULL; 1126 } 1127 } 1128 1129 /* 1130 * Initialize the transmit descriptors. 1131 */ 1132 static int 1133 vr_tx_ring_init(struct vr_softc *sc) 1134 { 1135 struct vr_ring_data *rd; 1136 struct vr_txdesc *txd; 1137 bus_addr_t addr; 1138 int i; 1139 1140 sc->vr_cdata.vr_tx_prod = 0; 1141 sc->vr_cdata.vr_tx_cons = 0; 1142 sc->vr_cdata.vr_tx_cnt = 0; 1143 sc->vr_cdata.vr_tx_pkts = 0; 1144 1145 rd = &sc->vr_rdata; 1146 bzero(rd->vr_tx_ring, VR_TX_RING_SIZE); 1147 for (i = 0; i < VR_TX_RING_CNT; i++) { 1148 if (i == VR_TX_RING_CNT - 1) 1149 addr = VR_TX_RING_ADDR(sc, 0); 1150 else 1151 addr = VR_TX_RING_ADDR(sc, i + 1); 1152 rd->vr_tx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1153 txd = &sc->vr_cdata.vr_txdesc[i]; 1154 txd->tx_m = NULL; 1155 } 1156 1157 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1158 sc->vr_cdata.vr_tx_ring_map, 1159 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1160 1161 return (0); 1162 } 1163 1164 /* 1165 * Initialize the RX descriptors and allocate mbufs for them. Note that 1166 * we arrange the descriptors in a closed ring, so that the last descriptor 1167 * points back to the first. 1168 */ 1169 static int 1170 vr_rx_ring_init(struct vr_softc *sc) 1171 { 1172 struct vr_ring_data *rd; 1173 struct vr_rxdesc *rxd; 1174 bus_addr_t addr; 1175 int i; 1176 1177 sc->vr_cdata.vr_rx_cons = 0; 1178 1179 rd = &sc->vr_rdata; 1180 bzero(rd->vr_rx_ring, VR_RX_RING_SIZE); 1181 for (i = 0; i < VR_RX_RING_CNT; i++) { 1182 rxd = &sc->vr_cdata.vr_rxdesc[i]; 1183 rxd->rx_m = NULL; 1184 rxd->desc = &rd->vr_rx_ring[i]; 1185 if (i == VR_RX_RING_CNT - 1) 1186 addr = VR_RX_RING_ADDR(sc, 0); 1187 else 1188 addr = VR_RX_RING_ADDR(sc, i + 1); 1189 rd->vr_rx_ring[i].vr_nextphys = htole32(VR_ADDR_LO(addr)); 1190 if (vr_newbuf(sc, i) != 0) 1191 return (ENOBUFS); 1192 } 1193 1194 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1195 sc->vr_cdata.vr_rx_ring_map, 1196 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1197 1198 return (0); 1199 } 1200 1201 static __inline void 1202 vr_discard_rxbuf(struct vr_rxdesc *rxd) 1203 { 1204 struct vr_desc *desc; 1205 1206 desc = rxd->desc; 1207 desc->vr_ctl = htole32(VR_RXCTL | (MCLBYTES - sizeof(uint64_t))); 1208 desc->vr_status = htole32(VR_RXSTAT_OWN); 1209 } 1210 1211 /* 1212 * Initialize an RX descriptor and attach an MBUF cluster. 1213 * Note: the length fields are only 11 bits wide, which means the 1214 * largest size we can specify is 2047. This is important because 1215 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 1216 * overflow the field and make a mess. 1217 */ 1218 static int 1219 vr_newbuf(struct vr_softc *sc, int idx) 1220 { 1221 struct vr_desc *desc; 1222 struct vr_rxdesc *rxd; 1223 struct mbuf *m; 1224 bus_dma_segment_t segs[1]; 1225 bus_dmamap_t map; 1226 int nsegs; 1227 1228 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1229 if (m == NULL) 1230 return (ENOBUFS); 1231 m->m_len = m->m_pkthdr.len = MCLBYTES; 1232 m_adj(m, sizeof(uint64_t)); 1233 1234 if (bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_rx_tag, 1235 sc->vr_cdata.vr_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1236 m_freem(m); 1237 return (ENOBUFS); 1238 } 1239 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1240 1241 rxd = &sc->vr_cdata.vr_rxdesc[idx]; 1242 if (rxd->rx_m != NULL) { 1243 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1244 BUS_DMASYNC_POSTREAD); 1245 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap); 1246 } 1247 map = rxd->rx_dmamap; 1248 rxd->rx_dmamap = sc->vr_cdata.vr_rx_sparemap; 1249 sc->vr_cdata.vr_rx_sparemap = map; 1250 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, rxd->rx_dmamap, 1251 BUS_DMASYNC_PREREAD); 1252 rxd->rx_m = m; 1253 desc = rxd->desc; 1254 desc->vr_data = htole32(VR_ADDR_LO(segs[0].ds_addr)); 1255 desc->vr_ctl = htole32(VR_RXCTL | segs[0].ds_len); 1256 desc->vr_status = htole32(VR_RXSTAT_OWN); 1257 1258 return (0); 1259 } 1260 1261 #ifndef __NO_STRICT_ALIGNMENT 1262 static __inline void 1263 vr_fixup_rx(struct mbuf *m) 1264 { 1265 uint16_t *src, *dst; 1266 int i; 1267 1268 src = mtod(m, uint16_t *); 1269 dst = src - 1; 1270 1271 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1272 *dst++ = *src++; 1273 1274 m->m_data -= ETHER_ALIGN; 1275 } 1276 #endif 1277 1278 /* 1279 * A frame has been uploaded: pass the resulting mbuf chain up to 1280 * the higher level protocols. 1281 */ 1282 static int 1283 vr_rxeof(struct vr_softc *sc) 1284 { 1285 struct vr_rxdesc *rxd; 1286 struct mbuf *m; 1287 struct ifnet *ifp; 1288 struct vr_desc *cur_rx; 1289 int cons, prog, total_len, rx_npkts; 1290 uint32_t rxstat, rxctl; 1291 1292 VR_LOCK_ASSERT(sc); 1293 ifp = sc->vr_ifp; 1294 cons = sc->vr_cdata.vr_rx_cons; 1295 rx_npkts = 0; 1296 1297 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1298 sc->vr_cdata.vr_rx_ring_map, 1299 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1300 1301 for (prog = 0; prog < VR_RX_RING_CNT; VR_INC(cons, VR_RX_RING_CNT)) { 1302 #ifdef DEVICE_POLLING 1303 if (ifp->if_capenable & IFCAP_POLLING) { 1304 if (sc->rxcycles <= 0) 1305 break; 1306 sc->rxcycles--; 1307 } 1308 #endif 1309 cur_rx = &sc->vr_rdata.vr_rx_ring[cons]; 1310 rxstat = le32toh(cur_rx->vr_status); 1311 rxctl = le32toh(cur_rx->vr_ctl); 1312 if ((rxstat & VR_RXSTAT_OWN) == VR_RXSTAT_OWN) 1313 break; 1314 1315 prog++; 1316 rxd = &sc->vr_cdata.vr_rxdesc[cons]; 1317 m = rxd->rx_m; 1318 1319 /* 1320 * If an error occurs, update stats, clear the 1321 * status word and leave the mbuf cluster in place: 1322 * it should simply get re-used next time this descriptor 1323 * comes up in the ring. 1324 * We don't support SG in Rx path yet, so discard 1325 * partial frame. 1326 */ 1327 if ((rxstat & VR_RXSTAT_RX_OK) == 0 || 1328 (rxstat & (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) != 1329 (VR_RXSTAT_FIRSTFRAG | VR_RXSTAT_LASTFRAG)) { 1330 ifp->if_ierrors++; 1331 sc->vr_stat.rx_errors++; 1332 if (rxstat & VR_RXSTAT_CRCERR) 1333 sc->vr_stat.rx_crc_errors++; 1334 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 1335 sc->vr_stat.rx_alignment++; 1336 if (rxstat & VR_RXSTAT_FIFOOFLOW) 1337 sc->vr_stat.rx_fifo_overflows++; 1338 if (rxstat & VR_RXSTAT_GIANT) 1339 sc->vr_stat.rx_giants++; 1340 if (rxstat & VR_RXSTAT_RUNT) 1341 sc->vr_stat.rx_runts++; 1342 if (rxstat & VR_RXSTAT_BUFFERR) 1343 sc->vr_stat.rx_no_buffers++; 1344 #ifdef VR_SHOW_ERRORS 1345 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1346 __func__, rxstat & 0xff, VR_RXSTAT_ERR_BITS); 1347 #endif 1348 vr_discard_rxbuf(rxd); 1349 continue; 1350 } 1351 1352 if (vr_newbuf(sc, cons) != 0) { 1353 ifp->if_iqdrops++; 1354 sc->vr_stat.rx_errors++; 1355 sc->vr_stat.rx_no_mbufs++; 1356 vr_discard_rxbuf(rxd); 1357 continue; 1358 } 1359 1360 /* 1361 * XXX The VIA Rhine chip includes the CRC with every 1362 * received frame, and there's no way to turn this 1363 * behavior off (at least, I can't find anything in 1364 * the manual that explains how to do it) so we have 1365 * to trim off the CRC manually. 1366 */ 1367 total_len = VR_RXBYTES(rxstat); 1368 total_len -= ETHER_CRC_LEN; 1369 m->m_pkthdr.len = m->m_len = total_len; 1370 #ifndef __NO_STRICT_ALIGNMENT 1371 /* 1372 * RX buffers must be 32-bit aligned. 1373 * Ignore the alignment problems on the non-strict alignment 1374 * platform. The performance hit incurred due to unaligned 1375 * accesses is much smaller than the hit produced by forcing 1376 * buffer copies all the time. 1377 */ 1378 vr_fixup_rx(m); 1379 #endif 1380 m->m_pkthdr.rcvif = ifp; 1381 ifp->if_ipackets++; 1382 sc->vr_stat.rx_ok++; 1383 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1384 (rxstat & VR_RXSTAT_FRAG) == 0 && 1385 (rxctl & VR_RXCTL_IP) != 0) { 1386 /* Checksum is valid for non-fragmented IP packets. */ 1387 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1388 if ((rxctl & VR_RXCTL_IPOK) == VR_RXCTL_IPOK) { 1389 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1390 if (rxctl & (VR_RXCTL_TCP | VR_RXCTL_UDP)) { 1391 m->m_pkthdr.csum_flags |= 1392 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1393 if ((rxctl & VR_RXCTL_TCPUDPOK) != 0) 1394 m->m_pkthdr.csum_data = 0xffff; 1395 } 1396 } 1397 } 1398 VR_UNLOCK(sc); 1399 (*ifp->if_input)(ifp, m); 1400 VR_LOCK(sc); 1401 rx_npkts++; 1402 } 1403 1404 if (prog > 0) { 1405 /* 1406 * Let controller know how many number of RX buffers 1407 * are posted but avoid expensive register access if 1408 * TX pause capability was not negotiated with link 1409 * partner. 1410 */ 1411 if ((sc->vr_flags & VR_F_TXPAUSE) != 0) { 1412 if (prog >= VR_RX_RING_CNT) 1413 prog = VR_RX_RING_CNT - 1; 1414 CSR_WRITE_1(sc, VR_FLOWCR0, prog); 1415 } 1416 sc->vr_cdata.vr_rx_cons = cons; 1417 bus_dmamap_sync(sc->vr_cdata.vr_rx_ring_tag, 1418 sc->vr_cdata.vr_rx_ring_map, 1419 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1420 } 1421 return (rx_npkts); 1422 } 1423 1424 /* 1425 * A frame was downloaded to the chip. It's safe for us to clean up 1426 * the list buffers. 1427 */ 1428 static void 1429 vr_txeof(struct vr_softc *sc) 1430 { 1431 struct vr_txdesc *txd; 1432 struct vr_desc *cur_tx; 1433 struct ifnet *ifp; 1434 uint32_t txctl, txstat; 1435 int cons, prod; 1436 1437 VR_LOCK_ASSERT(sc); 1438 1439 cons = sc->vr_cdata.vr_tx_cons; 1440 prod = sc->vr_cdata.vr_tx_prod; 1441 if (cons == prod) 1442 return; 1443 1444 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1445 sc->vr_cdata.vr_tx_ring_map, 1446 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1447 1448 ifp = sc->vr_ifp; 1449 /* 1450 * Go through our tx list and free mbufs for those 1451 * frames that have been transmitted. 1452 */ 1453 for (; cons != prod; VR_INC(cons, VR_TX_RING_CNT)) { 1454 cur_tx = &sc->vr_rdata.vr_tx_ring[cons]; 1455 txctl = le32toh(cur_tx->vr_ctl); 1456 txstat = le32toh(cur_tx->vr_status); 1457 if ((txstat & VR_TXSTAT_OWN) == VR_TXSTAT_OWN) 1458 break; 1459 1460 sc->vr_cdata.vr_tx_cnt--; 1461 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1462 /* Only the first descriptor in the chain is valid. */ 1463 if ((txctl & VR_TXCTL_FIRSTFRAG) == 0) 1464 continue; 1465 1466 txd = &sc->vr_cdata.vr_txdesc[cons]; 1467 KASSERT(txd->tx_m != NULL, ("%s: accessing NULL mbuf!\n", 1468 __func__)); 1469 1470 if ((txstat & VR_TXSTAT_ERRSUM) != 0) { 1471 ifp->if_oerrors++; 1472 sc->vr_stat.tx_errors++; 1473 if ((txstat & VR_TXSTAT_ABRT) != 0) { 1474 /* Give up and restart Tx. */ 1475 sc->vr_stat.tx_abort++; 1476 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 1477 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1478 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 1479 txd->tx_dmamap); 1480 m_freem(txd->tx_m); 1481 txd->tx_m = NULL; 1482 VR_INC(cons, VR_TX_RING_CNT); 1483 sc->vr_cdata.vr_tx_cons = cons; 1484 if (vr_tx_stop(sc) != 0) { 1485 device_printf(sc->vr_dev, 1486 "%s: Tx shutdown error -- " 1487 "resetting\n", __func__); 1488 sc->vr_flags |= VR_F_RESTART; 1489 return; 1490 } 1491 vr_tx_start(sc); 1492 break; 1493 } 1494 if ((sc->vr_revid < REV_ID_VT3071_A && 1495 (txstat & VR_TXSTAT_UNDERRUN)) || 1496 (txstat & (VR_TXSTAT_UDF | VR_TXSTAT_TBUFF))) { 1497 sc->vr_stat.tx_underrun++; 1498 /* Retry and restart Tx. */ 1499 sc->vr_cdata.vr_tx_cnt++; 1500 sc->vr_cdata.vr_tx_cons = cons; 1501 cur_tx->vr_status = htole32(VR_TXSTAT_OWN); 1502 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1503 sc->vr_cdata.vr_tx_ring_map, 1504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1505 vr_tx_underrun(sc); 1506 return; 1507 } 1508 if ((txstat & VR_TXSTAT_DEFER) != 0) { 1509 ifp->if_collisions++; 1510 sc->vr_stat.tx_collisions++; 1511 } 1512 if ((txstat & VR_TXSTAT_LATECOLL) != 0) { 1513 ifp->if_collisions++; 1514 sc->vr_stat.tx_late_collisions++; 1515 } 1516 } else { 1517 sc->vr_stat.tx_ok++; 1518 ifp->if_opackets++; 1519 } 1520 1521 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1522 BUS_DMASYNC_POSTWRITE); 1523 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1524 if (sc->vr_revid < REV_ID_VT3071_A) { 1525 ifp->if_collisions += 1526 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1527 sc->vr_stat.tx_collisions += 1528 (txstat & VR_TXSTAT_COLLCNT) >> 3; 1529 } else { 1530 ifp->if_collisions += (txstat & 0x0f); 1531 sc->vr_stat.tx_collisions += (txstat & 0x0f); 1532 } 1533 m_freem(txd->tx_m); 1534 txd->tx_m = NULL; 1535 } 1536 1537 sc->vr_cdata.vr_tx_cons = cons; 1538 if (sc->vr_cdata.vr_tx_cnt == 0) 1539 sc->vr_watchdog_timer = 0; 1540 } 1541 1542 static void 1543 vr_tick(void *xsc) 1544 { 1545 struct vr_softc *sc; 1546 struct mii_data *mii; 1547 1548 sc = (struct vr_softc *)xsc; 1549 1550 VR_LOCK_ASSERT(sc); 1551 1552 if ((sc->vr_flags & VR_F_RESTART) != 0) { 1553 device_printf(sc->vr_dev, "restarting\n"); 1554 sc->vr_stat.num_restart++; 1555 sc->vr_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1556 vr_init_locked(sc); 1557 sc->vr_flags &= ~VR_F_RESTART; 1558 } 1559 1560 mii = device_get_softc(sc->vr_miibus); 1561 mii_tick(mii); 1562 if ((sc->vr_flags & VR_F_LINK) == 0) 1563 vr_miibus_statchg(sc->vr_dev); 1564 vr_watchdog(sc); 1565 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 1566 } 1567 1568 #ifdef DEVICE_POLLING 1569 static poll_handler_t vr_poll; 1570 static poll_handler_t vr_poll_locked; 1571 1572 static int 1573 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1574 { 1575 struct vr_softc *sc; 1576 int rx_npkts; 1577 1578 sc = ifp->if_softc; 1579 rx_npkts = 0; 1580 1581 VR_LOCK(sc); 1582 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1583 rx_npkts = vr_poll_locked(ifp, cmd, count); 1584 VR_UNLOCK(sc); 1585 return (rx_npkts); 1586 } 1587 1588 static int 1589 vr_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 1590 { 1591 struct vr_softc *sc; 1592 int rx_npkts; 1593 1594 sc = ifp->if_softc; 1595 1596 VR_LOCK_ASSERT(sc); 1597 1598 sc->rxcycles = count; 1599 rx_npkts = vr_rxeof(sc); 1600 vr_txeof(sc); 1601 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1602 vr_start_locked(ifp); 1603 1604 if (cmd == POLL_AND_CHECK_STATUS) { 1605 uint16_t status; 1606 1607 /* Also check status register. */ 1608 status = CSR_READ_2(sc, VR_ISR); 1609 if (status) 1610 CSR_WRITE_2(sc, VR_ISR, status); 1611 1612 if ((status & VR_INTRS) == 0) 1613 return (rx_npkts); 1614 1615 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1616 VR_ISR_STATSOFLOW)) != 0) { 1617 if (vr_error(sc, status) != 0) 1618 return (rx_npkts); 1619 } 1620 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1621 #ifdef VR_SHOW_ERRORS 1622 device_printf(sc->vr_dev, "%s: receive error : 0x%b\n", 1623 __func__, status, VR_ISR_ERR_BITS); 1624 #endif 1625 vr_rx_start(sc); 1626 } 1627 } 1628 return (rx_npkts); 1629 } 1630 #endif /* DEVICE_POLLING */ 1631 1632 /* Back off the transmit threshold. */ 1633 static void 1634 vr_tx_underrun(struct vr_softc *sc) 1635 { 1636 int thresh; 1637 1638 device_printf(sc->vr_dev, "Tx underrun -- "); 1639 if (sc->vr_txthresh < VR_TXTHRESH_MAX) { 1640 thresh = sc->vr_txthresh; 1641 sc->vr_txthresh++; 1642 if (sc->vr_txthresh >= VR_TXTHRESH_MAX) { 1643 sc->vr_txthresh = VR_TXTHRESH_MAX; 1644 printf("using store and forward mode\n"); 1645 } else 1646 printf("increasing Tx threshold(%d -> %d)\n", 1647 vr_tx_threshold_tables[thresh].value, 1648 vr_tx_threshold_tables[thresh + 1].value); 1649 } else 1650 printf("\n"); 1651 sc->vr_stat.tx_underrun++; 1652 if (vr_tx_stop(sc) != 0) { 1653 device_printf(sc->vr_dev, "%s: Tx shutdown error -- " 1654 "resetting\n", __func__); 1655 sc->vr_flags |= VR_F_RESTART; 1656 return; 1657 } 1658 vr_tx_start(sc); 1659 } 1660 1661 static int 1662 vr_intr(void *arg) 1663 { 1664 struct vr_softc *sc; 1665 uint16_t status; 1666 1667 sc = (struct vr_softc *)arg; 1668 1669 status = CSR_READ_2(sc, VR_ISR); 1670 if (status == 0 || status == 0xffff || (status & VR_INTRS) == 0) 1671 return (FILTER_STRAY); 1672 1673 /* Disable interrupts. */ 1674 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1675 1676 taskqueue_enqueue_fast(taskqueue_fast, &sc->vr_inttask); 1677 1678 return (FILTER_HANDLED); 1679 } 1680 1681 static void 1682 vr_int_task(void *arg, int npending) 1683 { 1684 struct vr_softc *sc; 1685 struct ifnet *ifp; 1686 uint16_t status; 1687 1688 sc = (struct vr_softc *)arg; 1689 1690 VR_LOCK(sc); 1691 1692 if ((sc->vr_flags & VR_F_SUSPENDED) != 0) 1693 goto done_locked; 1694 1695 status = CSR_READ_2(sc, VR_ISR); 1696 ifp = sc->vr_ifp; 1697 #ifdef DEVICE_POLLING 1698 if ((ifp->if_capenable & IFCAP_POLLING) != 0) 1699 goto done_locked; 1700 #endif 1701 1702 /* Suppress unwanted interrupts. */ 1703 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1704 (sc->vr_flags & VR_F_RESTART) != 0) { 1705 CSR_WRITE_2(sc, VR_IMR, 0); 1706 CSR_WRITE_2(sc, VR_ISR, status); 1707 goto done_locked; 1708 } 1709 1710 for (; (status & VR_INTRS) != 0;) { 1711 CSR_WRITE_2(sc, VR_ISR, status); 1712 if ((status & (VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | 1713 VR_ISR_STATSOFLOW)) != 0) { 1714 if (vr_error(sc, status) != 0) { 1715 VR_UNLOCK(sc); 1716 return; 1717 } 1718 } 1719 vr_rxeof(sc); 1720 if ((status & (VR_ISR_RX_NOBUF | VR_ISR_RX_OFLOW)) != 0) { 1721 #ifdef VR_SHOW_ERRORS 1722 device_printf(sc->vr_dev, "%s: receive error = 0x%b\n", 1723 __func__, status, VR_ISR_ERR_BITS); 1724 #endif 1725 /* Restart Rx if RxDMA SM was stopped. */ 1726 vr_rx_start(sc); 1727 } 1728 vr_txeof(sc); 1729 1730 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1731 vr_start_locked(ifp); 1732 1733 status = CSR_READ_2(sc, VR_ISR); 1734 } 1735 1736 /* Re-enable interrupts. */ 1737 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1738 1739 done_locked: 1740 VR_UNLOCK(sc); 1741 } 1742 1743 static int 1744 vr_error(struct vr_softc *sc, uint16_t status) 1745 { 1746 uint16_t pcis; 1747 1748 status &= VR_ISR_BUSERR | VR_ISR_LINKSTAT2 | VR_ISR_STATSOFLOW; 1749 if ((status & VR_ISR_BUSERR) != 0) { 1750 status &= ~VR_ISR_BUSERR; 1751 sc->vr_stat.bus_errors++; 1752 /* Disable further interrupts. */ 1753 CSR_WRITE_2(sc, VR_IMR, 0); 1754 pcis = pci_read_config(sc->vr_dev, PCIR_STATUS, 2); 1755 device_printf(sc->vr_dev, "PCI bus error(0x%04x) -- " 1756 "resetting\n", pcis); 1757 pci_write_config(sc->vr_dev, PCIR_STATUS, pcis, 2); 1758 sc->vr_flags |= VR_F_RESTART; 1759 return (EAGAIN); 1760 } 1761 if ((status & VR_ISR_LINKSTAT2) != 0) { 1762 /* Link state change, duplex changes etc. */ 1763 status &= ~VR_ISR_LINKSTAT2; 1764 } 1765 if ((status & VR_ISR_STATSOFLOW) != 0) { 1766 status &= ~VR_ISR_STATSOFLOW; 1767 if (sc->vr_revid >= REV_ID_VT6105M_A0) { 1768 /* Update MIB counters. */ 1769 } 1770 } 1771 1772 if (status != 0) 1773 device_printf(sc->vr_dev, 1774 "unhandled interrupt, status = 0x%04x\n", status); 1775 return (0); 1776 } 1777 1778 /* 1779 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1780 * pointers to the fragment pointers. 1781 */ 1782 static int 1783 vr_encap(struct vr_softc *sc, struct mbuf **m_head) 1784 { 1785 struct vr_txdesc *txd; 1786 struct vr_desc *desc; 1787 struct mbuf *m; 1788 bus_dma_segment_t txsegs[VR_MAXFRAGS]; 1789 uint32_t csum_flags, txctl; 1790 int error, i, nsegs, prod, si; 1791 int padlen; 1792 1793 VR_LOCK_ASSERT(sc); 1794 1795 M_ASSERTPKTHDR((*m_head)); 1796 1797 /* 1798 * Some VIA Rhine wants packet buffers to be longword 1799 * aligned, but very often our mbufs aren't. Rather than 1800 * waste time trying to decide when to copy and when not 1801 * to copy, just do it all the time. 1802 */ 1803 if ((sc->vr_quirks & VR_Q_NEEDALIGN) != 0) { 1804 m = m_defrag(*m_head, M_NOWAIT); 1805 if (m == NULL) { 1806 m_freem(*m_head); 1807 *m_head = NULL; 1808 return (ENOBUFS); 1809 } 1810 *m_head = m; 1811 } 1812 1813 /* 1814 * The Rhine chip doesn't auto-pad, so we have to make 1815 * sure to pad short frames out to the minimum frame length 1816 * ourselves. 1817 */ 1818 if ((*m_head)->m_pkthdr.len < VR_MIN_FRAMELEN) { 1819 m = *m_head; 1820 padlen = VR_MIN_FRAMELEN - m->m_pkthdr.len; 1821 if (M_WRITABLE(m) == 0) { 1822 /* Get a writable copy. */ 1823 m = m_dup(*m_head, M_NOWAIT); 1824 m_freem(*m_head); 1825 if (m == NULL) { 1826 *m_head = NULL; 1827 return (ENOBUFS); 1828 } 1829 *m_head = m; 1830 } 1831 if (m->m_next != NULL || M_TRAILINGSPACE(m) < padlen) { 1832 m = m_defrag(m, M_NOWAIT); 1833 if (m == NULL) { 1834 m_freem(*m_head); 1835 *m_head = NULL; 1836 return (ENOBUFS); 1837 } 1838 } 1839 /* 1840 * Manually pad short frames, and zero the pad space 1841 * to avoid leaking data. 1842 */ 1843 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1844 m->m_pkthdr.len += padlen; 1845 m->m_len = m->m_pkthdr.len; 1846 *m_head = m; 1847 } 1848 1849 prod = sc->vr_cdata.vr_tx_prod; 1850 txd = &sc->vr_cdata.vr_txdesc[prod]; 1851 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1852 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1853 if (error == EFBIG) { 1854 m = m_collapse(*m_head, M_NOWAIT, VR_MAXFRAGS); 1855 if (m == NULL) { 1856 m_freem(*m_head); 1857 *m_head = NULL; 1858 return (ENOBUFS); 1859 } 1860 *m_head = m; 1861 error = bus_dmamap_load_mbuf_sg(sc->vr_cdata.vr_tx_tag, 1862 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1863 if (error != 0) { 1864 m_freem(*m_head); 1865 *m_head = NULL; 1866 return (error); 1867 } 1868 } else if (error != 0) 1869 return (error); 1870 if (nsegs == 0) { 1871 m_freem(*m_head); 1872 *m_head = NULL; 1873 return (EIO); 1874 } 1875 1876 /* Check number of available descriptors. */ 1877 if (sc->vr_cdata.vr_tx_cnt + nsegs >= (VR_TX_RING_CNT - 1)) { 1878 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap); 1879 return (ENOBUFS); 1880 } 1881 1882 txd->tx_m = *m_head; 1883 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, txd->tx_dmamap, 1884 BUS_DMASYNC_PREWRITE); 1885 1886 /* Set checksum offload. */ 1887 csum_flags = 0; 1888 if (((*m_head)->m_pkthdr.csum_flags & VR_CSUM_FEATURES) != 0) { 1889 if ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) 1890 csum_flags |= VR_TXCTL_IPCSUM; 1891 if ((*m_head)->m_pkthdr.csum_flags & CSUM_TCP) 1892 csum_flags |= VR_TXCTL_TCPCSUM; 1893 if ((*m_head)->m_pkthdr.csum_flags & CSUM_UDP) 1894 csum_flags |= VR_TXCTL_UDPCSUM; 1895 } 1896 1897 /* 1898 * Quite contrary to datasheet for VIA Rhine, VR_TXCTL_TLINK bit 1899 * is required for all descriptors regardless of single or 1900 * multiple buffers. Also VR_TXSTAT_OWN bit is valid only for 1901 * the first descriptor for a multi-fragmented frames. Without 1902 * that VIA Rhine chip generates Tx underrun interrupts and can't 1903 * send any frames. 1904 */ 1905 si = prod; 1906 for (i = 0; i < nsegs; i++) { 1907 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1908 desc->vr_status = 0; 1909 txctl = txsegs[i].ds_len | VR_TXCTL_TLINK | csum_flags; 1910 if (i == 0) 1911 txctl |= VR_TXCTL_FIRSTFRAG; 1912 desc->vr_ctl = htole32(txctl); 1913 desc->vr_data = htole32(VR_ADDR_LO(txsegs[i].ds_addr)); 1914 sc->vr_cdata.vr_tx_cnt++; 1915 VR_INC(prod, VR_TX_RING_CNT); 1916 } 1917 /* Update producer index. */ 1918 sc->vr_cdata.vr_tx_prod = prod; 1919 1920 prod = (prod + VR_TX_RING_CNT - 1) % VR_TX_RING_CNT; 1921 desc = &sc->vr_rdata.vr_tx_ring[prod]; 1922 1923 /* 1924 * Set EOP on the last desciptor and reuqest Tx completion 1925 * interrupt for every VR_TX_INTR_THRESH-th frames. 1926 */ 1927 VR_INC(sc->vr_cdata.vr_tx_pkts, VR_TX_INTR_THRESH); 1928 if (sc->vr_cdata.vr_tx_pkts == 0) 1929 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG | VR_TXCTL_FINT); 1930 else 1931 desc->vr_ctl |= htole32(VR_TXCTL_LASTFRAG); 1932 1933 /* Lastly turn the first descriptor ownership to hardware. */ 1934 desc = &sc->vr_rdata.vr_tx_ring[si]; 1935 desc->vr_status |= htole32(VR_TXSTAT_OWN); 1936 1937 /* Sync descriptors. */ 1938 bus_dmamap_sync(sc->vr_cdata.vr_tx_ring_tag, 1939 sc->vr_cdata.vr_tx_ring_map, 1940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1941 1942 return (0); 1943 } 1944 1945 static void 1946 vr_start(struct ifnet *ifp) 1947 { 1948 struct vr_softc *sc; 1949 1950 sc = ifp->if_softc; 1951 VR_LOCK(sc); 1952 vr_start_locked(ifp); 1953 VR_UNLOCK(sc); 1954 } 1955 1956 static void 1957 vr_start_locked(struct ifnet *ifp) 1958 { 1959 struct vr_softc *sc; 1960 struct mbuf *m_head; 1961 int enq; 1962 1963 sc = ifp->if_softc; 1964 1965 VR_LOCK_ASSERT(sc); 1966 1967 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1968 IFF_DRV_RUNNING || (sc->vr_flags & VR_F_LINK) == 0) 1969 return; 1970 1971 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1972 sc->vr_cdata.vr_tx_cnt < VR_TX_RING_CNT - 2; ) { 1973 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1974 if (m_head == NULL) 1975 break; 1976 /* 1977 * Pack the data into the transmit ring. If we 1978 * don't have room, set the OACTIVE flag and wait 1979 * for the NIC to drain the ring. 1980 */ 1981 if (vr_encap(sc, &m_head)) { 1982 if (m_head == NULL) 1983 break; 1984 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1985 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1986 break; 1987 } 1988 1989 enq++; 1990 /* 1991 * If there's a BPF listener, bounce a copy of this frame 1992 * to him. 1993 */ 1994 ETHER_BPF_MTAP(ifp, m_head); 1995 } 1996 1997 if (enq > 0) { 1998 /* Tell the chip to start transmitting. */ 1999 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2000 /* Set a timeout in case the chip goes out to lunch. */ 2001 sc->vr_watchdog_timer = 5; 2002 } 2003 } 2004 2005 static void 2006 vr_init(void *xsc) 2007 { 2008 struct vr_softc *sc; 2009 2010 sc = (struct vr_softc *)xsc; 2011 VR_LOCK(sc); 2012 vr_init_locked(sc); 2013 VR_UNLOCK(sc); 2014 } 2015 2016 static void 2017 vr_init_locked(struct vr_softc *sc) 2018 { 2019 struct ifnet *ifp; 2020 struct mii_data *mii; 2021 bus_addr_t addr; 2022 int i; 2023 2024 VR_LOCK_ASSERT(sc); 2025 2026 ifp = sc->vr_ifp; 2027 mii = device_get_softc(sc->vr_miibus); 2028 2029 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2030 return; 2031 2032 /* Cancel pending I/O and free all RX/TX buffers. */ 2033 vr_stop(sc); 2034 vr_reset(sc); 2035 2036 /* Set our station address. */ 2037 for (i = 0; i < ETHER_ADDR_LEN; i++) 2038 CSR_WRITE_1(sc, VR_PAR0 + i, IF_LLADDR(sc->vr_ifp)[i]); 2039 2040 /* Set DMA size. */ 2041 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 2042 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 2043 2044 /* 2045 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 2046 * so we must set both. 2047 */ 2048 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 2049 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 2050 2051 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 2052 VR_SETBIT(sc, VR_BCR1, vr_tx_threshold_tables[sc->vr_txthresh].bcr_cfg); 2053 2054 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 2055 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 2056 2057 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 2058 VR_SETBIT(sc, VR_TXCFG, vr_tx_threshold_tables[sc->vr_txthresh].tx_cfg); 2059 2060 /* Init circular RX list. */ 2061 if (vr_rx_ring_init(sc) != 0) { 2062 device_printf(sc->vr_dev, 2063 "initialization failed: no memory for rx buffers\n"); 2064 vr_stop(sc); 2065 return; 2066 } 2067 2068 /* Init tx descriptors. */ 2069 vr_tx_ring_init(sc); 2070 2071 if ((sc->vr_quirks & VR_Q_CAM) != 0) { 2072 uint8_t vcam[2] = { 0, 0 }; 2073 2074 /* Disable VLAN hardware tag insertion/stripping. */ 2075 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TXTAGEN | VR_TXCFG_RXTAGCTL); 2076 /* Disable VLAN hardware filtering. */ 2077 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_VLANFILT_ENB); 2078 /* Disable all CAM entries. */ 2079 vr_cam_mask(sc, VR_MCAST_CAM, 0); 2080 vr_cam_mask(sc, VR_VLAN_CAM, 0); 2081 /* Enable the first VLAN CAM. */ 2082 vr_cam_data(sc, VR_VLAN_CAM, 0, vcam); 2083 vr_cam_mask(sc, VR_VLAN_CAM, 1); 2084 } 2085 2086 /* 2087 * Set up receive filter. 2088 */ 2089 vr_set_filter(sc); 2090 2091 /* 2092 * Load the address of the RX ring. 2093 */ 2094 addr = VR_RX_RING_ADDR(sc, 0); 2095 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2096 /* 2097 * Load the address of the TX ring. 2098 */ 2099 addr = VR_TX_RING_ADDR(sc, 0); 2100 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2101 /* Default : full-duplex, no Tx poll. */ 2102 CSR_WRITE_1(sc, VR_CR1, VR_CR1_FULLDUPLEX | VR_CR1_TX_NOPOLL); 2103 2104 /* Set flow-control parameters for Rhine III. */ 2105 if (sc->vr_revid >= REV_ID_VT6105_A0) { 2106 /* 2107 * Configure Rx buffer count available for incoming 2108 * packet. 2109 * Even though data sheet says almost nothing about 2110 * this register, this register should be updated 2111 * whenever driver adds new RX buffers to controller. 2112 * Otherwise, XON frame is not sent to link partner 2113 * even if controller has enough RX buffers and you 2114 * would be isolated from network. 2115 * The controller is not smart enough to know number 2116 * of available RX buffers so driver have to let 2117 * controller know how many RX buffers are posted. 2118 * In other words, this register works like a residue 2119 * counter for RX buffers and should be initialized 2120 * to the number of total RX buffers - 1 before 2121 * enabling RX MAC. Note, this register is 8bits so 2122 * it effectively limits the maximum number of RX 2123 * buffer to be configured by controller is 255. 2124 */ 2125 CSR_WRITE_1(sc, VR_FLOWCR0, VR_RX_RING_CNT - 1); 2126 /* 2127 * Tx pause low threshold : 8 free receive buffers 2128 * Tx pause XON high threshold : 24 free receive buffers 2129 */ 2130 CSR_WRITE_1(sc, VR_FLOWCR1, 2131 VR_FLOWCR1_TXLO8 | VR_FLOWCR1_TXHI24 | VR_FLOWCR1_XONXOFF); 2132 /* Set Tx pause timer. */ 2133 CSR_WRITE_2(sc, VR_PAUSETIMER, 0xffff); 2134 } 2135 2136 /* Enable receiver and transmitter. */ 2137 CSR_WRITE_1(sc, VR_CR0, 2138 VR_CR0_START | VR_CR0_TX_ON | VR_CR0_RX_ON | VR_CR0_RX_GO); 2139 2140 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2141 #ifdef DEVICE_POLLING 2142 /* 2143 * Disable interrupts if we are polling. 2144 */ 2145 if (ifp->if_capenable & IFCAP_POLLING) 2146 CSR_WRITE_2(sc, VR_IMR, 0); 2147 else 2148 #endif 2149 /* 2150 * Enable interrupts and disable MII intrs. 2151 */ 2152 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2153 if (sc->vr_revid > REV_ID_VT6102_A) 2154 CSR_WRITE_2(sc, VR_MII_IMR, 0); 2155 2156 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2157 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2158 2159 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2160 mii_mediachg(mii); 2161 2162 callout_reset(&sc->vr_stat_callout, hz, vr_tick, sc); 2163 } 2164 2165 /* 2166 * Set media options. 2167 */ 2168 static int 2169 vr_ifmedia_upd(struct ifnet *ifp) 2170 { 2171 struct vr_softc *sc; 2172 struct mii_data *mii; 2173 struct mii_softc *miisc; 2174 int error; 2175 2176 sc = ifp->if_softc; 2177 VR_LOCK(sc); 2178 mii = device_get_softc(sc->vr_miibus); 2179 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2180 PHY_RESET(miisc); 2181 sc->vr_flags &= ~(VR_F_LINK | VR_F_TXPAUSE); 2182 error = mii_mediachg(mii); 2183 VR_UNLOCK(sc); 2184 2185 return (error); 2186 } 2187 2188 /* 2189 * Report current media status. 2190 */ 2191 static void 2192 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2193 { 2194 struct vr_softc *sc; 2195 struct mii_data *mii; 2196 2197 sc = ifp->if_softc; 2198 mii = device_get_softc(sc->vr_miibus); 2199 VR_LOCK(sc); 2200 if ((ifp->if_flags & IFF_UP) == 0) { 2201 VR_UNLOCK(sc); 2202 return; 2203 } 2204 mii_pollstat(mii); 2205 ifmr->ifm_active = mii->mii_media_active; 2206 ifmr->ifm_status = mii->mii_media_status; 2207 VR_UNLOCK(sc); 2208 } 2209 2210 static int 2211 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2212 { 2213 struct vr_softc *sc; 2214 struct ifreq *ifr; 2215 struct mii_data *mii; 2216 int error, mask; 2217 2218 sc = ifp->if_softc; 2219 ifr = (struct ifreq *)data; 2220 error = 0; 2221 2222 switch (command) { 2223 case SIOCSIFFLAGS: 2224 VR_LOCK(sc); 2225 if (ifp->if_flags & IFF_UP) { 2226 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2227 if ((ifp->if_flags ^ sc->vr_if_flags) & 2228 (IFF_PROMISC | IFF_ALLMULTI)) 2229 vr_set_filter(sc); 2230 } else { 2231 if ((sc->vr_flags & VR_F_DETACHED) == 0) 2232 vr_init_locked(sc); 2233 } 2234 } else { 2235 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2236 vr_stop(sc); 2237 } 2238 sc->vr_if_flags = ifp->if_flags; 2239 VR_UNLOCK(sc); 2240 break; 2241 case SIOCADDMULTI: 2242 case SIOCDELMULTI: 2243 VR_LOCK(sc); 2244 vr_set_filter(sc); 2245 VR_UNLOCK(sc); 2246 break; 2247 case SIOCGIFMEDIA: 2248 case SIOCSIFMEDIA: 2249 mii = device_get_softc(sc->vr_miibus); 2250 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2251 break; 2252 case SIOCSIFCAP: 2253 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2254 #ifdef DEVICE_POLLING 2255 if (mask & IFCAP_POLLING) { 2256 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2257 error = ether_poll_register(vr_poll, ifp); 2258 if (error != 0) 2259 break; 2260 VR_LOCK(sc); 2261 /* Disable interrupts. */ 2262 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2263 ifp->if_capenable |= IFCAP_POLLING; 2264 VR_UNLOCK(sc); 2265 } else { 2266 error = ether_poll_deregister(ifp); 2267 /* Enable interrupts. */ 2268 VR_LOCK(sc); 2269 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 2270 ifp->if_capenable &= ~IFCAP_POLLING; 2271 VR_UNLOCK(sc); 2272 } 2273 } 2274 #endif /* DEVICE_POLLING */ 2275 if ((mask & IFCAP_TXCSUM) != 0 && 2276 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2277 ifp->if_capenable ^= IFCAP_TXCSUM; 2278 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2279 ifp->if_hwassist |= VR_CSUM_FEATURES; 2280 else 2281 ifp->if_hwassist &= ~VR_CSUM_FEATURES; 2282 } 2283 if ((mask & IFCAP_RXCSUM) != 0 && 2284 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 2285 ifp->if_capenable ^= IFCAP_RXCSUM; 2286 if ((mask & IFCAP_WOL_UCAST) != 0 && 2287 (ifp->if_capabilities & IFCAP_WOL_UCAST) != 0) 2288 ifp->if_capenable ^= IFCAP_WOL_UCAST; 2289 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2290 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2291 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2292 break; 2293 default: 2294 error = ether_ioctl(ifp, command, data); 2295 break; 2296 } 2297 2298 return (error); 2299 } 2300 2301 static void 2302 vr_watchdog(struct vr_softc *sc) 2303 { 2304 struct ifnet *ifp; 2305 2306 VR_LOCK_ASSERT(sc); 2307 2308 if (sc->vr_watchdog_timer == 0 || --sc->vr_watchdog_timer) 2309 return; 2310 2311 ifp = sc->vr_ifp; 2312 /* 2313 * Reclaim first as we don't request interrupt for every packets. 2314 */ 2315 vr_txeof(sc); 2316 if (sc->vr_cdata.vr_tx_cnt == 0) 2317 return; 2318 2319 if ((sc->vr_flags & VR_F_LINK) == 0) { 2320 if (bootverbose) 2321 if_printf(sc->vr_ifp, "watchdog timeout " 2322 "(missed link)\n"); 2323 ifp->if_oerrors++; 2324 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2325 vr_init_locked(sc); 2326 return; 2327 } 2328 2329 ifp->if_oerrors++; 2330 if_printf(ifp, "watchdog timeout\n"); 2331 2332 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2333 vr_init_locked(sc); 2334 2335 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2336 vr_start_locked(ifp); 2337 } 2338 2339 static void 2340 vr_tx_start(struct vr_softc *sc) 2341 { 2342 bus_addr_t addr; 2343 uint8_t cmd; 2344 2345 cmd = CSR_READ_1(sc, VR_CR0); 2346 if ((cmd & VR_CR0_TX_ON) == 0) { 2347 addr = VR_TX_RING_ADDR(sc, sc->vr_cdata.vr_tx_cons); 2348 CSR_WRITE_4(sc, VR_TXADDR, VR_ADDR_LO(addr)); 2349 cmd |= VR_CR0_TX_ON; 2350 CSR_WRITE_1(sc, VR_CR0, cmd); 2351 } 2352 if (sc->vr_cdata.vr_tx_cnt != 0) { 2353 sc->vr_watchdog_timer = 5; 2354 VR_SETBIT(sc, VR_CR0, VR_CR0_TX_GO); 2355 } 2356 } 2357 2358 static void 2359 vr_rx_start(struct vr_softc *sc) 2360 { 2361 bus_addr_t addr; 2362 uint8_t cmd; 2363 2364 cmd = CSR_READ_1(sc, VR_CR0); 2365 if ((cmd & VR_CR0_RX_ON) == 0) { 2366 addr = VR_RX_RING_ADDR(sc, sc->vr_cdata.vr_rx_cons); 2367 CSR_WRITE_4(sc, VR_RXADDR, VR_ADDR_LO(addr)); 2368 cmd |= VR_CR0_RX_ON; 2369 CSR_WRITE_1(sc, VR_CR0, cmd); 2370 } 2371 CSR_WRITE_1(sc, VR_CR0, cmd | VR_CR0_RX_GO); 2372 } 2373 2374 static int 2375 vr_tx_stop(struct vr_softc *sc) 2376 { 2377 int i; 2378 uint8_t cmd; 2379 2380 cmd = CSR_READ_1(sc, VR_CR0); 2381 if ((cmd & VR_CR0_TX_ON) != 0) { 2382 cmd &= ~VR_CR0_TX_ON; 2383 CSR_WRITE_1(sc, VR_CR0, cmd); 2384 for (i = VR_TIMEOUT; i > 0; i--) { 2385 DELAY(5); 2386 cmd = CSR_READ_1(sc, VR_CR0); 2387 if ((cmd & VR_CR0_TX_ON) == 0) 2388 break; 2389 } 2390 if (i == 0) 2391 return (ETIMEDOUT); 2392 } 2393 return (0); 2394 } 2395 2396 static int 2397 vr_rx_stop(struct vr_softc *sc) 2398 { 2399 int i; 2400 uint8_t cmd; 2401 2402 cmd = CSR_READ_1(sc, VR_CR0); 2403 if ((cmd & VR_CR0_RX_ON) != 0) { 2404 cmd &= ~VR_CR0_RX_ON; 2405 CSR_WRITE_1(sc, VR_CR0, cmd); 2406 for (i = VR_TIMEOUT; i > 0; i--) { 2407 DELAY(5); 2408 cmd = CSR_READ_1(sc, VR_CR0); 2409 if ((cmd & VR_CR0_RX_ON) == 0) 2410 break; 2411 } 2412 if (i == 0) 2413 return (ETIMEDOUT); 2414 } 2415 return (0); 2416 } 2417 2418 /* 2419 * Stop the adapter and free any mbufs allocated to the 2420 * RX and TX lists. 2421 */ 2422 static void 2423 vr_stop(struct vr_softc *sc) 2424 { 2425 struct vr_txdesc *txd; 2426 struct vr_rxdesc *rxd; 2427 struct ifnet *ifp; 2428 int i; 2429 2430 VR_LOCK_ASSERT(sc); 2431 2432 ifp = sc->vr_ifp; 2433 sc->vr_watchdog_timer = 0; 2434 2435 callout_stop(&sc->vr_stat_callout); 2436 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2437 2438 CSR_WRITE_1(sc, VR_CR0, VR_CR0_STOP); 2439 if (vr_rx_stop(sc) != 0) 2440 device_printf(sc->vr_dev, "%s: Rx shutdown error\n", __func__); 2441 if (vr_tx_stop(sc) != 0) 2442 device_printf(sc->vr_dev, "%s: Tx shutdown error\n", __func__); 2443 /* Clear pending interrupts. */ 2444 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 2445 CSR_WRITE_2(sc, VR_IMR, 0x0000); 2446 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 2447 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 2448 2449 /* 2450 * Free RX and TX mbufs still in the queues. 2451 */ 2452 for (i = 0; i < VR_RX_RING_CNT; i++) { 2453 rxd = &sc->vr_cdata.vr_rxdesc[i]; 2454 if (rxd->rx_m != NULL) { 2455 bus_dmamap_sync(sc->vr_cdata.vr_rx_tag, 2456 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2457 bus_dmamap_unload(sc->vr_cdata.vr_rx_tag, 2458 rxd->rx_dmamap); 2459 m_freem(rxd->rx_m); 2460 rxd->rx_m = NULL; 2461 } 2462 } 2463 for (i = 0; i < VR_TX_RING_CNT; i++) { 2464 txd = &sc->vr_cdata.vr_txdesc[i]; 2465 if (txd->tx_m != NULL) { 2466 bus_dmamap_sync(sc->vr_cdata.vr_tx_tag, 2467 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2468 bus_dmamap_unload(sc->vr_cdata.vr_tx_tag, 2469 txd->tx_dmamap); 2470 m_freem(txd->tx_m); 2471 txd->tx_m = NULL; 2472 } 2473 } 2474 } 2475 2476 /* 2477 * Stop all chip I/O so that the kernel's probe routines don't 2478 * get confused by errant DMAs when rebooting. 2479 */ 2480 static int 2481 vr_shutdown(device_t dev) 2482 { 2483 2484 return (vr_suspend(dev)); 2485 } 2486 2487 static int 2488 vr_suspend(device_t dev) 2489 { 2490 struct vr_softc *sc; 2491 2492 sc = device_get_softc(dev); 2493 2494 VR_LOCK(sc); 2495 vr_stop(sc); 2496 vr_setwol(sc); 2497 sc->vr_flags |= VR_F_SUSPENDED; 2498 VR_UNLOCK(sc); 2499 2500 return (0); 2501 } 2502 2503 static int 2504 vr_resume(device_t dev) 2505 { 2506 struct vr_softc *sc; 2507 struct ifnet *ifp; 2508 2509 sc = device_get_softc(dev); 2510 2511 VR_LOCK(sc); 2512 ifp = sc->vr_ifp; 2513 vr_clrwol(sc); 2514 vr_reset(sc); 2515 if (ifp->if_flags & IFF_UP) 2516 vr_init_locked(sc); 2517 2518 sc->vr_flags &= ~VR_F_SUSPENDED; 2519 VR_UNLOCK(sc); 2520 2521 return (0); 2522 } 2523 2524 static void 2525 vr_setwol(struct vr_softc *sc) 2526 { 2527 struct ifnet *ifp; 2528 int pmc; 2529 uint16_t pmstat; 2530 uint8_t v; 2531 2532 VR_LOCK_ASSERT(sc); 2533 2534 if (sc->vr_revid < REV_ID_VT6102_A || 2535 pci_find_cap(sc->vr_dev, PCIY_PMG, &pmc) != 0) 2536 return; 2537 2538 ifp = sc->vr_ifp; 2539 2540 /* Clear WOL configuration. */ 2541 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2542 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2543 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2544 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2545 if (sc->vr_revid > REV_ID_VT6105_B0) { 2546 /* Newer Rhine III supports two additional patterns. */ 2547 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2548 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2549 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2550 } 2551 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 2552 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_UCAST); 2553 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2554 CSR_WRITE_1(sc, VR_WOLCR_SET, VR_WOLCR_MAGIC); 2555 /* 2556 * It seems that multicast wakeup frames require programming pattern 2557 * registers and valid CRC as well as pattern mask for each pattern. 2558 * While it's possible to setup such a pattern it would complicate 2559 * WOL configuration so ignore multicast wakeup frames. 2560 */ 2561 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2562 CSR_WRITE_1(sc, VR_WOLCFG_SET, VR_WOLCFG_SAB | VR_WOLCFG_SAM); 2563 v = CSR_READ_1(sc, VR_STICKHW); 2564 CSR_WRITE_1(sc, VR_STICKHW, v | VR_STICKHW_WOL_ENB); 2565 CSR_WRITE_1(sc, VR_PWRCFG_SET, VR_PWRCFG_WOLEN); 2566 } 2567 2568 /* Put hardware into sleep. */ 2569 v = CSR_READ_1(sc, VR_STICKHW); 2570 v |= VR_STICKHW_DS0 | VR_STICKHW_DS1; 2571 CSR_WRITE_1(sc, VR_STICKHW, v); 2572 2573 /* Request PME if WOL is requested. */ 2574 pmstat = pci_read_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, 2); 2575 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2576 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2577 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2578 pci_write_config(sc->vr_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2579 } 2580 2581 static void 2582 vr_clrwol(struct vr_softc *sc) 2583 { 2584 uint8_t v; 2585 2586 VR_LOCK_ASSERT(sc); 2587 2588 if (sc->vr_revid < REV_ID_VT6102_A) 2589 return; 2590 2591 /* Take hardware out of sleep. */ 2592 v = CSR_READ_1(sc, VR_STICKHW); 2593 v &= ~(VR_STICKHW_DS0 | VR_STICKHW_DS1 | VR_STICKHW_WOL_ENB); 2594 CSR_WRITE_1(sc, VR_STICKHW, v); 2595 2596 /* Clear WOL configuration as WOL may interfere normal operation. */ 2597 CSR_WRITE_1(sc, VR_WOLCR_CLR, 0xFF); 2598 CSR_WRITE_1(sc, VR_WOLCFG_CLR, 2599 VR_WOLCFG_SAB | VR_WOLCFG_SAM | VR_WOLCFG_PMEOVR); 2600 CSR_WRITE_1(sc, VR_PWRCSR_CLR, 0xFF); 2601 CSR_WRITE_1(sc, VR_PWRCFG_CLR, VR_PWRCFG_WOLEN); 2602 if (sc->vr_revid > REV_ID_VT6105_B0) { 2603 /* Newer Rhine III supports two additional patterns. */ 2604 CSR_WRITE_1(sc, VR_WOLCFG_CLR, VR_WOLCFG_PATTERN_PAGE); 2605 CSR_WRITE_1(sc, VR_TESTREG_CLR, 3); 2606 CSR_WRITE_1(sc, VR_PWRCSR1_CLR, 3); 2607 } 2608 } 2609 2610 static int 2611 vr_sysctl_stats(SYSCTL_HANDLER_ARGS) 2612 { 2613 struct vr_softc *sc; 2614 struct vr_statistics *stat; 2615 int error; 2616 int result; 2617 2618 result = -1; 2619 error = sysctl_handle_int(oidp, &result, 0, req); 2620 2621 if (error != 0 || req->newptr == NULL) 2622 return (error); 2623 2624 if (result == 1) { 2625 sc = (struct vr_softc *)arg1; 2626 stat = &sc->vr_stat; 2627 2628 printf("%s statistics:\n", device_get_nameunit(sc->vr_dev)); 2629 printf("Outbound good frames : %ju\n", 2630 (uintmax_t)stat->tx_ok); 2631 printf("Inbound good frames : %ju\n", 2632 (uintmax_t)stat->rx_ok); 2633 printf("Outbound errors : %u\n", stat->tx_errors); 2634 printf("Inbound errors : %u\n", stat->rx_errors); 2635 printf("Inbound no buffers : %u\n", stat->rx_no_buffers); 2636 printf("Inbound no mbuf clusters: %d\n", stat->rx_no_mbufs); 2637 printf("Inbound FIFO overflows : %d\n", 2638 stat->rx_fifo_overflows); 2639 printf("Inbound CRC errors : %u\n", stat->rx_crc_errors); 2640 printf("Inbound frame alignment errors : %u\n", 2641 stat->rx_alignment); 2642 printf("Inbound giant frames : %u\n", stat->rx_giants); 2643 printf("Inbound runt frames : %u\n", stat->rx_runts); 2644 printf("Outbound aborted with excessive collisions : %u\n", 2645 stat->tx_abort); 2646 printf("Outbound collisions : %u\n", stat->tx_collisions); 2647 printf("Outbound late collisions : %u\n", 2648 stat->tx_late_collisions); 2649 printf("Outbound underrun : %u\n", stat->tx_underrun); 2650 printf("PCI bus errors : %u\n", stat->bus_errors); 2651 printf("driver restarted due to Rx/Tx shutdown failure : %u\n", 2652 stat->num_restart); 2653 } 2654 2655 return (error); 2656 } 2657