1 /* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Rhine fast ethernet PCI NIC driver 38 * 39 * Supports various network adapters based on the VIA Rhine 40 * and Rhine II PCI controllers, including the D-Link DFE530TX. 41 * Datasheets are available at http://www.via.com.tw. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47 48 /* 49 * The VIA Rhine controllers are similar in some respects to the 50 * the DEC tulip chips, except less complicated. The controller 51 * uses an MII bus and an external physical layer interface. The 52 * receiver has a one entry perfect filter and a 64-bit hash table 53 * multicast filter. Transmit and receive descriptors are similar 54 * to the tulip. 55 * 56 * The Rhine has a serious flaw in its transmit DMA mechanism: 57 * transmit buffers must be longword aligned. Unfortunately, 58 * FreeBSD doesn't guarantee that mbufs will be filled in starting 59 * at longword boundaries, so we have to do a buffer copy before 60 * transmission. 61 */ 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/sockio.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/kernel.h> 69 #include <sys/module.h> 70 #include <sys/socket.h> 71 72 #include <net/if.h> 73 #include <net/if_arp.h> 74 #include <net/ethernet.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 78 #include <net/bpf.h> 79 80 #include <vm/vm.h> /* for vtophys */ 81 #include <vm/pmap.h> /* for vtophys */ 82 #include <machine/bus_pio.h> 83 #include <machine/bus_memio.h> 84 #include <machine/bus.h> 85 #include <machine/resource.h> 86 #include <sys/bus.h> 87 #include <sys/rman.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #define VR_USEIOSPACE 96 97 #include <pci/if_vrreg.h> 98 99 MODULE_DEPEND(vr, pci, 1, 1, 1); 100 MODULE_DEPEND(vr, ether, 1, 1, 1); 101 MODULE_DEPEND(vr, miibus, 1, 1, 1); 102 103 /* "controller miibus0" required. See GENERIC if you get errors here. */ 104 #include "miibus_if.h" 105 106 #undef VR_USESWSHIFT 107 108 /* 109 * Various supported device vendors/types and their names. 110 */ 111 static struct vr_type vr_devs[] = { 112 { VIA_VENDORID, VIA_DEVICEID_RHINE, 113 "VIA VT3043 Rhine I 10/100BaseTX" }, 114 { VIA_VENDORID, VIA_DEVICEID_RHINE_II, 115 "VIA VT86C100A Rhine II 10/100BaseTX" }, 116 { VIA_VENDORID, VIA_DEVICEID_RHINE_II_2, 117 "VIA VT6102 Rhine II 10/100BaseTX" }, 118 { VIA_VENDORID, VIA_DEVICEID_RHINE_III, 119 "VIA VT6105 Rhine III 10/100BaseTX" }, 120 { VIA_VENDORID, VIA_DEVICEID_RHINE_III_M, 121 "VIA VT6105M Rhine III 10/100BaseTX" }, 122 { DELTA_VENDORID, DELTA_DEVICEID_RHINE_II, 123 "Delta Electronics Rhine II 10/100BaseTX" }, 124 { ADDTRON_VENDORID, ADDTRON_DEVICEID_RHINE_II, 125 "Addtron Technology Rhine II 10/100BaseTX" }, 126 { 0, 0, NULL } 127 }; 128 129 static int vr_probe (device_t); 130 static int vr_attach (device_t); 131 static int vr_detach (device_t); 132 133 static int vr_newbuf (struct vr_softc *, 134 struct vr_chain_onefrag *, 135 struct mbuf *); 136 static int vr_encap (struct vr_softc *, struct vr_chain *, 137 struct mbuf * ); 138 139 static void vr_rxeof (struct vr_softc *); 140 static void vr_rxeoc (struct vr_softc *); 141 static void vr_txeof (struct vr_softc *); 142 static void vr_tick (void *); 143 static void vr_intr (void *); 144 static void vr_start (struct ifnet *); 145 static int vr_ioctl (struct ifnet *, u_long, caddr_t); 146 static void vr_init (void *); 147 static void vr_stop (struct vr_softc *); 148 static void vr_watchdog (struct ifnet *); 149 static void vr_shutdown (device_t); 150 static int vr_ifmedia_upd (struct ifnet *); 151 static void vr_ifmedia_sts (struct ifnet *, struct ifmediareq *); 152 153 #ifdef VR_USESWSHIFT 154 static void vr_mii_sync (struct vr_softc *); 155 static void vr_mii_send (struct vr_softc *, uint32_t, int); 156 #endif 157 static int vr_mii_readreg (struct vr_softc *, struct vr_mii_frame *); 158 static int vr_mii_writereg (struct vr_softc *, struct vr_mii_frame *); 159 static int vr_miibus_readreg (device_t, uint16_t, uint16_t); 160 static int vr_miibus_writereg (device_t, uint16_t, uint16_t, uint16_t); 161 static void vr_miibus_statchg (device_t); 162 163 static void vr_setcfg (struct vr_softc *, int); 164 static void vr_setmulti (struct vr_softc *); 165 static void vr_reset (struct vr_softc *); 166 static int vr_list_rx_init (struct vr_softc *); 167 static int vr_list_tx_init (struct vr_softc *); 168 169 #ifdef VR_USEIOSPACE 170 #define VR_RES SYS_RES_IOPORT 171 #define VR_RID VR_PCI_LOIO 172 #else 173 #define VR_RES SYS_RES_MEMORY 174 #define VR_RID VR_PCI_LOMEM 175 #endif 176 177 static device_method_t vr_methods[] = { 178 /* Device interface */ 179 DEVMETHOD(device_probe, vr_probe), 180 DEVMETHOD(device_attach, vr_attach), 181 DEVMETHOD(device_detach, vr_detach), 182 DEVMETHOD(device_shutdown, vr_shutdown), 183 184 /* bus interface */ 185 DEVMETHOD(bus_print_child, bus_generic_print_child), 186 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 187 188 /* MII interface */ 189 DEVMETHOD(miibus_readreg, vr_miibus_readreg), 190 DEVMETHOD(miibus_writereg, vr_miibus_writereg), 191 DEVMETHOD(miibus_statchg, vr_miibus_statchg), 192 193 { 0, 0 } 194 }; 195 196 static driver_t vr_driver = { 197 "vr", 198 vr_methods, 199 sizeof(struct vr_softc) 200 }; 201 202 static devclass_t vr_devclass; 203 204 DRIVER_MODULE(vr, pci, vr_driver, vr_devclass, 0, 0); 205 DRIVER_MODULE(miibus, vr, miibus_driver, miibus_devclass, 0, 0); 206 207 #define VR_SETBIT(sc, reg, x) \ 208 CSR_WRITE_1(sc, reg, \ 209 CSR_READ_1(sc, reg) | (x)) 210 211 #define VR_CLRBIT(sc, reg, x) \ 212 CSR_WRITE_1(sc, reg, \ 213 CSR_READ_1(sc, reg) & ~(x)) 214 215 #define VR_SETBIT16(sc, reg, x) \ 216 CSR_WRITE_2(sc, reg, \ 217 CSR_READ_2(sc, reg) | (x)) 218 219 #define VR_CLRBIT16(sc, reg, x) \ 220 CSR_WRITE_2(sc, reg, \ 221 CSR_READ_2(sc, reg) & ~(x)) 222 223 #define VR_SETBIT32(sc, reg, x) \ 224 CSR_WRITE_4(sc, reg, \ 225 CSR_READ_4(sc, reg) | (x)) 226 227 #define VR_CLRBIT32(sc, reg, x) \ 228 CSR_WRITE_4(sc, reg, \ 229 CSR_READ_4(sc, reg) & ~(x)) 230 231 #define SIO_SET(x) \ 232 CSR_WRITE_1(sc, VR_MIICMD, \ 233 CSR_READ_1(sc, VR_MIICMD) | (x)) 234 235 #define SIO_CLR(x) \ 236 CSR_WRITE_1(sc, VR_MIICMD, \ 237 CSR_READ_1(sc, VR_MIICMD) & ~(x)) 238 239 #ifdef VR_USESWSHIFT 240 /* 241 * Sync the PHYs by setting data bit and strobing the clock 32 times. 242 */ 243 static void 244 vr_mii_sync(struct vr_softc *sc) 245 { 246 register int i; 247 248 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN); 249 250 for (i = 0; i < 32; i++) { 251 SIO_SET(VR_MIICMD_CLK); 252 DELAY(1); 253 SIO_CLR(VR_MIICMD_CLK); 254 DELAY(1); 255 } 256 } 257 258 /* 259 * Clock a series of bits through the MII. 260 */ 261 static void 262 vr_mii_send(struct vr_softc *sc, uint32_t bits, int cnt) 263 { 264 int i; 265 266 SIO_CLR(VR_MIICMD_CLK); 267 268 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 269 if (bits & i) { 270 SIO_SET(VR_MIICMD_DATAIN); 271 } else { 272 SIO_CLR(VR_MIICMD_DATAIN); 273 } 274 DELAY(1); 275 SIO_CLR(VR_MIICMD_CLK); 276 DELAY(1); 277 SIO_SET(VR_MIICMD_CLK); 278 } 279 } 280 #endif 281 282 /* 283 * Read an PHY register through the MII. 284 */ 285 static int 286 vr_mii_readreg(struct vr_softc *sc, struct vr_mii_frame *frame) 287 #ifdef VR_USESWSHIFT 288 { 289 int i, ack; 290 291 /* Set up frame for RX. */ 292 frame->mii_stdelim = VR_MII_STARTDELIM; 293 frame->mii_opcode = VR_MII_READOP; 294 frame->mii_turnaround = 0; 295 frame->mii_data = 0; 296 297 CSR_WRITE_1(sc, VR_MIICMD, 0); 298 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 299 300 /* Turn on data xmit. */ 301 SIO_SET(VR_MIICMD_DIR); 302 303 vr_mii_sync(sc); 304 305 /* Send command/address info. */ 306 vr_mii_send(sc, frame->mii_stdelim, 2); 307 vr_mii_send(sc, frame->mii_opcode, 2); 308 vr_mii_send(sc, frame->mii_phyaddr, 5); 309 vr_mii_send(sc, frame->mii_regaddr, 5); 310 311 /* Idle bit. */ 312 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN)); 313 DELAY(1); 314 SIO_SET(VR_MIICMD_CLK); 315 DELAY(1); 316 317 /* Turn off xmit. */ 318 SIO_CLR(VR_MIICMD_DIR); 319 320 /* Check for ack */ 321 SIO_CLR(VR_MIICMD_CLK); 322 DELAY(1); 323 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT; 324 SIO_SET(VR_MIICMD_CLK); 325 DELAY(1); 326 327 /* 328 * Now try reading data bits. If the ack failed, we still 329 * need to clock through 16 cycles to keep the PHY(s) in sync. 330 */ 331 if (ack) { 332 for(i = 0; i < 16; i++) { 333 SIO_CLR(VR_MIICMD_CLK); 334 DELAY(1); 335 SIO_SET(VR_MIICMD_CLK); 336 DELAY(1); 337 } 338 goto fail; 339 } 340 341 for (i = 0x8000; i; i >>= 1) { 342 SIO_CLR(VR_MIICMD_CLK); 343 DELAY(1); 344 if (!ack) { 345 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT) 346 frame->mii_data |= i; 347 DELAY(1); 348 } 349 SIO_SET(VR_MIICMD_CLK); 350 DELAY(1); 351 } 352 353 fail: 354 SIO_CLR(VR_MIICMD_CLK); 355 DELAY(1); 356 SIO_SET(VR_MIICMD_CLK); 357 DELAY(1); 358 359 if (ack) 360 return (1); 361 return (0); 362 } 363 #else 364 { 365 int i; 366 367 /* Set the PHY address. */ 368 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 369 frame->mii_phyaddr); 370 371 /* Set the register address. */ 372 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 373 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB); 374 375 for (i = 0; i < 10000; i++) { 376 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0) 377 break; 378 DELAY(1); 379 } 380 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA); 381 382 return (0); 383 } 384 #endif 385 386 387 /* 388 * Write to a PHY register through the MII. 389 */ 390 static int 391 vr_mii_writereg(struct vr_softc *sc, struct vr_mii_frame *frame) 392 #ifdef VR_USESWSHIFT 393 { 394 CSR_WRITE_1(sc, VR_MIICMD, 0); 395 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM); 396 397 /* Set up frame for TX. */ 398 frame->mii_stdelim = VR_MII_STARTDELIM; 399 frame->mii_opcode = VR_MII_WRITEOP; 400 frame->mii_turnaround = VR_MII_TURNAROUND; 401 402 /* Turn on data output. */ 403 SIO_SET(VR_MIICMD_DIR); 404 405 vr_mii_sync(sc); 406 407 vr_mii_send(sc, frame->mii_stdelim, 2); 408 vr_mii_send(sc, frame->mii_opcode, 2); 409 vr_mii_send(sc, frame->mii_phyaddr, 5); 410 vr_mii_send(sc, frame->mii_regaddr, 5); 411 vr_mii_send(sc, frame->mii_turnaround, 2); 412 vr_mii_send(sc, frame->mii_data, 16); 413 414 /* Idle bit. */ 415 SIO_SET(VR_MIICMD_CLK); 416 DELAY(1); 417 SIO_CLR(VR_MIICMD_CLK); 418 DELAY(1); 419 420 /* Turn off xmit. */ 421 SIO_CLR(VR_MIICMD_DIR); 422 423 return (0); 424 } 425 #else 426 { 427 int i; 428 429 /* Set the PHY address. */ 430 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)| 431 frame->mii_phyaddr); 432 433 /* Set the register address and data to write. */ 434 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr); 435 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data); 436 437 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB); 438 439 for (i = 0; i < 10000; i++) { 440 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0) 441 break; 442 DELAY(1); 443 } 444 445 return (0); 446 } 447 #endif 448 449 static int 450 vr_miibus_readreg(device_t dev, uint16_t phy, uint16_t reg) 451 { 452 struct vr_mii_frame frame; 453 struct vr_softc *sc = device_get_softc(dev); 454 455 switch (sc->vr_revid) { 456 case REV_ID_VT6102_APOLLO: 457 if (phy != 1) { 458 frame.mii_data = 0; 459 goto out; 460 } 461 default: 462 break; 463 } 464 465 bzero((char *)&frame, sizeof(frame)); 466 frame.mii_phyaddr = phy; 467 frame.mii_regaddr = reg; 468 vr_mii_readreg(sc, &frame); 469 470 out: 471 return (frame.mii_data); 472 } 473 474 static int 475 vr_miibus_writereg(device_t dev, uint16_t phy, uint16_t reg, uint16_t data) 476 { 477 struct vr_mii_frame frame; 478 struct vr_softc *sc = device_get_softc(dev); 479 480 switch (sc->vr_revid) { 481 case REV_ID_VT6102_APOLLO: 482 if (phy != 1) 483 return (0); 484 default: 485 break; 486 } 487 488 bzero((char *)&frame, sizeof(frame)); 489 frame.mii_phyaddr = phy; 490 frame.mii_regaddr = reg; 491 frame.mii_data = data; 492 vr_mii_writereg(sc, &frame); 493 494 return (0); 495 } 496 497 static void 498 vr_miibus_statchg(device_t dev) 499 { 500 struct mii_data *mii; 501 struct vr_softc *sc = device_get_softc(dev); 502 503 mii = device_get_softc(sc->vr_miibus); 504 vr_setcfg(sc, mii->mii_media_active); 505 } 506 507 /* 508 * Program the 64-bit multicast hash filter. 509 */ 510 static void 511 vr_setmulti(struct vr_softc *sc) 512 { 513 struct ifnet *ifp = &sc->arpcom.ac_if; 514 int h = 0; 515 uint32_t hashes[2] = { 0, 0 }; 516 struct ifmultiaddr *ifma; 517 uint8_t rxfilt; 518 int mcnt = 0; 519 520 VR_LOCK_ASSERT(sc); 521 522 rxfilt = CSR_READ_1(sc, VR_RXCFG); 523 524 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 525 rxfilt |= VR_RXCFG_RX_MULTI; 526 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 527 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF); 528 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF); 529 return; 530 } 531 532 /* First, zero out all the existing hash bits. */ 533 CSR_WRITE_4(sc, VR_MAR0, 0); 534 CSR_WRITE_4(sc, VR_MAR1, 0); 535 536 /* Now program new ones. */ 537 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 538 if (ifma->ifma_addr->sa_family != AF_LINK) 539 continue; 540 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 541 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 542 if (h < 32) 543 hashes[0] |= (1 << h); 544 else 545 hashes[1] |= (1 << (h - 32)); 546 mcnt++; 547 } 548 549 if (mcnt) 550 rxfilt |= VR_RXCFG_RX_MULTI; 551 else 552 rxfilt &= ~VR_RXCFG_RX_MULTI; 553 554 CSR_WRITE_4(sc, VR_MAR0, hashes[0]); 555 CSR_WRITE_4(sc, VR_MAR1, hashes[1]); 556 CSR_WRITE_1(sc, VR_RXCFG, rxfilt); 557 } 558 559 /* 560 * In order to fiddle with the 561 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 562 * first have to put the transmit and/or receive logic in the idle state. 563 */ 564 static void 565 vr_setcfg(struct vr_softc *sc, int media) 566 { 567 int restart = 0; 568 569 VR_LOCK_ASSERT(sc); 570 571 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) { 572 restart = 1; 573 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON)); 574 } 575 576 if ((media & IFM_GMASK) == IFM_FDX) 577 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 578 else 579 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX); 580 581 if (restart) 582 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON); 583 } 584 585 static void 586 vr_reset(struct vr_softc *sc) 587 { 588 register int i; 589 590 VR_LOCK_ASSERT(sc); 591 592 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET); 593 594 for (i = 0; i < VR_TIMEOUT; i++) { 595 DELAY(10); 596 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET)) 597 break; 598 } 599 if (i == VR_TIMEOUT) { 600 if (sc->vr_revid < REV_ID_VT3065_A) 601 printf("vr%d: reset never completed!\n", sc->vr_unit); 602 else { 603 /* Use newer force reset command */ 604 printf("vr%d: Using force reset command.\n", 605 sc->vr_unit); 606 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST); 607 } 608 } 609 610 /* Wait a little while for the chip to get its brains in order. */ 611 DELAY(1000); 612 } 613 614 /* 615 * Probe for a VIA Rhine chip. Check the PCI vendor and device 616 * IDs against our list and return a device name if we find a match. 617 */ 618 static int 619 vr_probe(device_t dev) 620 { 621 struct vr_type *t = vr_devs; 622 623 while (t->vr_name != NULL) { 624 if ((pci_get_vendor(dev) == t->vr_vid) && 625 (pci_get_device(dev) == t->vr_did)) { 626 device_set_desc(dev, t->vr_name); 627 return (0); 628 } 629 t++; 630 } 631 632 return (ENXIO); 633 } 634 635 /* 636 * Attach the interface. Allocate softc structures, do ifmedia 637 * setup and ethernet/BPF attach. 638 */ 639 static int 640 vr_attach(dev) 641 device_t dev; 642 { 643 int i; 644 u_char eaddr[ETHER_ADDR_LEN]; 645 struct vr_softc *sc; 646 struct ifnet *ifp; 647 int unit, error = 0, rid; 648 649 sc = device_get_softc(dev); 650 unit = device_get_unit(dev); 651 652 mtx_init(&sc->vr_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 653 MTX_DEF); 654 /* 655 * Map control/status registers. 656 */ 657 pci_enable_busmaster(dev); 658 sc->vr_revid = pci_read_config(dev, VR_PCI_REVID, 4) & 0x000000FF; 659 660 rid = VR_RID; 661 sc->vr_res = bus_alloc_resource_any(dev, VR_RES, &rid, RF_ACTIVE); 662 663 if (sc->vr_res == NULL) { 664 printf("vr%d: couldn't map ports/memory\n", unit); 665 error = ENXIO; 666 goto fail; 667 } 668 669 sc->vr_btag = rman_get_bustag(sc->vr_res); 670 sc->vr_bhandle = rman_get_bushandle(sc->vr_res); 671 672 /* Allocate interrupt */ 673 rid = 0; 674 sc->vr_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 675 RF_SHAREABLE | RF_ACTIVE); 676 677 if (sc->vr_irq == NULL) { 678 printf("vr%d: couldn't map interrupt\n", unit); 679 error = ENXIO; 680 goto fail; 681 } 682 683 /* 684 * Windows may put the chip in suspend mode when it 685 * shuts down. Be sure to kick it in the head to wake it 686 * up again. 687 */ 688 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1)); 689 690 /* Reset the adapter. */ 691 VR_LOCK(sc); 692 vr_reset(sc); 693 VR_UNLOCK(sc); 694 695 /* 696 * Turn on bit2 (MIION) in PCI configuration register 0x53 during 697 * initialization and disable AUTOPOLL. 698 */ 699 pci_write_config(dev, VR_PCI_MODE, 700 pci_read_config(dev, VR_PCI_MODE, 4) | (VR_MODE3_MIION << 24), 4); 701 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL); 702 703 /* 704 * Get station address. The way the Rhine chips work, 705 * you're not allowed to directly access the EEPROM once 706 * they've been programmed a special way. Consequently, 707 * we need to read the node address from the PAR0 and PAR1 708 * registers. 709 */ 710 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD); 711 DELAY(200); 712 for (i = 0; i < ETHER_ADDR_LEN; i++) 713 eaddr[i] = CSR_READ_1(sc, VR_PAR0 + i); 714 715 sc->vr_unit = unit; 716 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 717 718 sc->vr_ldata = contigmalloc(sizeof(struct vr_list_data), M_DEVBUF, 719 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 720 721 if (sc->vr_ldata == NULL) { 722 printf("vr%d: no memory for list buffers!\n", unit); 723 error = ENXIO; 724 goto fail; 725 } 726 727 bzero(sc->vr_ldata, sizeof(struct vr_list_data)); 728 729 ifp = &sc->arpcom.ac_if; 730 ifp->if_softc = sc; 731 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 732 ifp->if_mtu = ETHERMTU; 733 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 734 ifp->if_ioctl = vr_ioctl; 735 ifp->if_start = vr_start; 736 ifp->if_watchdog = vr_watchdog; 737 ifp->if_init = vr_init; 738 ifp->if_baudrate = 10000000; 739 ifp->if_snd.ifq_maxlen = VR_TX_LIST_CNT - 1; 740 #ifdef DEVICE_POLLING 741 ifp->if_capabilities |= IFCAP_POLLING; 742 #endif 743 ifp->if_capenable = ifp->if_capabilities; 744 745 /* Do MII setup. */ 746 if (mii_phy_probe(dev, &sc->vr_miibus, 747 vr_ifmedia_upd, vr_ifmedia_sts)) { 748 printf("vr%d: MII without any phy!\n", sc->vr_unit); 749 error = ENXIO; 750 goto fail; 751 } 752 753 callout_handle_init(&sc->vr_stat_ch); 754 755 /* Call MI attach routine. */ 756 ether_ifattach(ifp, eaddr); 757 758 /* Hook interrupt last to avoid having to lock softc */ 759 error = bus_setup_intr(dev, sc->vr_irq, INTR_TYPE_NET | INTR_MPSAFE, 760 vr_intr, sc, &sc->vr_intrhand); 761 762 if (error) { 763 printf("vr%d: couldn't set up irq\n", unit); 764 ether_ifdetach(ifp); 765 goto fail; 766 } 767 768 fail: 769 if (error) 770 vr_detach(dev); 771 772 return (error); 773 } 774 775 /* 776 * Shutdown hardware and free up resources. This can be called any 777 * time after the mutex has been initialized. It is called in both 778 * the error case in attach and the normal detach case so it needs 779 * to be careful about only freeing resources that have actually been 780 * allocated. 781 */ 782 static int 783 vr_detach(device_t dev) 784 { 785 struct vr_softc *sc = device_get_softc(dev); 786 struct ifnet *ifp = &sc->arpcom.ac_if; 787 788 KASSERT(mtx_initialized(&sc->vr_mtx), ("vr mutex not initialized")); 789 790 VR_LOCK(sc); 791 792 /* These should only be active if attach succeeded */ 793 if (device_is_attached(dev)) { 794 vr_stop(sc); 795 ether_ifdetach(ifp); 796 } 797 if (sc->vr_miibus) 798 device_delete_child(dev, sc->vr_miibus); 799 bus_generic_detach(dev); 800 801 if (sc->vr_intrhand) 802 bus_teardown_intr(dev, sc->vr_irq, sc->vr_intrhand); 803 if (sc->vr_irq) 804 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vr_irq); 805 if (sc->vr_res) 806 bus_release_resource(dev, VR_RES, VR_RID, sc->vr_res); 807 808 if (sc->vr_ldata) 809 contigfree(sc->vr_ldata, sizeof(struct vr_list_data), M_DEVBUF); 810 811 VR_UNLOCK(sc); 812 mtx_destroy(&sc->vr_mtx); 813 814 return (0); 815 } 816 817 /* 818 * Initialize the transmit descriptors. 819 */ 820 static int 821 vr_list_tx_init(struct vr_softc *sc) 822 { 823 struct vr_chain_data *cd; 824 struct vr_list_data *ld; 825 int i; 826 827 cd = &sc->vr_cdata; 828 ld = sc->vr_ldata; 829 for (i = 0; i < VR_TX_LIST_CNT; i++) { 830 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i]; 831 if (i == (VR_TX_LIST_CNT - 1)) 832 cd->vr_tx_chain[i].vr_nextdesc = 833 &cd->vr_tx_chain[0]; 834 else 835 cd->vr_tx_chain[i].vr_nextdesc = 836 &cd->vr_tx_chain[i + 1]; 837 } 838 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0]; 839 840 return (0); 841 } 842 843 844 /* 845 * Initialize the RX descriptors and allocate mbufs for them. Note that 846 * we arrange the descriptors in a closed ring, so that the last descriptor 847 * points back to the first. 848 */ 849 static int 850 vr_list_rx_init(struct vr_softc *sc) 851 { 852 struct vr_chain_data *cd; 853 struct vr_list_data *ld; 854 int i; 855 856 VR_LOCK_ASSERT(sc); 857 858 cd = &sc->vr_cdata; 859 ld = sc->vr_ldata; 860 861 for (i = 0; i < VR_RX_LIST_CNT; i++) { 862 cd->vr_rx_chain[i].vr_ptr = 863 (struct vr_desc *)&ld->vr_rx_list[i]; 864 if (vr_newbuf(sc, &cd->vr_rx_chain[i], NULL) == ENOBUFS) 865 return (ENOBUFS); 866 if (i == (VR_RX_LIST_CNT - 1)) { 867 cd->vr_rx_chain[i].vr_nextdesc = 868 &cd->vr_rx_chain[0]; 869 ld->vr_rx_list[i].vr_next = 870 vtophys(&ld->vr_rx_list[0]); 871 } else { 872 cd->vr_rx_chain[i].vr_nextdesc = 873 &cd->vr_rx_chain[i + 1]; 874 ld->vr_rx_list[i].vr_next = 875 vtophys(&ld->vr_rx_list[i + 1]); 876 } 877 } 878 879 cd->vr_rx_head = &cd->vr_rx_chain[0]; 880 881 return (0); 882 } 883 884 /* 885 * Initialize an RX descriptor and attach an MBUF cluster. 886 * Note: the length fields are only 11 bits wide, which means the 887 * largest size we can specify is 2047. This is important because 888 * MCLBYTES is 2048, so we have to subtract one otherwise we'll 889 * overflow the field and make a mess. 890 */ 891 static int 892 vr_newbuf(struct vr_softc *sc, struct vr_chain_onefrag *c, struct mbuf *m) 893 { 894 struct mbuf *m_new = NULL; 895 896 if (m == NULL) { 897 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 898 if (m_new == NULL) 899 return (ENOBUFS); 900 901 MCLGET(m_new, M_DONTWAIT); 902 if (!(m_new->m_flags & M_EXT)) { 903 m_freem(m_new); 904 return (ENOBUFS); 905 } 906 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 907 } else { 908 m_new = m; 909 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 910 m_new->m_data = m_new->m_ext.ext_buf; 911 } 912 913 m_adj(m_new, sizeof(uint64_t)); 914 915 c->vr_mbuf = m_new; 916 c->vr_ptr->vr_status = VR_RXSTAT; 917 c->vr_ptr->vr_data = vtophys(mtod(m_new, caddr_t)); 918 c->vr_ptr->vr_ctl = VR_RXCTL | VR_RXLEN; 919 920 return (0); 921 } 922 923 /* 924 * A frame has been uploaded: pass the resulting mbuf chain up to 925 * the higher level protocols. 926 */ 927 static void 928 vr_rxeof(struct vr_softc *sc) 929 { 930 struct mbuf *m, *m0; 931 struct ifnet *ifp; 932 struct vr_chain_onefrag *cur_rx; 933 int total_len = 0; 934 uint32_t rxstat; 935 936 VR_LOCK_ASSERT(sc); 937 ifp = &sc->arpcom.ac_if; 938 939 while (!((rxstat = sc->vr_cdata.vr_rx_head->vr_ptr->vr_status) & 940 VR_RXSTAT_OWN)) { 941 #ifdef DEVICE_POLLING 942 if (ifp->if_flags & IFF_POLLING) { 943 if (sc->rxcycles <= 0) 944 break; 945 sc->rxcycles--; 946 } 947 #endif /* DEVICE_POLLING */ 948 m0 = NULL; 949 cur_rx = sc->vr_cdata.vr_rx_head; 950 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc; 951 m = cur_rx->vr_mbuf; 952 953 /* 954 * If an error occurs, update stats, clear the 955 * status word and leave the mbuf cluster in place: 956 * it should simply get re-used next time this descriptor 957 * comes up in the ring. 958 */ 959 if (rxstat & VR_RXSTAT_RXERR) { 960 ifp->if_ierrors++; 961 printf("vr%d: rx error (%02x):", sc->vr_unit, 962 rxstat & 0x000000ff); 963 if (rxstat & VR_RXSTAT_CRCERR) 964 printf(" crc error"); 965 if (rxstat & VR_RXSTAT_FRAMEALIGNERR) 966 printf(" frame alignment error\n"); 967 if (rxstat & VR_RXSTAT_FIFOOFLOW) 968 printf(" FIFO overflow"); 969 if (rxstat & VR_RXSTAT_GIANT) 970 printf(" received giant packet"); 971 if (rxstat & VR_RXSTAT_RUNT) 972 printf(" received runt packet"); 973 if (rxstat & VR_RXSTAT_BUSERR) 974 printf(" system bus error"); 975 if (rxstat & VR_RXSTAT_BUFFERR) 976 printf("rx buffer error"); 977 printf("\n"); 978 vr_newbuf(sc, cur_rx, m); 979 continue; 980 } 981 982 /* No errors; receive the packet. */ 983 total_len = VR_RXBYTES(cur_rx->vr_ptr->vr_status); 984 985 /* 986 * XXX The VIA Rhine chip includes the CRC with every 987 * received frame, and there's no way to turn this 988 * behavior off (at least, I can't find anything in 989 * the manual that explains how to do it) so we have 990 * to trim off the CRC manually. 991 */ 992 total_len -= ETHER_CRC_LEN; 993 994 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 995 NULL); 996 vr_newbuf(sc, cur_rx, m); 997 if (m0 == NULL) { 998 ifp->if_ierrors++; 999 continue; 1000 } 1001 m = m0; 1002 1003 ifp->if_ipackets++; 1004 VR_UNLOCK(sc); 1005 (*ifp->if_input)(ifp, m); 1006 VR_LOCK(sc); 1007 } 1008 } 1009 1010 static void 1011 vr_rxeoc(struct vr_softc *sc) 1012 { 1013 struct ifnet *ifp = &sc->arpcom.ac_if; 1014 int i; 1015 1016 VR_LOCK_ASSERT(sc); 1017 1018 ifp->if_ierrors++; 1019 1020 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1021 DELAY(10000); 1022 1023 /* Wait for receiver to stop */ 1024 for (i = 0x400; 1025 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON); 1026 i--) { 1027 ; 1028 } 1029 1030 if (!i) { 1031 printf("vr%d: rx shutdown error!\n", sc->vr_unit); 1032 sc->vr_flags |= VR_F_RESTART; 1033 return; 1034 } 1035 1036 vr_rxeof(sc); 1037 1038 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1039 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON); 1040 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO); 1041 } 1042 1043 /* 1044 * A frame was downloaded to the chip. It's safe for us to clean up 1045 * the list buffers. 1046 */ 1047 static void 1048 vr_txeof(struct vr_softc *sc) 1049 { 1050 struct vr_chain *cur_tx; 1051 struct ifnet *ifp = &sc->arpcom.ac_if; 1052 1053 VR_LOCK_ASSERT(sc); 1054 1055 /* 1056 * Go through our tx list and free mbufs for those 1057 * frames that have been transmitted. 1058 */ 1059 cur_tx = sc->vr_cdata.vr_tx_cons; 1060 while (cur_tx->vr_mbuf != NULL) { 1061 uint32_t txstat; 1062 int i; 1063 1064 txstat = cur_tx->vr_ptr->vr_status; 1065 1066 if ((txstat & VR_TXSTAT_ABRT) || 1067 (txstat & VR_TXSTAT_UDF)) { 1068 for (i = 0x400; 1069 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON); 1070 i--) 1071 ; /* Wait for chip to shutdown */ 1072 if (!i) { 1073 printf("vr%d: tx shutdown timeout\n", 1074 sc->vr_unit); 1075 sc->vr_flags |= VR_F_RESTART; 1076 break; 1077 } 1078 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1079 CSR_WRITE_4(sc, VR_TXADDR, vtophys(cur_tx->vr_ptr)); 1080 break; 1081 } 1082 1083 if (txstat & VR_TXSTAT_OWN) 1084 break; 1085 1086 if (txstat & VR_TXSTAT_ERRSUM) { 1087 ifp->if_oerrors++; 1088 if (txstat & VR_TXSTAT_DEFER) 1089 ifp->if_collisions++; 1090 if (txstat & VR_TXSTAT_LATECOLL) 1091 ifp->if_collisions++; 1092 } 1093 1094 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3; 1095 1096 ifp->if_opackets++; 1097 m_freem(cur_tx->vr_mbuf); 1098 cur_tx->vr_mbuf = NULL; 1099 ifp->if_flags &= ~IFF_OACTIVE; 1100 1101 cur_tx = cur_tx->vr_nextdesc; 1102 } 1103 sc->vr_cdata.vr_tx_cons = cur_tx; 1104 if (cur_tx->vr_mbuf == NULL) 1105 ifp->if_timer = 0; 1106 } 1107 1108 static void 1109 vr_tick(void *xsc) 1110 { 1111 struct vr_softc *sc = xsc; 1112 struct mii_data *mii; 1113 1114 VR_LOCK(sc); 1115 1116 if (sc->vr_flags & VR_F_RESTART) { 1117 printf("vr%d: restarting\n", sc->vr_unit); 1118 vr_stop(sc); 1119 vr_reset(sc); 1120 vr_init(sc); 1121 sc->vr_flags &= ~VR_F_RESTART; 1122 } 1123 1124 mii = device_get_softc(sc->vr_miibus); 1125 mii_tick(mii); 1126 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1127 1128 VR_UNLOCK(sc); 1129 } 1130 1131 #ifdef DEVICE_POLLING 1132 static poll_handler_t vr_poll; 1133 1134 static void 1135 vr_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1136 { 1137 struct vr_softc *sc = ifp->if_softc; 1138 1139 VR_LOCK(sc); 1140 1141 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1142 ether_poll_deregister(ifp); 1143 cmd = POLL_DEREGISTER; 1144 } 1145 1146 if (cmd == POLL_DEREGISTER) { 1147 /* Final call, enable interrupts. */ 1148 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1149 goto done; 1150 } 1151 1152 sc->rxcycles = count; 1153 vr_rxeof(sc); 1154 vr_txeof(sc); 1155 if (ifp->if_snd.ifq_head != NULL) { 1156 VR_UNLOCK(sc); 1157 vr_start(ifp); 1158 VR_LOCK(sc); 1159 } 1160 1161 if (cmd == POLL_AND_CHECK_STATUS) { 1162 uint16_t status; 1163 1164 /* Also check status register. */ 1165 status = CSR_READ_2(sc, VR_ISR); 1166 if (status) 1167 CSR_WRITE_2(sc, VR_ISR, status); 1168 1169 if ((status & VR_INTRS) == 0) 1170 goto done; 1171 1172 if (status & VR_ISR_RX_DROPPED) { 1173 printf("vr%d: rx packet lost\n", sc->vr_unit); 1174 ifp->if_ierrors++; 1175 } 1176 1177 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1178 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1179 printf("vr%d: receive error (%04x)", 1180 sc->vr_unit, status); 1181 if (status & VR_ISR_RX_NOBUF) 1182 printf(" no buffers"); 1183 if (status & VR_ISR_RX_OFLOW) 1184 printf(" overflow"); 1185 if (status & VR_ISR_RX_DROPPED) 1186 printf(" packet lost"); 1187 printf("\n"); 1188 vr_rxeoc(sc); 1189 } 1190 1191 if ((status & VR_ISR_BUSERR) || 1192 (status & VR_ISR_TX_UNDERRUN)) { 1193 vr_reset(sc); 1194 VR_UNLOCK(sc); 1195 vr_init(sc); 1196 return; 1197 } 1198 1199 if ((status & VR_ISR_UDFI) || 1200 (status & VR_ISR_TX_ABRT2) || 1201 (status & VR_ISR_TX_ABRT)) { 1202 ifp->if_oerrors++; 1203 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1204 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON); 1205 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_GO); 1206 } 1207 } 1208 } 1209 done: 1210 VR_UNLOCK(sc); 1211 } 1212 #endif /* DEVICE_POLLING */ 1213 1214 static void 1215 vr_intr(void *arg) 1216 { 1217 struct vr_softc *sc = arg; 1218 struct ifnet *ifp = &sc->arpcom.ac_if; 1219 uint16_t status; 1220 1221 VR_LOCK(sc); 1222 #ifdef DEVICE_POLLING 1223 if (ifp->if_flags & IFF_POLLING) { 1224 VR_UNLOCK(sc); 1225 return; 1226 } 1227 if ((ifp->if_capenable & IFCAP_POLLING) && 1228 ether_poll_register(vr_poll, ifp)) { 1229 /* OK, disable interrupts. */ 1230 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1231 VR_UNLOCK(sc); 1232 vr_poll(ifp, 0, 1); 1233 return; 1234 } 1235 #endif /* DEVICE_POLLING */ 1236 1237 /* Supress unwanted interrupts. */ 1238 if (!(ifp->if_flags & IFF_UP)) { 1239 vr_stop(sc); 1240 VR_UNLOCK(sc); 1241 return; 1242 } 1243 1244 /* Disable interrupts. */ 1245 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1246 1247 for (;;) { 1248 status = CSR_READ_2(sc, VR_ISR); 1249 if (status) 1250 CSR_WRITE_2(sc, VR_ISR, status); 1251 1252 if ((status & VR_INTRS) == 0) 1253 break; 1254 1255 if (status & VR_ISR_RX_OK) 1256 vr_rxeof(sc); 1257 1258 if (status & VR_ISR_RX_DROPPED) { 1259 printf("vr%d: rx packet lost\n", sc->vr_unit); 1260 ifp->if_ierrors++; 1261 } 1262 1263 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) || 1264 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) { 1265 printf("vr%d: receive error (%04x)", 1266 sc->vr_unit, status); 1267 if (status & VR_ISR_RX_NOBUF) 1268 printf(" no buffers"); 1269 if (status & VR_ISR_RX_OFLOW) 1270 printf(" overflow"); 1271 if (status & VR_ISR_RX_DROPPED) 1272 printf(" packet lost"); 1273 printf("\n"); 1274 vr_rxeoc(sc); 1275 } 1276 1277 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) { 1278 vr_reset(sc); 1279 VR_UNLOCK(sc); 1280 vr_init(sc); 1281 VR_LOCK(sc); 1282 break; 1283 } 1284 1285 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) || 1286 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) { 1287 vr_txeof(sc); 1288 if ((status & VR_ISR_UDFI) || 1289 (status & VR_ISR_TX_ABRT2) || 1290 (status & VR_ISR_TX_ABRT)) { 1291 ifp->if_oerrors++; 1292 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) { 1293 VR_SETBIT16(sc, VR_COMMAND, 1294 VR_CMD_TX_ON); 1295 VR_SETBIT16(sc, VR_COMMAND, 1296 VR_CMD_TX_GO); 1297 } 1298 } 1299 } 1300 } 1301 1302 /* Re-enable interrupts. */ 1303 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1304 VR_UNLOCK(sc); 1305 1306 if (_IF_QLEN(&ifp->if_snd) != 0) 1307 vr_start(ifp); 1308 } 1309 1310 /* 1311 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1312 * pointers to the fragment pointers. 1313 */ 1314 static int 1315 vr_encap(struct vr_softc *sc, struct vr_chain *c, struct mbuf *m_head) 1316 { 1317 struct vr_desc *f = NULL; 1318 struct mbuf *m; 1319 1320 VR_LOCK_ASSERT(sc); 1321 /* 1322 * The VIA Rhine wants packet buffers to be longword 1323 * aligned, but very often our mbufs aren't. Rather than 1324 * waste time trying to decide when to copy and when not 1325 * to copy, just do it all the time. 1326 */ 1327 m = m_defrag(m_head, M_DONTWAIT); 1328 if (m == NULL) 1329 return (1); 1330 1331 /* 1332 * The Rhine chip doesn't auto-pad, so we have to make 1333 * sure to pad short frames out to the minimum frame length 1334 * ourselves. 1335 */ 1336 if (m->m_len < VR_MIN_FRAMELEN) { 1337 m->m_pkthdr.len += VR_MIN_FRAMELEN - m->m_len; 1338 m->m_len = m->m_pkthdr.len; 1339 } 1340 1341 c->vr_mbuf = m; 1342 f = c->vr_ptr; 1343 f->vr_data = vtophys(mtod(m, caddr_t)); 1344 f->vr_ctl = m->m_len; 1345 f->vr_ctl |= VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG; 1346 f->vr_status = 0; 1347 f->vr_ctl |= VR_TXCTL_LASTFRAG|VR_TXCTL_FINT; 1348 f->vr_next = vtophys(c->vr_nextdesc->vr_ptr); 1349 1350 return (0); 1351 } 1352 1353 /* 1354 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1355 * to the mbuf data regions directly in the transmit lists. We also save a 1356 * copy of the pointers since the transmit list fragment pointers are 1357 * physical addresses. 1358 */ 1359 1360 static void 1361 vr_start(struct ifnet *ifp) 1362 { 1363 struct vr_softc *sc = ifp->if_softc; 1364 struct mbuf *m_head; 1365 struct vr_chain *cur_tx; 1366 1367 if (ifp->if_flags & IFF_OACTIVE) 1368 return; 1369 1370 VR_LOCK(sc); 1371 1372 cur_tx = sc->vr_cdata.vr_tx_prod; 1373 while (cur_tx->vr_mbuf == NULL) { 1374 IF_DEQUEUE(&ifp->if_snd, m_head); 1375 if (m_head == NULL) 1376 break; 1377 1378 /* Pack the data into the descriptor. */ 1379 if (vr_encap(sc, cur_tx, m_head)) { 1380 /* Rollback, send what we were able to encap. */ 1381 IF_PREPEND(&ifp->if_snd, m_head); 1382 break; 1383 } 1384 1385 VR_TXOWN(cur_tx) = VR_TXSTAT_OWN; 1386 1387 /* 1388 * If there's a BPF listener, bounce a copy of this frame 1389 * to him. 1390 */ 1391 BPF_MTAP(ifp, cur_tx->vr_mbuf); 1392 1393 cur_tx = cur_tx->vr_nextdesc; 1394 } 1395 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) { 1396 sc->vr_cdata.vr_tx_prod = cur_tx; 1397 1398 /* Tell the chip to start transmitting. */ 1399 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/ VR_CMD_TX_GO); 1400 1401 /* Set a timeout in case the chip goes out to lunch. */ 1402 ifp->if_timer = 5; 1403 1404 if (cur_tx->vr_mbuf != NULL) 1405 ifp->if_flags |= IFF_OACTIVE; 1406 } 1407 1408 VR_UNLOCK(sc); 1409 } 1410 1411 static void 1412 vr_init(void *xsc) 1413 { 1414 struct vr_softc *sc = xsc; 1415 struct ifnet *ifp = &sc->arpcom.ac_if; 1416 struct mii_data *mii; 1417 int i; 1418 1419 VR_LOCK(sc); 1420 1421 mii = device_get_softc(sc->vr_miibus); 1422 1423 /* Cancel pending I/O and free all RX/TX buffers. */ 1424 vr_stop(sc); 1425 vr_reset(sc); 1426 1427 /* Set our station address. */ 1428 for (i = 0; i < ETHER_ADDR_LEN; i++) 1429 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1430 1431 /* Set DMA size. */ 1432 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH); 1433 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD); 1434 1435 /* 1436 * BCR0 and BCR1 can override the RXCFG and TXCFG registers, 1437 * so we must set both. 1438 */ 1439 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH); 1440 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES); 1441 1442 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH); 1443 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD); 1444 1445 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH); 1446 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES); 1447 1448 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH); 1449 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD); 1450 1451 /* Init circular RX list. */ 1452 if (vr_list_rx_init(sc) == ENOBUFS) { 1453 printf( 1454 "vr%d: initialization failed: no memory for rx buffers\n", sc->vr_unit); 1455 vr_stop(sc); 1456 VR_UNLOCK(sc); 1457 return; 1458 } 1459 1460 /* Init tx descriptors. */ 1461 vr_list_tx_init(sc); 1462 1463 /* If we want promiscuous mode, set the allframes bit. */ 1464 if (ifp->if_flags & IFF_PROMISC) 1465 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1466 else 1467 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC); 1468 1469 /* Set capture broadcast bit to capture broadcast frames. */ 1470 if (ifp->if_flags & IFF_BROADCAST) 1471 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1472 else 1473 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD); 1474 1475 /* 1476 * Program the multicast filter, if necessary. 1477 */ 1478 vr_setmulti(sc); 1479 1480 /* 1481 * Load the address of the RX list. 1482 */ 1483 CSR_WRITE_4(sc, VR_RXADDR, vtophys(sc->vr_cdata.vr_rx_head->vr_ptr)); 1484 1485 /* Enable receiver and transmitter. */ 1486 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START| 1487 VR_CMD_TX_ON|VR_CMD_RX_ON| 1488 VR_CMD_RX_GO); 1489 1490 CSR_WRITE_4(sc, VR_TXADDR, vtophys(&sc->vr_ldata->vr_tx_list[0])); 1491 1492 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); 1493 #ifdef DEVICE_POLLING 1494 /* 1495 * Disable interrupts if we are polling. 1496 */ 1497 if (ifp->if_flags & IFF_POLLING) 1498 CSR_WRITE_2(sc, VR_IMR, 0); 1499 else 1500 #endif /* DEVICE_POLLING */ 1501 /* 1502 * Enable interrupts. 1503 */ 1504 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); 1505 1506 mii_mediachg(mii); 1507 1508 ifp->if_flags |= IFF_RUNNING; 1509 ifp->if_flags &= ~IFF_OACTIVE; 1510 1511 sc->vr_stat_ch = timeout(vr_tick, sc, hz); 1512 1513 VR_UNLOCK(sc); 1514 } 1515 1516 /* 1517 * Set media options. 1518 */ 1519 static int 1520 vr_ifmedia_upd(struct ifnet *ifp) 1521 { 1522 struct vr_softc *sc = ifp->if_softc; 1523 1524 if (ifp->if_flags & IFF_UP) 1525 vr_init(sc); 1526 1527 return (0); 1528 } 1529 1530 /* 1531 * Report current media status. 1532 */ 1533 static void 1534 vr_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1535 { 1536 struct vr_softc *sc = ifp->if_softc; 1537 struct mii_data *mii; 1538 1539 mii = device_get_softc(sc->vr_miibus); 1540 mii_pollstat(mii); 1541 ifmr->ifm_active = mii->mii_media_active; 1542 ifmr->ifm_status = mii->mii_media_status; 1543 } 1544 1545 static int 1546 vr_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1547 { 1548 struct vr_softc *sc = ifp->if_softc; 1549 struct ifreq *ifr = (struct ifreq *) data; 1550 struct mii_data *mii; 1551 int error = 0; 1552 1553 switch (command) { 1554 case SIOCSIFFLAGS: 1555 if (ifp->if_flags & IFF_UP) { 1556 vr_init(sc); 1557 } else { 1558 if (ifp->if_flags & IFF_RUNNING) { 1559 VR_LOCK(sc); 1560 vr_stop(sc); 1561 VR_UNLOCK(sc); 1562 } 1563 } 1564 error = 0; 1565 break; 1566 case SIOCADDMULTI: 1567 case SIOCDELMULTI: 1568 VR_LOCK(sc); 1569 vr_setmulti(sc); 1570 VR_UNLOCK(sc); 1571 error = 0; 1572 break; 1573 case SIOCGIFMEDIA: 1574 case SIOCSIFMEDIA: 1575 mii = device_get_softc(sc->vr_miibus); 1576 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1577 break; 1578 case SIOCSIFCAP: 1579 ifp->if_capenable = ifr->ifr_reqcap; 1580 break; 1581 default: 1582 error = ether_ioctl(ifp, command, data); 1583 break; 1584 } 1585 1586 return (error); 1587 } 1588 1589 static void 1590 vr_watchdog(struct ifnet *ifp) 1591 { 1592 struct vr_softc *sc = ifp->if_softc; 1593 1594 VR_LOCK(sc); 1595 ifp->if_oerrors++; 1596 printf("vr%d: watchdog timeout\n", sc->vr_unit); 1597 1598 vr_stop(sc); 1599 vr_reset(sc); 1600 VR_UNLOCK(sc); 1601 1602 vr_init(sc); 1603 if (ifp->if_snd.ifq_head != NULL) 1604 vr_start(ifp); 1605 } 1606 1607 /* 1608 * Stop the adapter and free any mbufs allocated to the 1609 * RX and TX lists. 1610 */ 1611 static void 1612 vr_stop(struct vr_softc *sc) 1613 { 1614 register int i; 1615 struct ifnet *ifp; 1616 1617 VR_LOCK_ASSERT(sc); 1618 1619 ifp = &sc->arpcom.ac_if; 1620 ifp->if_timer = 0; 1621 1622 untimeout(vr_tick, sc, sc->vr_stat_ch); 1623 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1624 #ifdef DEVICE_POLLING 1625 ether_poll_deregister(ifp); 1626 #endif /* DEVICE_POLLING */ 1627 1628 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP); 1629 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON)); 1630 CSR_WRITE_2(sc, VR_IMR, 0x0000); 1631 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000); 1632 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000); 1633 1634 /* 1635 * Free data in the RX lists. 1636 */ 1637 for (i = 0; i < VR_RX_LIST_CNT; i++) { 1638 if (sc->vr_cdata.vr_rx_chain[i].vr_mbuf != NULL) { 1639 m_freem(sc->vr_cdata.vr_rx_chain[i].vr_mbuf); 1640 sc->vr_cdata.vr_rx_chain[i].vr_mbuf = NULL; 1641 } 1642 } 1643 bzero((char *)&sc->vr_ldata->vr_rx_list, 1644 sizeof(sc->vr_ldata->vr_rx_list)); 1645 1646 /* 1647 * Free the TX list buffers. 1648 */ 1649 for (i = 0; i < VR_TX_LIST_CNT; i++) { 1650 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) { 1651 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf); 1652 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL; 1653 } 1654 } 1655 bzero((char *)&sc->vr_ldata->vr_tx_list, 1656 sizeof(sc->vr_ldata->vr_tx_list)); 1657 } 1658 1659 /* 1660 * Stop all chip I/O so that the kernel's probe routines don't 1661 * get confused by errant DMAs when rebooting. 1662 */ 1663 static void 1664 vr_shutdown(device_t dev) 1665 { 1666 struct vr_softc *sc = device_get_softc(dev); 1667 1668 VR_LOCK(sc); 1669 vr_stop(sc); 1670 VR_UNLOCK(sc); 1671 } 1672