1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #ifndef THUNDER_BGX_H 29 #define THUNDER_BGX_H 30 31 #define MAX_BGX_THUNDER 8 /* Max 4 nodes, 2 per node */ 32 #define MAX_BGX_PER_CN88XX 2 33 #define MAX_LMAC_PER_BGX 4 34 #define MAX_BGX_CHANS_PER_LMAC 16 35 #define MAX_DMAC_PER_LMAC 8 36 #define MAX_FRAME_SIZE 9216 37 38 #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 39 40 #define MAX_LMAC (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX) 41 42 /* Registers */ 43 #define BGX_CMRX_CFG 0x00 44 #define CMR_PKT_TX_EN (1UL << 13) 45 #define CMR_PKT_RX_EN (1UL << 14) 46 #define CMR_EN (1UL << 15) 47 #define BGX_CMR_GLOBAL_CFG 0x08 48 #define CMR_GLOBAL_CFG_FCS_STRIP (1UL << 6) 49 #define BGX_CMRX_RX_ID_MAP 0x60 50 #define BGX_CMRX_RX_STAT0 0x70 51 #define BGX_CMRX_RX_STAT1 0x78 52 #define BGX_CMRX_RX_STAT2 0x80 53 #define BGX_CMRX_RX_STAT3 0x88 54 #define BGX_CMRX_RX_STAT4 0x90 55 #define BGX_CMRX_RX_STAT5 0x98 56 #define BGX_CMRX_RX_STAT6 0xA0 57 #define BGX_CMRX_RX_STAT7 0xA8 58 #define BGX_CMRX_RX_STAT8 0xB0 59 #define BGX_CMRX_RX_STAT9 0xB8 60 #define BGX_CMRX_RX_STAT10 0xC0 61 #define BGX_CMRX_RX_BP_DROP 0xC8 62 #define BGX_CMRX_RX_DMAC_CTL 0x0E8 63 #define BGX_CMR_RX_DMACX_CAM 0x200 64 #define RX_DMACX_CAM_EN (1UL << 48) 65 #define RX_DMACX_CAM_LMACID(x) (x << 49) 66 #define RX_DMAC_COUNT 32 67 #define BGX_CMR_RX_STREERING 0x300 68 #define RX_TRAFFIC_STEER_RULE_COUNT 8 69 #define BGX_CMR_CHAN_MSK_AND 0x450 70 #define BGX_CMR_BIST_STATUS 0x460 71 #define BGX_CMR_RX_LMACS 0x468 72 #define BGX_CMRX_TX_STAT0 0x600 73 #define BGX_CMRX_TX_STAT1 0x608 74 #define BGX_CMRX_TX_STAT2 0x610 75 #define BGX_CMRX_TX_STAT3 0x618 76 #define BGX_CMRX_TX_STAT4 0x620 77 #define BGX_CMRX_TX_STAT5 0x628 78 #define BGX_CMRX_TX_STAT6 0x630 79 #define BGX_CMRX_TX_STAT7 0x638 80 #define BGX_CMRX_TX_STAT8 0x640 81 #define BGX_CMRX_TX_STAT9 0x648 82 #define BGX_CMRX_TX_STAT10 0x650 83 #define BGX_CMRX_TX_STAT11 0x658 84 #define BGX_CMRX_TX_STAT12 0x660 85 #define BGX_CMRX_TX_STAT13 0x668 86 #define BGX_CMRX_TX_STAT14 0x670 87 #define BGX_CMRX_TX_STAT15 0x678 88 #define BGX_CMRX_TX_STAT16 0x680 89 #define BGX_CMRX_TX_STAT17 0x688 90 #define BGX_CMR_TX_LMACS 0x1000 91 92 #define BGX_SPUX_CONTROL1 0x10000 93 #define SPU_CTL_LOW_POWER (1UL << 11) 94 #define SPU_CTL_LOOPBACK (1UL << 14) 95 #define SPU_CTL_RESET (1UL << 15) 96 #define BGX_SPUX_STATUS1 0x10008 97 #define SPU_STATUS1_RCV_LNK (1UL << 2) 98 #define BGX_SPUX_STATUS2 0x10020 99 #define SPU_STATUS2_RCVFLT (1UL << 10) 100 #define BGX_SPUX_BX_STATUS 0x10028 101 #define SPU_BX_STATUS_RX_ALIGN (1UL << 12) 102 #define BGX_SPUX_BR_STATUS1 0x10030 103 #define SPU_BR_STATUS_BLK_LOCK (1UL << 0) 104 #define SPU_BR_STATUS_RCV_LNK (1UL << 12) 105 #define BGX_SPUX_BR_PMD_CRTL 0x10068 106 #define SPU_PMD_CRTL_TRAIN_EN (1UL << 1) 107 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 108 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 109 #define BGX_SPUX_BR_PMD_LD_REP 0x10090 110 #define BGX_SPUX_FEC_CONTROL 0x100A0 111 #define SPU_FEC_CTL_FEC_EN (1UL << 0) 112 #define SPU_FEC_CTL_ERR_EN (1UL << 1) 113 #define BGX_SPUX_AN_CONTROL 0x100C8 114 #define SPU_AN_CTL_AN_EN (1UL << 12) 115 #define SPU_AN_CTL_XNP_EN (1UL << 13) 116 #define BGX_SPUX_AN_ADV 0x100D8 117 #define BGX_SPUX_MISC_CONTROL 0x10218 118 #define SPU_MISC_CTL_INTLV_RDISP (1UL << 10) 119 #define SPU_MISC_CTL_RX_DIS (1UL << 12) 120 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 121 #define BGX_SPUX_INT_W1S 0x10228 122 #define BGX_SPUX_INT_ENA_W1C 0x10230 123 #define BGX_SPUX_INT_ENA_W1S 0x10238 124 #define BGX_SPU_DBG_CONTROL 0x10300 125 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN (1UL << 18) 126 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS (1UL << 29) 127 128 #define BGX_SMUX_RX_INT 0x20000 129 #define BGX_SMUX_RX_JABBER 0x20030 130 #define BGX_SMUX_RX_CTL 0x20048 131 #define SMU_RX_CTL_STATUS (3UL << 0) 132 #define BGX_SMUX_TX_APPEND 0x20100 133 #define SMU_TX_APPEND_FCS_D (1UL << 2) 134 #define BGX_SMUX_TX_MIN_PKT 0x20118 135 #define BGX_SMUX_TX_INT 0x20140 136 #define BGX_SMUX_TX_CTL 0x20178 137 #define SMU_TX_CTL_DIC_EN (1UL << 0) 138 #define SMU_TX_CTL_UNI_EN (1UL << 1) 139 #define SMU_TX_CTL_LNK_STATUS (3UL << 4) 140 #define BGX_SMUX_TX_THRESH 0x20180 141 #define BGX_SMUX_CTL 0x20200 142 #define SMU_CTL_RX_IDLE (1UL << 0) 143 #define SMU_CTL_TX_IDLE (1UL << 1) 144 145 #define BGX_GMP_PCS_MRX_CTL 0x30000 146 #define PCS_MRX_CTL_RST_AN (1UL << 9) 147 #define PCS_MRX_CTL_PWR_DN (1UL << 11) 148 #define PCS_MRX_CTL_AN_EN (1UL << 12) 149 #define PCS_MRX_CTL_LOOPBACK1 (1UL << 14) 150 #define PCS_MRX_CTL_RESET (1UL << 15) 151 #define BGX_GMP_PCS_MRX_STATUS 0x30008 152 #define PCS_MRX_STATUS_AN_CPT (1UL << 5) 153 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 154 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 155 #define BGX_GMP_PCS_MISCX_CTL 0x30078 156 #define PCS_MISC_CTL_GMX_ENO (1UL << 11) 157 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7FUL 158 #define BGX_GMP_GMI_PRTX_CFG 0x38020 159 #define GMI_PORT_CFG_SPEED (1UL << 1) 160 #define GMI_PORT_CFG_DUPLEX (1UL << 2) 161 #define GMI_PORT_CFG_SLOT_TIME (1UL << 3) 162 #define GMI_PORT_CFG_SPEED_MSB (1UL << 8) 163 #define BGX_GMP_GMI_RXX_JABBER 0x38038 164 #define BGX_GMP_GMI_TXX_THRESH 0x38210 165 #define BGX_GMP_GMI_TXX_APPEND 0x38218 166 #define BGX_GMP_GMI_TXX_SLOT 0x38220 167 #define BGX_GMP_GMI_TXX_BURST 0x38228 168 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 169 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 170 171 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 172 #define BGX_MSIX_VEC_0_29_CTL 0x400008 173 #define BGX_MSIX_PBA_0 0x4F0000 174 175 /* MSI-X interrupts */ 176 #define BGX_MSIX_VECTORS 30 177 #define BGX_LMAC_VEC_OFFSET 7 178 #define BGX_MSIX_VEC_SHIFT 4 179 180 #define CMRX_INT 0 181 #define SPUX_INT 1 182 #define SMUX_RX_INT 2 183 #define SMUX_TX_INT 3 184 #define GMPX_PCS_INT 4 185 #define GMPX_GMI_RX_INT 5 186 #define GMPX_GMI_TX_INT 6 187 #define CMR_MEM_INT 28 188 #define SPU_MEM_INT 29 189 190 #define LMAC_INTR_LINK_UP (1 << 0) 191 #define LMAC_INTR_LINK_DOWN (1 << 1) 192 193 /* RX_DMAC_CTL configuration*/ 194 enum MCAST_MODE { 195 MCAST_MODE_REJECT, 196 MCAST_MODE_ACCEPT, 197 MCAST_MODE_CAM_FILTER, 198 RSVD 199 }; 200 201 #define BCAST_ACCEPT 1 202 #define CAM_ACCEPT 1 203 204 void octeon_mdiobus_force_mod_depencency(void); 205 void bgx_add_dmac_addr(uint64_t dmac, int node, int bgx_idx, int lmac); 206 unsigned bgx_get_map(int node); 207 int bgx_get_lmac_count(int node, int bgx); 208 const uint8_t *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid); 209 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const uint8_t *mac); 210 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status); 211 void bgx_lmac_internal_loopback(int node, int bgx_idx, 212 int lmac_idx, boolean_t enable); 213 uint64_t bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx); 214 uint64_t bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx); 215 #define BGX_RX_STATS_COUNT 11 216 #define BGX_TX_STATS_COUNT 18 217 218 struct bgx_stats { 219 uint64_t rx_stats[BGX_RX_STATS_COUNT]; 220 uint64_t tx_stats[BGX_TX_STATS_COUNT]; 221 }; 222 223 #define BGX_IN_PROMISCUOUS_MODE 1 224 225 enum LMAC_TYPE { 226 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 227 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 228 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 229 BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 230 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 231 BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 232 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 233 BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 234 }; 235 236 enum qlm_mode { 237 QLM_MODE_SGMII, /* SGMII, each lane independent */ 238 QLM_MODE_XAUI_1X4, /* 1 XAUI or DXAUI, 4 lanes */ 239 QLM_MODE_RXAUI_2X2, /* 2 RXAUI, 2 lanes each */ 240 QLM_MODE_XFI_4X1, /* 4 XFI, 1 lane each */ 241 QLM_MODE_XLAUI_1X4, /* 1 XLAUI, 4 lanes each */ 242 QLM_MODE_10G_KR_4X1, /* 4 10GBASE-KR, 1 lane each */ 243 QLM_MODE_40G_KR4_1X4, /* 1 40GBASE-KR4, 4 lanes each */ 244 }; 245 246 #endif /* THUNDER_BGX_H */ 247