xref: /freebsd/sys/dev/vnic/thunder_bgx.h (revision 3c0086b81391c0b6daf6ba3f58a6d3aebb0cdaca)
1 /*
2  * Copyright (C) 2015 Cavium Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  *
26  * $FreeBSD$
27  *
28  */
29 
30 #ifndef THUNDER_BGX_H
31 #define THUNDER_BGX_H
32 
33 #define    MAX_BGX_THUNDER			8 /* Max 4 nodes, 2 per node */
34 #define    MAX_BGX_PER_CN88XX			2
35 #define    MAX_LMAC_PER_BGX			4
36 #define    MAX_BGX_CHANS_PER_LMAC		16
37 #define    MAX_DMAC_PER_LMAC			8
38 #define    MAX_FRAME_SIZE			9216
39 
40 #define    MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE	2
41 
42 #define    MAX_LMAC	(MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX)
43 
44 /* Registers */
45 #define BGX_CMRX_CFG			0x00
46 #define  CMR_PKT_TX_EN				BIT_ULL(13)
47 #define  CMR_PKT_RX_EN				BIT_ULL(14)
48 #define  CMR_EN					BIT_ULL(15)
49 #define BGX_CMR_GLOBAL_CFG		0x08
50 #define  CMR_GLOBAL_CFG_FCS_STRIP		BIT_ULL(6)
51 #define BGX_CMRX_RX_ID_MAP		0x60
52 #define BGX_CMRX_RX_STAT0		0x70
53 #define BGX_CMRX_RX_STAT1		0x78
54 #define BGX_CMRX_RX_STAT2		0x80
55 #define BGX_CMRX_RX_STAT3		0x88
56 #define BGX_CMRX_RX_STAT4		0x90
57 #define BGX_CMRX_RX_STAT5		0x98
58 #define BGX_CMRX_RX_STAT6		0xA0
59 #define BGX_CMRX_RX_STAT7		0xA8
60 #define BGX_CMRX_RX_STAT8		0xB0
61 #define BGX_CMRX_RX_STAT9		0xB8
62 #define BGX_CMRX_RX_STAT10		0xC0
63 #define BGX_CMRX_RX_BP_DROP		0xC8
64 #define BGX_CMRX_RX_DMAC_CTL		0x0E8
65 #define BGX_CMR_RX_DMACX_CAM		0x200
66 #define  RX_DMACX_CAM_EN			BIT_ULL(48)
67 #define  RX_DMACX_CAM_LMACID(x)			(x << 49)
68 #define  RX_DMAC_COUNT				32
69 #define BGX_CMR_RX_STREERING		0x300
70 #define  RX_TRAFFIC_STEER_RULE_COUNT		8
71 #define BGX_CMR_CHAN_MSK_AND		0x450
72 #define BGX_CMR_BIST_STATUS		0x460
73 #define BGX_CMR_RX_LMACS		0x468
74 #define BGX_CMRX_TX_STAT0		0x600
75 #define BGX_CMRX_TX_STAT1		0x608
76 #define BGX_CMRX_TX_STAT2		0x610
77 #define BGX_CMRX_TX_STAT3		0x618
78 #define BGX_CMRX_TX_STAT4		0x620
79 #define BGX_CMRX_TX_STAT5		0x628
80 #define BGX_CMRX_TX_STAT6		0x630
81 #define BGX_CMRX_TX_STAT7		0x638
82 #define BGX_CMRX_TX_STAT8		0x640
83 #define BGX_CMRX_TX_STAT9		0x648
84 #define BGX_CMRX_TX_STAT10		0x650
85 #define BGX_CMRX_TX_STAT11		0x658
86 #define BGX_CMRX_TX_STAT12		0x660
87 #define BGX_CMRX_TX_STAT13		0x668
88 #define BGX_CMRX_TX_STAT14		0x670
89 #define BGX_CMRX_TX_STAT15		0x678
90 #define BGX_CMRX_TX_STAT16		0x680
91 #define BGX_CMRX_TX_STAT17		0x688
92 #define BGX_CMR_TX_LMACS		0x1000
93 
94 #define BGX_SPUX_CONTROL1		0x10000
95 #define  SPU_CTL_LOW_POWER			BIT_ULL(11)
96 #define  SPU_CTL_LOOPBACK			BIT_ULL(14)
97 #define  SPU_CTL_RESET				BIT_ULL(15)
98 #define BGX_SPUX_STATUS1		0x10008
99 #define  SPU_STATUS1_RCV_LNK			BIT_ULL(2)
100 #define BGX_SPUX_STATUS2		0x10020
101 #define  SPU_STATUS2_RCVFLT			BIT_ULL(10)
102 #define BGX_SPUX_BX_STATUS		0x10028
103 #define  SPU_BX_STATUS_RX_ALIGN			BIT_ULL(12)
104 #define BGX_SPUX_BR_STATUS1		0x10030
105 #define  SPU_BR_STATUS_BLK_LOCK			BIT_ULL(0)
106 #define  SPU_BR_STATUS_RCV_LNK			BIT_ULL(12)
107 #define BGX_SPUX_BR_PMD_CRTL		0x10068
108 #define  SPU_PMD_CRTL_TRAIN_EN			BIT_ULL(1)
109 #define BGX_SPUX_BR_PMD_LP_CUP		0x10078
110 #define BGX_SPUX_BR_PMD_LD_CUP		0x10088
111 #define BGX_SPUX_BR_PMD_LD_REP		0x10090
112 #define BGX_SPUX_FEC_CONTROL		0x100A0
113 #define  SPU_FEC_CTL_FEC_EN			BIT_ULL(0)
114 #define  SPU_FEC_CTL_ERR_EN			BIT_ULL(1)
115 #define BGX_SPUX_AN_CONTROL		0x100C8
116 #define  SPU_AN_CTL_AN_EN			BIT_ULL(12)
117 #define  SPU_AN_CTL_XNP_EN			BIT_ULL(13)
118 #define BGX_SPUX_AN_ADV			0x100D8
119 #define BGX_SPUX_MISC_CONTROL		0x10218
120 #define  SPU_MISC_CTL_INTLV_RDISP		BIT_ULL(10)
121 #define  SPU_MISC_CTL_RX_DIS			BIT_ULL(12)
122 #define BGX_SPUX_INT			0x10220	/* +(0..3) << 20 */
123 #define BGX_SPUX_INT_W1S		0x10228
124 #define BGX_SPUX_INT_ENA_W1C		0x10230
125 #define BGX_SPUX_INT_ENA_W1S		0x10238
126 #define BGX_SPU_DBG_CONTROL		0x10300
127 #define  SPU_DBG_CTL_AN_ARB_LINK_CHK_EN		BIT_ULL(18)
128 #define  SPU_DBG_CTL_AN_NONCE_MCT_DIS		BIT_ULL(29)
129 
130 #define BGX_SMUX_RX_INT			0x20000
131 #define BGX_SMUX_RX_JABBER		0x20030
132 #define BGX_SMUX_RX_CTL			0x20048
133 #define  SMU_RX_CTL_STATUS			(3ull << 0)
134 #define BGX_SMUX_TX_APPEND		0x20100
135 #define  SMU_TX_APPEND_FCS_D			BIT_ULL(2)
136 #define BGX_SMUX_TX_MIN_PKT		0x20118
137 #define BGX_SMUX_TX_INT			0x20140
138 #define BGX_SMUX_TX_CTL			0x20178
139 #define  SMU_TX_CTL_DIC_EN			BIT_ULL(0)
140 #define  SMU_TX_CTL_UNI_EN			BIT_ULL(1)
141 #define  SMU_TX_CTL_LNK_STATUS			(3ull << 4)
142 #define BGX_SMUX_TX_THRESH		0x20180
143 #define BGX_SMUX_CTL			0x20200
144 #define  SMU_CTL_RX_IDLE			BIT_ULL(0)
145 #define  SMU_CTL_TX_IDLE			BIT_ULL(1)
146 
147 #define BGX_GMP_PCS_MRX_CTL		0x30000
148 #define	 PCS_MRX_CTL_RST_AN			BIT_ULL(9)
149 #define	 PCS_MRX_CTL_PWR_DN			BIT_ULL(11)
150 #define	 PCS_MRX_CTL_AN_EN			BIT_ULL(12)
151 #define	 PCS_MRX_CTL_LOOPBACK1			BIT_ULL(14)
152 #define	 PCS_MRX_CTL_RESET			BIT_ULL(15)
153 #define BGX_GMP_PCS_MRX_STATUS		0x30008
154 #define	 PCS_MRX_STATUS_AN_CPT			BIT_ULL(5)
155 #define BGX_GMP_PCS_ANX_AN_RESULTS	0x30020
156 #define BGX_GMP_PCS_SGM_AN_ADV		0x30068
157 #define BGX_GMP_PCS_MISCX_CTL		0x30078
158 #define  PCS_MISC_CTL_GMX_ENO			BIT_ULL(11)
159 #define  PCS_MISC_CTL_SAMP_PT_MASK	0x7Full
160 #define BGX_GMP_GMI_PRTX_CFG		0x38020
161 #define  GMI_PORT_CFG_SPEED			BIT_ULL(1)
162 #define  GMI_PORT_CFG_DUPLEX			BIT_ULL(2)
163 #define  GMI_PORT_CFG_SLOT_TIME			BIT_ULL(3)
164 #define  GMI_PORT_CFG_SPEED_MSB			BIT_ULL(8)
165 #define BGX_GMP_GMI_RXX_JABBER		0x38038
166 #define BGX_GMP_GMI_TXX_THRESH		0x38210
167 #define BGX_GMP_GMI_TXX_APPEND		0x38218
168 #define BGX_GMP_GMI_TXX_SLOT		0x38220
169 #define BGX_GMP_GMI_TXX_BURST		0x38228
170 #define BGX_GMP_GMI_TXX_MIN_PKT		0x38240
171 #define BGX_GMP_GMI_TXX_SGMII_CTL	0x38300
172 
173 #define BGX_MSIX_VEC_0_29_ADDR		0x400000 /* +(0..29) << 4 */
174 #define BGX_MSIX_VEC_0_29_CTL		0x400008
175 #define BGX_MSIX_PBA_0			0x4F0000
176 
177 /* MSI-X interrupts */
178 #define BGX_MSIX_VECTORS	30
179 #define BGX_LMAC_VEC_OFFSET	7
180 #define BGX_MSIX_VEC_SHIFT	4
181 
182 #define CMRX_INT		0
183 #define SPUX_INT		1
184 #define SMUX_RX_INT		2
185 #define SMUX_TX_INT		3
186 #define GMPX_PCS_INT		4
187 #define GMPX_GMI_RX_INT		5
188 #define GMPX_GMI_TX_INT		6
189 #define CMR_MEM_INT		28
190 #define SPU_MEM_INT		29
191 
192 #define LMAC_INTR_LINK_UP	BIT(0)
193 #define LMAC_INTR_LINK_DOWN	BIT(1)
194 
195 /*  RX_DMAC_CTL configuration*/
196 enum MCAST_MODE {
197 		MCAST_MODE_REJECT,
198 		MCAST_MODE_ACCEPT,
199 		MCAST_MODE_CAM_FILTER,
200 		RSVD
201 };
202 
203 #define BCAST_ACCEPT	1
204 #define CAM_ACCEPT	1
205 
206 void octeon_mdiobus_force_mod_depencency(void);
207 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac);
208 unsigned bgx_get_map(int node);
209 int bgx_get_lmac_count(int node, int bgx);
210 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);
211 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);
212 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status);
213 void bgx_lmac_internal_loopback(int node, int bgx_idx,
214 				int lmac_idx, bool enable);
215 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx);
216 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx);
217 #define BGX_RX_STATS_COUNT 11
218 #define BGX_TX_STATS_COUNT 18
219 
220 struct bgx_stats {
221 	u64 rx_stats[BGX_RX_STATS_COUNT];
222 	u64 tx_stats[BGX_TX_STATS_COUNT];
223 };
224 
225 #define BGX_IN_PROMISCUOUS_MODE 1
226 
227 enum LMAC_TYPE {
228 	BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */
229 	BGX_MODE_XAUI = 1,  /* 4 lanes, 3.125 Gbaud */
230 	BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */
231 	BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */
232 	BGX_MODE_XFI = 3,   /* 1 lane, 10.3125 Gbaud */
233 	BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */
234 	BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */
235 	BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */
236 };
237 
238 enum qlm_mode {
239 	QLM_MODE_SGMII,         /* SGMII, each lane independent */
240 	QLM_MODE_XAUI_1X4,      /* 1 XAUI or DXAUI, 4 lanes */
241 	QLM_MODE_RXAUI_2X2,     /* 2 RXAUI, 2 lanes each */
242 	QLM_MODE_XFI_4X1,       /* 4 XFI, 1 lane each */
243 	QLM_MODE_XLAUI_1X4,     /* 1 XLAUI, 4 lanes each */
244 	QLM_MODE_10G_KR_4X1,    /* 4 10GBASE-KR, 1 lane each */
245 	QLM_MODE_40G_KR4_1X4,   /* 1 40GBASE-KR4, 4 lanes each */
246 };
247 
248 #endif /* THUNDER_BGX_H */
249