1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bitset.h> 36 #include <sys/bitstring.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/pciio.h> 44 #include <sys/pcpu.h> 45 #include <sys/proc.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/cpuset.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_media.h> 55 56 #include <machine/bus.h> 57 #include <machine/_inttypes.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 62 #include <sys/dnv.h> 63 #include <sys/nv.h> 64 #ifdef PCI_IOV 65 #include <sys/iov_schema.h> 66 #include <dev/pci/pci_iov.h> 67 #endif 68 69 #include "thunder_bgx.h" 70 #include "nic_reg.h" 71 #include "nic.h" 72 #include "q_struct.h" 73 74 #define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" 75 76 #define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) 77 78 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) 79 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) 80 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) 81 82 /* Structure to be used by the SR-IOV for VF configuration schemas */ 83 struct nicvf_info { 84 boolean_t vf_enabled; 85 int vf_flags; 86 }; 87 88 struct nicpf { 89 device_t dev; 90 uint8_t node; 91 u_int flags; 92 uint8_t num_vf_en; /* No of VF enabled */ 93 struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; 94 struct resource * reg_base; /* Register start address */ 95 struct pkind_cfg pkind; 96 uint8_t vf_lmac_map[MAX_LMAC]; 97 boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; 98 99 struct callout check_link; 100 struct mtx check_link_mtx; 101 102 uint8_t link[MAX_LMAC]; 103 uint8_t duplex[MAX_LMAC]; 104 uint32_t speed[MAX_LMAC]; 105 uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; 106 uint16_t rssi_base[MAX_NUM_VFS_SUPPORTED]; 107 uint16_t rss_ind_tbl_size; 108 109 /* MSI-X */ 110 boolean_t msix_enabled; 111 uint8_t num_vec; 112 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; 113 struct resource * msix_table_res; 114 }; 115 116 static int nicpf_probe(device_t); 117 static int nicpf_attach(device_t); 118 static int nicpf_detach(device_t); 119 120 #ifdef PCI_IOV 121 static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); 122 static void nicpf_iov_uninit(device_t); 123 static int nicpf_iov_add_vf(device_t, uint16_t, const nvlist_t *); 124 #endif 125 126 static device_method_t nicpf_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, nicpf_probe), 129 DEVMETHOD(device_attach, nicpf_attach), 130 DEVMETHOD(device_detach, nicpf_detach), 131 /* PCI SR-IOV interface */ 132 #ifdef PCI_IOV 133 DEVMETHOD(pci_iov_init, nicpf_iov_init), 134 DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), 135 DEVMETHOD(pci_iov_add_vf, nicpf_iov_add_vf), 136 #endif 137 DEVMETHOD_END, 138 }; 139 140 static driver_t vnicpf_driver = { 141 "vnicpf", 142 nicpf_methods, 143 sizeof(struct nicpf), 144 }; 145 146 static devclass_t vnicpf_devclass; 147 148 DRIVER_MODULE(vnicpf, pci, vnicpf_driver, vnicpf_devclass, 0, 0); 149 MODULE_VERSION(vnicpf, 1); 150 MODULE_DEPEND(vnicpf, pci, 1, 1, 1); 151 MODULE_DEPEND(vnicpf, ether, 1, 1, 1); 152 MODULE_DEPEND(vnicpf, thunder_bgx, 1, 1, 1); 153 154 static int nicpf_alloc_res(struct nicpf *); 155 static void nicpf_free_res(struct nicpf *); 156 static void nic_set_lmac_vf_mapping(struct nicpf *); 157 static void nic_init_hw(struct nicpf *); 158 static int nic_sriov_init(device_t, struct nicpf *); 159 static void nic_poll_for_link(void *); 160 static int nic_register_interrupts(struct nicpf *); 161 static void nic_unregister_interrupts(struct nicpf *); 162 163 /* 164 * Device interface 165 */ 166 static int 167 nicpf_probe(device_t dev) 168 { 169 uint16_t vendor_id; 170 uint16_t device_id; 171 172 vendor_id = pci_get_vendor(dev); 173 device_id = pci_get_device(dev); 174 175 if (vendor_id == PCI_VENDOR_ID_CAVIUM && 176 device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { 177 device_set_desc(dev, VNIC_PF_DEVSTR); 178 return (BUS_PROBE_DEFAULT); 179 } 180 181 return (ENXIO); 182 } 183 184 static int 185 nicpf_attach(device_t dev) 186 { 187 struct nicpf *nic; 188 int err; 189 190 nic = device_get_softc(dev); 191 nic->dev = dev; 192 193 /* Enable bus mastering */ 194 pci_enable_busmaster(dev); 195 196 /* Allocate PCI resources */ 197 err = nicpf_alloc_res(nic); 198 if (err != 0) { 199 device_printf(dev, "Could not allocate PCI resources\n"); 200 return (err); 201 } 202 203 nic->node = nic_get_node_id(nic->reg_base); 204 205 /* Enable Traffic Network Switch (TNS) bypass mode by default */ 206 nic->flags &= ~NIC_TNS_ENABLED; 207 nic_set_lmac_vf_mapping(nic); 208 209 /* Initialize hardware */ 210 nic_init_hw(nic); 211 212 /* Set RSS TBL size for each VF */ 213 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 214 215 /* Setup interrupts */ 216 err = nic_register_interrupts(nic); 217 if (err != 0) 218 goto err_free_res; 219 220 /* Configure SRIOV */ 221 err = nic_sriov_init(dev, nic); 222 if (err != 0) 223 goto err_free_intr; 224 225 if (nic->flags & NIC_TNS_ENABLED) 226 return (0); 227 228 mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); 229 /* Register physical link status poll callout */ 230 callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); 231 mtx_lock(&nic->check_link_mtx); 232 nic_poll_for_link(nic); 233 mtx_unlock(&nic->check_link_mtx); 234 235 return (0); 236 237 err_free_intr: 238 nic_unregister_interrupts(nic); 239 err_free_res: 240 nicpf_free_res(nic); 241 pci_disable_busmaster(dev); 242 243 return (err); 244 } 245 246 static int 247 nicpf_detach(device_t dev) 248 { 249 struct nicpf *nic; 250 251 nic = device_get_softc(dev); 252 253 callout_drain(&nic->check_link); 254 mtx_destroy(&nic->check_link_mtx); 255 256 nic_unregister_interrupts(nic); 257 nicpf_free_res(nic); 258 pci_disable_busmaster(dev); 259 260 return (0); 261 } 262 263 /* 264 * SR-IOV interface 265 */ 266 #ifdef PCI_IOV 267 static int 268 nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 269 { 270 struct nicpf *nic; 271 272 nic = device_get_softc(dev); 273 274 if (num_vfs == 0) 275 return (ENXIO); 276 277 nic->flags |= NIC_SRIOV_ENABLED; 278 279 return (0); 280 } 281 282 static void 283 nicpf_iov_uninit(device_t dev) 284 { 285 286 /* ARM64TODO: Implement this function */ 287 } 288 289 static int 290 nicpf_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 291 { 292 const void *mac; 293 struct nicpf *nic; 294 size_t size; 295 int bgx, lmac; 296 297 nic = device_get_softc(dev); 298 299 if ((nic->flags & NIC_SRIOV_ENABLED) == 0) 300 return (ENXIO); 301 302 if (vfnum > (nic->num_vf_en - 1)) 303 return (EINVAL); 304 305 if (nvlist_exists_binary(params, "mac-addr") != 0) { 306 mac = nvlist_get_binary(params, "mac-addr", &size); 307 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 308 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 309 bgx_set_lmac_mac(nic->node, bgx, lmac, mac); 310 } 311 312 return (0); 313 } 314 #endif 315 316 /* 317 * Helper routines 318 */ 319 static int 320 nicpf_alloc_res(struct nicpf *nic) 321 { 322 device_t dev; 323 int rid; 324 325 dev = nic->dev; 326 327 rid = VNIC_PF_REG_RID; 328 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 329 RF_ACTIVE); 330 if (nic->reg_base == NULL) { 331 /* For verbose output print some more details */ 332 if (bootverbose) { 333 device_printf(dev, 334 "Could not allocate registers memory\n"); 335 } 336 return (ENXIO); 337 } 338 339 return (0); 340 } 341 342 static void 343 nicpf_free_res(struct nicpf *nic) 344 { 345 device_t dev; 346 347 dev = nic->dev; 348 349 if (nic->reg_base != NULL) { 350 bus_release_resource(dev, SYS_RES_MEMORY, 351 rman_get_rid(nic->reg_base), nic->reg_base); 352 } 353 } 354 355 /* Register read/write APIs */ 356 static __inline void 357 nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, 358 uint64_t val) 359 { 360 361 bus_write_8(nic->reg_base, offset, val); 362 } 363 364 static __inline uint64_t 365 nic_reg_read(struct nicpf *nic, uint64_t offset) 366 { 367 uint64_t val; 368 369 val = bus_read_8(nic->reg_base, offset); 370 return (val); 371 } 372 373 /* PF -> VF mailbox communication APIs */ 374 static void 375 nic_enable_mbx_intr(struct nicpf *nic) 376 { 377 378 /* Enable mailbox interrupt for all 128 VFs */ 379 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); 380 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); 381 } 382 383 static void 384 nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 385 { 386 387 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); 388 } 389 390 static uint64_t 391 nic_get_mbx_addr(int vf) 392 { 393 394 return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); 395 } 396 397 /* 398 * Send a mailbox message to VF 399 * @vf: vf to which this message to be sent 400 * @mbx: Message to be sent 401 */ 402 static void 403 nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 404 { 405 bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); 406 uint64_t *msg = (uint64_t *)mbx; 407 408 /* 409 * In first revision HW, mbox interrupt is triggerred 410 * when PF writes to MBOX(1), in next revisions when 411 * PF writes to MBOX(0) 412 */ 413 if (pass1_silicon(nic->dev)) { 414 nic_reg_write(nic, mbx_addr + 0, msg[0]); 415 nic_reg_write(nic, mbx_addr + 8, msg[1]); 416 } else { 417 nic_reg_write(nic, mbx_addr + 8, msg[1]); 418 nic_reg_write(nic, mbx_addr + 0, msg[0]); 419 } 420 } 421 422 /* 423 * Responds to VF's READY message with VF's 424 * ID, node, MAC address e.t.c 425 * @vf: VF which sent READY message 426 */ 427 static void 428 nic_mbx_send_ready(struct nicpf *nic, int vf) 429 { 430 union nic_mbx mbx = {}; 431 int bgx_idx, lmac; 432 const char *mac; 433 434 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 435 mbx.nic_cfg.vf_id = vf; 436 437 if (nic->flags & NIC_TNS_ENABLED) 438 mbx.nic_cfg.tns_mode = NIC_TNS_MODE; 439 else 440 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 441 442 if (vf < MAX_LMAC) { 443 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 444 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 445 446 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 447 if (mac) { 448 memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, 449 ETHER_ADDR_LEN); 450 } 451 } 452 mbx.nic_cfg.node_id = nic->node; 453 454 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; 455 456 nic_send_msg_to_vf(nic, vf, &mbx); 457 } 458 459 /* 460 * ACKs VF's mailbox message 461 * @vf: VF to which ACK to be sent 462 */ 463 static void 464 nic_mbx_send_ack(struct nicpf *nic, int vf) 465 { 466 union nic_mbx mbx = {}; 467 468 mbx.msg.msg = NIC_MBOX_MSG_ACK; 469 nic_send_msg_to_vf(nic, vf, &mbx); 470 } 471 472 /* 473 * NACKs VF's mailbox message that PF is not able to 474 * complete the action 475 * @vf: VF to which ACK to be sent 476 */ 477 static void 478 nic_mbx_send_nack(struct nicpf *nic, int vf) 479 { 480 union nic_mbx mbx = {}; 481 482 mbx.msg.msg = NIC_MBOX_MSG_NACK; 483 nic_send_msg_to_vf(nic, vf, &mbx); 484 } 485 486 /* 487 * Flush all in flight receive packets to memory and 488 * bring down an active RQ 489 */ 490 static int 491 nic_rcv_queue_sw_sync(struct nicpf *nic) 492 { 493 uint16_t timeout = ~0x00; 494 495 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 496 /* Wait till sync cycle is finished */ 497 while (timeout) { 498 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 499 break; 500 timeout--; 501 } 502 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 503 if (!timeout) { 504 device_printf(nic->dev, "Receive queue software sync failed\n"); 505 return (ETIMEDOUT); 506 } 507 return (0); 508 } 509 510 /* Get BGX Rx/Tx stats and respond to VF's request */ 511 static void 512 nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 513 { 514 int bgx_idx, lmac; 515 union nic_mbx mbx = {}; 516 517 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 518 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 519 520 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 521 mbx.bgx_stats.vf_id = bgx->vf_id; 522 mbx.bgx_stats.rx = bgx->rx; 523 mbx.bgx_stats.idx = bgx->idx; 524 if (bgx->rx != 0) { 525 mbx.bgx_stats.stats = 526 bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); 527 } else { 528 mbx.bgx_stats.stats = 529 bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); 530 } 531 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 532 } 533 534 /* Update hardware min/max frame size */ 535 static int 536 nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 537 { 538 539 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { 540 device_printf(nic->dev, 541 "Invalid MTU setting from VF%d rejected, " 542 "should be between %d and %d\n", 543 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); 544 return (EINVAL); 545 } 546 new_frs += ETHER_HDR_LEN; 547 if (new_frs <= nic->pkind.maxlen) 548 return (0); 549 550 nic->pkind.maxlen = new_frs; 551 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); 552 return (0); 553 } 554 555 /* Set minimum transmit packet size */ 556 static void 557 nic_set_tx_pkt_pad(struct nicpf *nic, int size) 558 { 559 int lmac; 560 uint64_t lmac_cfg; 561 562 /* Max value that can be set is 60 */ 563 if (size > 60) 564 size = 60; 565 566 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { 567 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 568 lmac_cfg &= ~(0xF << 2); 569 lmac_cfg |= ((size / 4) << 2); 570 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 571 } 572 } 573 574 /* 575 * Function to check number of LMACs present and set VF::LMAC mapping. 576 * Mapping will be used while initializing channels. 577 */ 578 static void 579 nic_set_lmac_vf_mapping(struct nicpf *nic) 580 { 581 unsigned bgx_map = bgx_get_map(nic->node); 582 int bgx, next_bgx_lmac = 0; 583 int lmac, lmac_cnt = 0; 584 uint64_t lmac_credit; 585 586 nic->num_vf_en = 0; 587 if (nic->flags & NIC_TNS_ENABLED) { 588 nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; 589 return; 590 } 591 592 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { 593 if ((bgx_map & (1 << bgx)) == 0) 594 continue; 595 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 596 for (lmac = 0; lmac < lmac_cnt; lmac++) 597 nic->vf_lmac_map[next_bgx_lmac++] = 598 NIC_SET_VF_LMAC_MAP(bgx, lmac); 599 nic->num_vf_en += lmac_cnt; 600 601 /* Program LMAC credits */ 602 lmac_credit = (1UL << 1); /* channel credit enable */ 603 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 604 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 605 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 606 NIC_HW_MAX_FRS) / 16) << 12); 607 lmac = bgx * MAX_LMAC_PER_BGX; 608 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { 609 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 610 lmac_credit); 611 } 612 } 613 } 614 615 #define TNS_PORT0_BLOCK 6 616 #define TNS_PORT1_BLOCK 7 617 #define BGX0_BLOCK 8 618 #define BGX1_BLOCK 9 619 620 static void 621 nic_init_hw(struct nicpf *nic) 622 { 623 int i; 624 625 /* Enable NIC HW block */ 626 nic_reg_write(nic, NIC_PF_CFG, 0x3); 627 628 /* Enable backpressure */ 629 nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); 630 631 if (nic->flags & NIC_TNS_ENABLED) { 632 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 633 (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); 634 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 635 (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); 636 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 637 (1UL << 63) | TNS_PORT0_BLOCK); 638 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 639 (1UL << 63) | TNS_PORT1_BLOCK); 640 641 } else { 642 /* Disable TNS mode on both interfaces */ 643 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 644 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 645 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 646 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 647 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 648 (1UL << 63) | BGX0_BLOCK); 649 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 650 (1UL << 63) | BGX1_BLOCK); 651 } 652 653 /* PKIND configuration */ 654 nic->pkind.minlen = 0; 655 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; 656 nic->pkind.lenerr_en = 1; 657 nic->pkind.rx_hdr = 0; 658 nic->pkind.hdr_sl = 0; 659 660 for (i = 0; i < NIC_MAX_PKIND; i++) { 661 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 662 *(uint64_t *)&nic->pkind); 663 } 664 665 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 666 667 /* Timer config */ 668 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 669 670 /* Enable VLAN ethertype matching and stripping */ 671 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 672 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); 673 } 674 675 /* Channel parse index configuration */ 676 static void 677 nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 678 { 679 uint32_t vnic, bgx, lmac, chan; 680 uint32_t padd, cpi_count = 0; 681 uint64_t cpi_base, cpi, rssi_base, rssi; 682 uint8_t qset, rq_idx = 0; 683 684 vnic = cfg->vf_id; 685 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 686 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 687 688 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 689 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); 690 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); 691 692 /* Rx channel configuration */ 693 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 694 (1UL << 63) | (vnic << 0)); 695 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 696 ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); 697 698 if (cfg->cpi_alg == CPI_ALG_NONE) 699 cpi_count = 1; 700 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 701 cpi_count = 8; 702 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 703 cpi_count = 16; 704 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 705 cpi_count = NIC_MAX_CPI_PER_LMAC; 706 707 /* RSS Qset, Qidx mapping */ 708 qset = cfg->vf_id; 709 rssi = rssi_base; 710 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 711 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 712 (qset << 3) | rq_idx); 713 rq_idx++; 714 } 715 716 rssi = 0; 717 cpi = cpi_base; 718 for (; cpi < (cpi_base + cpi_count); cpi++) { 719 /* Determine port to channel adder */ 720 if (cfg->cpi_alg != CPI_ALG_DIFF) 721 padd = cpi % cpi_count; 722 else 723 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 724 725 /* Leave RSS_SIZE as '0' to disable RSS */ 726 if (pass1_silicon(nic->dev)) { 727 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 728 (vnic << 24) | (padd << 16) | (rssi_base + rssi)); 729 } else { 730 /* Set MPI_ALG to '0' to disable MCAM parsing */ 731 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 732 (padd << 16)); 733 /* MPI index is same as CPI if MPI_ALG is not enabled */ 734 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3), 735 (vnic << 24) | (rssi_base + rssi)); 736 } 737 738 if ((rssi + 1) >= cfg->rq_cnt) 739 continue; 740 741 if (cfg->cpi_alg == CPI_ALG_VLAN) 742 rssi++; 743 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 744 rssi = ((cpi - cpi_base) & 0xe) >> 1; 745 else if (cfg->cpi_alg == CPI_ALG_DIFF) 746 rssi = ((cpi - cpi_base) & 0x38) >> 3; 747 } 748 nic->cpi_base[cfg->vf_id] = cpi_base; 749 nic->rssi_base[cfg->vf_id] = rssi_base; 750 } 751 752 /* Responsds to VF with its RSS indirection table size */ 753 static void 754 nic_send_rss_size(struct nicpf *nic, int vf) 755 { 756 union nic_mbx mbx = {}; 757 uint64_t *msg; 758 759 msg = (uint64_t *)&mbx; 760 761 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE; 762 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size; 763 nic_send_msg_to_vf(nic, vf, &mbx); 764 } 765 766 /* 767 * Receive side scaling configuration 768 * configure: 769 * - RSS index 770 * - indir table i.e hash::RQ mapping 771 * - no of hash bits to consider 772 */ 773 static void 774 nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg) 775 { 776 uint8_t qset, idx; 777 uint64_t cpi_cfg, cpi_base, rssi_base, rssi; 778 uint64_t idx_addr; 779 780 idx = 0; 781 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset; 782 783 rssi = rssi_base; 784 qset = cfg->vf_id; 785 786 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) { 787 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 788 (qset << 3) | (cfg->ind_tbl[idx] & 0x7)); 789 idx++; 790 } 791 792 cpi_base = nic->cpi_base[cfg->vf_id]; 793 if (pass1_silicon(nic->dev)) 794 idx_addr = NIC_PF_CPI_0_2047_CFG; 795 else 796 idx_addr = NIC_PF_MPI_0_2047_CFG; 797 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3)); 798 cpi_cfg &= ~(0xFUL << 20); 799 cpi_cfg |= (cfg->hash_bits << 20); 800 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg); 801 } 802 803 /* 804 * 4 level transmit side scheduler configutation 805 * for TNS bypass mode 806 * 807 * Sample configuration for SQ0 808 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 809 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 810 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 811 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 812 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 813 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 814 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 815 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 816 */ 817 static void 818 nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) 819 { 820 uint32_t bgx, lmac, chan; 821 uint32_t tl2, tl3, tl4; 822 uint32_t rr_quantum; 823 uint8_t sq_idx = sq->sq_num; 824 uint8_t pqs_vnic; 825 826 pqs_vnic = vnic; 827 828 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 829 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 830 831 /* 24 bytes for FCS, IPG and preamble */ 832 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 833 834 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); 835 tl4 += sq_idx; 836 837 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); 838 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 839 ((uint64_t)vnic << NIC_QS_ID_SHIFT) | 840 ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); 841 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 842 ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); 843 844 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 845 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 846 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 847 /* Enable backpressure on the channel */ 848 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 849 850 tl2 = tl3 >> 2; 851 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 852 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 853 /* No priorities as of now */ 854 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 855 } 856 857 static int 858 nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 859 { 860 int bgx_idx, lmac_idx; 861 862 if (lbk->vf_id > MAX_LMAC) 863 return (ENXIO); 864 865 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 866 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 867 868 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 869 870 return (0); 871 } 872 873 /* Interrupt handler to handle mailbox messages from VFs */ 874 static void 875 nic_handle_mbx_intr(struct nicpf *nic, int vf) 876 { 877 union nic_mbx mbx = {}; 878 uint64_t *mbx_data; 879 uint64_t mbx_addr; 880 uint64_t reg_addr; 881 uint64_t cfg; 882 int bgx, lmac; 883 int i; 884 int ret = 0; 885 886 nic->mbx_lock[vf] = TRUE; 887 888 mbx_addr = nic_get_mbx_addr(vf); 889 mbx_data = (uint64_t *)&mbx; 890 891 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 892 *mbx_data = nic_reg_read(nic, mbx_addr); 893 mbx_data++; 894 mbx_addr += sizeof(uint64_t); 895 } 896 897 switch (mbx.msg.msg) { 898 case NIC_MBOX_MSG_READY: 899 nic_mbx_send_ready(nic, vf); 900 if (vf < MAX_LMAC) { 901 nic->link[vf] = 0; 902 nic->duplex[vf] = 0; 903 nic->speed[vf] = 0; 904 } 905 ret = 1; 906 break; 907 case NIC_MBOX_MSG_QS_CFG: 908 reg_addr = NIC_PF_QSET_0_127_CFG | 909 (mbx.qs.num << NIC_QS_ID_SHIFT); 910 cfg = mbx.qs.cfg; 911 nic_reg_write(nic, reg_addr, cfg); 912 break; 913 case NIC_MBOX_MSG_RQ_CFG: 914 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 915 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 916 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 917 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 918 break; 919 case NIC_MBOX_MSG_RQ_BP_CFG: 920 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 921 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 922 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 923 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 924 break; 925 case NIC_MBOX_MSG_RQ_SW_SYNC: 926 ret = nic_rcv_queue_sw_sync(nic); 927 break; 928 case NIC_MBOX_MSG_RQ_DROP_CFG: 929 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 930 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 931 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 932 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 933 break; 934 case NIC_MBOX_MSG_SQ_CFG: 935 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 936 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 937 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 938 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 939 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 940 break; 941 case NIC_MBOX_MSG_SET_MAC: 942 lmac = mbx.mac.vf_id; 943 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 944 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 945 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 946 break; 947 case NIC_MBOX_MSG_SET_MAX_FRS: 948 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); 949 break; 950 case NIC_MBOX_MSG_CPI_CFG: 951 nic_config_cpi(nic, &mbx.cpi_cfg); 952 break; 953 case NIC_MBOX_MSG_RSS_SIZE: 954 nic_send_rss_size(nic, vf); 955 goto unlock; 956 case NIC_MBOX_MSG_RSS_CFG: 957 case NIC_MBOX_MSG_RSS_CFG_CONT: /* fall through */ 958 nic_config_rss(nic, &mbx.rss_cfg); 959 break; 960 case NIC_MBOX_MSG_CFG_DONE: 961 /* Last message of VF config msg sequence */ 962 nic->vf_info[vf].vf_enabled = TRUE; 963 goto unlock; 964 case NIC_MBOX_MSG_SHUTDOWN: 965 /* First msg in VF teardown sequence */ 966 nic->vf_info[vf].vf_enabled = FALSE; 967 break; 968 case NIC_MBOX_MSG_BGX_STATS: 969 nic_get_bgx_stats(nic, &mbx.bgx_stats); 970 goto unlock; 971 case NIC_MBOX_MSG_LOOPBACK: 972 ret = nic_config_loopback(nic, &mbx.lbk); 973 break; 974 default: 975 device_printf(nic->dev, 976 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 977 break; 978 } 979 980 if (ret == 0) 981 nic_mbx_send_ack(nic, vf); 982 else if (mbx.msg.msg != NIC_MBOX_MSG_READY) 983 nic_mbx_send_nack(nic, vf); 984 unlock: 985 nic->mbx_lock[vf] = FALSE; 986 } 987 988 static void 989 nic_mbx_intr_handler(struct nicpf *nic, int mbx) 990 { 991 uint64_t intr; 992 uint8_t vf, vf_per_mbx_reg = 64; 993 994 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 995 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 996 if (intr & (1UL << vf)) { 997 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 998 nic_clear_mbx_intr(nic, vf, mbx); 999 } 1000 } 1001 } 1002 1003 static void 1004 nic_mbx0_intr_handler (void *arg) 1005 { 1006 struct nicpf *nic = (struct nicpf *)arg; 1007 1008 nic_mbx_intr_handler(nic, 0); 1009 } 1010 1011 static void 1012 nic_mbx1_intr_handler (void *arg) 1013 { 1014 struct nicpf *nic = (struct nicpf *)arg; 1015 1016 nic_mbx_intr_handler(nic, 1); 1017 } 1018 1019 static int 1020 nic_enable_msix(struct nicpf *nic) 1021 { 1022 struct pci_devinfo *dinfo; 1023 int rid, count; 1024 int ret; 1025 1026 dinfo = device_get_ivars(nic->dev); 1027 rid = dinfo->cfg.msix.msix_table_bar; 1028 nic->msix_table_res = 1029 bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 1030 if (nic->msix_table_res == NULL) { 1031 device_printf(nic->dev, 1032 "Could not allocate memory for MSI-X table\n"); 1033 return (ENXIO); 1034 } 1035 1036 count = nic->num_vec = NIC_PF_MSIX_VECTORS; 1037 1038 ret = pci_alloc_msix(nic->dev, &count); 1039 if ((ret != 0) || (count != nic->num_vec)) { 1040 device_printf(nic->dev, 1041 "Request for #%d msix vectors failed, error: %d\n", 1042 nic->num_vec, ret); 1043 return (ret); 1044 } 1045 1046 nic->msix_enabled = 1; 1047 return (0); 1048 } 1049 1050 static void 1051 nic_disable_msix(struct nicpf *nic) 1052 { 1053 if (nic->msix_enabled) { 1054 pci_release_msi(nic->dev); 1055 nic->msix_enabled = 0; 1056 nic->num_vec = 0; 1057 } 1058 } 1059 1060 static void 1061 nic_free_all_interrupts(struct nicpf *nic) 1062 { 1063 int irq; 1064 1065 for (irq = 0; irq < nic->num_vec; irq++) { 1066 if (nic->msix_entries[irq].irq_res == NULL) 1067 continue; 1068 if (nic->msix_entries[irq].handle != NULL) { 1069 bus_teardown_intr(nic->dev, 1070 nic->msix_entries[irq].irq_res, 1071 nic->msix_entries[irq].handle); 1072 } 1073 1074 bus_release_resource(nic->dev, SYS_RES_IRQ, irq, 1075 nic->msix_entries[irq].irq_res); 1076 } 1077 } 1078 1079 static int 1080 nic_register_interrupts(struct nicpf *nic) 1081 { 1082 int irq, rid; 1083 int ret; 1084 1085 /* Enable MSI-X */ 1086 ret = nic_enable_msix(nic); 1087 if (ret != 0) 1088 return (ret); 1089 1090 /* Register mailbox interrupt handlers */ 1091 irq = NIC_PF_INTR_ID_MBOX0; 1092 rid = irq + 1; 1093 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1094 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1095 if (nic->msix_entries[irq].irq_res == NULL) { 1096 ret = ENXIO; 1097 goto fail; 1098 } 1099 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1100 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, 1101 &nic->msix_entries[irq].handle); 1102 if (ret != 0) 1103 goto fail; 1104 1105 irq = NIC_PF_INTR_ID_MBOX1; 1106 rid = irq + 1; 1107 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1108 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1109 if (nic->msix_entries[irq].irq_res == NULL) { 1110 ret = ENXIO; 1111 goto fail; 1112 } 1113 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1114 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, 1115 &nic->msix_entries[irq].handle); 1116 if (ret != 0) 1117 goto fail; 1118 1119 /* Enable mailbox interrupt */ 1120 nic_enable_mbx_intr(nic); 1121 return (0); 1122 1123 fail: 1124 nic_free_all_interrupts(nic); 1125 return (ret); 1126 } 1127 1128 static void 1129 nic_unregister_interrupts(struct nicpf *nic) 1130 { 1131 1132 nic_free_all_interrupts(nic); 1133 nic_disable_msix(nic); 1134 } 1135 1136 static int nic_sriov_init(device_t dev, struct nicpf *nic) 1137 { 1138 #ifdef PCI_IOV 1139 nvlist_t *pf_schema, *vf_schema; 1140 int iov_pos; 1141 int err; 1142 uint16_t total_vf_cnt; 1143 1144 err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 1145 if (err != 0) { 1146 device_printf(dev, 1147 "SR-IOV capability is not found in PCIe config space\n"); 1148 return (err); 1149 } 1150 /* Fix-up the number of enabled VFs */ 1151 total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); 1152 if (total_vf_cnt == 0) 1153 return (ENXIO); 1154 1155 /* Attach SR-IOV */ 1156 pf_schema = pci_iov_schema_alloc_node(); 1157 vf_schema = pci_iov_schema_alloc_node(); 1158 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 1159 /* 1160 * All VFs can change their MACs. 1161 * This flag will be ignored but we set it just for the record. 1162 */ 1163 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 1164 IOV_SCHEMA_HASDEFAULT, TRUE); 1165 1166 err = pci_iov_attach(dev, pf_schema, vf_schema); 1167 if (err != 0) { 1168 device_printf(dev, 1169 "Failed to initialize SR-IOV (error=%d)\n", 1170 err); 1171 return (err); 1172 } 1173 #endif 1174 return (0); 1175 } 1176 1177 /* 1178 * Poll for BGX LMAC link status and update corresponding VF 1179 * if there is a change, valid only if internal L2 switch 1180 * is not present otherwise VF link is always treated as up 1181 */ 1182 static void 1183 nic_poll_for_link(void *arg) 1184 { 1185 union nic_mbx mbx = {}; 1186 struct nicpf *nic; 1187 struct bgx_link_status link; 1188 uint8_t vf, bgx, lmac; 1189 1190 nic = (struct nicpf *)arg; 1191 1192 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1193 1194 for (vf = 0; vf < nic->num_vf_en; vf++) { 1195 /* Poll only if VF is UP */ 1196 if (!nic->vf_info[vf].vf_enabled) 1197 continue; 1198 1199 /* Get BGX, LMAC indices for the VF */ 1200 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1201 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1202 /* Get interface link status */ 1203 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1204 1205 /* Inform VF only if link status changed */ 1206 if (nic->link[vf] == link.link_up) 1207 continue; 1208 1209 if (!nic->mbx_lock[vf]) { 1210 nic->link[vf] = link.link_up; 1211 nic->duplex[vf] = link.duplex; 1212 nic->speed[vf] = link.speed; 1213 1214 /* Send a mbox message to VF with current link status */ 1215 mbx.link_status.link_up = link.link_up; 1216 mbx.link_status.duplex = link.duplex; 1217 mbx.link_status.speed = link.speed; 1218 nic_send_msg_to_vf(nic, vf, &mbx); 1219 } 1220 } 1221 callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); 1222 } 1223