1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bitset.h> 36 #include <sys/bitstring.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/rman.h> 43 #include <sys/pciio.h> 44 #include <sys/pcpu.h> 45 #include <sys/proc.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/cpuset.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 52 #include <net/ethernet.h> 53 #include <net/if.h> 54 #include <net/if_media.h> 55 56 #include <machine/bus.h> 57 #include <machine/_inttypes.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 62 #include <sys/dnv.h> 63 #include <sys/nv.h> 64 #ifdef PCI_IOV 65 #include <sys/iov_schema.h> 66 #include <dev/pci/pci_iov.h> 67 #endif 68 69 #include "thunder_bgx.h" 70 #include "nic_reg.h" 71 #include "nic.h" 72 #include "q_struct.h" 73 74 #define VNIC_PF_DEVSTR "Cavium Thunder NIC Physical Function Driver" 75 76 #define VNIC_PF_REG_RID PCIR_BAR(PCI_CFG_REG_BAR_NUM) 77 78 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF)) 79 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF) 80 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF) 81 82 /* Structure to be used by the SR-IOV for VF configuration schemas */ 83 struct nicvf_info { 84 boolean_t vf_enabled; 85 int vf_flags; 86 }; 87 88 struct nicpf { 89 device_t dev; 90 uint8_t rev_id; 91 uint8_t node; 92 u_int flags; 93 uint8_t num_vf_en; /* No of VF enabled */ 94 struct nicvf_info vf_info[MAX_NUM_VFS_SUPPORTED]; 95 struct resource * reg_base; /* Register start address */ 96 struct pkind_cfg pkind; 97 uint8_t vf_lmac_map[MAX_LMAC]; 98 boolean_t mbx_lock[MAX_NUM_VFS_SUPPORTED]; 99 100 struct callout check_link; 101 struct mtx check_link_mtx; 102 103 uint8_t link[MAX_LMAC]; 104 uint8_t duplex[MAX_LMAC]; 105 uint32_t speed[MAX_LMAC]; 106 uint16_t cpi_base[MAX_NUM_VFS_SUPPORTED]; 107 uint16_t rss_ind_tbl_size; 108 109 /* MSI-X */ 110 boolean_t msix_enabled; 111 uint8_t num_vec; 112 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS]; 113 struct resource * msix_table_res; 114 }; 115 116 static int nicpf_probe(device_t); 117 static int nicpf_attach(device_t); 118 static int nicpf_detach(device_t); 119 120 #ifdef PCI_IOV 121 static int nicpf_iov_init(device_t, uint16_t, const nvlist_t *); 122 static void nicpf_iov_uninit(device_t); 123 static int nicpf_iov_addr_vf(device_t, uint16_t, const nvlist_t *); 124 #endif 125 126 static device_method_t nicpf_methods[] = { 127 /* Device interface */ 128 DEVMETHOD(device_probe, nicpf_probe), 129 DEVMETHOD(device_attach, nicpf_attach), 130 DEVMETHOD(device_detach, nicpf_detach), 131 /* PCI SR-IOV interface */ 132 #ifdef PCI_IOV 133 DEVMETHOD(pci_iov_init, nicpf_iov_init), 134 DEVMETHOD(pci_iov_uninit, nicpf_iov_uninit), 135 DEVMETHOD(pci_iov_add_vf, nicpf_iov_addr_vf), 136 #endif 137 DEVMETHOD_END, 138 }; 139 140 static driver_t nicpf_driver = { 141 "vnicpf", 142 nicpf_methods, 143 sizeof(struct nicpf), 144 }; 145 146 static devclass_t nicpf_devclass; 147 148 DRIVER_MODULE(nicpf, pci, nicpf_driver, nicpf_devclass, 0, 0); 149 MODULE_DEPEND(nicpf, pci, 1, 1, 1); 150 MODULE_DEPEND(nicpf, ether, 1, 1, 1); 151 MODULE_DEPEND(nicpf, thunder_bgx, 1, 1, 1); 152 153 static int nicpf_alloc_res(struct nicpf *); 154 static void nicpf_free_res(struct nicpf *); 155 static void nic_set_lmac_vf_mapping(struct nicpf *); 156 static void nic_init_hw(struct nicpf *); 157 static int nic_sriov_init(device_t, struct nicpf *); 158 static void nic_poll_for_link(void *); 159 static int nic_register_interrupts(struct nicpf *); 160 static void nic_unregister_interrupts(struct nicpf *); 161 162 /* 163 * Device interface 164 */ 165 static int 166 nicpf_probe(device_t dev) 167 { 168 uint16_t vendor_id; 169 uint16_t device_id; 170 171 vendor_id = pci_get_vendor(dev); 172 device_id = pci_get_device(dev); 173 174 if (vendor_id == PCI_VENDOR_ID_CAVIUM && 175 device_id == PCI_DEVICE_ID_THUNDER_NIC_PF) { 176 device_set_desc(dev, VNIC_PF_DEVSTR); 177 return (BUS_PROBE_DEFAULT); 178 } 179 180 return (ENXIO); 181 } 182 183 static int 184 nicpf_attach(device_t dev) 185 { 186 struct nicpf *nic; 187 int err; 188 189 nic = device_get_softc(dev); 190 nic->dev = dev; 191 192 /* Enable bus mastering */ 193 pci_enable_busmaster(dev); 194 195 /* Allocate PCI resources */ 196 err = nicpf_alloc_res(nic); 197 if (err != 0) { 198 device_printf(dev, "Could not allocate PCI resources\n"); 199 return (err); 200 } 201 202 nic->node = nic_get_node_id(nic->reg_base); 203 nic->rev_id = pci_read_config(dev, PCIR_REVID, 1); 204 205 /* Enable Traffic Network Switch (TNS) bypass mode by default */ 206 nic->flags &= ~NIC_TNS_ENABLED; 207 nic_set_lmac_vf_mapping(nic); 208 209 /* Initialize hardware */ 210 nic_init_hw(nic); 211 212 /* Set RSS TBL size for each VF */ 213 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE; 214 215 /* Setup interrupts */ 216 err = nic_register_interrupts(nic); 217 if (err != 0) 218 goto err_free_res; 219 220 /* Configure SRIOV */ 221 err = nic_sriov_init(dev, nic); 222 if (err != 0) 223 goto err_free_intr; 224 225 if (nic->flags & NIC_TNS_ENABLED) 226 return (0); 227 228 mtx_init(&nic->check_link_mtx, "VNIC PF link poll", NULL, MTX_DEF); 229 /* Register physical link status poll callout */ 230 callout_init_mtx(&nic->check_link, &nic->check_link_mtx, 0); 231 mtx_lock(&nic->check_link_mtx); 232 nic_poll_for_link(nic); 233 mtx_unlock(&nic->check_link_mtx); 234 235 return (0); 236 237 err_free_intr: 238 nic_unregister_interrupts(nic); 239 err_free_res: 240 nicpf_free_res(nic); 241 pci_disable_busmaster(dev); 242 243 return (err); 244 } 245 246 static int 247 nicpf_detach(device_t dev) 248 { 249 struct nicpf *nic; 250 251 nic = device_get_softc(dev); 252 253 callout_drain(&nic->check_link); 254 mtx_destroy(&nic->check_link_mtx); 255 256 nic_unregister_interrupts(nic); 257 nicpf_free_res(nic); 258 pci_disable_busmaster(dev); 259 260 return (0); 261 } 262 263 /* 264 * SR-IOV interface 265 */ 266 #ifdef PCI_IOV 267 static int 268 nicpf_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *params) 269 { 270 struct nicpf *nic; 271 272 nic = device_get_softc(dev); 273 274 nic->num_vf_en = 0; 275 if (num_vfs == 0) 276 return (ENXIO); 277 if (num_vfs > MAX_NUM_VFS_SUPPORTED) 278 return (EINVAL); 279 280 /* 281 * Just set variables here. 282 * The number of VFs will be written to configuration 283 * space later in PCI_ADD_VF(). 284 */ 285 nic->num_vf_en = num_vfs; 286 nic->flags |= NIC_SRIOV_ENABLED; 287 288 return (0); 289 } 290 291 static void 292 nicpf_iov_uninit(device_t dev) 293 { 294 295 /* ARM64TODO: Implement this function */ 296 } 297 298 static int 299 nicpf_iov_addr_vf(device_t dev, uint16_t vfnum, const nvlist_t *params) 300 { 301 const void *mac; 302 struct nicpf *nic; 303 size_t size; 304 int bgx, lmac; 305 306 nic = device_get_softc(dev); 307 308 if ((nic->flags & NIC_SRIOV_ENABLED) == 0) 309 return (ENXIO); 310 311 if (nvlist_exists_binary(params, "mac-addr") != 0) { 312 mac = nvlist_get_binary(params, "mac-addr", &size); 313 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 314 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vfnum]); 315 bgx_set_lmac_mac(nic->node, bgx, lmac, mac); 316 } 317 318 return (0); 319 } 320 #endif 321 322 /* 323 * Helper routines 324 */ 325 static int 326 nicpf_alloc_res(struct nicpf *nic) 327 { 328 device_t dev; 329 int rid; 330 331 dev = nic->dev; 332 333 rid = VNIC_PF_REG_RID; 334 nic->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 335 RF_ACTIVE); 336 if (nic->reg_base == NULL) { 337 /* For verbose output print some more details */ 338 if (bootverbose) { 339 device_printf(dev, 340 "Could not allocate registers memory\n"); 341 } 342 return (ENXIO); 343 } 344 345 return (0); 346 } 347 348 static void 349 nicpf_free_res(struct nicpf *nic) 350 { 351 device_t dev; 352 353 dev = nic->dev; 354 355 if (nic->reg_base != NULL) { 356 bus_release_resource(dev, SYS_RES_MEMORY, 357 rman_get_rid(nic->reg_base), nic->reg_base); 358 } 359 } 360 361 /* Register read/write APIs */ 362 static __inline void 363 nic_reg_write(struct nicpf *nic, bus_space_handle_t offset, 364 uint64_t val) 365 { 366 367 bus_write_8(nic->reg_base, offset, val); 368 } 369 370 static __inline uint64_t 371 nic_reg_read(struct nicpf *nic, uint64_t offset) 372 { 373 uint64_t val; 374 375 val = bus_read_8(nic->reg_base, offset); 376 return (val); 377 } 378 379 /* PF -> VF mailbox communication APIs */ 380 static void 381 nic_enable_mbx_intr(struct nicpf *nic) 382 { 383 384 /* Enable mailbox interrupt for all 128 VFs */ 385 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0UL); 386 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(uint64_t), ~0UL); 387 } 388 389 static void 390 nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg) 391 { 392 393 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), (1UL << vf)); 394 } 395 396 static uint64_t 397 nic_get_mbx_addr(int vf) 398 { 399 400 return (NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT)); 401 } 402 403 /* 404 * Send a mailbox message to VF 405 * @vf: vf to which this message to be sent 406 * @mbx: Message to be sent 407 */ 408 static void 409 nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx) 410 { 411 bus_space_handle_t mbx_addr = nic_get_mbx_addr(vf); 412 uint64_t *msg = (uint64_t *)mbx; 413 414 /* 415 * In first revision HW, mbox interrupt is triggerred 416 * when PF writes to MBOX(1), in next revisions when 417 * PF writes to MBOX(0) 418 */ 419 if (nic->rev_id == 0) { 420 nic_reg_write(nic, mbx_addr + 0, msg[0]); 421 nic_reg_write(nic, mbx_addr + 8, msg[1]); 422 } else { 423 nic_reg_write(nic, mbx_addr + 8, msg[1]); 424 nic_reg_write(nic, mbx_addr + 0, msg[0]); 425 } 426 } 427 428 /* 429 * Responds to VF's READY message with VF's 430 * ID, node, MAC address e.t.c 431 * @vf: VF which sent READY message 432 */ 433 static void 434 nic_mbx_send_ready(struct nicpf *nic, int vf) 435 { 436 union nic_mbx mbx = {}; 437 int bgx_idx, lmac; 438 const char *mac; 439 440 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY; 441 mbx.nic_cfg.vf_id = vf; 442 443 if (nic->flags & NIC_TNS_ENABLED) 444 mbx.nic_cfg.tns_mode = NIC_TNS_MODE; 445 else 446 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE; 447 448 if (vf < MAX_LMAC) { 449 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 450 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 451 452 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac); 453 if (mac) { 454 memcpy((uint8_t *)&mbx.nic_cfg.mac_addr, mac, 455 ETHER_ADDR_LEN); 456 } 457 } 458 mbx.nic_cfg.node_id = nic->node; 459 460 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC; 461 462 nic_send_msg_to_vf(nic, vf, &mbx); 463 } 464 465 /* 466 * ACKs VF's mailbox message 467 * @vf: VF to which ACK to be sent 468 */ 469 static void 470 nic_mbx_send_ack(struct nicpf *nic, int vf) 471 { 472 union nic_mbx mbx = {}; 473 474 mbx.msg.msg = NIC_MBOX_MSG_ACK; 475 nic_send_msg_to_vf(nic, vf, &mbx); 476 } 477 478 /* 479 * NACKs VF's mailbox message that PF is not able to 480 * complete the action 481 * @vf: VF to which ACK to be sent 482 */ 483 static void 484 nic_mbx_send_nack(struct nicpf *nic, int vf) 485 { 486 union nic_mbx mbx = {}; 487 488 mbx.msg.msg = NIC_MBOX_MSG_NACK; 489 nic_send_msg_to_vf(nic, vf, &mbx); 490 } 491 492 /* 493 * Flush all in flight receive packets to memory and 494 * bring down an active RQ 495 */ 496 static int 497 nic_rcv_queue_sw_sync(struct nicpf *nic) 498 { 499 uint16_t timeout = ~0x00; 500 501 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01); 502 /* Wait till sync cycle is finished */ 503 while (timeout) { 504 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1) 505 break; 506 timeout--; 507 } 508 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00); 509 if (!timeout) { 510 device_printf(nic->dev, "Receive queue software sync failed\n"); 511 return (ETIMEDOUT); 512 } 513 return (0); 514 } 515 516 /* Get BGX Rx/Tx stats and respond to VF's request */ 517 static void 518 nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx) 519 { 520 int bgx_idx, lmac; 521 union nic_mbx mbx = {}; 522 523 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 524 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]); 525 526 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS; 527 mbx.bgx_stats.vf_id = bgx->vf_id; 528 mbx.bgx_stats.rx = bgx->rx; 529 mbx.bgx_stats.idx = bgx->idx; 530 if (bgx->rx != 0) { 531 mbx.bgx_stats.stats = 532 bgx_get_rx_stats(nic->node, bgx_idx, lmac, bgx->idx); 533 } else { 534 mbx.bgx_stats.stats = 535 bgx_get_tx_stats(nic->node, bgx_idx, lmac, bgx->idx); 536 } 537 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx); 538 } 539 540 /* Update hardware min/max frame size */ 541 static int 542 nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf) 543 { 544 545 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) { 546 device_printf(nic->dev, 547 "Invalid MTU setting from VF%d rejected, " 548 "should be between %d and %d\n", 549 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS); 550 return (EINVAL); 551 } 552 new_frs += ETHER_HDR_LEN; 553 if (new_frs <= nic->pkind.maxlen) 554 return (0); 555 556 nic->pkind.maxlen = new_frs; 557 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(uint64_t *)&nic->pkind); 558 return (0); 559 } 560 561 /* Set minimum transmit packet size */ 562 static void 563 nic_set_tx_pkt_pad(struct nicpf *nic, int size) 564 { 565 int lmac; 566 uint64_t lmac_cfg; 567 568 /* Max value that can be set is 60 */ 569 if (size > 60) 570 size = 60; 571 572 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) { 573 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3)); 574 lmac_cfg &= ~(0xF << 2); 575 lmac_cfg |= ((size / 4) << 2); 576 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg); 577 } 578 } 579 580 /* 581 * Function to check number of LMACs present and set VF::LMAC mapping. 582 * Mapping will be used while initializing channels. 583 */ 584 static void 585 nic_set_lmac_vf_mapping(struct nicpf *nic) 586 { 587 unsigned bgx_map = bgx_get_map(nic->node); 588 int bgx, next_bgx_lmac = 0; 589 int lmac, lmac_cnt = 0; 590 uint64_t lmac_credit; 591 592 nic->num_vf_en = 0; 593 if (nic->flags & NIC_TNS_ENABLED) { 594 nic->num_vf_en = DEFAULT_NUM_VF_ENABLED; 595 return; 596 } 597 598 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) { 599 if ((bgx_map & (1 << bgx)) == 0) 600 continue; 601 lmac_cnt = bgx_get_lmac_count(nic->node, bgx); 602 for (lmac = 0; lmac < lmac_cnt; lmac++) 603 nic->vf_lmac_map[next_bgx_lmac++] = 604 NIC_SET_VF_LMAC_MAP(bgx, lmac); 605 nic->num_vf_en += lmac_cnt; 606 607 /* Program LMAC credits */ 608 lmac_credit = (1UL << 1); /* channel credit enable */ 609 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */ 610 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */ 611 lmac_credit |= (((((48 * 1024) / lmac_cnt) - 612 NIC_HW_MAX_FRS) / 16) << 12); 613 lmac = bgx * MAX_LMAC_PER_BGX; 614 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++) { 615 nic_reg_write(nic, NIC_PF_LMAC_0_7_CREDIT + (lmac * 8), 616 lmac_credit); 617 } 618 } 619 } 620 621 #define TNS_PORT0_BLOCK 6 622 #define TNS_PORT1_BLOCK 7 623 #define BGX0_BLOCK 8 624 #define BGX1_BLOCK 9 625 626 static void 627 nic_init_hw(struct nicpf *nic) 628 { 629 int i; 630 631 /* Reset NIC, in case the driver is repeatedly inserted and removed */ 632 nic_reg_write(nic, NIC_PF_SOFT_RESET, 1); 633 634 /* Enable NIC HW block */ 635 nic_reg_write(nic, NIC_PF_CFG, 0x3); 636 637 /* Enable backpressure */ 638 nic_reg_write(nic, NIC_PF_BP_CFG, (1UL << 6) | 0x03); 639 640 if (nic->flags & NIC_TNS_ENABLED) { 641 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 642 (NIC_TNS_MODE << 7) | TNS_PORT0_BLOCK); 643 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 644 (NIC_TNS_MODE << 7) | TNS_PORT1_BLOCK); 645 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 646 (1UL << 63) | TNS_PORT0_BLOCK); 647 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 648 (1UL << 63) | TNS_PORT1_BLOCK); 649 650 } else { 651 /* Disable TNS mode on both interfaces */ 652 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG, 653 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK); 654 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8), 655 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK); 656 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG, 657 (1UL << 63) | BGX0_BLOCK); 658 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8), 659 (1UL << 63) | BGX1_BLOCK); 660 } 661 662 /* PKIND configuration */ 663 nic->pkind.minlen = 0; 664 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETHER_HDR_LEN; 665 nic->pkind.lenerr_en = 1; 666 nic->pkind.rx_hdr = 0; 667 nic->pkind.hdr_sl = 0; 668 669 for (i = 0; i < NIC_MAX_PKIND; i++) { 670 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3), 671 *(uint64_t *)&nic->pkind); 672 } 673 674 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS); 675 676 /* Timer config */ 677 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK); 678 679 /* Enable VLAN ethertype matching and stripping */ 680 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7, 681 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETHERTYPE_VLAN); 682 } 683 684 /* Channel parse index configuration */ 685 static void 686 nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg) 687 { 688 uint32_t vnic, bgx, lmac, chan; 689 uint32_t padd, cpi_count = 0; 690 uint64_t cpi_base, cpi, rssi_base, rssi; 691 uint8_t qset, rq_idx = 0; 692 693 vnic = cfg->vf_id; 694 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 695 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]); 696 697 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 698 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX); 699 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX); 700 701 /* Rx channel configuration */ 702 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3), 703 (1UL << 63) | (vnic << 0)); 704 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3), 705 ((uint64_t)cfg->cpi_alg << 62) | (cpi_base << 48)); 706 707 if (cfg->cpi_alg == CPI_ALG_NONE) 708 cpi_count = 1; 709 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */ 710 cpi_count = 8; 711 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */ 712 cpi_count = 16; 713 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */ 714 cpi_count = NIC_MAX_CPI_PER_LMAC; 715 716 /* RSS Qset, Qidx mapping */ 717 qset = cfg->vf_id; 718 rssi = rssi_base; 719 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) { 720 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3), 721 (qset << 3) | rq_idx); 722 rq_idx++; 723 } 724 725 rssi = 0; 726 cpi = cpi_base; 727 for (; cpi < (cpi_base + cpi_count); cpi++) { 728 /* Determine port to channel adder */ 729 if (cfg->cpi_alg != CPI_ALG_DIFF) 730 padd = cpi % cpi_count; 731 else 732 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */ 733 734 /* Leave RSS_SIZE as '0' to disable RSS */ 735 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3), 736 (vnic << 24) | (padd << 16) | (rssi_base + rssi)); 737 738 if ((rssi + 1) >= cfg->rq_cnt) 739 continue; 740 741 if (cfg->cpi_alg == CPI_ALG_VLAN) 742 rssi++; 743 else if (cfg->cpi_alg == CPI_ALG_VLAN16) 744 rssi = ((cpi - cpi_base) & 0xe) >> 1; 745 else if (cfg->cpi_alg == CPI_ALG_DIFF) 746 rssi = ((cpi - cpi_base) & 0x38) >> 3; 747 } 748 nic->cpi_base[cfg->vf_id] = cpi_base; 749 } 750 751 /* 752 * 4 level transmit side scheduler configutation 753 * for TNS bypass mode 754 * 755 * Sample configuration for SQ0 756 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0 757 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0 758 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0 759 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0 760 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1 761 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1 762 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1 763 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1 764 */ 765 static void 766 nic_tx_channel_cfg(struct nicpf *nic, uint8_t vnic, struct sq_cfg_msg *sq) 767 { 768 uint32_t bgx, lmac, chan; 769 uint32_t tl2, tl3, tl4; 770 uint32_t rr_quantum; 771 uint8_t sq_idx = sq->sq_num; 772 uint8_t pqs_vnic; 773 774 pqs_vnic = vnic; 775 776 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 777 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]); 778 779 /* 24 bytes for FCS, IPG and preamble */ 780 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4); 781 782 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX); 783 tl4 += sq_idx; 784 785 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3); 786 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 | 787 ((uint64_t)vnic << NIC_QS_ID_SHIFT) | 788 ((uint32_t)sq_idx << NIC_Q_NUM_SHIFT), tl4); 789 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3), 790 ((uint64_t)vnic << 27) | ((uint32_t)sq_idx << 24) | rr_quantum); 791 792 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum); 793 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF); 794 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan); 795 /* Enable backpressure on the channel */ 796 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1); 797 798 tl2 = tl3 >> 2; 799 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2); 800 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum); 801 /* No priorities as of now */ 802 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00); 803 } 804 805 static int 806 nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk) 807 { 808 int bgx_idx, lmac_idx; 809 810 if (lbk->vf_id > MAX_LMAC) 811 return (ENXIO); 812 813 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 814 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]); 815 816 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable); 817 818 return (0); 819 } 820 821 /* Interrupt handler to handle mailbox messages from VFs */ 822 static void 823 nic_handle_mbx_intr(struct nicpf *nic, int vf) 824 { 825 union nic_mbx mbx = {}; 826 uint64_t *mbx_data; 827 uint64_t mbx_addr; 828 uint64_t reg_addr; 829 uint64_t cfg; 830 int bgx, lmac; 831 int i; 832 int ret = 0; 833 834 nic->mbx_lock[vf] = TRUE; 835 836 mbx_addr = nic_get_mbx_addr(vf); 837 mbx_data = (uint64_t *)&mbx; 838 839 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) { 840 *mbx_data = nic_reg_read(nic, mbx_addr); 841 mbx_data++; 842 mbx_addr += sizeof(uint64_t); 843 } 844 845 switch (mbx.msg.msg) { 846 case NIC_MBOX_MSG_READY: 847 nic_mbx_send_ready(nic, vf); 848 if (vf < MAX_LMAC) { 849 nic->link[vf] = 0; 850 nic->duplex[vf] = 0; 851 nic->speed[vf] = 0; 852 } 853 ret = 1; 854 break; 855 case NIC_MBOX_MSG_QS_CFG: 856 reg_addr = NIC_PF_QSET_0_127_CFG | 857 (mbx.qs.num << NIC_QS_ID_SHIFT); 858 cfg = mbx.qs.cfg; 859 nic_reg_write(nic, reg_addr, cfg); 860 break; 861 case NIC_MBOX_MSG_RQ_CFG: 862 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG | 863 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 864 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 865 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 866 break; 867 case NIC_MBOX_MSG_RQ_BP_CFG: 868 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG | 869 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 870 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 871 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 872 break; 873 case NIC_MBOX_MSG_RQ_SW_SYNC: 874 ret = nic_rcv_queue_sw_sync(nic); 875 break; 876 case NIC_MBOX_MSG_RQ_DROP_CFG: 877 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG | 878 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) | 879 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT); 880 nic_reg_write(nic, reg_addr, mbx.rq.cfg); 881 break; 882 case NIC_MBOX_MSG_SQ_CFG: 883 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG | 884 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) | 885 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT); 886 nic_reg_write(nic, reg_addr, mbx.sq.cfg); 887 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq); 888 break; 889 case NIC_MBOX_MSG_SET_MAC: 890 lmac = mbx.mac.vf_id; 891 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 892 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]); 893 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr); 894 break; 895 case NIC_MBOX_MSG_SET_MAX_FRS: 896 ret = nic_update_hw_frs(nic, mbx.frs.max_frs, mbx.frs.vf_id); 897 break; 898 case NIC_MBOX_MSG_CPI_CFG: 899 nic_config_cpi(nic, &mbx.cpi_cfg); 900 break; 901 case NIC_MBOX_MSG_CFG_DONE: 902 /* Last message of VF config msg sequence */ 903 nic->vf_info[vf].vf_enabled = TRUE; 904 goto unlock; 905 case NIC_MBOX_MSG_SHUTDOWN: 906 /* First msg in VF teardown sequence */ 907 nic->vf_info[vf].vf_enabled = FALSE; 908 break; 909 case NIC_MBOX_MSG_BGX_STATS: 910 nic_get_bgx_stats(nic, &mbx.bgx_stats); 911 goto unlock; 912 case NIC_MBOX_MSG_LOOPBACK: 913 ret = nic_config_loopback(nic, &mbx.lbk); 914 break; 915 default: 916 device_printf(nic->dev, 917 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg); 918 break; 919 } 920 921 if (ret == 0) 922 nic_mbx_send_ack(nic, vf); 923 else if (mbx.msg.msg != NIC_MBOX_MSG_READY) 924 nic_mbx_send_nack(nic, vf); 925 unlock: 926 nic->mbx_lock[vf] = FALSE; 927 } 928 929 static void 930 nic_mbx_intr_handler(struct nicpf *nic, int mbx) 931 { 932 uint64_t intr; 933 uint8_t vf, vf_per_mbx_reg = 64; 934 935 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3)); 936 for (vf = 0; vf < vf_per_mbx_reg; vf++) { 937 if (intr & (1UL << vf)) { 938 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg)); 939 nic_clear_mbx_intr(nic, vf, mbx); 940 } 941 } 942 } 943 944 static void 945 nic_mbx0_intr_handler (void *arg) 946 { 947 struct nicpf *nic = (struct nicpf *)arg; 948 949 nic_mbx_intr_handler(nic, 0); 950 } 951 952 static void 953 nic_mbx1_intr_handler (void *arg) 954 { 955 struct nicpf *nic = (struct nicpf *)arg; 956 957 nic_mbx_intr_handler(nic, 1); 958 } 959 960 static int 961 nic_enable_msix(struct nicpf *nic) 962 { 963 struct pci_devinfo *dinfo; 964 int rid, count; 965 int ret; 966 967 dinfo = device_get_ivars(nic->dev); 968 rid = dinfo->cfg.msix.msix_table_bar; 969 nic->msix_table_res = 970 bus_alloc_resource_any(nic->dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); 971 if (nic->msix_table_res == NULL) { 972 device_printf(nic->dev, 973 "Could not allocate memory for MSI-X table\n"); 974 return (ENXIO); 975 } 976 977 count = nic->num_vec = NIC_PF_MSIX_VECTORS; 978 979 ret = pci_alloc_msix(nic->dev, &count); 980 if ((ret != 0) || (count != nic->num_vec)) { 981 device_printf(nic->dev, 982 "Request for #%d msix vectors failed, error: %d\n", 983 nic->num_vec, ret); 984 return (ret); 985 } 986 987 nic->msix_enabled = 1; 988 return (0); 989 } 990 991 static void 992 nic_disable_msix(struct nicpf *nic) 993 { 994 if (nic->msix_enabled) { 995 pci_release_msi(nic->dev); 996 nic->msix_enabled = 0; 997 nic->num_vec = 0; 998 } 999 } 1000 1001 static void 1002 nic_free_all_interrupts(struct nicpf *nic) 1003 { 1004 int irq; 1005 1006 for (irq = 0; irq < nic->num_vec; irq++) { 1007 if (nic->msix_entries[irq].irq_res == NULL) 1008 continue; 1009 if (nic->msix_entries[irq].handle != NULL) { 1010 bus_teardown_intr(nic->dev, 1011 nic->msix_entries[irq].irq_res, 1012 nic->msix_entries[irq].handle); 1013 } 1014 1015 bus_release_resource(nic->dev, SYS_RES_IRQ, irq, 1016 nic->msix_entries[irq].irq_res); 1017 } 1018 } 1019 1020 static int 1021 nic_register_interrupts(struct nicpf *nic) 1022 { 1023 int irq, rid; 1024 int ret; 1025 1026 /* Enable MSI-X */ 1027 ret = nic_enable_msix(nic); 1028 if (ret != 0) 1029 return (ret); 1030 1031 /* Register mailbox interrupt handlers */ 1032 irq = NIC_PF_INTR_ID_MBOX0; 1033 rid = irq + 1; 1034 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1035 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1036 if (nic->msix_entries[irq].irq_res == NULL) { 1037 ret = ENXIO; 1038 goto fail; 1039 } 1040 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1041 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx0_intr_handler, nic, 1042 &nic->msix_entries[irq].handle); 1043 if (ret != 0) 1044 goto fail; 1045 1046 irq = NIC_PF_INTR_ID_MBOX1; 1047 rid = irq + 1; 1048 nic->msix_entries[irq].irq_res = bus_alloc_resource_any(nic->dev, 1049 SYS_RES_IRQ, &rid, (RF_SHAREABLE | RF_ACTIVE)); 1050 if (nic->msix_entries[irq].irq_res == NULL) { 1051 ret = ENXIO; 1052 goto fail; 1053 } 1054 ret = bus_setup_intr(nic->dev, nic->msix_entries[irq].irq_res, 1055 (INTR_MPSAFE | INTR_TYPE_MISC), NULL, nic_mbx1_intr_handler, nic, 1056 &nic->msix_entries[irq].handle); 1057 if (ret != 0) 1058 goto fail; 1059 1060 /* Enable mailbox interrupt */ 1061 nic_enable_mbx_intr(nic); 1062 return (0); 1063 1064 fail: 1065 nic_free_all_interrupts(nic); 1066 return (ret); 1067 } 1068 1069 static void 1070 nic_unregister_interrupts(struct nicpf *nic) 1071 { 1072 1073 nic_free_all_interrupts(nic); 1074 nic_disable_msix(nic); 1075 } 1076 1077 static int nic_sriov_init(device_t dev, struct nicpf *nic) 1078 { 1079 #ifdef PCI_IOV 1080 nvlist_t *pf_schema, *vf_schema; 1081 int iov_pos; 1082 int err; 1083 uint16_t total_vf_cnt; 1084 1085 err = pci_find_extcap(dev, PCIZ_SRIOV, &iov_pos); 1086 if (err != 0) { 1087 device_printf(dev, 1088 "SR-IOV capability is not found in PCIe config space\n"); 1089 return (err); 1090 } 1091 /* Fix-up the number of enabled VFs */ 1092 total_vf_cnt = pci_read_config(dev, iov_pos + PCIR_SRIOV_TOTAL_VFS, 2); 1093 if (total_vf_cnt < nic->num_vf_en) 1094 nic->num_vf_en = total_vf_cnt; 1095 1096 if (total_vf_cnt == 0) 1097 return (0); 1098 1099 /* Attach SR-IOV */ 1100 pf_schema = pci_iov_schema_alloc_node(); 1101 vf_schema = pci_iov_schema_alloc_node(); 1102 pci_iov_schema_add_unicast_mac(vf_schema, "mac-addr", 0, NULL); 1103 /* 1104 * All VFs can change their MACs. 1105 * This flag will be ignored but we set it just for the record. 1106 */ 1107 pci_iov_schema_add_bool(vf_schema, "allow-set-mac", 1108 IOV_SCHEMA_HASDEFAULT, TRUE); 1109 1110 err = pci_iov_attach(dev, pf_schema, vf_schema); 1111 if (err != 0) { 1112 device_printf(dev, 1113 "Failed to initialize SR-IOV (error=%d)\n", 1114 err); 1115 nic->num_vf_en = 0; 1116 return (err); 1117 } 1118 #endif 1119 return (0); 1120 } 1121 1122 /* 1123 * Poll for BGX LMAC link status and update corresponding VF 1124 * if there is a change, valid only if internal L2 switch 1125 * is not present otherwise VF link is always treated as up 1126 */ 1127 static void 1128 nic_poll_for_link(void *arg) 1129 { 1130 union nic_mbx mbx = {}; 1131 struct nicpf *nic; 1132 struct bgx_link_status link; 1133 uint8_t vf, bgx, lmac; 1134 1135 nic = (struct nicpf *)arg; 1136 1137 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE; 1138 1139 for (vf = 0; vf < nic->num_vf_en; vf++) { 1140 /* Poll only if VF is UP */ 1141 if (!nic->vf_info[vf].vf_enabled) 1142 continue; 1143 1144 /* Get BGX, LMAC indices for the VF */ 1145 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1146 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]); 1147 /* Get interface link status */ 1148 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link); 1149 1150 /* Inform VF only if link status changed */ 1151 if (nic->link[vf] == link.link_up) 1152 continue; 1153 1154 if (!nic->mbx_lock[vf]) { 1155 nic->link[vf] = link.link_up; 1156 nic->duplex[vf] = link.duplex; 1157 nic->speed[vf] = link.speed; 1158 1159 /* Send a mbox message to VF with current link status */ 1160 mbx.link_status.link_up = link.link_up; 1161 mbx.link_status.duplex = link.duplex; 1162 mbx.link_status.speed = link.speed; 1163 nic_send_msg_to_vf(nic, vf, &mbx); 1164 } 1165 } 1166 callout_reset(&nic->check_link, hz * 2, nic_poll_for_link, nic); 1167 } 1168