1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28 #ifndef NIC_H 29 #define NIC_H 30 31 /* PCI vendor ID */ 32 #define PCI_VENDOR_ID_CAVIUM 0x177D 33 /* PCI device IDs */ 34 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 35 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 36 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 37 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 38 39 /* PCI BAR nos */ 40 #define PCI_CFG_REG_BAR_NUM 0 41 #define PCI_MSIX_REG_BAR_NUM 4 42 43 /* PCI revision IDs */ 44 #define PCI_REVID_PASS2 8 45 46 /* NIC SRIOV VF count */ 47 #define MAX_NUM_VFS_SUPPORTED 128 48 #define DEFAULT_NUM_VF_ENABLED 8 49 50 #define NIC_TNS_BYPASS_MODE 0 51 #define NIC_TNS_MODE 1 52 53 /* NIC priv flags */ 54 #define NIC_SRIOV_ENABLED (1 << 0) 55 #define NIC_TNS_ENABLED (1 << 1) 56 57 /* ARM64TODO */ 58 #if 0 59 /* VNIC HW optimiation features */ 60 #define VNIC_RSS_SUPPORT 61 #define VNIC_MULTI_QSET_SUPPORT 62 #endif 63 64 /* Min/Max packet size */ 65 #define NIC_HW_MIN_FRS 64 66 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 67 68 /* Max pkinds */ 69 #define NIC_MAX_PKIND 16 70 71 /* 72 * Rx Channels */ 73 /* Receive channel configuration in TNS bypass mode 74 * Below is configuration in TNS bypass mode 75 * BGX0-LMAC0-CHAN0 - VNIC CHAN0 76 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 77 * ... 78 * BGX1-LMAC0-CHAN0 - VNIC CHAN128 79 * ... 80 * BGX1-LMAC3-CHAN0 - VNIC CHAN174 81 */ 82 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 83 #define NIC_CHANS_PER_INF 128 84 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 85 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 86 87 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 88 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 89 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 90 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 91 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 92 93 /* Tx scheduling */ 94 #define NIC_MAX_TL4 1024 95 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 96 #define NIC_MAX_TL3 256 97 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 98 #define NIC_MAX_TL2 64 99 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 100 #define NIC_MAX_TL1 2 101 102 /* TNS bypass mode */ 103 #define NIC_TL2_PER_BGX 32 104 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 105 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 106 107 /* NIC VF Interrupts */ 108 #define NICVF_INTR_CQ 0 109 #define NICVF_INTR_SQ 1 110 #define NICVF_INTR_RBDR 2 111 #define NICVF_INTR_PKT_DROP 3 112 #define NICVF_INTR_TCP_TIMER 4 113 #define NICVF_INTR_MBOX 5 114 #define NICVF_INTR_QS_ERR 6 115 116 #define NICVF_INTR_CQ_SHIFT 0 117 #define NICVF_INTR_SQ_SHIFT 8 118 #define NICVF_INTR_RBDR_SHIFT 16 119 #define NICVF_INTR_PKT_DROP_SHIFT 20 120 #define NICVF_INTR_TCP_TIMER_SHIFT 21 121 #define NICVF_INTR_MBOX_SHIFT 22 122 #define NICVF_INTR_QS_ERR_SHIFT 23 123 124 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 125 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 126 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 127 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT) 128 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT) 129 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT) 130 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT) 131 132 /* MSI-X interrupts */ 133 #define NIC_PF_MSIX_VECTORS 10 134 #define NIC_VF_MSIX_VECTORS 20 135 136 #define NIC_PF_INTR_ID_ECC0_SBE 0 137 #define NIC_PF_INTR_ID_ECC0_DBE 1 138 #define NIC_PF_INTR_ID_ECC1_SBE 2 139 #define NIC_PF_INTR_ID_ECC1_DBE 3 140 #define NIC_PF_INTR_ID_ECC2_SBE 4 141 #define NIC_PF_INTR_ID_ECC2_DBE 5 142 #define NIC_PF_INTR_ID_ECC3_SBE 6 143 #define NIC_PF_INTR_ID_ECC3_DBE 7 144 #define NIC_PF_INTR_ID_MBOX0 8 145 #define NIC_PF_INTR_ID_MBOX1 9 146 147 struct msix_entry { 148 struct resource * irq_res; 149 void * handle; 150 }; 151 152 /* 153 * Global timer for CQ timer thresh interrupts 154 * Calculated for SCLK of 700Mhz 155 * value written should be a 1/16th of what is expected 156 * 157 * 1 tick per 0.05usec = value of 2.2 158 * This 10% would be covered in CQ timer thresh value 159 */ 160 #define NICPF_CLK_PER_INT_TICK 2 161 162 /* 163 * Time to wait before we decide that a SQ is stuck. 164 * 165 * Since both pkt rx and tx notifications are done with same CQ, 166 * when packets are being received at very high rate (eg: L2 forwarding) 167 * then freeing transmitted skbs will be delayed and watchdog 168 * will kick in, resetting interface. Hence keeping this value high. 169 */ 170 #define NICVF_TX_TIMEOUT (50 * HZ) 171 172 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 173 #define NIC_MAX_RSS_HASH_BITS 8 174 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 175 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 176 177 struct nicvf_rss_info { 178 boolean_t enable; 179 #define RSS_L2_EXTENDED_HASH_ENA (1UL << 0) 180 #define RSS_IP_HASH_ENA (1UL << 1) 181 #define RSS_TCP_HASH_ENA (1UL << 2) 182 #define RSS_TCP_SYN_DIS (1UL << 3) 183 #define RSS_UDP_HASH_ENA (1UL << 4) 184 #define RSS_L4_EXTENDED_HASH_ENA (1UL << 5) 185 #define RSS_ROCE_ENA (1UL << 6) 186 #define RSS_L3_BI_DIRECTION_ENA (1UL << 7) 187 #define RSS_L4_BI_DIRECTION_ENA (1UL << 8) 188 uint64_t cfg; 189 uint8_t hash_bits; 190 uint16_t rss_size; 191 uint8_t ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE]; 192 uint64_t key[RSS_HASH_KEY_SIZE]; 193 }; 194 195 enum rx_stats_reg_offset { 196 RX_OCTS = 0x0, 197 RX_UCAST = 0x1, 198 RX_BCAST = 0x2, 199 RX_MCAST = 0x3, 200 RX_RED = 0x4, 201 RX_RED_OCTS = 0x5, 202 RX_ORUN = 0x6, 203 RX_ORUN_OCTS = 0x7, 204 RX_FCS = 0x8, 205 RX_L2ERR = 0x9, 206 RX_DRP_BCAST = 0xa, 207 RX_DRP_MCAST = 0xb, 208 RX_DRP_L3BCAST = 0xc, 209 RX_DRP_L3MCAST = 0xd, 210 RX_STATS_ENUM_LAST, 211 }; 212 213 enum tx_stats_reg_offset { 214 TX_OCTS = 0x0, 215 TX_UCAST = 0x1, 216 TX_BCAST = 0x2, 217 TX_MCAST = 0x3, 218 TX_DROP = 0x4, 219 TX_STATS_ENUM_LAST, 220 }; 221 222 struct nicvf_hw_stats { 223 uint64_t rx_bytes; 224 uint64_t rx_ucast_frames; 225 uint64_t rx_bcast_frames; 226 uint64_t rx_mcast_frames; 227 uint64_t rx_fcs_errors; 228 uint64_t rx_l2_errors; 229 uint64_t rx_drop_red; 230 uint64_t rx_drop_red_bytes; 231 uint64_t rx_drop_overrun; 232 uint64_t rx_drop_overrun_bytes; 233 uint64_t rx_drop_bcast; 234 uint64_t rx_drop_mcast; 235 uint64_t rx_drop_l3_bcast; 236 uint64_t rx_drop_l3_mcast; 237 uint64_t rx_bgx_truncated_pkts; 238 uint64_t rx_jabber_errs; 239 uint64_t rx_fcs_errs; 240 uint64_t rx_bgx_errs; 241 uint64_t rx_prel2_errs; 242 uint64_t rx_l2_hdr_malformed; 243 uint64_t rx_oversize; 244 uint64_t rx_undersize; 245 uint64_t rx_l2_len_mismatch; 246 uint64_t rx_l2_pclp; 247 uint64_t rx_ip_ver_errs; 248 uint64_t rx_ip_csum_errs; 249 uint64_t rx_ip_hdr_malformed; 250 uint64_t rx_ip_payload_malformed; 251 uint64_t rx_ip_ttl_errs; 252 uint64_t rx_l3_pclp; 253 uint64_t rx_l4_malformed; 254 uint64_t rx_l4_csum_errs; 255 uint64_t rx_udp_len_errs; 256 uint64_t rx_l4_port_errs; 257 uint64_t rx_tcp_flag_errs; 258 uint64_t rx_tcp_offset_errs; 259 uint64_t rx_l4_pclp; 260 uint64_t rx_truncated_pkts; 261 262 uint64_t tx_bytes_ok; 263 uint64_t tx_ucast_frames_ok; 264 uint64_t tx_bcast_frames_ok; 265 uint64_t tx_mcast_frames_ok; 266 uint64_t tx_drops; 267 }; 268 269 struct nicvf_drv_stats { 270 /* Rx */ 271 uint64_t rx_frames_ok; 272 uint64_t rx_frames_64; 273 uint64_t rx_frames_127; 274 uint64_t rx_frames_255; 275 uint64_t rx_frames_511; 276 uint64_t rx_frames_1023; 277 uint64_t rx_frames_1518; 278 uint64_t rx_frames_jumbo; 279 uint64_t rx_drops; 280 281 /* Tx */ 282 uint64_t tx_frames_ok; 283 uint64_t tx_drops; 284 uint64_t tx_tso; 285 uint64_t txq_stop; 286 uint64_t txq_wake; 287 }; 288 289 struct nicvf { 290 struct nicvf *pnicvf; 291 device_t dev; 292 293 if_t ifp; 294 struct sx core_sx; 295 struct ifmedia if_media; 296 uint32_t if_flags; 297 298 uint8_t hwaddr[ETHER_ADDR_LEN]; 299 uint8_t vf_id; 300 uint8_t node; 301 boolean_t tns_mode:1; 302 boolean_t sqs_mode:1; 303 bool loopback_supported:1; 304 struct nicvf_rss_info rss_info; 305 uint16_t mtu; 306 struct queue_set *qs; 307 uint8_t rx_queues; 308 uint8_t tx_queues; 309 uint8_t max_queues; 310 struct resource *reg_base; 311 boolean_t link_up; 312 boolean_t hw_tso; 313 uint8_t duplex; 314 uint32_t speed; 315 uint8_t cpi_alg; 316 /* Interrupt coalescing settings */ 317 uint32_t cq_coalesce_usecs; 318 319 uint32_t msg_enable; 320 struct nicvf_hw_stats hw_stats; 321 struct nicvf_drv_stats drv_stats; 322 struct bgx_stats bgx_stats; 323 324 /* Interface statistics */ 325 struct callout stats_callout; 326 struct mtx stats_mtx; 327 328 /* MSI-X */ 329 boolean_t msix_enabled; 330 uint8_t num_vec; 331 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 332 struct resource * msix_table_res; 333 char irq_name[NIC_VF_MSIX_VECTORS][20]; 334 boolean_t irq_allocated[NIC_VF_MSIX_VECTORS]; 335 336 /* VF <-> PF mailbox communication */ 337 boolean_t pf_acked; 338 boolean_t pf_nacked; 339 } __aligned(CACHE_LINE_SIZE); 340 341 /* 342 * PF <--> VF Mailbox communication 343 * Eight 64bit registers are shared between PF and VF. 344 * Separate set for each VF. 345 * Writing '1' into last register mbx7 means end of message. 346 */ 347 348 /* PF <--> VF mailbox communication */ 349 #define NIC_PF_VF_MAILBOX_SIZE 2 350 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 351 352 /* Mailbox message types */ 353 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 354 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 355 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 356 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 357 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 358 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 359 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 360 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 361 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 362 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 363 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 364 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 365 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 366 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 367 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 368 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 369 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 370 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 371 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 372 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 373 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 374 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 375 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 376 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 377 378 struct nic_cfg_msg { 379 uint8_t msg; 380 uint8_t vf_id; 381 uint8_t node_id; 382 boolean_t tns_mode:1; 383 boolean_t sqs_mode:1; 384 boolean_t loopback_supported:1; 385 uint8_t mac_addr[ETHER_ADDR_LEN]; 386 }; 387 388 /* Qset configuration */ 389 struct qs_cfg_msg { 390 uint8_t msg; 391 uint8_t num; 392 uint8_t sqs_count; 393 uint64_t cfg; 394 }; 395 396 /* Receive queue configuration */ 397 struct rq_cfg_msg { 398 uint8_t msg; 399 uint8_t qs_num; 400 uint8_t rq_num; 401 uint64_t cfg; 402 }; 403 404 /* Send queue configuration */ 405 struct sq_cfg_msg { 406 uint8_t msg; 407 uint8_t qs_num; 408 uint8_t sq_num; 409 boolean_t sqs_mode; 410 uint64_t cfg; 411 }; 412 413 /* Set VF's MAC address */ 414 struct set_mac_msg { 415 uint8_t msg; 416 uint8_t vf_id; 417 uint8_t mac_addr[ETHER_ADDR_LEN]; 418 }; 419 420 /* Set Maximum frame size */ 421 struct set_frs_msg { 422 uint8_t msg; 423 uint8_t vf_id; 424 uint16_t max_frs; 425 }; 426 427 /* Set CPI algorithm type */ 428 struct cpi_cfg_msg { 429 uint8_t msg; 430 uint8_t vf_id; 431 uint8_t rq_cnt; 432 uint8_t cpi_alg; 433 }; 434 435 /* Get RSS table size */ 436 struct rss_sz_msg { 437 uint8_t msg; 438 uint8_t vf_id; 439 uint16_t ind_tbl_size; 440 }; 441 442 /* Set RSS configuration */ 443 struct rss_cfg_msg { 444 uint8_t msg; 445 uint8_t vf_id; 446 uint8_t hash_bits; 447 uint8_t tbl_len; 448 uint8_t tbl_offset; 449 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 450 uint8_t ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 451 }; 452 453 struct bgx_stats_msg { 454 uint8_t msg; 455 uint8_t vf_id; 456 uint8_t rx; 457 uint8_t idx; 458 uint64_t stats; 459 }; 460 461 /* Physical interface link status */ 462 struct bgx_link_status { 463 uint8_t msg; 464 uint8_t link_up; 465 uint8_t duplex; 466 uint32_t speed; 467 }; 468 469 /* Set interface in loopback mode */ 470 struct set_loopback { 471 uint8_t msg; 472 uint8_t vf_id; 473 boolean_t enable; 474 }; 475 476 /* 128 bit shared memory between PF and each VF */ 477 union nic_mbx { 478 struct { 479 uint8_t msg; 480 } msg; 481 struct nic_cfg_msg nic_cfg; 482 struct qs_cfg_msg qs; 483 struct rq_cfg_msg rq; 484 struct sq_cfg_msg sq; 485 struct set_mac_msg mac; 486 struct set_frs_msg frs; 487 struct cpi_cfg_msg cpi_cfg; 488 struct rss_sz_msg rss_size; 489 struct rss_cfg_msg rss_cfg; 490 struct bgx_stats_msg bgx_stats; 491 struct bgx_link_status link_status; 492 struct set_loopback lbk; 493 }; 494 495 #define NIC_NODE_ID_MASK 0x03 496 #define NIC_NODE_ID_SHIFT 44 497 498 static __inline int 499 nic_get_node_id(struct resource *res) 500 { 501 pci_addr_t addr; 502 503 addr = rman_get_start(res); 504 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 505 } 506 507 static __inline boolean_t 508 pass1_silicon(device_t dev) 509 { 510 511 /* Check if the chip revision is < Pass2 */ 512 return (pci_get_revid(dev) < PCI_REVID_PASS2); 513 } 514 515 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 516 517 #endif /* NIC_H */ 518