1 /* 2 * Copyright (C) 2015 Cavium Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef NIC_H 31 #define NIC_H 32 33 /* PCI vendor ID */ 34 #define PCI_VENDOR_ID_CAVIUM 0x177D 35 /* PCI device IDs */ 36 #define PCI_DEVICE_ID_THUNDER_NIC_PF 0xA01E 37 #define PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF 0x0011 38 #define PCI_DEVICE_ID_THUNDER_NIC_VF 0xA034 39 #define PCI_DEVICE_ID_THUNDER_BGX 0xA026 40 41 /* PCI BAR nos */ 42 #define PCI_CFG_REG_BAR_NUM 0 43 #define PCI_MSIX_REG_BAR_NUM 4 44 45 /* PCI revision IDs */ 46 #define PCI_REVID_PASS2 8 47 48 /* NIC SRIOV VF count */ 49 #define MAX_NUM_VFS_SUPPORTED 128 50 #define DEFAULT_NUM_VF_ENABLED 8 51 52 #define NIC_TNS_BYPASS_MODE 0 53 #define NIC_TNS_MODE 1 54 55 /* NIC priv flags */ 56 #define NIC_SRIOV_ENABLED (1 << 0) 57 #define NIC_TNS_ENABLED (1 << 1) 58 59 /* ARM64TODO */ 60 #if 0 61 /* VNIC HW optimiation features */ 62 #define VNIC_RSS_SUPPORT 63 #define VNIC_MULTI_QSET_SUPPORT 64 #endif 65 66 /* Min/Max packet size */ 67 #define NIC_HW_MIN_FRS 64 68 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */ 69 70 /* Max pkinds */ 71 #define NIC_MAX_PKIND 16 72 73 /* 74 * Rx Channels */ 75 /* Receive channel configuration in TNS bypass mode 76 * Below is configuration in TNS bypass mode 77 * BGX0-LMAC0-CHAN0 - VNIC CHAN0 78 * BGX0-LMAC1-CHAN0 - VNIC CHAN16 79 * ... 80 * BGX1-LMAC0-CHAN0 - VNIC CHAN128 81 * ... 82 * BGX1-LMAC3-CHAN0 - VNIC CHAN174 83 */ 84 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */ 85 #define NIC_CHANS_PER_INF 128 86 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF) 87 #define NIC_CPI_COUNT 2048 /* No of channel parse indices */ 88 89 /* TNS bypass mode: 1-1 mapping between VNIC and BGX:LMAC */ 90 #define NIC_MAX_BGX MAX_BGX_PER_CN88XX 91 #define NIC_CPI_PER_BGX (NIC_CPI_COUNT / NIC_MAX_BGX) 92 #define NIC_MAX_CPI_PER_LMAC 64 /* Max when CPI_ALG is IP diffserv */ 93 #define NIC_RSSI_PER_BGX (NIC_RSSI_COUNT / NIC_MAX_BGX) 94 95 /* Tx scheduling */ 96 #define NIC_MAX_TL4 1024 97 #define NIC_MAX_TL4_SHAPERS 256 /* 1 shaper for 4 TL4s */ 98 #define NIC_MAX_TL3 256 99 #define NIC_MAX_TL3_SHAPERS 64 /* 1 shaper for 4 TL3s */ 100 #define NIC_MAX_TL2 64 101 #define NIC_MAX_TL2_SHAPERS 2 /* 1 shaper for 32 TL2s */ 102 #define NIC_MAX_TL1 2 103 104 /* TNS bypass mode */ 105 #define NIC_TL2_PER_BGX 32 106 #define NIC_TL4_PER_BGX (NIC_MAX_TL4 / NIC_MAX_BGX) 107 #define NIC_TL4_PER_LMAC (NIC_MAX_TL4 / NIC_CHANS_PER_INF) 108 109 /* NIC VF Interrupts */ 110 #define NICVF_INTR_CQ 0 111 #define NICVF_INTR_SQ 1 112 #define NICVF_INTR_RBDR 2 113 #define NICVF_INTR_PKT_DROP 3 114 #define NICVF_INTR_TCP_TIMER 4 115 #define NICVF_INTR_MBOX 5 116 #define NICVF_INTR_QS_ERR 6 117 118 #define NICVF_INTR_CQ_SHIFT 0 119 #define NICVF_INTR_SQ_SHIFT 8 120 #define NICVF_INTR_RBDR_SHIFT 16 121 #define NICVF_INTR_PKT_DROP_SHIFT 20 122 #define NICVF_INTR_TCP_TIMER_SHIFT 21 123 #define NICVF_INTR_MBOX_SHIFT 22 124 #define NICVF_INTR_QS_ERR_SHIFT 23 125 126 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT) 127 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT) 128 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT) 129 #define NICVF_INTR_PKT_DROP_MASK (1 << NICVF_INTR_PKT_DROP_SHIFT) 130 #define NICVF_INTR_TCP_TIMER_MASK (1 << NICVF_INTR_TCP_TIMER_SHIFT) 131 #define NICVF_INTR_MBOX_MASK (1 << NICVF_INTR_MBOX_SHIFT) 132 #define NICVF_INTR_QS_ERR_MASK (1 << NICVF_INTR_QS_ERR_SHIFT) 133 134 /* MSI-X interrupts */ 135 #define NIC_PF_MSIX_VECTORS 10 136 #define NIC_VF_MSIX_VECTORS 20 137 138 #define NIC_PF_INTR_ID_ECC0_SBE 0 139 #define NIC_PF_INTR_ID_ECC0_DBE 1 140 #define NIC_PF_INTR_ID_ECC1_SBE 2 141 #define NIC_PF_INTR_ID_ECC1_DBE 3 142 #define NIC_PF_INTR_ID_ECC2_SBE 4 143 #define NIC_PF_INTR_ID_ECC2_DBE 5 144 #define NIC_PF_INTR_ID_ECC3_SBE 6 145 #define NIC_PF_INTR_ID_ECC3_DBE 7 146 #define NIC_PF_INTR_ID_MBOX0 8 147 #define NIC_PF_INTR_ID_MBOX1 9 148 149 struct msix_entry { 150 struct resource * irq_res; 151 void * handle; 152 }; 153 154 /* 155 * Global timer for CQ timer thresh interrupts 156 * Calculated for SCLK of 700Mhz 157 * value written should be a 1/16th of what is expected 158 * 159 * 1 tick per 0.05usec = value of 2.2 160 * This 10% would be covered in CQ timer thresh value 161 */ 162 #define NICPF_CLK_PER_INT_TICK 2 163 164 /* 165 * Time to wait before we decide that a SQ is stuck. 166 * 167 * Since both pkt rx and tx notifications are done with same CQ, 168 * when packets are being received at very high rate (eg: L2 forwarding) 169 * then freeing transmitted skbs will be delayed and watchdog 170 * will kick in, resetting interface. Hence keeping this value high. 171 */ 172 #define NICVF_TX_TIMEOUT (50 * HZ) 173 174 #define NIC_RSSI_COUNT 4096 /* Total no of RSS indices */ 175 #define NIC_MAX_RSS_HASH_BITS 8 176 #define NIC_MAX_RSS_IDR_TBL_SIZE (1 << NIC_MAX_RSS_HASH_BITS) 177 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */ 178 179 enum rx_stats_reg_offset { 180 RX_OCTS = 0x0, 181 RX_UCAST = 0x1, 182 RX_BCAST = 0x2, 183 RX_MCAST = 0x3, 184 RX_RED = 0x4, 185 RX_RED_OCTS = 0x5, 186 RX_ORUN = 0x6, 187 RX_ORUN_OCTS = 0x7, 188 RX_FCS = 0x8, 189 RX_L2ERR = 0x9, 190 RX_DRP_BCAST = 0xa, 191 RX_DRP_MCAST = 0xb, 192 RX_DRP_L3BCAST = 0xc, 193 RX_DRP_L3MCAST = 0xd, 194 RX_STATS_ENUM_LAST, 195 }; 196 197 enum tx_stats_reg_offset { 198 TX_OCTS = 0x0, 199 TX_UCAST = 0x1, 200 TX_BCAST = 0x2, 201 TX_MCAST = 0x3, 202 TX_DROP = 0x4, 203 TX_STATS_ENUM_LAST, 204 }; 205 206 struct nicvf_hw_stats { 207 uint64_t rx_bytes; 208 uint64_t rx_ucast_frames; 209 uint64_t rx_bcast_frames; 210 uint64_t rx_mcast_frames; 211 uint64_t rx_fcs_errors; 212 uint64_t rx_l2_errors; 213 uint64_t rx_drop_red; 214 uint64_t rx_drop_red_bytes; 215 uint64_t rx_drop_overrun; 216 uint64_t rx_drop_overrun_bytes; 217 uint64_t rx_drop_bcast; 218 uint64_t rx_drop_mcast; 219 uint64_t rx_drop_l3_bcast; 220 uint64_t rx_drop_l3_mcast; 221 uint64_t rx_bgx_truncated_pkts; 222 uint64_t rx_jabber_errs; 223 uint64_t rx_fcs_errs; 224 uint64_t rx_bgx_errs; 225 uint64_t rx_prel2_errs; 226 uint64_t rx_l2_hdr_malformed; 227 uint64_t rx_oversize; 228 uint64_t rx_undersize; 229 uint64_t rx_l2_len_mismatch; 230 uint64_t rx_l2_pclp; 231 uint64_t rx_ip_ver_errs; 232 uint64_t rx_ip_csum_errs; 233 uint64_t rx_ip_hdr_malformed; 234 uint64_t rx_ip_payload_malformed; 235 uint64_t rx_ip_ttl_errs; 236 uint64_t rx_l3_pclp; 237 uint64_t rx_l4_malformed; 238 uint64_t rx_l4_csum_errs; 239 uint64_t rx_udp_len_errs; 240 uint64_t rx_l4_port_errs; 241 uint64_t rx_tcp_flag_errs; 242 uint64_t rx_tcp_offset_errs; 243 uint64_t rx_l4_pclp; 244 uint64_t rx_truncated_pkts; 245 246 uint64_t tx_bytes_ok; 247 uint64_t tx_ucast_frames_ok; 248 uint64_t tx_bcast_frames_ok; 249 uint64_t tx_mcast_frames_ok; 250 uint64_t tx_drops; 251 }; 252 253 struct nicvf_drv_stats { 254 /* Rx */ 255 uint64_t rx_frames_ok; 256 uint64_t rx_frames_64; 257 uint64_t rx_frames_127; 258 uint64_t rx_frames_255; 259 uint64_t rx_frames_511; 260 uint64_t rx_frames_1023; 261 uint64_t rx_frames_1518; 262 uint64_t rx_frames_jumbo; 263 uint64_t rx_drops; 264 265 /* Tx */ 266 uint64_t tx_frames_ok; 267 uint64_t tx_drops; 268 uint64_t tx_tso; 269 uint64_t txq_stop; 270 uint64_t txq_wake; 271 }; 272 273 struct nicvf { 274 struct nicvf *pnicvf; 275 device_t dev; 276 277 struct ifnet * ifp; 278 struct sx core_sx; 279 struct ifmedia if_media; 280 uint32_t if_flags; 281 282 uint8_t hwaddr[ETHER_ADDR_LEN]; 283 uint8_t vf_id; 284 uint8_t node; 285 boolean_t tns_mode:1; 286 boolean_t sqs_mode:1; 287 bool loopback_supported:1; 288 uint16_t mtu; 289 struct queue_set *qs; 290 uint8_t rx_queues; 291 uint8_t tx_queues; 292 uint8_t max_queues; 293 struct resource *reg_base; 294 boolean_t link_up; 295 boolean_t hw_tso; 296 uint8_t duplex; 297 uint32_t speed; 298 uint8_t cpi_alg; 299 /* Interrupt coalescing settings */ 300 uint32_t cq_coalesce_usecs; 301 302 uint32_t msg_enable; 303 struct nicvf_hw_stats hw_stats; 304 struct nicvf_drv_stats drv_stats; 305 struct bgx_stats bgx_stats; 306 307 /* Interface statistics */ 308 struct callout stats_callout; 309 struct mtx stats_mtx; 310 311 /* MSI-X */ 312 boolean_t msix_enabled; 313 uint8_t num_vec; 314 struct msix_entry msix_entries[NIC_VF_MSIX_VECTORS]; 315 struct resource * msix_table_res; 316 char irq_name[NIC_VF_MSIX_VECTORS][20]; 317 boolean_t irq_allocated[NIC_VF_MSIX_VECTORS]; 318 319 /* VF <-> PF mailbox communication */ 320 boolean_t pf_acked; 321 boolean_t pf_nacked; 322 } __aligned(CACHE_LINE_SIZE); 323 324 /* 325 * PF <--> VF Mailbox communication 326 * Eight 64bit registers are shared between PF and VF. 327 * Separate set for each VF. 328 * Writing '1' into last register mbx7 means end of message. 329 */ 330 331 /* PF <--> VF mailbox communication */ 332 #define NIC_PF_VF_MAILBOX_SIZE 2 333 #define NIC_MBOX_MSG_TIMEOUT 2000 /* ms */ 334 335 /* Mailbox message types */ 336 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */ 337 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */ 338 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */ 339 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */ 340 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */ 341 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */ 342 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */ 343 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */ 344 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */ 345 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */ 346 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */ 347 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */ 348 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */ 349 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */ 350 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */ 351 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */ 352 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */ 353 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */ 354 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */ 355 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */ 356 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */ 357 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */ 358 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */ 359 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */ 360 361 struct nic_cfg_msg { 362 uint8_t msg; 363 uint8_t vf_id; 364 uint8_t node_id; 365 boolean_t tns_mode:1; 366 boolean_t sqs_mode:1; 367 boolean_t loopback_supported:1; 368 uint8_t mac_addr[ETHER_ADDR_LEN]; 369 }; 370 371 /* Qset configuration */ 372 struct qs_cfg_msg { 373 uint8_t msg; 374 uint8_t num; 375 uint8_t sqs_count; 376 uint64_t cfg; 377 }; 378 379 /* Receive queue configuration */ 380 struct rq_cfg_msg { 381 uint8_t msg; 382 uint8_t qs_num; 383 uint8_t rq_num; 384 uint64_t cfg; 385 }; 386 387 /* Send queue configuration */ 388 struct sq_cfg_msg { 389 uint8_t msg; 390 uint8_t qs_num; 391 uint8_t sq_num; 392 boolean_t sqs_mode; 393 uint64_t cfg; 394 }; 395 396 /* Set VF's MAC address */ 397 struct set_mac_msg { 398 uint8_t msg; 399 uint8_t vf_id; 400 uint8_t mac_addr[ETHER_ADDR_LEN]; 401 }; 402 403 /* Set Maximum frame size */ 404 struct set_frs_msg { 405 uint8_t msg; 406 uint8_t vf_id; 407 uint16_t max_frs; 408 }; 409 410 /* Set CPI algorithm type */ 411 struct cpi_cfg_msg { 412 uint8_t msg; 413 uint8_t vf_id; 414 uint8_t rq_cnt; 415 uint8_t cpi_alg; 416 }; 417 418 /* Get RSS table size */ 419 struct rss_sz_msg { 420 uint8_t msg; 421 uint8_t vf_id; 422 uint16_t ind_tbl_size; 423 }; 424 425 /* Set RSS configuration */ 426 struct rss_cfg_msg { 427 uint8_t msg; 428 uint8_t vf_id; 429 uint8_t hash_bits; 430 uint8_t tbl_len; 431 uint8_t tbl_offset; 432 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8 433 uint8_t ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG]; 434 }; 435 436 struct bgx_stats_msg { 437 uint8_t msg; 438 uint8_t vf_id; 439 uint8_t rx; 440 uint8_t idx; 441 uint64_t stats; 442 }; 443 444 /* Physical interface link status */ 445 struct bgx_link_status { 446 uint8_t msg; 447 uint8_t link_up; 448 uint8_t duplex; 449 uint32_t speed; 450 }; 451 452 /* Set interface in loopback mode */ 453 struct set_loopback { 454 uint8_t msg; 455 uint8_t vf_id; 456 boolean_t enable; 457 }; 458 459 /* 128 bit shared memory between PF and each VF */ 460 union nic_mbx { 461 struct { 462 uint8_t msg; 463 } msg; 464 struct nic_cfg_msg nic_cfg; 465 struct qs_cfg_msg qs; 466 struct rq_cfg_msg rq; 467 struct sq_cfg_msg sq; 468 struct set_mac_msg mac; 469 struct set_frs_msg frs; 470 struct cpi_cfg_msg cpi_cfg; 471 struct rss_sz_msg rss_size; 472 struct rss_cfg_msg rss_cfg; 473 struct bgx_stats_msg bgx_stats; 474 struct bgx_link_status link_status; 475 struct set_loopback lbk; 476 }; 477 478 #define NIC_NODE_ID_MASK 0x03 479 #define NIC_NODE_ID_SHIFT 44 480 481 static __inline int 482 nic_get_node_id(struct resource *res) 483 { 484 pci_addr_t addr; 485 486 addr = rman_get_start(res); 487 return ((addr >> NIC_NODE_ID_SHIFT) & NIC_NODE_ID_MASK); 488 } 489 490 static __inline boolean_t 491 pass1_silicon(device_t dev) 492 { 493 494 /* Check if the chip revision is < Pass2 */ 495 return (pci_get_revid(dev) < PCI_REVID_PASS2); 496 } 497 498 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx); 499 500 #endif /* NIC_H */ 501