1 /*- 2 * Copyright (c) 2013 Tsubai Masanari 3 * Copyright (c) 2013 Bryan Venteicher <bryanv@FreeBSD.org> 4 * Copyright (c) 2018 Patrick Kelsey 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _IF_VMXVAR_H 20 #define _IF_VMXVAR_H 21 22 struct vmxnet3_softc; 23 24 /* 25 * The number of Rx/Tx queues this driver prefers. 26 */ 27 #define VMXNET3_DEF_RX_QUEUES 8 28 #define VMXNET3_DEF_TX_QUEUES 8 29 30 /* 31 * The number of Rx rings in each Rx queue. 32 */ 33 #define VMXNET3_RXRINGS_PERQ 2 34 35 /* 36 * The number of descriptors in each Rx/Tx ring. 37 */ 38 #define VMXNET3_DEF_TX_NDESC 512 39 #define VMXNET3_MAX_TX_NDESC 4096 40 #define VMXNET3_MIN_TX_NDESC 32 41 #define VMXNET3_MASK_TX_NDESC 0x1F 42 #define VMXNET3_DEF_RX_NDESC 512 43 #define VMXNET3_MAX_RX_NDESC 2048 44 #define VMXNET3_MIN_RX_NDESC 32 45 #define VMXNET3_MASK_RX_NDESC 0x1F 46 47 #define VMXNET3_MAX_TX_NCOMPDESC VMXNET3_MAX_TX_NDESC 48 #define VMXNET3_MAX_RX_NCOMPDESC \ 49 (VMXNET3_MAX_RX_NDESC * VMXNET3_RXRINGS_PERQ) 50 51 struct vmxnet3_txring { 52 u_int vxtxr_next; 53 u_int vxtxr_ndesc; 54 int vxtxr_gen; 55 struct vmxnet3_txdesc *vxtxr_txd; 56 bus_addr_t vxtxr_paddr; 57 }; 58 59 struct vmxnet3_rxring { 60 struct vmxnet3_rxdesc *vxrxr_rxd; 61 u_int vxrxr_ndesc; 62 int vxrxr_gen; 63 bus_addr_t vxrxr_paddr; 64 uint64_t vxrxr_desc_skips; 65 uint16_t vxrxr_refill_start; 66 }; 67 68 struct vmxnet3_comp_ring { 69 union { 70 struct vmxnet3_txcompdesc *txcd; 71 struct vmxnet3_rxcompdesc *rxcd; 72 } vxcr_u; 73 /* 74 * vxcr_next is used on the transmit side to track the next index to 75 * begin cleaning at. It is not used on the receive side. 76 */ 77 u_int vxcr_next; 78 u_int vxcr_ndesc; 79 int vxcr_gen; 80 bus_addr_t vxcr_paddr; 81 uint64_t vxcr_zero_length; 82 uint64_t vcxr_zero_length_frag; 83 uint64_t vxcr_pkt_errors; 84 }; 85 86 struct vmxnet3_txqueue { 87 struct vmxnet3_softc *vxtxq_sc; 88 int vxtxq_id; 89 int vxtxq_last_flush; 90 int vxtxq_intr_idx; 91 struct vmxnet3_txring vxtxq_cmd_ring; 92 struct vmxnet3_comp_ring vxtxq_comp_ring; 93 struct vmxnet3_txq_shared *vxtxq_ts; 94 struct sysctl_oid_list *vxtxq_sysctl; 95 char vxtxq_name[16]; 96 } __aligned(CACHE_LINE_SIZE); 97 98 struct vmxnet3_rxqueue { 99 struct vmxnet3_softc *vxrxq_sc; 100 int vxrxq_id; 101 int vxrxq_intr_idx; 102 struct if_irq vxrxq_irq; 103 struct vmxnet3_rxring vxrxq_cmd_ring[VMXNET3_RXRINGS_PERQ]; 104 struct vmxnet3_comp_ring vxrxq_comp_ring; 105 struct vmxnet3_rxq_shared *vxrxq_rs; 106 struct sysctl_oid_list *vxrxq_sysctl; 107 char vxrxq_name[16]; 108 } __aligned(CACHE_LINE_SIZE); 109 110 struct vmxnet3_softc { 111 device_t vmx_dev; 112 if_ctx_t vmx_ctx; 113 if_shared_ctx_t vmx_sctx; 114 if_softc_ctx_t vmx_scctx; 115 if_t vmx_ifp; 116 struct vmxnet3_driver_shared *vmx_ds; 117 uint32_t vmx_flags; 118 #define VMXNET3_FLAG_RSS 0x0002 119 #define VMXNET3_FLAG_SOFT_RSS 0x0004 /* Software RSS is enabled with 120 compatible algorithm. */ 121 122 struct vmxnet3_rxqueue *vmx_rxq; 123 struct vmxnet3_txqueue *vmx_txq; 124 125 struct resource *vmx_res0; 126 bus_space_tag_t vmx_iot0; 127 bus_space_handle_t vmx_ioh0; 128 struct resource *vmx_res1; 129 bus_space_tag_t vmx_iot1; 130 bus_space_handle_t vmx_ioh1; 131 132 int vmx_link_active; 133 134 int vmx_intr_mask_mode; 135 int vmx_event_intr_idx; 136 struct if_irq vmx_event_intr_irq; 137 138 uint8_t *vmx_mcast; 139 struct vmxnet3_rss_shared *vmx_rss; 140 struct iflib_dma_info vmx_ds_dma; 141 struct iflib_dma_info vmx_qs_dma; 142 struct iflib_dma_info vmx_mcast_dma; 143 struct iflib_dma_info vmx_rss_dma; 144 struct ifmedia *vmx_media; 145 uint32_t vmx_vlan_filter[4096/32]; 146 uint8_t vmx_lladdr[ETHER_ADDR_LEN]; 147 }; 148 149 /* 150 * Our driver version we report to the hypervisor; we just keep 151 * this value constant. 152 */ 153 #define VMXNET3_DRIVER_VERSION 0x00010000 154 155 /* 156 * Max descriptors per Tx packet. We must limit the size of the 157 * any TSO packets based on the number of segments. 158 */ 159 #define VMXNET3_TX_MAXSEGS 32 /* 64K @ 2K segment size */ 160 #define VMXNET3_TX_MAXSIZE (VMXNET3_TX_MAXSEGS * MCLBYTES) 161 #define VMXNET3_TSO_MAXSIZE (VMXNET3_TX_MAXSIZE - ETHER_VLAN_ENCAP_LEN) 162 163 /* 164 * Maximum supported Tx segment size. The length field in the 165 * Tx descriptor is 14 bits. 166 * 167 * XXX It's possible a descriptor length field of 0 means 2^14, but this 168 * isn't confirmed, so limit to 2^14 - 1 for now. 169 */ 170 #define VMXNET3_TX_MAXSEGSIZE ((1 << 14) - 1) 171 172 /* 173 * Maximum supported Rx segment size. The length field in the 174 * Rx descriptor is 14 bits. 175 * 176 * The reference drivers skip zero-length descriptors, which seems to be a 177 * strong indication that on the receive side, a descriptor length field of 178 * zero does not mean 2^14. 179 */ 180 #define VMXNET3_RX_MAXSEGSIZE ((1 << 14) - 1) 181 182 /* 183 * Predetermined size of the multicast MACs filter table. If the 184 * number of multicast addresses exceeds this size, then the 185 * ALL_MULTI mode is use instead. 186 */ 187 #define VMXNET3_MULTICAST_MAX 32 188 189 /* 190 * IP protocols that we can perform Tx checksum offloading of. 191 */ 192 #define VMXNET3_CSUM_OFFLOAD (CSUM_TCP | CSUM_UDP) 193 #define VMXNET3_CSUM_OFFLOAD_IPV6 (CSUM_TCP_IPV6 | CSUM_UDP_IPV6) 194 195 #define VMXNET3_CSUM_ALL_OFFLOAD \ 196 (VMXNET3_CSUM_OFFLOAD | VMXNET3_CSUM_OFFLOAD_IPV6 | CSUM_TSO) 197 198 #endif /* _IF_VMXVAR_H */ 199