xref: /freebsd/sys/dev/vmware/vmxnet3/if_vmxreg.h (revision 5dd76dd0cc19450133aa379ce0ce4a68ae07fb39)
1 /*-
2  * Copyright (c) 2013 Tsubai Masanari
3  *
4  * Permission to use, copy, modify, and distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  *
16  * $OpenBSD: src/sys/dev/pci/if_vmxreg.h,v 1.2 2013/06/12 01:07:33 uebayasi Exp $
17  *
18  * $FreeBSD$
19  */
20 
21 #ifndef _IF_VMXREG_H
22 #define _IF_VMXREG_H
23 
24 struct UPT1_TxStats {
25 	uint64_t	TSO_packets;
26 	uint64_t	TSO_bytes;
27 	uint64_t	ucast_packets;
28 	uint64_t	ucast_bytes;
29 	uint64_t	mcast_packets;
30 	uint64_t	mcast_bytes;
31 	uint64_t	bcast_packets;
32 	uint64_t	bcast_bytes;
33 	uint64_t	error;
34 	uint64_t	discard;
35 } __packed;
36 
37 struct UPT1_RxStats {
38 	uint64_t	LRO_packets;
39 	uint64_t	LRO_bytes;
40 	uint64_t	ucast_packets;
41 	uint64_t	ucast_bytes;
42 	uint64_t	mcast_packets;
43 	uint64_t	mcast_bytes;
44 	uint64_t	bcast_packets;
45 	uint64_t	bcast_bytes;
46 	uint64_t	nobuffer;
47 	uint64_t	error;
48 } __packed;
49 
50 /* Interrupt moderation levels */
51 #define UPT1_IMOD_NONE		0	/* No moderation */
52 #define UPT1_IMOD_HIGHEST	7	/* Least interrupts */
53 #define UPT1_IMOD_ADAPTIVE	8	/* Adaptive interrupt moderation */
54 
55 /* Hardware features */
56 #define UPT1_F_CSUM	0x0001		/* Rx checksum verification */
57 #define UPT1_F_RSS	0x0002		/* Receive side scaling */
58 #define UPT1_F_VLAN	0x0004		/* VLAN tag stripping */
59 #define UPT1_F_LRO	0x0008		/* Large receive offloading */
60 
61 #define VMXNET3_BAR0_IMASK(irq)	(0x000 + (irq) * 8)	/* Interrupt mask */
62 #define VMXNET3_BAR0_TXH(q)	(0x600 + (q) * 8)	/* Tx head */
63 #define VMXNET3_BAR0_RXH1(q)	(0x800 + (q) * 8)	/* Ring1 Rx head */
64 #define VMXNET3_BAR0_RXH2(q)	(0xA00 + (q) * 8)	/* Ring2 Rx head */
65 #define VMXNET3_BAR1_VRRS	0x000	/* VMXNET3 revision report selection */
66 #define VMXNET3_BAR1_UVRS	0x008	/* UPT version report selection */
67 #define VMXNET3_BAR1_DSL	0x010	/* Driver shared address low */
68 #define VMXNET3_BAR1_DSH	0x018	/* Driver shared address high */
69 #define VMXNET3_BAR1_CMD	0x020	/* Command */
70 #define VMXNET3_BAR1_MACL	0x028	/* MAC address low */
71 #define VMXNET3_BAR1_MACH	0x030	/* MAC address high */
72 #define VMXNET3_BAR1_INTR	0x038	/* Interrupt status */
73 #define VMXNET3_BAR1_EVENT	0x040	/* Event status */
74 
75 #define VMXNET3_CMD_ENABLE	0xCAFE0000	/* Enable VMXNET3 */
76 #define VMXNET3_CMD_DISABLE	0xCAFE0001	/* Disable VMXNET3 */
77 #define VMXNET3_CMD_RESET	0xCAFE0002	/* Reset device */
78 #define VMXNET3_CMD_SET_RXMODE	0xCAFE0003	/* Set interface flags */
79 #define VMXNET3_CMD_SET_FILTER	0xCAFE0004	/* Set address filter */
80 #define VMXNET3_CMD_VLAN_FILTER	0xCAFE0005	/* Set VLAN filter */
81 #define VMXNET3_CMD_GET_STATUS	0xF00D0000	/* Get queue errors */
82 #define VMXNET3_CMD_GET_STATS	0xF00D0001	/* Get queue statistics */
83 #define VMXNET3_CMD_GET_LINK	0xF00D0002	/* Get link status */
84 #define VMXNET3_CMD_GET_MACL	0xF00D0003	/* Get MAC address low */
85 #define VMXNET3_CMD_GET_MACH	0xF00D0004	/* Get MAC address high */
86 #define VMXNET3_CMD_GET_INTRCFG	0xF00D0008	/* Get interrupt config */
87 
88 #define VMXNET3_DMADESC_ALIGN	128
89 #define VMXNET3_INIT_GEN	1
90 
91 struct vmxnet3_txdesc {
92 	uint64_t	addr;
93 
94 	uint32_t	len:14;
95 	uint32_t	gen:1;		/* Generation */
96 	uint32_t	pad1:1;
97 	uint32_t	dtype:1;	/* Descriptor type */
98 	uint32_t	pad2:1;
99 	uint32_t	offload_pos:14;	/* Offloading position */
100 
101 	uint32_t	hlen:10;	/* Header len */
102 	uint32_t	offload_mode:2;	/* Offloading mode */
103 	uint32_t	eop:1;		/* End of packet */
104 	uint32_t	compreq:1;	/* Completion request */
105 	uint32_t	pad3:1;
106 	uint32_t	vtag_mode:1;	/* VLAN tag insertion mode */
107 	uint32_t	vtag:16;	/* VLAN tag */
108 } __packed;
109 
110 /* Offloading modes */
111 #define VMXNET3_OM_NONE	0
112 #define VMXNET3_OM_CSUM 2
113 #define VMXNET3_OM_TSO  3
114 
115 struct vmxnet3_txcompdesc {
116 	uint32_t	eop_idx:12;	/* EOP index in Tx ring */
117 	uint32_t	pad1:20;
118 
119 	uint32_t	pad2:32;
120 	uint32_t	pad3:32;
121 
122 	uint32_t	rsvd:24;
123 	uint32_t	type:7;
124 	uint32_t	gen:1;
125 } __packed;
126 
127 struct vmxnet3_rxdesc {
128 	uint64_t	addr;
129 
130 	uint32_t	len:14;
131 	uint32_t	btype:1;	/* Buffer type */
132 	uint32_t	dtype:1;	/* Descriptor type */
133 	uint32_t	rsvd:15;
134 	uint32_t	gen:1;
135 
136 	uint32_t	pad1:32;
137 } __packed;
138 
139 /* Buffer types */
140 #define VMXNET3_BTYPE_HEAD	0	/* Head only */
141 #define VMXNET3_BTYPE_BODY	1	/* Body only */
142 
143 struct vmxnet3_rxcompdesc {
144 	uint32_t	rxd_idx:12;	/* Rx descriptor index */
145 	uint32_t	pad1:2;
146 	uint32_t	eop:1;		/* End of packet */
147 	uint32_t	sop:1;		/* Start of packet */
148 	uint32_t	qid:10;
149 	uint32_t	rss_type:4;
150 	uint32_t	no_csum:1;	/* No checksum calculated */
151 	uint32_t	pad2:1;
152 
153 	uint32_t	rss_hash:32;	/* RSS hash value */
154 
155 	uint32_t	len:14;
156 	uint32_t	error:1;
157 	uint32_t	vlan:1;		/* 802.1Q VLAN frame */
158 	uint32_t	vtag:16;	/* VLAN tag */
159 
160 	uint32_t	csum:16;
161 	uint32_t	csum_ok:1;	/* TCP/UDP checksum ok */
162 	uint32_t	udp:1;
163 	uint32_t	tcp:1;
164 	uint32_t	ipcsum_ok:1;	/* IP checksum OK */
165 	uint32_t	ipv6:1;
166 	uint32_t	ipv4:1;
167 	uint32_t	fragment:1;	/* IP fragment */
168 	uint32_t	fcs:1;		/* Frame CRC correct */
169 	uint32_t	type:7;
170 	uint32_t	gen:1;
171 } __packed;
172 
173 #define VMXNET3_REV1_MAGIC	0XBABEFEE1
174 
175 #define VMXNET3_GOS_UNKNOWN	0x00
176 #define VMXNET3_GOS_LINUX	0x04
177 #define VMXNET3_GOS_WINDOWS	0x08
178 #define VMXNET3_GOS_SOLARIS	0x0C
179 #define VMXNET3_GOS_FREEBSD	0x10
180 #define VMXNET3_GOS_PXE		0x14
181 
182 #define VMXNET3_GOS_32BIT	0x01
183 #define VMXNET3_GOS_64BIT	0x02
184 
185 #define VMXNET3_MAX_TX_QUEUES	8
186 #define VMXNET3_MAX_RX_QUEUES	16
187 #define VMXNET3_MAX_INTRS \
188     (VMXNET3_MAX_TX_QUEUES + VMXNET3_MAX_RX_QUEUES + 1)
189 
190 #define VMXNET3_ICTRL_DISABLE_ALL	0x01
191 
192 #define VMXNET3_RXMODE_UCAST	0x01
193 #define VMXNET3_RXMODE_MCAST	0x02
194 #define VMXNET3_RXMODE_BCAST	0x04
195 #define VMXNET3_RXMODE_ALLMULTI	0x08
196 #define VMXNET3_RXMODE_PROMISC	0x10
197 
198 #define VMXNET3_EVENT_RQERROR	0x01
199 #define VMXNET3_EVENT_TQERROR	0x02
200 #define VMXNET3_EVENT_LINK	0x04
201 #define VMXNET3_EVENT_DIC	0x08
202 #define VMXNET3_EVENT_DEBUG	0x10
203 
204 #define VMXNET3_MIN_MTU		60
205 #define VMXNET3_MAX_MTU		9000
206 
207 /* Interrupt mask mode. */
208 #define VMXNET3_IMM_AUTO	0x00
209 #define VMXNET3_IMM_ACTIVE	0x01
210 #define VMXNET3_IMM_LAZY	0x02
211 
212 /* Interrupt type. */
213 #define VMXNET3_IT_AUTO		0x00
214 #define VMXNET3_IT_LEGACY	0x01
215 #define VMXNET3_IT_MSI		0x02
216 #define VMXNET3_IT_MSIX		0x03
217 
218 struct vmxnet3_driver_shared {
219 	uint32_t	magic;
220 	uint32_t	pad1;
221 
222 	/* Misc. control */
223 	uint32_t	version;		/* Driver version */
224 	uint32_t	guest;			/* Guest OS */
225 	uint32_t	vmxnet3_revision;	/* Supported VMXNET3 revision */
226 	uint32_t	upt_version;		/* Supported UPT version */
227 	uint64_t	upt_features;
228 	uint64_t	driver_data;
229 	uint64_t	queue_shared;
230 	uint32_t	driver_data_len;
231 	uint32_t	queue_shared_len;
232 	uint32_t	mtu;
233 	uint16_t	nrxsg_max;
234 	uint8_t		ntxqueue;
235 	uint8_t		nrxqueue;
236 	uint32_t	reserved1[4];
237 
238 	/* Interrupt control */
239 	uint8_t		automask;
240 	uint8_t		nintr;
241 	uint8_t		evintr;
242 	uint8_t		modlevel[VMXNET3_MAX_INTRS];
243 	uint32_t	ictrl;
244 	uint32_t	reserved2[2];
245 
246 	/* Receive filter parameters */
247 	uint32_t	rxmode;
248 	uint16_t	mcast_tablelen;
249 	uint16_t	pad2;
250 	uint64_t	mcast_table;
251 	uint32_t	vlan_filter[4096 / 32];
252 
253 	struct {
254 		uint32_t version;
255 		uint32_t len;
256 		uint64_t paddr;
257 	}		rss, pm, plugin;
258 
259 	uint32_t	event;
260 	uint32_t	reserved3[5];
261 } __packed;
262 
263 struct vmxnet3_txq_shared {
264 	/* Control */
265 	uint32_t	npending;
266 	uint32_t	intr_threshold;
267 	uint64_t	reserved1;
268 
269 	/* Config */
270 	uint64_t	cmd_ring;
271 	uint64_t	data_ring;
272 	uint64_t	comp_ring;
273 	uint64_t	driver_data;
274 	uint64_t	reserved2;
275 	uint32_t	cmd_ring_len;
276 	uint32_t	data_ring_len;
277 	uint32_t	comp_ring_len;
278 	uint32_t	driver_data_len;
279 	uint8_t		intr_idx;
280 	uint8_t		pad1[7];
281 
282 	/* Queue status */
283 	uint8_t		stopped;
284 	uint8_t		pad2[3];
285 	uint32_t	error;
286 
287 	struct		UPT1_TxStats stats;
288 
289 	uint8_t		pad3[88];
290 } __packed;
291 
292 struct vmxnet3_rxq_shared {
293 	uint8_t		update_rxhead;
294 	uint8_t		pad1[7];
295 	uint64_t	reserved1;
296 
297 	uint64_t	cmd_ring[2];
298 	uint64_t	comp_ring;
299 	uint64_t	driver_data;
300 	uint64_t	reserved2;
301 	uint32_t	cmd_ring_len[2];
302 	uint32_t	comp_ring_len;
303 	uint32_t	driver_data_len;
304 	uint8_t		intr_idx;
305 	uint8_t		pad2[7];
306 
307 	uint8_t		stopped;
308 	uint8_t		pad3[3];
309 	uint32_t	error;
310 
311 	struct		UPT1_RxStats stats;
312 
313 	uint8_t		pad4[88];
314 } __packed;
315 
316 #endif /* _IF_VMXREG_H */
317