1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 #define VGE_JUMBO_MTU 9000 36 37 #define VGE_TX_DESC_CNT 256 38 #define VGE_RX_DESC_CNT 252 /* Must be a multiple of 4!! */ 39 #define VGE_TX_RING_ALIGN 64 40 #define VGE_RX_RING_ALIGN 64 41 #define VGE_MAXTXSEGS 6 42 #define VGE_RX_BUF_ALIGN sizeof(uint32_t) 43 44 /* 45 * VIA Velocity allows 64bit DMA addressing but high 16bits 46 * of the DMA address should be the same for Tx/Rx buffers. 47 * Because this condition can't be guaranteed vge(4) limit 48 * DMA address space to 48bits. 49 */ 50 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 51 #define VGE_BUF_DMA_MAXADDR BUS_SPACE_MAXADDR 52 #else 53 #define VGE_BUF_DMA_MAXADDR 0xFFFFFFFFFFFF 54 #endif 55 56 #define VGE_RX_LIST_SZ (VGE_RX_DESC_CNT * sizeof(struct vge_rx_desc)) 57 #define VGE_TX_LIST_SZ (VGE_TX_DESC_CNT * sizeof(struct vge_tx_desc)) 58 #define VGE_TX_DESC_INC(x) ((x) = ((x) + 1) % VGE_TX_DESC_CNT) 59 #define VGE_TX_DESC_DEC(x) \ 60 ((x) = (((x) + VGE_TX_DESC_CNT - 1) % VGE_TX_DESC_CNT)) 61 #define VGE_RX_DESC_INC(x) ((x) = ((x) + 1) % VGE_RX_DESC_CNT) 62 #define VGE_ADDR_LO(y) ((uint64_t) (y) & 0xFFFFFFFF) 63 #define VGE_ADDR_HI(y) ((uint64_t) (y) >> 32) 64 #define VGE_BUFLEN(y) ((y) & 0x3FFF) 65 #define VGE_RXBYTES(x) (((x) & VGE_RDSTS_BUFSIZ) >> 16) 66 #define VGE_MIN_FRAMELEN 60 67 68 #ifdef VGE_FIXUP_RX 69 #define VGE_ETHER_ALIGN sizeof(uint32_t) 70 #else 71 #define VGE_ETHER_ALIGN 0 72 #endif 73 74 struct vge_type { 75 uint16_t vge_vid; 76 uint16_t vge_did; 77 char *vge_name; 78 }; 79 80 struct vge_txdesc { 81 struct mbuf *tx_m; 82 bus_dmamap_t tx_dmamap; 83 struct vge_tx_desc *tx_desc; 84 struct vge_txdesc *txd_prev; 85 }; 86 87 struct vge_rxdesc { 88 struct mbuf *rx_m; 89 bus_dmamap_t rx_dmamap; 90 struct vge_rx_desc *rx_desc; 91 struct vge_rxdesc *rxd_prev; 92 }; 93 94 struct vge_chain_data{ 95 bus_dma_tag_t vge_ring_tag; 96 bus_dma_tag_t vge_buffer_tag; 97 bus_dma_tag_t vge_tx_tag; 98 struct vge_txdesc vge_txdesc[VGE_TX_DESC_CNT]; 99 bus_dma_tag_t vge_rx_tag; 100 struct vge_rxdesc vge_rxdesc[VGE_RX_DESC_CNT]; 101 bus_dma_tag_t vge_tx_ring_tag; 102 bus_dmamap_t vge_tx_ring_map; 103 bus_dma_tag_t vge_rx_ring_tag; 104 bus_dmamap_t vge_rx_ring_map; 105 bus_dmamap_t vge_rx_sparemap; 106 107 int vge_tx_prodidx; 108 int vge_tx_considx; 109 int vge_tx_cnt; 110 int vge_rx_prodidx; 111 int vge_rx_commit; 112 113 struct mbuf *vge_head; 114 struct mbuf *vge_tail; 115 }; 116 117 #define VGE_CHAIN_RESET(_sc) \ 118 do { \ 119 if ((_sc)->vge_cdata.vge_head != NULL) { \ 120 m_freem((_sc)->vge_cdata.vge_head); \ 121 (_sc)->vge_cdata.vge_head = NULL; \ 122 (_sc)->vge_cdata.vge_tail = NULL; \ 123 } \ 124 } while (0); 125 126 struct vge_ring_data { 127 struct vge_tx_desc *vge_tx_ring; 128 bus_addr_t vge_tx_ring_paddr; 129 struct vge_rx_desc *vge_rx_ring; 130 bus_addr_t vge_rx_ring_paddr; 131 }; 132 133 struct vge_softc { 134 struct ifnet *vge_ifp; /* interface info */ 135 device_t vge_dev; 136 struct resource *vge_res; 137 struct resource *vge_irq; 138 void *vge_intrhand; 139 device_t vge_miibus; 140 uint8_t vge_type; 141 int vge_if_flags; 142 int vge_phyaddr; 143 int vge_flags; 144 #define VGE_FLAG_PCIE 0x0001 145 #define VGE_FLAG_MSI 0x0002 146 #define VGE_FLAG_LINK 0x8000 147 int vge_expcap; 148 int vge_camidx; 149 struct mtx vge_mtx; 150 struct callout vge_watchdog; 151 int vge_timer; 152 153 struct vge_chain_data vge_cdata; 154 struct vge_ring_data vge_rdata; 155 156 int suspended; /* 0 = normal 1 = suspended */ 157 }; 158 159 #define VGE_LOCK(_sc) mtx_lock(&(_sc)->vge_mtx) 160 #define VGE_UNLOCK(_sc) mtx_unlock(&(_sc)->vge_mtx) 161 #define VGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vge_mtx, MA_OWNED) 162 163 /* 164 * register space access macros 165 */ 166 #define CSR_WRITE_STREAM_4(sc, reg, val) \ 167 bus_write_stream_4(sc->vge_res, reg, val) 168 #define CSR_WRITE_4(sc, reg, val) \ 169 bus_write_4(sc->vge_res, reg, val) 170 #define CSR_WRITE_2(sc, reg, val) \ 171 bus_write_2(sc->vge_res, reg, val) 172 #define CSR_WRITE_1(sc, reg, val) \ 173 bus_write_1(sc->vge_res, reg, val) 174 175 #define CSR_READ_4(sc, reg) \ 176 bus_read_4(sc->vge_res, reg) 177 #define CSR_READ_2(sc, reg) \ 178 bus_read_2(sc->vge_res, reg) 179 #define CSR_READ_1(sc, reg) \ 180 bus_read_1(sc->vge_res, reg) 181 182 #define CSR_SETBIT_1(sc, reg, x) \ 183 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x)) 184 #define CSR_SETBIT_2(sc, reg, x) \ 185 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x)) 186 #define CSR_SETBIT_4(sc, reg, x) \ 187 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 188 189 #define CSR_CLRBIT_1(sc, reg, x) \ 190 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x)) 191 #define CSR_CLRBIT_2(sc, reg, x) \ 192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x)) 193 #define CSR_CLRBIT_4(sc, reg, x) \ 194 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 195 196 #define VGE_RXCHUNK 4 197 #define VGE_TIMEOUT 10000 198 199