1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #ifdef HAVE_KERNEL_OPTION_HEADERS 84 #include "opt_device_polling.h" 85 #endif 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/module.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/sysctl.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_var.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <sys/bus.h> 112 #include <sys/rman.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 117 #include <dev/pci/pcireg.h> 118 #include <dev/pci/pcivar.h> 119 120 MODULE_DEPEND(vge, pci, 1, 1, 1); 121 MODULE_DEPEND(vge, ether, 1, 1, 1); 122 MODULE_DEPEND(vge, miibus, 1, 1, 1); 123 124 /* "device miibus" required. See GENERIC if you get errors here. */ 125 #include "miibus_if.h" 126 127 #include <dev/vge/if_vgereg.h> 128 #include <dev/vge/if_vgevar.h> 129 130 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 131 132 /* Tunables */ 133 static int msi_disable = 0; 134 TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 135 136 /* 137 * The SQE error counter of MIB seems to report bogus value. 138 * Vendor's workaround does not seem to work on PCIe based 139 * controllers. Disable it until we find better workaround. 140 */ 141 #undef VGE_ENABLE_SQEERR 142 143 /* 144 * Various supported device vendors/types and their names. 145 */ 146 static struct vge_type vge_devs[] = { 147 { VIA_VENDORID, VIA_DEVICEID_61XX, 148 "VIA Networking Velocity Gigabit Ethernet" }, 149 { 0, 0, NULL } 150 }; 151 152 static int vge_attach(device_t); 153 static int vge_detach(device_t); 154 static int vge_probe(device_t); 155 static int vge_resume(device_t); 156 static int vge_shutdown(device_t); 157 static int vge_suspend(device_t); 158 159 static void vge_cam_clear(struct vge_softc *); 160 static int vge_cam_set(struct vge_softc *, uint8_t *); 161 static void vge_clrwol(struct vge_softc *); 162 static void vge_discard_rxbuf(struct vge_softc *, int); 163 static int vge_dma_alloc(struct vge_softc *); 164 static void vge_dma_free(struct vge_softc *); 165 static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 166 #ifdef VGE_EEPROM 167 static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 168 #endif 169 static int vge_encap(struct vge_softc *, struct mbuf **); 170 #ifndef __NO_STRICT_ALIGNMENT 171 static __inline void 172 vge_fixup_rx(struct mbuf *); 173 #endif 174 static void vge_freebufs(struct vge_softc *); 175 static void vge_ifmedia_sts(if_t, struct ifmediareq *); 176 static int vge_ifmedia_upd(if_t); 177 static int vge_ifmedia_upd_locked(struct vge_softc *); 178 static void vge_init(void *); 179 static void vge_init_locked(struct vge_softc *); 180 static void vge_intr(void *); 181 static void vge_intr_holdoff(struct vge_softc *); 182 static int vge_ioctl(if_t, u_long, caddr_t); 183 static void vge_link_statchg(void *); 184 static int vge_miibus_readreg(device_t, int, int); 185 static int vge_miibus_writereg(device_t, int, int, int); 186 static void vge_miipoll_start(struct vge_softc *); 187 static void vge_miipoll_stop(struct vge_softc *); 188 static int vge_newbuf(struct vge_softc *, int); 189 static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 190 static void vge_reset(struct vge_softc *); 191 static int vge_rx_list_init(struct vge_softc *); 192 static int vge_rxeof(struct vge_softc *, int); 193 static void vge_rxfilter(struct vge_softc *); 194 static void vge_setmedia(struct vge_softc *); 195 static void vge_setvlan(struct vge_softc *); 196 static void vge_setwol(struct vge_softc *); 197 static void vge_start(if_t); 198 static void vge_start_locked(if_t); 199 static void vge_stats_clear(struct vge_softc *); 200 static void vge_stats_update(struct vge_softc *); 201 static void vge_stop(struct vge_softc *); 202 static void vge_sysctl_node(struct vge_softc *); 203 static int vge_tx_list_init(struct vge_softc *); 204 static void vge_txeof(struct vge_softc *); 205 static void vge_watchdog(void *); 206 207 static device_method_t vge_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_probe, vge_probe), 210 DEVMETHOD(device_attach, vge_attach), 211 DEVMETHOD(device_detach, vge_detach), 212 DEVMETHOD(device_suspend, vge_suspend), 213 DEVMETHOD(device_resume, vge_resume), 214 DEVMETHOD(device_shutdown, vge_shutdown), 215 216 /* MII interface */ 217 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 218 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 219 220 DEVMETHOD_END 221 }; 222 223 static driver_t vge_driver = { 224 "vge", 225 vge_methods, 226 sizeof(struct vge_softc) 227 }; 228 229 DRIVER_MODULE(vge, pci, vge_driver, 0, 0); 230 DRIVER_MODULE(miibus, vge, miibus_driver, 0, 0); 231 232 #ifdef VGE_EEPROM 233 /* 234 * Read a word of data stored in the EEPROM at address 'addr.' 235 */ 236 static void 237 vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 238 { 239 int i; 240 uint16_t word = 0; 241 242 /* 243 * Enter EEPROM embedded programming mode. In order to 244 * access the EEPROM at all, we first have to set the 245 * EELOAD bit in the CHIPCFG2 register. 246 */ 247 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 248 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 249 250 /* Select the address of the word we want to read */ 251 CSR_WRITE_1(sc, VGE_EEADDR, addr); 252 253 /* Issue read command */ 254 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 255 256 /* Wait for the done bit to be set. */ 257 for (i = 0; i < VGE_TIMEOUT; i++) { 258 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 259 break; 260 } 261 262 if (i == VGE_TIMEOUT) { 263 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 264 *dest = 0; 265 return; 266 } 267 268 /* Read the result */ 269 word = CSR_READ_2(sc, VGE_EERDDAT); 270 271 /* Turn off EEPROM access mode. */ 272 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 273 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 274 275 *dest = word; 276 } 277 #endif 278 279 /* 280 * Read a sequence of words from the EEPROM. 281 */ 282 static void 283 vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 284 { 285 int i; 286 #ifdef VGE_EEPROM 287 uint16_t word = 0, *ptr; 288 289 for (i = 0; i < cnt; i++) { 290 vge_eeprom_getword(sc, off + i, &word); 291 ptr = (uint16_t *)(dest + (i * 2)); 292 if (swap) 293 *ptr = ntohs(word); 294 else 295 *ptr = word; 296 } 297 #else 298 for (i = 0; i < ETHER_ADDR_LEN; i++) 299 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 300 #endif 301 } 302 303 static void 304 vge_miipoll_stop(struct vge_softc *sc) 305 { 306 int i; 307 308 CSR_WRITE_1(sc, VGE_MIICMD, 0); 309 310 for (i = 0; i < VGE_TIMEOUT; i++) { 311 DELAY(1); 312 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 313 break; 314 } 315 316 if (i == VGE_TIMEOUT) 317 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 318 } 319 320 static void 321 vge_miipoll_start(struct vge_softc *sc) 322 { 323 int i; 324 325 /* First, make sure we're idle. */ 326 327 CSR_WRITE_1(sc, VGE_MIICMD, 0); 328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 329 330 for (i = 0; i < VGE_TIMEOUT; i++) { 331 DELAY(1); 332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 333 break; 334 } 335 336 if (i == VGE_TIMEOUT) { 337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 338 return; 339 } 340 341 /* Now enable auto poll mode. */ 342 343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 344 345 /* And make sure it started. */ 346 347 for (i = 0; i < VGE_TIMEOUT; i++) { 348 DELAY(1); 349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 350 break; 351 } 352 353 if (i == VGE_TIMEOUT) 354 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 355 } 356 357 static int 358 vge_miibus_readreg(device_t dev, int phy, int reg) 359 { 360 struct vge_softc *sc; 361 int i; 362 uint16_t rval = 0; 363 364 sc = device_get_softc(dev); 365 366 vge_miipoll_stop(sc); 367 368 /* Specify the register we want to read. */ 369 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 370 371 /* Issue read command. */ 372 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 373 374 /* Wait for the read command bit to self-clear. */ 375 for (i = 0; i < VGE_TIMEOUT; i++) { 376 DELAY(1); 377 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 378 break; 379 } 380 381 if (i == VGE_TIMEOUT) 382 device_printf(sc->vge_dev, "MII read timed out\n"); 383 else 384 rval = CSR_READ_2(sc, VGE_MIIDATA); 385 386 vge_miipoll_start(sc); 387 388 return (rval); 389 } 390 391 static int 392 vge_miibus_writereg(device_t dev, int phy, int reg, int data) 393 { 394 struct vge_softc *sc; 395 int i, rval = 0; 396 397 sc = device_get_softc(dev); 398 399 vge_miipoll_stop(sc); 400 401 /* Specify the register we want to write. */ 402 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 403 404 /* Specify the data we want to write. */ 405 CSR_WRITE_2(sc, VGE_MIIDATA, data); 406 407 /* Issue write command. */ 408 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 409 410 /* Wait for the write command bit to self-clear. */ 411 for (i = 0; i < VGE_TIMEOUT; i++) { 412 DELAY(1); 413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 414 break; 415 } 416 417 if (i == VGE_TIMEOUT) { 418 device_printf(sc->vge_dev, "MII write timed out\n"); 419 rval = EIO; 420 } 421 422 vge_miipoll_start(sc); 423 424 return (rval); 425 } 426 427 static void 428 vge_cam_clear(struct vge_softc *sc) 429 { 430 int i; 431 432 /* 433 * Turn off all the mask bits. This tells the chip 434 * that none of the entries in the CAM filter are valid. 435 * desired entries will be enabled as we fill the filter in. 436 */ 437 438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 441 for (i = 0; i < 8; i++) 442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 443 444 /* Clear the VLAN filter too. */ 445 446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 447 for (i = 0; i < 8; i++) 448 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 449 450 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 453 454 sc->vge_camidx = 0; 455 } 456 457 static int 458 vge_cam_set(struct vge_softc *sc, uint8_t *addr) 459 { 460 int i, error = 0; 461 462 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 463 return (ENOSPC); 464 465 /* Select the CAM data page. */ 466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 468 469 /* Set the filter entry we want to update and enable writing. */ 470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 471 472 /* Write the address to the CAM registers */ 473 for (i = 0; i < ETHER_ADDR_LEN; i++) 474 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 475 476 /* Issue a write command. */ 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 478 479 /* Wake for it to clear. */ 480 for (i = 0; i < VGE_TIMEOUT; i++) { 481 DELAY(1); 482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 483 break; 484 } 485 486 if (i == VGE_TIMEOUT) { 487 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 488 error = EIO; 489 goto fail; 490 } 491 492 /* Select the CAM mask page. */ 493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 495 496 /* Set the mask bit that enables this filter. */ 497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 498 1<<(sc->vge_camidx & 7)); 499 500 sc->vge_camidx++; 501 502 fail: 503 /* Turn off access to CAM. */ 504 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 505 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 507 508 return (error); 509 } 510 511 static void 512 vge_setvlan(struct vge_softc *sc) 513 { 514 if_t ifp; 515 uint8_t cfg; 516 517 VGE_LOCK_ASSERT(sc); 518 519 ifp = sc->vge_ifp; 520 cfg = CSR_READ_1(sc, VGE_RXCFG); 521 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 522 cfg |= VGE_VTAG_OPT2; 523 else 524 cfg &= ~VGE_VTAG_OPT2; 525 CSR_WRITE_1(sc, VGE_RXCFG, cfg); 526 } 527 528 static u_int 529 vge_set_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 530 { 531 struct vge_softc *sc = arg; 532 533 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 534 return (0); 535 536 (void )vge_cam_set(sc, LLADDR(sdl)); 537 538 return (1); 539 } 540 541 static u_int 542 vge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 543 { 544 uint32_t h, *hashes = arg; 545 546 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 547 if (h < 32) 548 hashes[0] |= (1 << h); 549 else 550 hashes[1] |= (1 << (h - 32)); 551 552 return (1); 553 } 554 555 /* 556 * Program the multicast filter. We use the 64-entry CAM filter 557 * for perfect filtering. If there's more than 64 multicast addresses, 558 * we use the hash filter instead. 559 */ 560 static void 561 vge_rxfilter(struct vge_softc *sc) 562 { 563 if_t ifp; 564 uint32_t hashes[2]; 565 uint8_t rxcfg; 566 567 VGE_LOCK_ASSERT(sc); 568 569 /* First, zot all the multicast entries. */ 570 hashes[0] = 0; 571 hashes[1] = 0; 572 573 rxcfg = CSR_READ_1(sc, VGE_RXCTL); 574 rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | 575 VGE_RXCTL_RX_PROMISC); 576 /* 577 * Always allow VLAN oversized frames and frames for 578 * this host. 579 */ 580 rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; 581 582 ifp = sc->vge_ifp; 583 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 584 rxcfg |= VGE_RXCTL_RX_BCAST; 585 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 586 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 587 rxcfg |= VGE_RXCTL_RX_PROMISC; 588 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 589 hashes[0] = 0xFFFFFFFF; 590 hashes[1] = 0xFFFFFFFF; 591 } 592 goto done; 593 } 594 595 vge_cam_clear(sc); 596 597 /* Now program new ones */ 598 if_foreach_llmaddr(ifp, vge_set_maddr, sc); 599 600 /* If there were too many addresses, use the hash filter. */ 601 if (sc->vge_camidx == VGE_CAM_MAXADDRS) { 602 vge_cam_clear(sc); 603 if_foreach_llmaddr(ifp, vge_hash_maddr, hashes); 604 } 605 606 done: 607 if (hashes[0] != 0 || hashes[1] != 0) 608 rxcfg |= VGE_RXCTL_RX_MCAST; 609 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 610 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 611 CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); 612 } 613 614 static void 615 vge_reset(struct vge_softc *sc) 616 { 617 int i; 618 619 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 620 621 for (i = 0; i < VGE_TIMEOUT; i++) { 622 DELAY(5); 623 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 624 break; 625 } 626 627 if (i == VGE_TIMEOUT) { 628 device_printf(sc->vge_dev, "soft reset timed out\n"); 629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 630 DELAY(2000); 631 } 632 633 DELAY(5000); 634 } 635 636 /* 637 * Probe for a VIA gigabit chip. Check the PCI vendor and device 638 * IDs against our list and return a device name if we find a match. 639 */ 640 static int 641 vge_probe(device_t dev) 642 { 643 struct vge_type *t; 644 645 t = vge_devs; 646 647 while (t->vge_name != NULL) { 648 if ((pci_get_vendor(dev) == t->vge_vid) && 649 (pci_get_device(dev) == t->vge_did)) { 650 device_set_desc(dev, t->vge_name); 651 return (BUS_PROBE_DEFAULT); 652 } 653 t++; 654 } 655 656 return (ENXIO); 657 } 658 659 /* 660 * Map a single buffer address. 661 */ 662 663 struct vge_dmamap_arg { 664 bus_addr_t vge_busaddr; 665 }; 666 667 static void 668 vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 669 { 670 struct vge_dmamap_arg *ctx; 671 672 if (error != 0) 673 return; 674 675 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 676 677 ctx = (struct vge_dmamap_arg *)arg; 678 ctx->vge_busaddr = segs[0].ds_addr; 679 } 680 681 static int 682 vge_dma_alloc(struct vge_softc *sc) 683 { 684 struct vge_dmamap_arg ctx; 685 struct vge_txdesc *txd; 686 struct vge_rxdesc *rxd; 687 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 688 int error, i; 689 690 /* 691 * It seems old PCI controllers do not support DAC. DAC 692 * configuration can be enabled by accessing VGE_CHIPCFG3 693 * register but honor EEPROM configuration instead of 694 * blindly overriding DAC configuration. PCIe based 695 * controllers are supposed to support 64bit DMA so enable 696 * 64bit DMA on these controllers. 697 */ 698 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 699 lowaddr = BUS_SPACE_MAXADDR; 700 else 701 lowaddr = BUS_SPACE_MAXADDR_32BIT; 702 703 again: 704 /* Create parent ring tag. */ 705 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 706 1, 0, /* algnmnt, boundary */ 707 lowaddr, /* lowaddr */ 708 BUS_SPACE_MAXADDR, /* highaddr */ 709 NULL, NULL, /* filter, filterarg */ 710 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 711 0, /* nsegments */ 712 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 713 0, /* flags */ 714 NULL, NULL, /* lockfunc, lockarg */ 715 &sc->vge_cdata.vge_ring_tag); 716 if (error != 0) { 717 device_printf(sc->vge_dev, 718 "could not create parent DMA tag.\n"); 719 goto fail; 720 } 721 722 /* Create tag for Tx ring. */ 723 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 724 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 725 BUS_SPACE_MAXADDR, /* lowaddr */ 726 BUS_SPACE_MAXADDR, /* highaddr */ 727 NULL, NULL, /* filter, filterarg */ 728 VGE_TX_LIST_SZ, /* maxsize */ 729 1, /* nsegments */ 730 VGE_TX_LIST_SZ, /* maxsegsize */ 731 0, /* flags */ 732 NULL, NULL, /* lockfunc, lockarg */ 733 &sc->vge_cdata.vge_tx_ring_tag); 734 if (error != 0) { 735 device_printf(sc->vge_dev, 736 "could not allocate Tx ring DMA tag.\n"); 737 goto fail; 738 } 739 740 /* Create tag for Rx ring. */ 741 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 742 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 743 BUS_SPACE_MAXADDR, /* lowaddr */ 744 BUS_SPACE_MAXADDR, /* highaddr */ 745 NULL, NULL, /* filter, filterarg */ 746 VGE_RX_LIST_SZ, /* maxsize */ 747 1, /* nsegments */ 748 VGE_RX_LIST_SZ, /* maxsegsize */ 749 0, /* flags */ 750 NULL, NULL, /* lockfunc, lockarg */ 751 &sc->vge_cdata.vge_rx_ring_tag); 752 if (error != 0) { 753 device_printf(sc->vge_dev, 754 "could not allocate Rx ring DMA tag.\n"); 755 goto fail; 756 } 757 758 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 759 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 760 (void **)&sc->vge_rdata.vge_tx_ring, 761 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 762 &sc->vge_cdata.vge_tx_ring_map); 763 if (error != 0) { 764 device_printf(sc->vge_dev, 765 "could not allocate DMA'able memory for Tx ring.\n"); 766 goto fail; 767 } 768 769 ctx.vge_busaddr = 0; 770 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 771 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 772 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 773 if (error != 0 || ctx.vge_busaddr == 0) { 774 device_printf(sc->vge_dev, 775 "could not load DMA'able memory for Tx ring.\n"); 776 goto fail; 777 } 778 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 779 780 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 781 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 782 (void **)&sc->vge_rdata.vge_rx_ring, 783 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 784 &sc->vge_cdata.vge_rx_ring_map); 785 if (error != 0) { 786 device_printf(sc->vge_dev, 787 "could not allocate DMA'able memory for Rx ring.\n"); 788 goto fail; 789 } 790 791 ctx.vge_busaddr = 0; 792 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 793 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 794 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 795 if (error != 0 || ctx.vge_busaddr == 0) { 796 device_printf(sc->vge_dev, 797 "could not load DMA'able memory for Rx ring.\n"); 798 goto fail; 799 } 800 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 801 802 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 803 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 804 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 805 if ((VGE_ADDR_HI(tx_ring_end) != 806 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 807 (VGE_ADDR_HI(rx_ring_end) != 808 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 809 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 810 device_printf(sc->vge_dev, "4GB boundary crossed, " 811 "switching to 32bit DMA address mode.\n"); 812 vge_dma_free(sc); 813 /* Limit DMA address space to 32bit and try again. */ 814 lowaddr = BUS_SPACE_MAXADDR_32BIT; 815 goto again; 816 } 817 818 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 819 lowaddr = VGE_BUF_DMA_MAXADDR; 820 else 821 lowaddr = BUS_SPACE_MAXADDR_32BIT; 822 /* Create parent buffer tag. */ 823 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 824 1, 0, /* algnmnt, boundary */ 825 lowaddr, /* lowaddr */ 826 BUS_SPACE_MAXADDR, /* highaddr */ 827 NULL, NULL, /* filter, filterarg */ 828 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 829 0, /* nsegments */ 830 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 831 0, /* flags */ 832 NULL, NULL, /* lockfunc, lockarg */ 833 &sc->vge_cdata.vge_buffer_tag); 834 if (error != 0) { 835 device_printf(sc->vge_dev, 836 "could not create parent buffer DMA tag.\n"); 837 goto fail; 838 } 839 840 /* Create tag for Tx buffers. */ 841 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 842 1, 0, /* algnmnt, boundary */ 843 BUS_SPACE_MAXADDR, /* lowaddr */ 844 BUS_SPACE_MAXADDR, /* highaddr */ 845 NULL, NULL, /* filter, filterarg */ 846 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 847 VGE_MAXTXSEGS, /* nsegments */ 848 MCLBYTES, /* maxsegsize */ 849 0, /* flags */ 850 NULL, NULL, /* lockfunc, lockarg */ 851 &sc->vge_cdata.vge_tx_tag); 852 if (error != 0) { 853 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 854 goto fail; 855 } 856 857 /* Create tag for Rx buffers. */ 858 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 859 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 860 BUS_SPACE_MAXADDR, /* lowaddr */ 861 BUS_SPACE_MAXADDR, /* highaddr */ 862 NULL, NULL, /* filter, filterarg */ 863 MCLBYTES, /* maxsize */ 864 1, /* nsegments */ 865 MCLBYTES, /* maxsegsize */ 866 0, /* flags */ 867 NULL, NULL, /* lockfunc, lockarg */ 868 &sc->vge_cdata.vge_rx_tag); 869 if (error != 0) { 870 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 871 goto fail; 872 } 873 874 /* Create DMA maps for Tx buffers. */ 875 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 876 txd = &sc->vge_cdata.vge_txdesc[i]; 877 txd->tx_m = NULL; 878 txd->tx_dmamap = NULL; 879 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 880 &txd->tx_dmamap); 881 if (error != 0) { 882 device_printf(sc->vge_dev, 883 "could not create Tx dmamap.\n"); 884 goto fail; 885 } 886 } 887 /* Create DMA maps for Rx buffers. */ 888 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 889 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 890 device_printf(sc->vge_dev, 891 "could not create spare Rx dmamap.\n"); 892 goto fail; 893 } 894 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 895 rxd = &sc->vge_cdata.vge_rxdesc[i]; 896 rxd->rx_m = NULL; 897 rxd->rx_dmamap = NULL; 898 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 899 &rxd->rx_dmamap); 900 if (error != 0) { 901 device_printf(sc->vge_dev, 902 "could not create Rx dmamap.\n"); 903 goto fail; 904 } 905 } 906 907 fail: 908 return (error); 909 } 910 911 static void 912 vge_dma_free(struct vge_softc *sc) 913 { 914 struct vge_txdesc *txd; 915 struct vge_rxdesc *rxd; 916 int i; 917 918 /* Tx ring. */ 919 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 920 if (sc->vge_rdata.vge_tx_ring_paddr) 921 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 922 sc->vge_cdata.vge_tx_ring_map); 923 if (sc->vge_rdata.vge_tx_ring) 924 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 925 sc->vge_rdata.vge_tx_ring, 926 sc->vge_cdata.vge_tx_ring_map); 927 sc->vge_rdata.vge_tx_ring = NULL; 928 sc->vge_rdata.vge_tx_ring_paddr = 0; 929 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 930 sc->vge_cdata.vge_tx_ring_tag = NULL; 931 } 932 /* Rx ring. */ 933 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 934 if (sc->vge_rdata.vge_rx_ring_paddr) 935 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 936 sc->vge_cdata.vge_rx_ring_map); 937 if (sc->vge_rdata.vge_rx_ring) 938 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 939 sc->vge_rdata.vge_rx_ring, 940 sc->vge_cdata.vge_rx_ring_map); 941 sc->vge_rdata.vge_rx_ring = NULL; 942 sc->vge_rdata.vge_rx_ring_paddr = 0; 943 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 944 sc->vge_cdata.vge_rx_ring_tag = NULL; 945 } 946 /* Tx buffers. */ 947 if (sc->vge_cdata.vge_tx_tag != NULL) { 948 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 949 txd = &sc->vge_cdata.vge_txdesc[i]; 950 if (txd->tx_dmamap != NULL) { 951 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 952 txd->tx_dmamap); 953 txd->tx_dmamap = NULL; 954 } 955 } 956 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 957 sc->vge_cdata.vge_tx_tag = NULL; 958 } 959 /* Rx buffers. */ 960 if (sc->vge_cdata.vge_rx_tag != NULL) { 961 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 962 rxd = &sc->vge_cdata.vge_rxdesc[i]; 963 if (rxd->rx_dmamap != NULL) { 964 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 965 rxd->rx_dmamap); 966 rxd->rx_dmamap = NULL; 967 } 968 } 969 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 970 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 971 sc->vge_cdata.vge_rx_sparemap); 972 sc->vge_cdata.vge_rx_sparemap = NULL; 973 } 974 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 975 sc->vge_cdata.vge_rx_tag = NULL; 976 } 977 978 if (sc->vge_cdata.vge_buffer_tag != NULL) { 979 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 980 sc->vge_cdata.vge_buffer_tag = NULL; 981 } 982 if (sc->vge_cdata.vge_ring_tag != NULL) { 983 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 984 sc->vge_cdata.vge_ring_tag = NULL; 985 } 986 } 987 988 /* 989 * Attach the interface. Allocate softc structures, do ifmedia 990 * setup and ethernet/BPF attach. 991 */ 992 static int 993 vge_attach(device_t dev) 994 { 995 u_char eaddr[ETHER_ADDR_LEN]; 996 struct vge_softc *sc; 997 if_t ifp; 998 int error = 0, cap, i, msic, rid; 999 1000 sc = device_get_softc(dev); 1001 sc->vge_dev = dev; 1002 1003 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1004 MTX_DEF); 1005 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 1006 1007 /* 1008 * Map control/status registers. 1009 */ 1010 pci_enable_busmaster(dev); 1011 1012 rid = PCIR_BAR(1); 1013 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1014 RF_ACTIVE); 1015 1016 if (sc->vge_res == NULL) { 1017 device_printf(dev, "couldn't map ports/memory\n"); 1018 error = ENXIO; 1019 goto fail; 1020 } 1021 1022 if (pci_find_cap(dev, PCIY_EXPRESS, &cap) == 0) { 1023 sc->vge_flags |= VGE_FLAG_PCIE; 1024 sc->vge_expcap = cap; 1025 } else 1026 sc->vge_flags |= VGE_FLAG_JUMBO; 1027 if (pci_find_cap(dev, PCIY_PMG, &cap) == 0) { 1028 sc->vge_flags |= VGE_FLAG_PMCAP; 1029 sc->vge_pmcap = cap; 1030 } 1031 rid = 0; 1032 msic = pci_msi_count(dev); 1033 if (msi_disable == 0 && msic > 0) { 1034 msic = 1; 1035 if (pci_alloc_msi(dev, &msic) == 0) { 1036 if (msic == 1) { 1037 sc->vge_flags |= VGE_FLAG_MSI; 1038 device_printf(dev, "Using %d MSI message\n", 1039 msic); 1040 rid = 1; 1041 } else 1042 pci_release_msi(dev); 1043 } 1044 } 1045 1046 /* Allocate interrupt */ 1047 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1048 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 1049 if (sc->vge_irq == NULL) { 1050 device_printf(dev, "couldn't map interrupt\n"); 1051 error = ENXIO; 1052 goto fail; 1053 } 1054 1055 /* Reset the adapter. */ 1056 vge_reset(sc); 1057 /* Reload EEPROM. */ 1058 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 1059 for (i = 0; i < VGE_TIMEOUT; i++) { 1060 DELAY(5); 1061 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1062 break; 1063 } 1064 if (i == VGE_TIMEOUT) 1065 device_printf(dev, "EEPROM reload timed out\n"); 1066 /* 1067 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1068 * MAC will receive magic packet which in turn confuses 1069 * controller. 1070 */ 1071 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1072 1073 /* 1074 * Get station address from the EEPROM. 1075 */ 1076 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1077 /* 1078 * Save configured PHY address. 1079 * It seems the PHY address of PCIe controllers just 1080 * reflects media jump strapping status so we assume the 1081 * internal PHY address of PCIe controller is at 1. 1082 */ 1083 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1084 sc->vge_phyaddr = 1; 1085 else 1086 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1087 VGE_MIICFG_PHYADDR; 1088 /* Clear WOL and take hardware from powerdown. */ 1089 vge_clrwol(sc); 1090 vge_sysctl_node(sc); 1091 error = vge_dma_alloc(sc); 1092 if (error) 1093 goto fail; 1094 1095 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1096 vge_miipoll_start(sc); 1097 /* Do MII setup */ 1098 error = mii_attach(dev, &sc->vge_miibus, ifp, vge_ifmedia_upd, 1099 vge_ifmedia_sts, BMSR_DEFCAPMASK, sc->vge_phyaddr, MII_OFFSET_ANY, 1100 MIIF_DOPAUSE); 1101 if (error != 0) { 1102 device_printf(dev, "attaching PHYs failed\n"); 1103 goto fail; 1104 } 1105 1106 if_setsoftc(ifp, sc); 1107 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1108 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1109 if_setioctlfn(ifp, vge_ioctl); 1110 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 1111 if_setstartfn(ifp, vge_start); 1112 if_sethwassist(ifp, VGE_CSUM_FEATURES); 1113 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 1114 IFCAP_VLAN_HWTAGGING, 0); 1115 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) 1116 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 1117 if_setcapenable(ifp, if_getcapabilities(ifp)); 1118 #ifdef DEVICE_POLLING 1119 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 1120 #endif 1121 if_setinitfn(ifp, vge_init); 1122 if_setsendqlen(ifp, VGE_TX_DESC_CNT - 1); 1123 if_setsendqready(ifp); 1124 1125 /* 1126 * Call MI attach routine. 1127 */ 1128 ether_ifattach(ifp, eaddr); 1129 1130 /* Tell the upper layer(s) we support long frames. */ 1131 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1132 1133 /* Hook interrupt last to avoid having to lock softc */ 1134 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1135 NULL, vge_intr, sc, &sc->vge_intrhand); 1136 1137 if (error) { 1138 device_printf(dev, "couldn't set up irq\n"); 1139 ether_ifdetach(ifp); 1140 goto fail; 1141 } 1142 1143 fail: 1144 if (error) 1145 vge_detach(dev); 1146 1147 return (error); 1148 } 1149 1150 /* 1151 * Shutdown hardware and free up resources. This can be called any 1152 * time after the mutex has been initialized. It is called in both 1153 * the error case in attach and the normal detach case so it needs 1154 * to be careful about only freeing resources that have actually been 1155 * allocated. 1156 */ 1157 static int 1158 vge_detach(device_t dev) 1159 { 1160 struct vge_softc *sc; 1161 if_t ifp; 1162 1163 sc = device_get_softc(dev); 1164 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1165 ifp = sc->vge_ifp; 1166 1167 #ifdef DEVICE_POLLING 1168 if (if_getcapenable(ifp) & IFCAP_POLLING) 1169 ether_poll_deregister(ifp); 1170 #endif 1171 1172 /* These should only be active if attach succeeded */ 1173 if (device_is_attached(dev)) { 1174 ether_ifdetach(ifp); 1175 VGE_LOCK(sc); 1176 vge_stop(sc); 1177 VGE_UNLOCK(sc); 1178 callout_drain(&sc->vge_watchdog); 1179 } 1180 bus_generic_detach(dev); 1181 1182 if (sc->vge_intrhand) 1183 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1184 if (sc->vge_irq) 1185 bus_release_resource(dev, SYS_RES_IRQ, 1186 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1187 if (sc->vge_flags & VGE_FLAG_MSI) 1188 pci_release_msi(dev); 1189 if (sc->vge_res) 1190 bus_release_resource(dev, SYS_RES_MEMORY, 1191 PCIR_BAR(1), sc->vge_res); 1192 if (ifp) 1193 if_free(ifp); 1194 1195 vge_dma_free(sc); 1196 mtx_destroy(&sc->vge_mtx); 1197 1198 return (0); 1199 } 1200 1201 static void 1202 vge_discard_rxbuf(struct vge_softc *sc, int prod) 1203 { 1204 struct vge_rxdesc *rxd; 1205 int i; 1206 1207 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1208 rxd->rx_desc->vge_sts = 0; 1209 rxd->rx_desc->vge_ctl = 0; 1210 1211 /* 1212 * Note: the manual fails to document the fact that for 1213 * proper operation, the driver needs to replentish the RX 1214 * DMA ring 4 descriptors at a time (rather than one at a 1215 * time, like most chips). We can allocate the new buffers 1216 * but we should not set the OWN bits until we're ready 1217 * to hand back 4 of them in one shot. 1218 */ 1219 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1220 for (i = VGE_RXCHUNK; i > 0; i--) { 1221 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1222 rxd = rxd->rxd_prev; 1223 } 1224 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1225 } 1226 } 1227 1228 static int 1229 vge_newbuf(struct vge_softc *sc, int prod) 1230 { 1231 struct vge_rxdesc *rxd; 1232 struct mbuf *m; 1233 bus_dma_segment_t segs[1]; 1234 bus_dmamap_t map; 1235 int i, nsegs; 1236 1237 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1238 if (m == NULL) 1239 return (ENOBUFS); 1240 /* 1241 * This is part of an evil trick to deal with strict-alignment 1242 * architectures. The VIA chip requires RX buffers to be aligned 1243 * on 32-bit boundaries, but that will hose strict-alignment 1244 * architectures. To get around this, we leave some empty space 1245 * at the start of each buffer and for non-strict-alignment hosts, 1246 * we copy the buffer back two bytes to achieve word alignment. 1247 * This is slightly more efficient than allocating a new buffer, 1248 * copying the contents, and discarding the old buffer. 1249 */ 1250 m->m_len = m->m_pkthdr.len = MCLBYTES; 1251 m_adj(m, VGE_RX_BUF_ALIGN); 1252 1253 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1254 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1255 m_freem(m); 1256 return (ENOBUFS); 1257 } 1258 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1259 1260 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1261 if (rxd->rx_m != NULL) { 1262 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1263 BUS_DMASYNC_POSTREAD); 1264 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1265 } 1266 map = rxd->rx_dmamap; 1267 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1268 sc->vge_cdata.vge_rx_sparemap = map; 1269 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1270 BUS_DMASYNC_PREREAD); 1271 rxd->rx_m = m; 1272 1273 rxd->rx_desc->vge_sts = 0; 1274 rxd->rx_desc->vge_ctl = 0; 1275 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1276 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1277 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1278 1279 /* 1280 * Note: the manual fails to document the fact that for 1281 * proper operation, the driver needs to replenish the RX 1282 * DMA ring 4 descriptors at a time (rather than one at a 1283 * time, like most chips). We can allocate the new buffers 1284 * but we should not set the OWN bits until we're ready 1285 * to hand back 4 of them in one shot. 1286 */ 1287 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1288 for (i = VGE_RXCHUNK; i > 0; i--) { 1289 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1290 rxd = rxd->rxd_prev; 1291 } 1292 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1293 } 1294 1295 return (0); 1296 } 1297 1298 static int 1299 vge_tx_list_init(struct vge_softc *sc) 1300 { 1301 struct vge_ring_data *rd; 1302 struct vge_txdesc *txd; 1303 int i; 1304 1305 VGE_LOCK_ASSERT(sc); 1306 1307 sc->vge_cdata.vge_tx_prodidx = 0; 1308 sc->vge_cdata.vge_tx_considx = 0; 1309 sc->vge_cdata.vge_tx_cnt = 0; 1310 1311 rd = &sc->vge_rdata; 1312 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1313 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1314 txd = &sc->vge_cdata.vge_txdesc[i]; 1315 txd->tx_m = NULL; 1316 txd->tx_desc = &rd->vge_tx_ring[i]; 1317 } 1318 1319 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1320 sc->vge_cdata.vge_tx_ring_map, 1321 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1322 1323 return (0); 1324 } 1325 1326 static int 1327 vge_rx_list_init(struct vge_softc *sc) 1328 { 1329 struct vge_ring_data *rd; 1330 struct vge_rxdesc *rxd; 1331 int i; 1332 1333 VGE_LOCK_ASSERT(sc); 1334 1335 sc->vge_cdata.vge_rx_prodidx = 0; 1336 sc->vge_cdata.vge_head = NULL; 1337 sc->vge_cdata.vge_tail = NULL; 1338 sc->vge_cdata.vge_rx_commit = 0; 1339 1340 rd = &sc->vge_rdata; 1341 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1342 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1343 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1344 rxd->rx_m = NULL; 1345 rxd->rx_desc = &rd->vge_rx_ring[i]; 1346 if (i == 0) 1347 rxd->rxd_prev = 1348 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1349 else 1350 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1351 if (vge_newbuf(sc, i) != 0) 1352 return (ENOBUFS); 1353 } 1354 1355 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1356 sc->vge_cdata.vge_rx_ring_map, 1357 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1358 1359 sc->vge_cdata.vge_rx_commit = 0; 1360 1361 return (0); 1362 } 1363 1364 static void 1365 vge_freebufs(struct vge_softc *sc) 1366 { 1367 struct vge_txdesc *txd; 1368 struct vge_rxdesc *rxd; 1369 if_t ifp; 1370 int i; 1371 1372 VGE_LOCK_ASSERT(sc); 1373 1374 ifp = sc->vge_ifp; 1375 /* 1376 * Free RX and TX mbufs still in the queues. 1377 */ 1378 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1379 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1380 if (rxd->rx_m != NULL) { 1381 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1382 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1383 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1384 rxd->rx_dmamap); 1385 m_freem(rxd->rx_m); 1386 rxd->rx_m = NULL; 1387 } 1388 } 1389 1390 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1391 txd = &sc->vge_cdata.vge_txdesc[i]; 1392 if (txd->tx_m != NULL) { 1393 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1394 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1395 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1396 txd->tx_dmamap); 1397 m_freem(txd->tx_m); 1398 txd->tx_m = NULL; 1399 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1400 } 1401 } 1402 } 1403 1404 #ifndef __NO_STRICT_ALIGNMENT 1405 static __inline void 1406 vge_fixup_rx(struct mbuf *m) 1407 { 1408 int i; 1409 uint16_t *src, *dst; 1410 1411 src = mtod(m, uint16_t *); 1412 dst = src - 1; 1413 1414 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1415 *dst++ = *src++; 1416 1417 m->m_data -= ETHER_ALIGN; 1418 } 1419 #endif 1420 1421 /* 1422 * RX handler. We support the reception of jumbo frames that have 1423 * been fragmented across multiple 2K mbuf cluster buffers. 1424 */ 1425 static int 1426 vge_rxeof(struct vge_softc *sc, int count) 1427 { 1428 struct mbuf *m; 1429 if_t ifp; 1430 int prod, prog, total_len; 1431 struct vge_rxdesc *rxd; 1432 struct vge_rx_desc *cur_rx; 1433 uint32_t rxstat, rxctl; 1434 1435 VGE_LOCK_ASSERT(sc); 1436 1437 ifp = sc->vge_ifp; 1438 1439 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1440 sc->vge_cdata.vge_rx_ring_map, 1441 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1442 1443 prod = sc->vge_cdata.vge_rx_prodidx; 1444 for (prog = 0; count > 0 && 1445 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1446 VGE_RX_DESC_INC(prod)) { 1447 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1448 rxstat = le32toh(cur_rx->vge_sts); 1449 if ((rxstat & VGE_RDSTS_OWN) != 0) 1450 break; 1451 count--; 1452 prog++; 1453 rxctl = le32toh(cur_rx->vge_ctl); 1454 total_len = VGE_RXBYTES(rxstat); 1455 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1456 m = rxd->rx_m; 1457 1458 /* 1459 * If the 'start of frame' bit is set, this indicates 1460 * either the first fragment in a multi-fragment receive, 1461 * or an intermediate fragment. Either way, we want to 1462 * accumulate the buffers. 1463 */ 1464 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1465 if (vge_newbuf(sc, prod) != 0) { 1466 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1467 VGE_CHAIN_RESET(sc); 1468 vge_discard_rxbuf(sc, prod); 1469 continue; 1470 } 1471 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1472 if (sc->vge_cdata.vge_head == NULL) { 1473 sc->vge_cdata.vge_head = m; 1474 sc->vge_cdata.vge_tail = m; 1475 } else { 1476 m->m_flags &= ~M_PKTHDR; 1477 sc->vge_cdata.vge_tail->m_next = m; 1478 sc->vge_cdata.vge_tail = m; 1479 } 1480 continue; 1481 } 1482 1483 /* 1484 * Bad/error frames will have the RXOK bit cleared. 1485 * However, there's one error case we want to allow: 1486 * if a VLAN tagged frame arrives and the chip can't 1487 * match it against the CAM filter, it considers this 1488 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1489 * We don't want to drop the frame though: our VLAN 1490 * filtering is done in software. 1491 * We also want to receive bad-checksummed frames and 1492 * and frames with bad-length. 1493 */ 1494 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1495 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1496 VGE_RDSTS_CSUMERR)) == 0) { 1497 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1498 /* 1499 * If this is part of a multi-fragment packet, 1500 * discard all the pieces. 1501 */ 1502 VGE_CHAIN_RESET(sc); 1503 vge_discard_rxbuf(sc, prod); 1504 continue; 1505 } 1506 1507 if (vge_newbuf(sc, prod) != 0) { 1508 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1509 VGE_CHAIN_RESET(sc); 1510 vge_discard_rxbuf(sc, prod); 1511 continue; 1512 } 1513 1514 /* Chain received mbufs. */ 1515 if (sc->vge_cdata.vge_head != NULL) { 1516 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1517 /* 1518 * Special case: if there's 4 bytes or less 1519 * in this buffer, the mbuf can be discarded: 1520 * the last 4 bytes is the CRC, which we don't 1521 * care about anyway. 1522 */ 1523 if (m->m_len <= ETHER_CRC_LEN) { 1524 sc->vge_cdata.vge_tail->m_len -= 1525 (ETHER_CRC_LEN - m->m_len); 1526 m_freem(m); 1527 } else { 1528 m->m_len -= ETHER_CRC_LEN; 1529 m->m_flags &= ~M_PKTHDR; 1530 sc->vge_cdata.vge_tail->m_next = m; 1531 } 1532 m = sc->vge_cdata.vge_head; 1533 m->m_flags |= M_PKTHDR; 1534 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1535 } else { 1536 m->m_flags |= M_PKTHDR; 1537 m->m_pkthdr.len = m->m_len = 1538 (total_len - ETHER_CRC_LEN); 1539 } 1540 1541 #ifndef __NO_STRICT_ALIGNMENT 1542 vge_fixup_rx(m); 1543 #endif 1544 m->m_pkthdr.rcvif = ifp; 1545 1546 /* Do RX checksumming if enabled */ 1547 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 1548 (rxctl & VGE_RDCTL_FRAG) == 0) { 1549 /* Check IP header checksum */ 1550 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1551 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1552 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1553 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1554 1555 /* Check TCP/UDP checksum */ 1556 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1557 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1558 m->m_pkthdr.csum_flags |= 1559 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1560 m->m_pkthdr.csum_data = 0xffff; 1561 } 1562 } 1563 1564 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1565 /* 1566 * The 32-bit rxctl register is stored in little-endian. 1567 * However, the 16-bit vlan tag is stored in big-endian, 1568 * so we have to byte swap it. 1569 */ 1570 m->m_pkthdr.ether_vtag = 1571 bswap16(rxctl & VGE_RDCTL_VLANID); 1572 m->m_flags |= M_VLANTAG; 1573 } 1574 1575 VGE_UNLOCK(sc); 1576 if_input(ifp, m); 1577 VGE_LOCK(sc); 1578 sc->vge_cdata.vge_head = NULL; 1579 sc->vge_cdata.vge_tail = NULL; 1580 } 1581 1582 if (prog > 0) { 1583 sc->vge_cdata.vge_rx_prodidx = prod; 1584 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1585 sc->vge_cdata.vge_rx_ring_map, 1586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1587 /* Update residue counter. */ 1588 if (sc->vge_cdata.vge_rx_commit != 0) { 1589 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1590 sc->vge_cdata.vge_rx_commit); 1591 sc->vge_cdata.vge_rx_commit = 0; 1592 } 1593 } 1594 return (prog); 1595 } 1596 1597 static void 1598 vge_txeof(struct vge_softc *sc) 1599 { 1600 if_t ifp; 1601 struct vge_tx_desc *cur_tx; 1602 struct vge_txdesc *txd; 1603 uint32_t txstat; 1604 int cons, prod; 1605 1606 VGE_LOCK_ASSERT(sc); 1607 1608 ifp = sc->vge_ifp; 1609 1610 if (sc->vge_cdata.vge_tx_cnt == 0) 1611 return; 1612 1613 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1614 sc->vge_cdata.vge_tx_ring_map, 1615 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1616 1617 /* 1618 * Go through our tx list and free mbufs for those 1619 * frames that have been transmitted. 1620 */ 1621 cons = sc->vge_cdata.vge_tx_considx; 1622 prod = sc->vge_cdata.vge_tx_prodidx; 1623 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1624 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1625 txstat = le32toh(cur_tx->vge_sts); 1626 if ((txstat & VGE_TDSTS_OWN) != 0) 1627 break; 1628 sc->vge_cdata.vge_tx_cnt--; 1629 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1630 1631 txd = &sc->vge_cdata.vge_txdesc[cons]; 1632 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1633 BUS_DMASYNC_POSTWRITE); 1634 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1635 1636 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1637 __func__)); 1638 m_freem(txd->tx_m); 1639 txd->tx_m = NULL; 1640 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1641 } 1642 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1643 sc->vge_cdata.vge_tx_ring_map, 1644 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1645 sc->vge_cdata.vge_tx_considx = cons; 1646 if (sc->vge_cdata.vge_tx_cnt == 0) 1647 sc->vge_timer = 0; 1648 } 1649 1650 static void 1651 vge_link_statchg(void *xsc) 1652 { 1653 struct vge_softc *sc; 1654 if_t ifp; 1655 uint8_t physts; 1656 1657 sc = xsc; 1658 ifp = sc->vge_ifp; 1659 VGE_LOCK_ASSERT(sc); 1660 1661 physts = CSR_READ_1(sc, VGE_PHYSTS0); 1662 if ((physts & VGE_PHYSTS_RESETSTS) == 0) { 1663 if ((physts & VGE_PHYSTS_LINK) == 0) { 1664 sc->vge_flags &= ~VGE_FLAG_LINK; 1665 if_link_state_change(sc->vge_ifp, 1666 LINK_STATE_DOWN); 1667 } else { 1668 sc->vge_flags |= VGE_FLAG_LINK; 1669 if_link_state_change(sc->vge_ifp, 1670 LINK_STATE_UP); 1671 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE | 1672 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1673 if ((physts & VGE_PHYSTS_FDX) != 0) { 1674 if ((physts & VGE_PHYSTS_TXFLOWCAP) != 0) 1675 CSR_WRITE_1(sc, VGE_CRS2, 1676 VGE_CR2_FDX_TXFLOWCTL_ENABLE); 1677 if ((physts & VGE_PHYSTS_RXFLOWCAP) != 0) 1678 CSR_WRITE_1(sc, VGE_CRS2, 1679 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1680 } 1681 if (!if_sendq_empty(ifp)) 1682 vge_start_locked(ifp); 1683 } 1684 } 1685 /* 1686 * Restart MII auto-polling because link state change interrupt 1687 * will disable it. 1688 */ 1689 vge_miipoll_start(sc); 1690 } 1691 1692 #ifdef DEVICE_POLLING 1693 static int 1694 vge_poll (if_t ifp, enum poll_cmd cmd, int count) 1695 { 1696 struct vge_softc *sc = if_getsoftc(ifp); 1697 int rx_npkts = 0; 1698 1699 VGE_LOCK(sc); 1700 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) 1701 goto done; 1702 1703 rx_npkts = vge_rxeof(sc, count); 1704 vge_txeof(sc); 1705 1706 if (!if_sendq_empty(ifp)) 1707 vge_start_locked(ifp); 1708 1709 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1710 uint32_t status; 1711 status = CSR_READ_4(sc, VGE_ISR); 1712 if (status == 0xFFFFFFFF) 1713 goto done; 1714 if (status) 1715 CSR_WRITE_4(sc, VGE_ISR, status); 1716 1717 /* 1718 * XXX check behaviour on receiver stalls. 1719 */ 1720 1721 if (status & VGE_ISR_TXDMA_STALL || 1722 status & VGE_ISR_RXDMA_STALL) { 1723 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1724 vge_init_locked(sc); 1725 } 1726 1727 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1728 vge_rxeof(sc, count); 1729 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1730 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1731 } 1732 } 1733 done: 1734 VGE_UNLOCK(sc); 1735 return (rx_npkts); 1736 } 1737 #endif /* DEVICE_POLLING */ 1738 1739 static void 1740 vge_intr(void *arg) 1741 { 1742 struct vge_softc *sc; 1743 if_t ifp; 1744 uint32_t status; 1745 1746 sc = arg; 1747 VGE_LOCK(sc); 1748 1749 ifp = sc->vge_ifp; 1750 if ((sc->vge_flags & VGE_FLAG_SUSPENDED) != 0 || 1751 (if_getflags(ifp) & IFF_UP) == 0) { 1752 VGE_UNLOCK(sc); 1753 return; 1754 } 1755 1756 #ifdef DEVICE_POLLING 1757 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1758 status = CSR_READ_4(sc, VGE_ISR); 1759 CSR_WRITE_4(sc, VGE_ISR, status); 1760 if (status != 0xFFFFFFFF && (status & VGE_ISR_LINKSTS) != 0) 1761 vge_link_statchg(sc); 1762 VGE_UNLOCK(sc); 1763 return; 1764 } 1765 #endif 1766 1767 /* Disable interrupts */ 1768 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1769 status = CSR_READ_4(sc, VGE_ISR); 1770 CSR_WRITE_4(sc, VGE_ISR, status | VGE_ISR_HOLDOFF_RELOAD); 1771 /* If the card has gone away the read returns 0xffff. */ 1772 if (status == 0xFFFFFFFF || (status & VGE_INTRS) == 0) 1773 goto done; 1774 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1775 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1776 vge_rxeof(sc, VGE_RX_DESC_CNT); 1777 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1778 vge_rxeof(sc, VGE_RX_DESC_CNT); 1779 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1780 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1781 } 1782 1783 if (status & (VGE_ISR_TXOK0|VGE_ISR_TXOK_HIPRIO)) 1784 vge_txeof(sc); 1785 1786 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1787 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1788 vge_init_locked(sc); 1789 } 1790 1791 if (status & VGE_ISR_LINKSTS) 1792 vge_link_statchg(sc); 1793 } 1794 done: 1795 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1796 /* Re-enable interrupts */ 1797 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1798 1799 if (!if_sendq_empty(ifp)) 1800 vge_start_locked(ifp); 1801 } 1802 VGE_UNLOCK(sc); 1803 } 1804 1805 static int 1806 vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1807 { 1808 struct vge_txdesc *txd; 1809 struct vge_tx_frag *frag; 1810 struct mbuf *m; 1811 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1812 int error, i, nsegs, padlen; 1813 uint32_t cflags; 1814 1815 VGE_LOCK_ASSERT(sc); 1816 1817 M_ASSERTPKTHDR((*m_head)); 1818 1819 /* Argh. This chip does not autopad short frames. */ 1820 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1821 m = *m_head; 1822 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1823 if (M_WRITABLE(m) == 0) { 1824 /* Get a writable copy. */ 1825 m = m_dup(*m_head, M_NOWAIT); 1826 m_freem(*m_head); 1827 if (m == NULL) { 1828 *m_head = NULL; 1829 return (ENOBUFS); 1830 } 1831 *m_head = m; 1832 } 1833 if (M_TRAILINGSPACE(m) < padlen) { 1834 m = m_defrag(m, M_NOWAIT); 1835 if (m == NULL) { 1836 m_freem(*m_head); 1837 *m_head = NULL; 1838 return (ENOBUFS); 1839 } 1840 } 1841 /* 1842 * Manually pad short frames, and zero the pad space 1843 * to avoid leaking data. 1844 */ 1845 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1846 m->m_pkthdr.len += padlen; 1847 m->m_len = m->m_pkthdr.len; 1848 *m_head = m; 1849 } 1850 1851 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1852 1853 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1854 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1855 if (error == EFBIG) { 1856 m = m_collapse(*m_head, M_NOWAIT, VGE_MAXTXSEGS); 1857 if (m == NULL) { 1858 m_freem(*m_head); 1859 *m_head = NULL; 1860 return (ENOMEM); 1861 } 1862 *m_head = m; 1863 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1864 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1865 if (error != 0) { 1866 m_freem(*m_head); 1867 *m_head = NULL; 1868 return (error); 1869 } 1870 } else if (error != 0) 1871 return (error); 1872 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1873 BUS_DMASYNC_PREWRITE); 1874 1875 m = *m_head; 1876 cflags = 0; 1877 1878 /* Configure checksum offload. */ 1879 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1880 cflags |= VGE_TDCTL_IPCSUM; 1881 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1882 cflags |= VGE_TDCTL_TCPCSUM; 1883 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1884 cflags |= VGE_TDCTL_UDPCSUM; 1885 1886 /* Configure VLAN. */ 1887 if ((m->m_flags & M_VLANTAG) != 0) 1888 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1889 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1890 /* 1891 * XXX 1892 * Velocity family seems to support TSO but no information 1893 * for MSS configuration is available. Also the number of 1894 * fragments supported by a descriptor is too small to hold 1895 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1896 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1897 * longer chain of buffers but no additional information is 1898 * available. 1899 * 1900 * When telling the chip how many segments there are, we 1901 * must use nsegs + 1 instead of just nsegs. Darned if I 1902 * know why. This also means we can't use the last fragment 1903 * field of Tx descriptor. 1904 */ 1905 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1906 VGE_TD_LS_NORM); 1907 for (i = 0; i < nsegs; i++) { 1908 frag = &txd->tx_desc->vge_frag[i]; 1909 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1910 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1911 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1912 } 1913 1914 sc->vge_cdata.vge_tx_cnt++; 1915 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1916 1917 /* 1918 * Finally request interrupt and give the first descriptor 1919 * ownership to hardware. 1920 */ 1921 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1922 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1923 txd->tx_m = m; 1924 1925 return (0); 1926 } 1927 1928 /* 1929 * Main transmit routine. 1930 */ 1931 1932 static void 1933 vge_start(if_t ifp) 1934 { 1935 struct vge_softc *sc; 1936 1937 sc = if_getsoftc(ifp); 1938 VGE_LOCK(sc); 1939 vge_start_locked(ifp); 1940 VGE_UNLOCK(sc); 1941 } 1942 1943 static void 1944 vge_start_locked(if_t ifp) 1945 { 1946 struct vge_softc *sc; 1947 struct vge_txdesc *txd; 1948 struct mbuf *m_head; 1949 int enq, idx; 1950 1951 sc = if_getsoftc(ifp); 1952 1953 VGE_LOCK_ASSERT(sc); 1954 1955 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1956 (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1957 IFF_DRV_RUNNING) 1958 return; 1959 1960 idx = sc->vge_cdata.vge_tx_prodidx; 1961 VGE_TX_DESC_DEC(idx); 1962 for (enq = 0; !if_sendq_empty(ifp) && 1963 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1964 m_head = if_dequeue(ifp); 1965 if (m_head == NULL) 1966 break; 1967 /* 1968 * Pack the data into the transmit ring. If we 1969 * don't have room, set the OACTIVE flag and wait 1970 * for the NIC to drain the ring. 1971 */ 1972 if (vge_encap(sc, &m_head)) { 1973 if (m_head == NULL) 1974 break; 1975 if_sendq_prepend(ifp, m_head); 1976 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1977 break; 1978 } 1979 1980 txd = &sc->vge_cdata.vge_txdesc[idx]; 1981 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1982 VGE_TX_DESC_INC(idx); 1983 1984 enq++; 1985 /* 1986 * If there's a BPF listener, bounce a copy of this frame 1987 * to him. 1988 */ 1989 ETHER_BPF_MTAP(ifp, m_head); 1990 } 1991 1992 if (enq > 0) { 1993 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1994 sc->vge_cdata.vge_tx_ring_map, 1995 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1996 /* Issue a transmit command. */ 1997 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1998 /* 1999 * Set a timeout in case the chip goes out to lunch. 2000 */ 2001 sc->vge_timer = 5; 2002 } 2003 } 2004 2005 static void 2006 vge_init(void *xsc) 2007 { 2008 struct vge_softc *sc = xsc; 2009 2010 VGE_LOCK(sc); 2011 vge_init_locked(sc); 2012 VGE_UNLOCK(sc); 2013 } 2014 2015 static void 2016 vge_init_locked(struct vge_softc *sc) 2017 { 2018 if_t ifp = sc->vge_ifp; 2019 int error, i; 2020 2021 VGE_LOCK_ASSERT(sc); 2022 2023 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2024 return; 2025 2026 /* 2027 * Cancel pending I/O and free all RX/TX buffers. 2028 */ 2029 vge_stop(sc); 2030 vge_reset(sc); 2031 vge_miipoll_start(sc); 2032 2033 /* 2034 * Initialize the RX and TX descriptors and mbufs. 2035 */ 2036 2037 error = vge_rx_list_init(sc); 2038 if (error != 0) { 2039 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2040 return; 2041 } 2042 vge_tx_list_init(sc); 2043 /* Clear MAC statistics. */ 2044 vge_stats_clear(sc); 2045 /* Set our station address */ 2046 for (i = 0; i < ETHER_ADDR_LEN; i++) 2047 CSR_WRITE_1(sc, VGE_PAR0 + i, if_getlladdr(sc->vge_ifp)[i]); 2048 2049 /* 2050 * Set receive FIFO threshold. Also allow transmission and 2051 * reception of VLAN tagged frames. 2052 */ 2053 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2054 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 2055 2056 /* Set DMA burst length */ 2057 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2058 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2059 2060 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2061 2062 /* Set collision backoff algorithm */ 2063 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2064 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2065 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2066 2067 /* Disable LPSEL field in priority resolution */ 2068 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2069 2070 /* 2071 * Load the addresses of the DMA queues into the chip. 2072 * Note that we only use one transmit queue. 2073 */ 2074 2075 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2076 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2077 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2078 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2079 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2080 2081 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2082 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2083 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2084 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2085 2086 /* Configure interrupt moderation. */ 2087 vge_intr_holdoff(sc); 2088 2089 /* Enable and wake up the RX descriptor queue */ 2090 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2091 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2092 2093 /* Enable the TX descriptor queue */ 2094 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2095 2096 /* Init the cam filter. */ 2097 vge_cam_clear(sc); 2098 2099 /* Set up receiver filter. */ 2100 vge_rxfilter(sc); 2101 vge_setvlan(sc); 2102 2103 /* Initialize pause timer. */ 2104 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); 2105 /* 2106 * Initialize flow control parameters. 2107 * TX XON high threshold : 48 2108 * TX pause low threshold : 24 2109 * Disable hald-duplex flow control 2110 */ 2111 CSR_WRITE_1(sc, VGE_CRC2, 0xFF); 2112 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B); 2113 2114 /* Enable jumbo frame reception (if desired) */ 2115 2116 /* Start the MAC. */ 2117 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2118 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2119 CSR_WRITE_1(sc, VGE_CRS0, 2120 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2121 2122 #ifdef DEVICE_POLLING 2123 /* 2124 * Disable interrupts except link state change if we are polling. 2125 */ 2126 if (if_getcapenable(ifp) & IFCAP_POLLING) { 2127 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2128 } else /* otherwise ... */ 2129 #endif 2130 { 2131 /* 2132 * Enable interrupts. 2133 */ 2134 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2135 } 2136 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2137 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2138 2139 sc->vge_flags &= ~VGE_FLAG_LINK; 2140 vge_ifmedia_upd_locked(sc); 2141 2142 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2143 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2144 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2145 } 2146 2147 /* 2148 * Set media options. 2149 */ 2150 static int 2151 vge_ifmedia_upd(if_t ifp) 2152 { 2153 struct vge_softc *sc; 2154 int error; 2155 2156 sc = if_getsoftc(ifp); 2157 VGE_LOCK(sc); 2158 error = vge_ifmedia_upd_locked(sc); 2159 VGE_UNLOCK(sc); 2160 2161 return (error); 2162 } 2163 2164 static int 2165 vge_ifmedia_upd_locked(struct vge_softc *sc) 2166 { 2167 struct mii_data *mii; 2168 struct mii_softc *miisc; 2169 int error; 2170 2171 mii = device_get_softc(sc->vge_miibus); 2172 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2173 PHY_RESET(miisc); 2174 vge_setmedia(sc); 2175 error = mii_mediachg(mii); 2176 2177 return (error); 2178 } 2179 2180 /* 2181 * Report current media status. 2182 */ 2183 static void 2184 vge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2185 { 2186 struct vge_softc *sc; 2187 struct mii_data *mii; 2188 2189 sc = if_getsoftc(ifp); 2190 mii = device_get_softc(sc->vge_miibus); 2191 2192 VGE_LOCK(sc); 2193 if ((if_getflags(ifp) & IFF_UP) == 0) { 2194 VGE_UNLOCK(sc); 2195 return; 2196 } 2197 mii_pollstat(mii); 2198 ifmr->ifm_active = mii->mii_media_active; 2199 ifmr->ifm_status = mii->mii_media_status; 2200 VGE_UNLOCK(sc); 2201 } 2202 2203 static void 2204 vge_setmedia(struct vge_softc *sc) 2205 { 2206 struct mii_data *mii; 2207 struct ifmedia_entry *ife; 2208 2209 mii = device_get_softc(sc->vge_miibus); 2210 ife = mii->mii_media.ifm_cur; 2211 2212 /* 2213 * If the user manually selects a media mode, we need to turn 2214 * on the forced MAC mode bit in the DIAGCTL register. If the 2215 * user happens to choose a full duplex mode, we also need to 2216 * set the 'force full duplex' bit. This applies only to 2217 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2218 * mode is disabled, and in 1000baseT mode, full duplex is 2219 * always implied, so we turn on the forced mode bit but leave 2220 * the FDX bit cleared. 2221 */ 2222 2223 switch (IFM_SUBTYPE(ife->ifm_media)) { 2224 case IFM_AUTO: 2225 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2226 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2227 break; 2228 case IFM_1000_T: 2229 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2230 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2231 break; 2232 case IFM_100_TX: 2233 case IFM_10_T: 2234 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2235 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2236 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2237 } else { 2238 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2239 } 2240 break; 2241 default: 2242 device_printf(sc->vge_dev, "unknown media type: %x\n", 2243 IFM_SUBTYPE(ife->ifm_media)); 2244 break; 2245 } 2246 } 2247 2248 static int 2249 vge_ioctl(if_t ifp, u_long command, caddr_t data) 2250 { 2251 struct vge_softc *sc = if_getsoftc(ifp); 2252 struct ifreq *ifr = (struct ifreq *) data; 2253 struct mii_data *mii; 2254 int error = 0, mask; 2255 2256 switch (command) { 2257 case SIOCSIFMTU: 2258 VGE_LOCK(sc); 2259 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > VGE_JUMBO_MTU) 2260 error = EINVAL; 2261 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 2262 if (ifr->ifr_mtu > ETHERMTU && 2263 (sc->vge_flags & VGE_FLAG_JUMBO) == 0) 2264 error = EINVAL; 2265 else 2266 if_setmtu(ifp, ifr->ifr_mtu); 2267 } 2268 VGE_UNLOCK(sc); 2269 break; 2270 case SIOCSIFFLAGS: 2271 VGE_LOCK(sc); 2272 if ((if_getflags(ifp) & IFF_UP) != 0) { 2273 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2274 ((if_getflags(ifp) ^ sc->vge_if_flags) & 2275 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2276 vge_rxfilter(sc); 2277 else 2278 vge_init_locked(sc); 2279 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2280 vge_stop(sc); 2281 sc->vge_if_flags = if_getflags(ifp); 2282 VGE_UNLOCK(sc); 2283 break; 2284 case SIOCADDMULTI: 2285 case SIOCDELMULTI: 2286 VGE_LOCK(sc); 2287 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2288 vge_rxfilter(sc); 2289 VGE_UNLOCK(sc); 2290 break; 2291 case SIOCGIFMEDIA: 2292 case SIOCSIFMEDIA: 2293 mii = device_get_softc(sc->vge_miibus); 2294 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2295 break; 2296 case SIOCSIFCAP: 2297 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2298 #ifdef DEVICE_POLLING 2299 if (mask & IFCAP_POLLING) { 2300 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2301 error = ether_poll_register(vge_poll, ifp); 2302 if (error) 2303 return (error); 2304 VGE_LOCK(sc); 2305 /* Disable interrupts */ 2306 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS_POLLING); 2307 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2308 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2309 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 2310 VGE_UNLOCK(sc); 2311 } else { 2312 error = ether_poll_deregister(ifp); 2313 /* Enable interrupts. */ 2314 VGE_LOCK(sc); 2315 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2316 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2317 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2318 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 2319 VGE_UNLOCK(sc); 2320 } 2321 } 2322 #endif /* DEVICE_POLLING */ 2323 VGE_LOCK(sc); 2324 if ((mask & IFCAP_TXCSUM) != 0 && 2325 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2326 if_togglecapenable(ifp, IFCAP_TXCSUM); 2327 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2328 if_sethwassistbits(ifp, VGE_CSUM_FEATURES, 0); 2329 else 2330 if_sethwassistbits(ifp, 0, VGE_CSUM_FEATURES); 2331 } 2332 if ((mask & IFCAP_RXCSUM) != 0 && 2333 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2334 if_togglecapenable(ifp, IFCAP_RXCSUM); 2335 if ((mask & IFCAP_WOL_UCAST) != 0 && 2336 (if_getcapabilities(ifp) & IFCAP_WOL_UCAST) != 0) 2337 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2338 if ((mask & IFCAP_WOL_MCAST) != 0 && 2339 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2340 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2341 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2342 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2343 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2344 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2345 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2346 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2347 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2348 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 2349 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2350 vge_setvlan(sc); 2351 } 2352 VGE_UNLOCK(sc); 2353 VLAN_CAPABILITIES(ifp); 2354 break; 2355 default: 2356 error = ether_ioctl(ifp, command, data); 2357 break; 2358 } 2359 2360 return (error); 2361 } 2362 2363 static void 2364 vge_watchdog(void *arg) 2365 { 2366 struct vge_softc *sc; 2367 if_t ifp; 2368 2369 sc = arg; 2370 VGE_LOCK_ASSERT(sc); 2371 vge_stats_update(sc); 2372 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2373 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2374 return; 2375 2376 ifp = sc->vge_ifp; 2377 if_printf(ifp, "watchdog timeout\n"); 2378 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2379 2380 vge_txeof(sc); 2381 vge_rxeof(sc, VGE_RX_DESC_CNT); 2382 2383 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2384 vge_init_locked(sc); 2385 } 2386 2387 /* 2388 * Stop the adapter and free any mbufs allocated to the 2389 * RX and TX lists. 2390 */ 2391 static void 2392 vge_stop(struct vge_softc *sc) 2393 { 2394 if_t ifp; 2395 2396 VGE_LOCK_ASSERT(sc); 2397 ifp = sc->vge_ifp; 2398 sc->vge_timer = 0; 2399 callout_stop(&sc->vge_watchdog); 2400 2401 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2402 2403 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2404 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2405 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2406 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2407 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2408 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2409 2410 vge_stats_update(sc); 2411 VGE_CHAIN_RESET(sc); 2412 vge_txeof(sc); 2413 vge_freebufs(sc); 2414 } 2415 2416 /* 2417 * Device suspend routine. Stop the interface and save some PCI 2418 * settings in case the BIOS doesn't restore them properly on 2419 * resume. 2420 */ 2421 static int 2422 vge_suspend(device_t dev) 2423 { 2424 struct vge_softc *sc; 2425 2426 sc = device_get_softc(dev); 2427 2428 VGE_LOCK(sc); 2429 vge_stop(sc); 2430 vge_setwol(sc); 2431 sc->vge_flags |= VGE_FLAG_SUSPENDED; 2432 VGE_UNLOCK(sc); 2433 2434 return (0); 2435 } 2436 2437 /* 2438 * Device resume routine. Restore some PCI settings in case the BIOS 2439 * doesn't, re-enable busmastering, and restart the interface if 2440 * appropriate. 2441 */ 2442 static int 2443 vge_resume(device_t dev) 2444 { 2445 struct vge_softc *sc; 2446 if_t ifp; 2447 uint16_t pmstat; 2448 2449 sc = device_get_softc(dev); 2450 VGE_LOCK(sc); 2451 if ((sc->vge_flags & VGE_FLAG_PMCAP) != 0) { 2452 /* Disable PME and clear PME status. */ 2453 pmstat = pci_read_config(sc->vge_dev, 2454 sc->vge_pmcap + PCIR_POWER_STATUS, 2); 2455 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2456 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2457 pci_write_config(sc->vge_dev, 2458 sc->vge_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2459 } 2460 } 2461 vge_clrwol(sc); 2462 /* Restart MII auto-polling. */ 2463 vge_miipoll_start(sc); 2464 ifp = sc->vge_ifp; 2465 /* Reinitialize interface if necessary. */ 2466 if ((if_getflags(ifp) & IFF_UP) != 0) { 2467 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2468 vge_init_locked(sc); 2469 } 2470 sc->vge_flags &= ~VGE_FLAG_SUSPENDED; 2471 VGE_UNLOCK(sc); 2472 2473 return (0); 2474 } 2475 2476 /* 2477 * Stop all chip I/O so that the kernel's probe routines don't 2478 * get confused by errant DMAs when rebooting. 2479 */ 2480 static int 2481 vge_shutdown(device_t dev) 2482 { 2483 2484 return (vge_suspend(dev)); 2485 } 2486 2487 #define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2488 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2489 2490 static void 2491 vge_sysctl_node(struct vge_softc *sc) 2492 { 2493 struct sysctl_ctx_list *ctx; 2494 struct sysctl_oid_list *child, *parent; 2495 struct sysctl_oid *tree; 2496 struct vge_hw_stats *stats; 2497 2498 stats = &sc->vge_stats; 2499 ctx = device_get_sysctl_ctx(sc->vge_dev); 2500 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); 2501 2502 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "int_holdoff", 2503 CTLFLAG_RW, &sc->vge_int_holdoff, 0, "interrupt holdoff"); 2504 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rx_coal_pkt", 2505 CTLFLAG_RW, &sc->vge_rx_coal_pkt, 0, "rx coalescing packet"); 2506 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "tx_coal_pkt", 2507 CTLFLAG_RW, &sc->vge_tx_coal_pkt, 0, "tx coalescing packet"); 2508 2509 /* Pull in device tunables. */ 2510 sc->vge_int_holdoff = VGE_INT_HOLDOFF_DEFAULT; 2511 resource_int_value(device_get_name(sc->vge_dev), 2512 device_get_unit(sc->vge_dev), "int_holdoff", &sc->vge_int_holdoff); 2513 sc->vge_rx_coal_pkt = VGE_RX_COAL_PKT_DEFAULT; 2514 resource_int_value(device_get_name(sc->vge_dev), 2515 device_get_unit(sc->vge_dev), "rx_coal_pkt", &sc->vge_rx_coal_pkt); 2516 sc->vge_tx_coal_pkt = VGE_TX_COAL_PKT_DEFAULT; 2517 resource_int_value(device_get_name(sc->vge_dev), 2518 device_get_unit(sc->vge_dev), "tx_coal_pkt", &sc->vge_tx_coal_pkt); 2519 2520 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2521 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "VGE statistics"); 2522 parent = SYSCTL_CHILDREN(tree); 2523 2524 /* Rx statistics. */ 2525 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2526 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "RX MAC statistics"); 2527 child = SYSCTL_CHILDREN(tree); 2528 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", 2529 &stats->rx_frames, "frames"); 2530 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2531 &stats->rx_good_frames, "Good frames"); 2532 VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2533 &stats->rx_fifo_oflows, "FIFO overflows"); 2534 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", 2535 &stats->rx_runts, "Too short frames"); 2536 VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", 2537 &stats->rx_runts_errs, "Too short frames with errors"); 2538 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2539 &stats->rx_pkts_64, "64 bytes frames"); 2540 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2541 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 2542 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2543 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 2544 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2545 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 2546 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2547 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 2548 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2549 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2550 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 2551 &stats->rx_pkts_1519_max, "1519 to max frames"); 2552 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", 2553 &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); 2554 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2555 &stats->rx_jumbos, "Jumbo frames"); 2556 VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", 2557 &stats->rx_crcerrs, "CRC errors"); 2558 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2559 &stats->rx_pause_frames, "Pause frames"); 2560 VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2561 &stats->rx_alignerrs, "Alignment errors"); 2562 VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", 2563 &stats->rx_nobufs, "Frames with no buffer event"); 2564 VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2565 &stats->rx_symerrs, "Frames with symbol errors"); 2566 VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2567 &stats->rx_lenerrs, "Frames with length mismatched"); 2568 2569 /* Tx statistics. */ 2570 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2571 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "TX MAC statistics"); 2572 child = SYSCTL_CHILDREN(tree); 2573 VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 2574 &stats->tx_good_frames, "Good frames"); 2575 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 2576 &stats->tx_pkts_64, "64 bytes frames"); 2577 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 2578 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 2579 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 2580 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 2581 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 2582 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 2583 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 2584 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 2585 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 2586 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 2587 VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 2588 &stats->tx_jumbos, "Jumbo frames"); 2589 VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", 2590 &stats->tx_colls, "Collisions"); 2591 VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 2592 &stats->tx_latecolls, "Late collisions"); 2593 VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 2594 &stats->tx_pause, "Pause frames"); 2595 #ifdef VGE_ENABLE_SQEERR 2596 VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", 2597 &stats->tx_sqeerrs, "SQE errors"); 2598 #endif 2599 /* Clear MAC statistics. */ 2600 vge_stats_clear(sc); 2601 } 2602 2603 #undef VGE_SYSCTL_STAT_ADD32 2604 2605 static void 2606 vge_stats_clear(struct vge_softc *sc) 2607 { 2608 int i; 2609 2610 CSR_WRITE_1(sc, VGE_MIBCSR, 2611 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); 2612 CSR_WRITE_1(sc, VGE_MIBCSR, 2613 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); 2614 for (i = VGE_TIMEOUT; i > 0; i--) { 2615 DELAY(1); 2616 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) 2617 break; 2618 } 2619 if (i == 0) 2620 device_printf(sc->vge_dev, "MIB clear timed out!\n"); 2621 CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & 2622 ~VGE_MIBCSR_FREEZE); 2623 } 2624 2625 static void 2626 vge_stats_update(struct vge_softc *sc) 2627 { 2628 struct vge_hw_stats *stats; 2629 if_t ifp; 2630 uint32_t mib[VGE_MIB_CNT], val; 2631 int i; 2632 2633 VGE_LOCK_ASSERT(sc); 2634 2635 stats = &sc->vge_stats; 2636 ifp = sc->vge_ifp; 2637 2638 CSR_WRITE_1(sc, VGE_MIBCSR, 2639 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); 2640 for (i = VGE_TIMEOUT; i > 0; i--) { 2641 DELAY(1); 2642 if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) 2643 break; 2644 } 2645 if (i == 0) { 2646 device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); 2647 vge_stats_clear(sc); 2648 return; 2649 } 2650 2651 bzero(mib, sizeof(mib)); 2652 reset_idx: 2653 /* Set MIB read index to 0. */ 2654 CSR_WRITE_1(sc, VGE_MIBCSR, 2655 CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); 2656 for (i = 0; i < VGE_MIB_CNT; i++) { 2657 val = CSR_READ_4(sc, VGE_MIBDATA); 2658 if (i != VGE_MIB_DATA_IDX(val)) { 2659 /* Reading interrupted. */ 2660 goto reset_idx; 2661 } 2662 mib[i] = val & VGE_MIB_DATA_MASK; 2663 } 2664 2665 /* Rx stats. */ 2666 stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; 2667 stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; 2668 stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; 2669 stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; 2670 stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; 2671 stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; 2672 stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; 2673 stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; 2674 stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; 2675 stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; 2676 stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; 2677 stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; 2678 stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; 2679 stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; 2680 stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; 2681 stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; 2682 stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; 2683 stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; 2684 stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; 2685 stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; 2686 2687 /* Tx stats. */ 2688 stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; 2689 stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; 2690 stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; 2691 stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; 2692 stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; 2693 stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; 2694 stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; 2695 stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; 2696 stats->tx_colls += mib[VGE_MIB_TX_COLLS]; 2697 stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; 2698 #ifdef VGE_ENABLE_SQEERR 2699 stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; 2700 #endif 2701 stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; 2702 2703 /* Update counters in ifnet. */ 2704 if_inc_counter(ifp, IFCOUNTER_OPACKETS, mib[VGE_MIB_TX_GOOD_FRAMES]); 2705 2706 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 2707 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]); 2708 2709 if_inc_counter(ifp, IFCOUNTER_OERRORS, 2710 mib[VGE_MIB_TX_COLLS] + mib[VGE_MIB_TX_LATECOLLS]); 2711 2712 if_inc_counter(ifp, IFCOUNTER_IPACKETS, mib[VGE_MIB_RX_GOOD_FRAMES]); 2713 2714 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2715 mib[VGE_MIB_RX_FIFO_OVERRUNS] + 2716 mib[VGE_MIB_RX_RUNTS] + 2717 mib[VGE_MIB_RX_RUNTS_ERRS] + 2718 mib[VGE_MIB_RX_CRCERRS] + 2719 mib[VGE_MIB_RX_ALIGNERRS] + 2720 mib[VGE_MIB_RX_NOBUFS] + 2721 mib[VGE_MIB_RX_SYMERRS] + 2722 mib[VGE_MIB_RX_LENERRS]); 2723 } 2724 2725 static void 2726 vge_intr_holdoff(struct vge_softc *sc) 2727 { 2728 uint8_t intctl; 2729 2730 VGE_LOCK_ASSERT(sc); 2731 2732 /* 2733 * Set Tx interrupt supression threshold. 2734 * It's possible to use single-shot timer in VGE_CRS1 register 2735 * in Tx path such that driver can remove most of Tx completion 2736 * interrupts. However this requires additional access to 2737 * VGE_CRS1 register to reload the timer in addintion to 2738 * activating Tx kick command. Another downside is we don't know 2739 * what single-shot timer value should be used in advance so 2740 * reclaiming transmitted mbufs could be delayed a lot which in 2741 * turn slows down Tx operation. 2742 */ 2743 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_TXSUPPTHR); 2744 CSR_WRITE_1(sc, VGE_TXSUPPTHR, sc->vge_tx_coal_pkt); 2745 2746 /* Set Rx interrupt suppresion threshold. */ 2747 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2748 CSR_WRITE_1(sc, VGE_RXSUPPTHR, sc->vge_rx_coal_pkt); 2749 2750 intctl = CSR_READ_1(sc, VGE_INTCTL1); 2751 intctl &= ~VGE_INTCTL_SC_RELOAD; 2752 intctl |= VGE_INTCTL_HC_RELOAD; 2753 if (sc->vge_tx_coal_pkt <= 0) 2754 intctl |= VGE_INTCTL_TXINTSUP_DISABLE; 2755 else 2756 intctl &= ~VGE_INTCTL_TXINTSUP_DISABLE; 2757 if (sc->vge_rx_coal_pkt <= 0) 2758 intctl |= VGE_INTCTL_RXINTSUP_DISABLE; 2759 else 2760 intctl &= ~VGE_INTCTL_RXINTSUP_DISABLE; 2761 CSR_WRITE_1(sc, VGE_INTCTL1, intctl); 2762 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_HOLDOFF); 2763 if (sc->vge_int_holdoff > 0) { 2764 /* Set interrupt holdoff timer. */ 2765 CSR_WRITE_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2766 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 2767 VGE_INT_HOLDOFF_USEC(sc->vge_int_holdoff)); 2768 /* Enable holdoff timer. */ 2769 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2770 } 2771 } 2772 2773 static void 2774 vge_setlinkspeed(struct vge_softc *sc) 2775 { 2776 struct mii_data *mii; 2777 int aneg, i; 2778 2779 VGE_LOCK_ASSERT(sc); 2780 2781 mii = device_get_softc(sc->vge_miibus); 2782 mii_pollstat(mii); 2783 aneg = 0; 2784 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2785 (IFM_ACTIVE | IFM_AVALID)) { 2786 switch IFM_SUBTYPE(mii->mii_media_active) { 2787 case IFM_10_T: 2788 case IFM_100_TX: 2789 return; 2790 case IFM_1000_T: 2791 aneg++; 2792 default: 2793 break; 2794 } 2795 } 2796 /* Clear forced MAC speed/duplex configuration. */ 2797 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2798 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2799 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_100T2CR, 0); 2800 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_ANAR, 2801 ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2802 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2803 BMCR_AUTOEN | BMCR_STARTNEG); 2804 DELAY(1000); 2805 if (aneg != 0) { 2806 /* Poll link state until vge(4) get a 10/100 link. */ 2807 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2808 mii_pollstat(mii); 2809 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2810 == (IFM_ACTIVE | IFM_AVALID)) { 2811 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2812 case IFM_10_T: 2813 case IFM_100_TX: 2814 return; 2815 default: 2816 break; 2817 } 2818 } 2819 VGE_UNLOCK(sc); 2820 pause("vgelnk", hz); 2821 VGE_LOCK(sc); 2822 } 2823 if (i == MII_ANEGTICKS_GIGE) 2824 device_printf(sc->vge_dev, "establishing link failed, " 2825 "WOL may not work!"); 2826 } 2827 /* 2828 * No link, force MAC to have 100Mbps, full-duplex link. 2829 * This is the last resort and may/may not work. 2830 */ 2831 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2832 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2833 } 2834 2835 static void 2836 vge_setwol(struct vge_softc *sc) 2837 { 2838 if_t ifp; 2839 uint16_t pmstat; 2840 uint8_t val; 2841 2842 VGE_LOCK_ASSERT(sc); 2843 2844 if ((sc->vge_flags & VGE_FLAG_PMCAP) == 0) { 2845 /* No PME capability, PHY power down. */ 2846 vge_miibus_writereg(sc->vge_dev, sc->vge_phyaddr, MII_BMCR, 2847 BMCR_PDOWN); 2848 vge_miipoll_stop(sc); 2849 return; 2850 } 2851 2852 ifp = sc->vge_ifp; 2853 2854 /* Clear WOL on pattern match. */ 2855 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2856 /* Disable WOL on magic/unicast packet. */ 2857 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2858 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2859 VGE_WOLCFG_PMEOVR); 2860 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 2861 vge_setlinkspeed(sc); 2862 val = 0; 2863 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2864 val |= VGE_WOLCR1_UCAST; 2865 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2866 val |= VGE_WOLCR1_MAGIC; 2867 CSR_WRITE_1(sc, VGE_WOLCR1S, val); 2868 val = 0; 2869 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2870 val |= VGE_WOLCFG_SAM | VGE_WOLCFG_SAB; 2871 CSR_WRITE_1(sc, VGE_WOLCFGS, val | VGE_WOLCFG_PMEOVR); 2872 /* Disable MII auto-polling. */ 2873 vge_miipoll_stop(sc); 2874 } 2875 CSR_SETBIT_1(sc, VGE_DIAGCTL, 2876 VGE_DIAGCTL_MACFORCE | VGE_DIAGCTL_FDXFORCE); 2877 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2878 2879 /* Clear WOL status on pattern match. */ 2880 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2881 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2882 2883 val = CSR_READ_1(sc, VGE_PWRSTAT); 2884 val |= VGE_STICKHW_SWPTAG; 2885 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2886 /* Put hardware into sleep. */ 2887 val = CSR_READ_1(sc, VGE_PWRSTAT); 2888 val |= VGE_STICKHW_DS0 | VGE_STICKHW_DS1; 2889 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2890 /* Request PME if WOL is requested. */ 2891 pmstat = pci_read_config(sc->vge_dev, sc->vge_pmcap + 2892 PCIR_POWER_STATUS, 2); 2893 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2894 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2895 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2896 pci_write_config(sc->vge_dev, sc->vge_pmcap + PCIR_POWER_STATUS, 2897 pmstat, 2); 2898 } 2899 2900 static void 2901 vge_clrwol(struct vge_softc *sc) 2902 { 2903 uint8_t val; 2904 2905 val = CSR_READ_1(sc, VGE_PWRSTAT); 2906 val &= ~VGE_STICKHW_SWPTAG; 2907 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2908 /* Disable WOL and clear power state indicator. */ 2909 val = CSR_READ_1(sc, VGE_PWRSTAT); 2910 val &= ~(VGE_STICKHW_DS0 | VGE_STICKHW_DS1); 2911 CSR_WRITE_1(sc, VGE_PWRSTAT, val); 2912 2913 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_GMII); 2914 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2915 2916 /* Clear WOL on pattern match. */ 2917 CSR_WRITE_1(sc, VGE_WOLCR0C, VGE_WOLCR0_PATTERN_ALL); 2918 /* Disable WOL on magic/unicast packet. */ 2919 CSR_WRITE_1(sc, VGE_WOLCR1C, 0x0F); 2920 CSR_WRITE_1(sc, VGE_WOLCFGC, VGE_WOLCFG_SAB | VGE_WOLCFG_SAM | 2921 VGE_WOLCFG_PMEOVR); 2922 /* Clear WOL status on pattern match. */ 2923 CSR_WRITE_1(sc, VGE_WOLSR0C, 0xFF); 2924 CSR_WRITE_1(sc, VGE_WOLSR1C, 0xFF); 2925 } 2926