1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/endian.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/module.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 #include <sys/taskqueue.h> 93 94 #include <net/if.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_types.h> 100 #include <net/if_vlan_var.h> 101 102 #include <net/bpf.h> 103 104 #include <machine/bus.h> 105 #include <machine/resource.h> 106 #include <sys/bus.h> 107 #include <sys/rman.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pci/pcireg.h> 113 #include <dev/pci/pcivar.h> 114 115 MODULE_DEPEND(vge, pci, 1, 1, 1); 116 MODULE_DEPEND(vge, ether, 1, 1, 1); 117 MODULE_DEPEND(vge, miibus, 1, 1, 1); 118 119 /* "controller miibus0" required. See GENERIC if you get errors here. */ 120 #include "miibus_if.h" 121 122 #include <dev/vge/if_vgereg.h> 123 #include <dev/vge/if_vgevar.h> 124 125 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 126 127 /* 128 * Various supported device vendors/types and their names. 129 */ 130 static struct vge_type vge_devs[] = { 131 { VIA_VENDORID, VIA_DEVICEID_61XX, 132 "VIA Networking Gigabit Ethernet" }, 133 { 0, 0, NULL } 134 }; 135 136 static int vge_probe (device_t); 137 static int vge_attach (device_t); 138 static int vge_detach (device_t); 139 140 static int vge_encap (struct vge_softc *, struct mbuf *, int); 141 142 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 143 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 144 bus_size_t, int); 145 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 146 bus_size_t, int); 147 static int vge_allocmem (device_t, struct vge_softc *); 148 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 149 static int vge_rx_list_init (struct vge_softc *); 150 static int vge_tx_list_init (struct vge_softc *); 151 #ifdef VGE_FIXUP_RX 152 static __inline void vge_fixup_rx 153 (struct mbuf *); 154 #endif 155 static void vge_rxeof (struct vge_softc *); 156 static void vge_txeof (struct vge_softc *); 157 static void vge_intr (void *); 158 static void vge_tick (void *); 159 static void vge_tx_task (void *, int); 160 static void vge_start (struct ifnet *); 161 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 162 static void vge_init (void *); 163 static void vge_stop (struct vge_softc *); 164 static void vge_watchdog (struct ifnet *); 165 static int vge_suspend (device_t); 166 static int vge_resume (device_t); 167 static void vge_shutdown (device_t); 168 static int vge_ifmedia_upd (struct ifnet *); 169 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 170 171 #ifdef VGE_EEPROM 172 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173 #endif 174 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 175 176 static void vge_miipoll_start (struct vge_softc *); 177 static void vge_miipoll_stop (struct vge_softc *); 178 static int vge_miibus_readreg (device_t, int, int); 179 static int vge_miibus_writereg (device_t, int, int, int); 180 static void vge_miibus_statchg (device_t); 181 182 static void vge_cam_clear (struct vge_softc *); 183 static int vge_cam_set (struct vge_softc *, uint8_t *); 184 #if __FreeBSD_version < 502113 185 static uint32_t vge_mchash (uint8_t *); 186 #endif 187 static void vge_setmulti (struct vge_softc *); 188 static void vge_reset (struct vge_softc *); 189 190 #define VGE_PCI_LOIO 0x10 191 #define VGE_PCI_LOMEM 0x14 192 193 static device_method_t vge_methods[] = { 194 /* Device interface */ 195 DEVMETHOD(device_probe, vge_probe), 196 DEVMETHOD(device_attach, vge_attach), 197 DEVMETHOD(device_detach, vge_detach), 198 DEVMETHOD(device_suspend, vge_suspend), 199 DEVMETHOD(device_resume, vge_resume), 200 DEVMETHOD(device_shutdown, vge_shutdown), 201 202 /* bus interface */ 203 DEVMETHOD(bus_print_child, bus_generic_print_child), 204 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 205 206 /* MII interface */ 207 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 208 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 209 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 210 211 { 0, 0 } 212 }; 213 214 static driver_t vge_driver = { 215 "vge", 216 vge_methods, 217 sizeof(struct vge_softc) 218 }; 219 220 static devclass_t vge_devclass; 221 222 DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 223 DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 224 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226 #ifdef VGE_EEPROM 227 /* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230 static void 231 vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235 { 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275 } 276 #endif 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 #ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301 #else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304 #endif 305 } 306 307 static void 308 vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310 { 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325 } 326 327 static void 328 vge_miipoll_start(sc) 329 struct vge_softc *sc; 330 { 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365 } 366 367 static int 368 vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371 { 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406 } 407 408 static int 409 vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412 { 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449 } 450 451 static void 452 vge_cam_clear(sc) 453 struct vge_softc *sc; 454 { 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482 } 483 484 static int 485 vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488 { 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531 fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538 } 539 540 #if __FreeBSD_version < 502113 541 static uint32_t 542 vge_mchash(addr) 543 uint8_t *addr; 544 { 545 uint32_t crc, carry; 546 int idx, bit; 547 uint8_t data; 548 549 /* Compute CRC for the address value. */ 550 crc = 0xFFFFFFFF; /* initial value */ 551 552 for (idx = 0; idx < 6; idx++) { 553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 555 crc <<= 1; 556 if (carry) 557 crc = (crc ^ 0x04c11db6) | carry; 558 } 559 } 560 561 return(crc); 562 } 563 #endif 564 565 /* 566 * Program the multicast filter. We use the 64-entry CAM filter 567 * for perfect filtering. If there's more than 64 multicast addresses, 568 * we use the hash filter insted. 569 */ 570 static void 571 vge_setmulti(sc) 572 struct vge_softc *sc; 573 { 574 struct ifnet *ifp; 575 int error = 0/*, h = 0*/; 576 struct ifmultiaddr *ifma; 577 u_int32_t h, hashes[2] = { 0, 0 }; 578 579 ifp = sc->vge_ifp; 580 581 /* First, zot all the multicast entries. */ 582 vge_cam_clear(sc); 583 CSR_WRITE_4(sc, VGE_MAR0, 0); 584 CSR_WRITE_4(sc, VGE_MAR1, 0); 585 586 /* 587 * If the user wants allmulti or promisc mode, enable reception 588 * of all multicast frames. 589 */ 590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 593 return; 594 } 595 596 /* Now program new ones */ 597 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 error = vge_cam_set(sc, 601 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 602 if (error) 603 break; 604 } 605 606 /* If there were too many addresses, use the hash filter. */ 607 if (error) { 608 vge_cam_clear(sc); 609 610 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 611 if (ifma->ifma_addr->sa_family != AF_LINK) 612 continue; 613 #if __FreeBSD_version < 502113 614 h = vge_mchash(LLADDR((struct sockaddr_dl *) 615 ifma->ifma_addr)) >> 26; 616 #else 617 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 618 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 619 #endif 620 if (h < 32) 621 hashes[0] |= (1 << h); 622 else 623 hashes[1] |= (1 << (h - 32)); 624 } 625 626 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 627 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 628 } 629 630 return; 631 } 632 633 static void 634 vge_reset(sc) 635 struct vge_softc *sc; 636 { 637 register int i; 638 639 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 640 641 for (i = 0; i < VGE_TIMEOUT; i++) { 642 DELAY(5); 643 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 644 break; 645 } 646 647 if (i == VGE_TIMEOUT) { 648 device_printf(sc->vge_dev, "soft reset timed out"); 649 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 650 DELAY(2000); 651 } 652 653 DELAY(5000); 654 655 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 656 657 for (i = 0; i < VGE_TIMEOUT; i++) { 658 DELAY(5); 659 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 660 break; 661 } 662 663 if (i == VGE_TIMEOUT) { 664 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 665 return; 666 } 667 668 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 669 670 return; 671 } 672 673 /* 674 * Probe for a VIA gigabit chip. Check the PCI vendor and device 675 * IDs against our list and return a device name if we find a match. 676 */ 677 static int 678 vge_probe(dev) 679 device_t dev; 680 { 681 struct vge_type *t; 682 struct vge_softc *sc; 683 684 t = vge_devs; 685 sc = device_get_softc(dev); 686 687 while (t->vge_name != NULL) { 688 if ((pci_get_vendor(dev) == t->vge_vid) && 689 (pci_get_device(dev) == t->vge_did)) { 690 device_set_desc(dev, t->vge_name); 691 return (BUS_PROBE_DEFAULT); 692 } 693 t++; 694 } 695 696 return (ENXIO); 697 } 698 699 static void 700 vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 701 void *arg; 702 bus_dma_segment_t *segs; 703 int nseg; 704 bus_size_t mapsize; 705 int error; 706 { 707 708 struct vge_dmaload_arg *ctx; 709 struct vge_rx_desc *d = NULL; 710 711 if (error) 712 return; 713 714 ctx = arg; 715 716 /* Signal error to caller if there's too many segments */ 717 if (nseg > ctx->vge_maxsegs) { 718 ctx->vge_maxsegs = 0; 719 return; 720 } 721 722 /* 723 * Map the segment array into descriptors. 724 */ 725 726 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 727 728 /* If this descriptor is still owned by the chip, bail. */ 729 730 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 731 device_printf(ctx->sc->vge_dev, 732 "tried to map busy descriptor\n"); 733 ctx->vge_maxsegs = 0; 734 return; 735 } 736 737 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 738 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 739 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 740 d->vge_sts = 0; 741 d->vge_ctl = 0; 742 743 ctx->vge_maxsegs = 1; 744 745 return; 746 } 747 748 static void 749 vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 750 void *arg; 751 bus_dma_segment_t *segs; 752 int nseg; 753 bus_size_t mapsize; 754 int error; 755 { 756 struct vge_dmaload_arg *ctx; 757 struct vge_tx_desc *d = NULL; 758 struct vge_tx_frag *f; 759 int i = 0; 760 761 if (error) 762 return; 763 764 ctx = arg; 765 766 /* Signal error to caller if there's too many segments */ 767 if (nseg > ctx->vge_maxsegs) { 768 ctx->vge_maxsegs = 0; 769 return; 770 } 771 772 /* Map the segment array into descriptors. */ 773 774 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 775 776 /* If this descriptor is still owned by the chip, bail. */ 777 778 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 779 ctx->vge_maxsegs = 0; 780 return; 781 } 782 783 for (i = 0; i < nseg; i++) { 784 f = &d->vge_frag[i]; 785 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 786 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 787 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 788 } 789 790 /* Argh. This chip does not autopad short frames */ 791 792 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 793 f = &d->vge_frag[i]; 794 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 795 ctx->vge_m0->m_pkthdr.len)); 796 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 797 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 798 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 799 i++; 800 } 801 802 /* 803 * When telling the chip how many segments there are, we 804 * must use nsegs + 1 instead of just nsegs. Darned if I 805 * know why. 806 */ 807 i++; 808 809 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 810 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 811 812 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 813 d->vge_ctl |= VGE_TDCTL_JUMBO; 814 815 ctx->vge_maxsegs = nseg; 816 817 return; 818 } 819 820 /* 821 * Map a single buffer address. 822 */ 823 824 static void 825 vge_dma_map_addr(arg, segs, nseg, error) 826 void *arg; 827 bus_dma_segment_t *segs; 828 int nseg; 829 int error; 830 { 831 bus_addr_t *addr; 832 833 if (error) 834 return; 835 836 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 837 addr = arg; 838 *addr = segs->ds_addr; 839 840 return; 841 } 842 843 static int 844 vge_allocmem(dev, sc) 845 device_t dev; 846 struct vge_softc *sc; 847 { 848 int error; 849 int nseg; 850 int i; 851 852 /* 853 * Allocate map for RX mbufs. 854 */ 855 nseg = 32; 856 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 857 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 858 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 859 NULL, NULL, &sc->vge_ldata.vge_mtag); 860 if (error) { 861 device_printf(dev, "could not allocate dma tag\n"); 862 return (ENOMEM); 863 } 864 865 /* 866 * Allocate map for TX descriptor list. 867 */ 868 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 869 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 870 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 871 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 872 if (error) { 873 device_printf(dev, "could not allocate dma tag\n"); 874 return (ENOMEM); 875 } 876 877 /* Allocate DMA'able memory for the TX ring */ 878 879 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 880 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 881 &sc->vge_ldata.vge_tx_list_map); 882 if (error) 883 return (ENOMEM); 884 885 /* Load the map for the TX ring. */ 886 887 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 888 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 889 VGE_TX_LIST_SZ, vge_dma_map_addr, 890 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 891 892 /* Create DMA maps for TX buffers */ 893 894 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 895 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 896 &sc->vge_ldata.vge_tx_dmamap[i]); 897 if (error) { 898 device_printf(dev, "can't create DMA map for TX\n"); 899 return (ENOMEM); 900 } 901 } 902 903 /* 904 * Allocate map for RX descriptor list. 905 */ 906 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 907 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 908 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 909 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 910 if (error) { 911 device_printf(dev, "could not allocate dma tag\n"); 912 return (ENOMEM); 913 } 914 915 /* Allocate DMA'able memory for the RX ring */ 916 917 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 918 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 919 &sc->vge_ldata.vge_rx_list_map); 920 if (error) 921 return (ENOMEM); 922 923 /* Load the map for the RX ring. */ 924 925 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 926 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 927 VGE_TX_LIST_SZ, vge_dma_map_addr, 928 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 929 930 /* Create DMA maps for RX buffers */ 931 932 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 933 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 934 &sc->vge_ldata.vge_rx_dmamap[i]); 935 if (error) { 936 device_printf(dev, "can't create DMA map for RX\n"); 937 return (ENOMEM); 938 } 939 } 940 941 return (0); 942 } 943 944 /* 945 * Attach the interface. Allocate softc structures, do ifmedia 946 * setup and ethernet/BPF attach. 947 */ 948 static int 949 vge_attach(dev) 950 device_t dev; 951 { 952 u_char eaddr[ETHER_ADDR_LEN]; 953 struct vge_softc *sc; 954 struct ifnet *ifp; 955 int unit, error = 0, rid; 956 957 sc = device_get_softc(dev); 958 unit = device_get_unit(dev); 959 sc->vge_dev = dev; 960 961 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 962 MTX_DEF | MTX_RECURSE); 963 /* 964 * Map control/status registers. 965 */ 966 pci_enable_busmaster(dev); 967 968 rid = VGE_PCI_LOMEM; 969 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 970 0, ~0, 1, RF_ACTIVE); 971 972 if (sc->vge_res == NULL) { 973 printf ("vge%d: couldn't map ports/memory\n", unit); 974 error = ENXIO; 975 goto fail; 976 } 977 978 sc->vge_btag = rman_get_bustag(sc->vge_res); 979 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 980 981 /* Allocate interrupt */ 982 rid = 0; 983 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 984 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 985 986 if (sc->vge_irq == NULL) { 987 printf("vge%d: couldn't map interrupt\n", unit); 988 error = ENXIO; 989 goto fail; 990 } 991 992 /* Reset the adapter. */ 993 vge_reset(sc); 994 995 /* 996 * Get station address from the EEPROM. 997 */ 998 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 999 1000 sc->vge_unit = unit; 1001 1002 #if __FreeBSD_version < 502113 1003 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1004 #endif 1005 1006 /* 1007 * Allocate the parent bus DMA tag appropriate for PCI. 1008 */ 1009 #define VGE_NSEG_NEW 32 1010 error = bus_dma_tag_create(NULL, /* parent */ 1011 1, 0, /* alignment, boundary */ 1012 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1013 BUS_SPACE_MAXADDR, /* highaddr */ 1014 NULL, NULL, /* filter, filterarg */ 1015 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1016 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1017 BUS_DMA_ALLOCNOW, /* flags */ 1018 NULL, NULL, /* lockfunc, lockarg */ 1019 &sc->vge_parent_tag); 1020 if (error) 1021 goto fail; 1022 1023 error = vge_allocmem(dev, sc); 1024 1025 if (error) 1026 goto fail; 1027 1028 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1029 if (ifp == NULL) { 1030 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1031 error = ENOSPC; 1032 goto fail; 1033 } 1034 1035 /* Do MII setup */ 1036 if (mii_phy_probe(dev, &sc->vge_miibus, 1037 vge_ifmedia_upd, vge_ifmedia_sts)) { 1038 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1039 error = ENXIO; 1040 goto fail; 1041 } 1042 1043 ifp->if_softc = sc; 1044 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1045 ifp->if_mtu = ETHERMTU; 1046 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1047 ifp->if_ioctl = vge_ioctl; 1048 ifp->if_capabilities = IFCAP_VLAN_MTU; 1049 ifp->if_start = vge_start; 1050 ifp->if_hwassist = VGE_CSUM_FEATURES; 1051 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1052 #ifdef DEVICE_POLLING 1053 #ifdef IFCAP_POLLING 1054 ifp->if_capabilities |= IFCAP_POLLING; 1055 #endif 1056 #endif 1057 ifp->if_watchdog = vge_watchdog; 1058 ifp->if_init = vge_init; 1059 ifp->if_baudrate = 1000000000; 1060 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1061 ifp->if_capenable = ifp->if_capabilities; 1062 1063 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1064 1065 /* 1066 * Call MI attach routine. 1067 */ 1068 ether_ifattach(ifp, eaddr); 1069 1070 /* Hook interrupt last to avoid having to lock softc */ 1071 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1072 vge_intr, sc, &sc->vge_intrhand); 1073 1074 if (error) { 1075 printf("vge%d: couldn't set up irq\n", unit); 1076 ether_ifdetach(ifp); 1077 goto fail; 1078 } 1079 1080 fail: 1081 if (error) 1082 vge_detach(dev); 1083 1084 return (error); 1085 } 1086 1087 /* 1088 * Shutdown hardware and free up resources. This can be called any 1089 * time after the mutex has been initialized. It is called in both 1090 * the error case in attach and the normal detach case so it needs 1091 * to be careful about only freeing resources that have actually been 1092 * allocated. 1093 */ 1094 static int 1095 vge_detach(dev) 1096 device_t dev; 1097 { 1098 struct vge_softc *sc; 1099 struct ifnet *ifp; 1100 int i; 1101 1102 sc = device_get_softc(dev); 1103 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1104 ifp = sc->vge_ifp; 1105 1106 /* These should only be active if attach succeeded */ 1107 if (device_is_attached(dev)) { 1108 vge_stop(sc); 1109 /* 1110 * Force off the IFF_UP flag here, in case someone 1111 * still had a BPF descriptor attached to this 1112 * interface. If they do, ether_ifattach() will cause 1113 * the BPF code to try and clear the promisc mode 1114 * flag, which will bubble down to vge_ioctl(), 1115 * which will try to call vge_init() again. This will 1116 * turn the NIC back on and restart the MII ticker, 1117 * which will panic the system when the kernel tries 1118 * to invoke the vge_tick() function that isn't there 1119 * anymore. 1120 */ 1121 ifp->if_flags &= ~IFF_UP; 1122 ether_ifdetach(ifp); 1123 if_free(ifp); 1124 } 1125 if (sc->vge_miibus) 1126 device_delete_child(dev, sc->vge_miibus); 1127 bus_generic_detach(dev); 1128 1129 if (sc->vge_intrhand) 1130 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1131 if (sc->vge_irq) 1132 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1133 if (sc->vge_res) 1134 bus_release_resource(dev, SYS_RES_MEMORY, 1135 VGE_PCI_LOMEM, sc->vge_res); 1136 1137 /* Unload and free the RX DMA ring memory and map */ 1138 1139 if (sc->vge_ldata.vge_rx_list_tag) { 1140 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1141 sc->vge_ldata.vge_rx_list_map); 1142 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1143 sc->vge_ldata.vge_rx_list, 1144 sc->vge_ldata.vge_rx_list_map); 1145 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1146 } 1147 1148 /* Unload and free the TX DMA ring memory and map */ 1149 1150 if (sc->vge_ldata.vge_tx_list_tag) { 1151 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1152 sc->vge_ldata.vge_tx_list_map); 1153 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1154 sc->vge_ldata.vge_tx_list, 1155 sc->vge_ldata.vge_tx_list_map); 1156 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1157 } 1158 1159 /* Destroy all the RX and TX buffer maps */ 1160 1161 if (sc->vge_ldata.vge_mtag) { 1162 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1163 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1164 sc->vge_ldata.vge_tx_dmamap[i]); 1165 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1166 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1167 sc->vge_ldata.vge_rx_dmamap[i]); 1168 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1169 } 1170 1171 if (sc->vge_parent_tag) 1172 bus_dma_tag_destroy(sc->vge_parent_tag); 1173 1174 mtx_destroy(&sc->vge_mtx); 1175 1176 return (0); 1177 } 1178 1179 static int 1180 vge_newbuf(sc, idx, m) 1181 struct vge_softc *sc; 1182 int idx; 1183 struct mbuf *m; 1184 { 1185 struct vge_dmaload_arg arg; 1186 struct mbuf *n = NULL; 1187 int i, error; 1188 1189 if (m == NULL) { 1190 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1191 if (n == NULL) 1192 return (ENOBUFS); 1193 m = n; 1194 } else 1195 m->m_data = m->m_ext.ext_buf; 1196 1197 1198 #ifdef VGE_FIXUP_RX 1199 /* 1200 * This is part of an evil trick to deal with non-x86 platforms. 1201 * The VIA chip requires RX buffers to be aligned on 32-bit 1202 * boundaries, but that will hose non-x86 machines. To get around 1203 * this, we leave some empty space at the start of each buffer 1204 * and for non-x86 hosts, we copy the buffer back two bytes 1205 * to achieve word alignment. This is slightly more efficient 1206 * than allocating a new buffer, copying the contents, and 1207 * discarding the old buffer. 1208 */ 1209 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1210 m_adj(m, VGE_ETHER_ALIGN); 1211 #else 1212 m->m_len = m->m_pkthdr.len = MCLBYTES; 1213 #endif 1214 1215 arg.sc = sc; 1216 arg.vge_idx = idx; 1217 arg.vge_maxsegs = 1; 1218 arg.vge_flags = 0; 1219 1220 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1221 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1222 &arg, BUS_DMA_NOWAIT); 1223 if (error || arg.vge_maxsegs != 1) { 1224 if (n != NULL) 1225 m_freem(n); 1226 return (ENOMEM); 1227 } 1228 1229 /* 1230 * Note: the manual fails to document the fact that for 1231 * proper opration, the driver needs to replentish the RX 1232 * DMA ring 4 descriptors at a time (rather than one at a 1233 * time, like most chips). We can allocate the new buffers 1234 * but we should not set the OWN bits until we're ready 1235 * to hand back 4 of them in one shot. 1236 */ 1237 1238 #define VGE_RXCHUNK 4 1239 sc->vge_rx_consumed++; 1240 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1241 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1242 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1243 htole32(VGE_RDSTS_OWN); 1244 sc->vge_rx_consumed = 0; 1245 } 1246 1247 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1248 1249 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1250 sc->vge_ldata.vge_rx_dmamap[idx], 1251 BUS_DMASYNC_PREREAD); 1252 1253 return (0); 1254 } 1255 1256 static int 1257 vge_tx_list_init(sc) 1258 struct vge_softc *sc; 1259 { 1260 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1261 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1262 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1263 1264 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1265 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1266 sc->vge_ldata.vge_tx_prodidx = 0; 1267 sc->vge_ldata.vge_tx_considx = 0; 1268 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1269 1270 return (0); 1271 } 1272 1273 static int 1274 vge_rx_list_init(sc) 1275 struct vge_softc *sc; 1276 { 1277 int i; 1278 1279 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1280 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1281 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1282 1283 sc->vge_rx_consumed = 0; 1284 1285 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1286 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1287 return (ENOBUFS); 1288 } 1289 1290 /* Flush the RX descriptors */ 1291 1292 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1293 sc->vge_ldata.vge_rx_list_map, 1294 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1295 1296 sc->vge_ldata.vge_rx_prodidx = 0; 1297 sc->vge_rx_consumed = 0; 1298 sc->vge_head = sc->vge_tail = NULL; 1299 1300 return (0); 1301 } 1302 1303 #ifdef VGE_FIXUP_RX 1304 static __inline void 1305 vge_fixup_rx(m) 1306 struct mbuf *m; 1307 { 1308 int i; 1309 uint16_t *src, *dst; 1310 1311 src = mtod(m, uint16_t *); 1312 dst = src - 1; 1313 1314 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1315 *dst++ = *src++; 1316 1317 m->m_data -= ETHER_ALIGN; 1318 1319 return; 1320 } 1321 #endif 1322 1323 /* 1324 * RX handler. We support the reception of jumbo frames that have 1325 * been fragmented across multiple 2K mbuf cluster buffers. 1326 */ 1327 static void 1328 vge_rxeof(sc) 1329 struct vge_softc *sc; 1330 { 1331 struct mbuf *m; 1332 struct ifnet *ifp; 1333 int i, total_len; 1334 int lim = 0; 1335 struct vge_rx_desc *cur_rx; 1336 u_int32_t rxstat, rxctl; 1337 1338 VGE_LOCK_ASSERT(sc); 1339 ifp = sc->vge_ifp; 1340 i = sc->vge_ldata.vge_rx_prodidx; 1341 1342 /* Invalidate the descriptor memory */ 1343 1344 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1345 sc->vge_ldata.vge_rx_list_map, 1346 BUS_DMASYNC_POSTREAD); 1347 1348 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1349 1350 #ifdef DEVICE_POLLING 1351 if (ifp->if_flags & IFF_POLLING) { 1352 if (sc->rxcycles <= 0) 1353 break; 1354 sc->rxcycles--; 1355 } 1356 #endif /* DEVICE_POLLING */ 1357 1358 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1359 m = sc->vge_ldata.vge_rx_mbuf[i]; 1360 total_len = VGE_RXBYTES(cur_rx); 1361 rxstat = le32toh(cur_rx->vge_sts); 1362 rxctl = le32toh(cur_rx->vge_ctl); 1363 1364 /* Invalidate the RX mbuf and unload its map */ 1365 1366 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1367 sc->vge_ldata.vge_rx_dmamap[i], 1368 BUS_DMASYNC_POSTWRITE); 1369 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1370 sc->vge_ldata.vge_rx_dmamap[i]); 1371 1372 /* 1373 * If the 'start of frame' bit is set, this indicates 1374 * either the first fragment in a multi-fragment receive, 1375 * or an intermediate fragment. Either way, we want to 1376 * accumulate the buffers. 1377 */ 1378 if (rxstat & VGE_RXPKT_SOF) { 1379 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1380 if (sc->vge_head == NULL) 1381 sc->vge_head = sc->vge_tail = m; 1382 else { 1383 m->m_flags &= ~M_PKTHDR; 1384 sc->vge_tail->m_next = m; 1385 sc->vge_tail = m; 1386 } 1387 vge_newbuf(sc, i, NULL); 1388 VGE_RX_DESC_INC(i); 1389 continue; 1390 } 1391 1392 /* 1393 * Bad/error frames will have the RXOK bit cleared. 1394 * However, there's one error case we want to allow: 1395 * if a VLAN tagged frame arrives and the chip can't 1396 * match it against the CAM filter, it considers this 1397 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1398 * We don't want to drop the frame though: our VLAN 1399 * filtering is done in software. 1400 */ 1401 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1402 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1403 ifp->if_ierrors++; 1404 /* 1405 * If this is part of a multi-fragment packet, 1406 * discard all the pieces. 1407 */ 1408 if (sc->vge_head != NULL) { 1409 m_freem(sc->vge_head); 1410 sc->vge_head = sc->vge_tail = NULL; 1411 } 1412 vge_newbuf(sc, i, m); 1413 VGE_RX_DESC_INC(i); 1414 continue; 1415 } 1416 1417 /* 1418 * If allocating a replacement mbuf fails, 1419 * reload the current one. 1420 */ 1421 1422 if (vge_newbuf(sc, i, NULL)) { 1423 ifp->if_ierrors++; 1424 if (sc->vge_head != NULL) { 1425 m_freem(sc->vge_head); 1426 sc->vge_head = sc->vge_tail = NULL; 1427 } 1428 vge_newbuf(sc, i, m); 1429 VGE_RX_DESC_INC(i); 1430 continue; 1431 } 1432 1433 VGE_RX_DESC_INC(i); 1434 1435 if (sc->vge_head != NULL) { 1436 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1437 /* 1438 * Special case: if there's 4 bytes or less 1439 * in this buffer, the mbuf can be discarded: 1440 * the last 4 bytes is the CRC, which we don't 1441 * care about anyway. 1442 */ 1443 if (m->m_len <= ETHER_CRC_LEN) { 1444 sc->vge_tail->m_len -= 1445 (ETHER_CRC_LEN - m->m_len); 1446 m_freem(m); 1447 } else { 1448 m->m_len -= ETHER_CRC_LEN; 1449 m->m_flags &= ~M_PKTHDR; 1450 sc->vge_tail->m_next = m; 1451 } 1452 m = sc->vge_head; 1453 sc->vge_head = sc->vge_tail = NULL; 1454 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1455 } else 1456 m->m_pkthdr.len = m->m_len = 1457 (total_len - ETHER_CRC_LEN); 1458 1459 #ifdef VGE_FIXUP_RX 1460 vge_fixup_rx(m); 1461 #endif 1462 ifp->if_ipackets++; 1463 m->m_pkthdr.rcvif = ifp; 1464 1465 /* Do RX checksumming if enabled */ 1466 if (ifp->if_capenable & IFCAP_RXCSUM) { 1467 1468 /* Check IP header checksum */ 1469 if (rxctl & VGE_RDCTL_IPPKT) 1470 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1471 if (rxctl & VGE_RDCTL_IPCSUMOK) 1472 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1473 1474 /* Check TCP/UDP checksum */ 1475 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1476 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1477 m->m_pkthdr.csum_flags |= 1478 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1479 m->m_pkthdr.csum_data = 0xffff; 1480 } 1481 } 1482 1483 if (rxstat & VGE_RDSTS_VTAG) 1484 VLAN_INPUT_TAG(ifp, m, 1485 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1486 1487 VGE_UNLOCK(sc); 1488 (*ifp->if_input)(ifp, m); 1489 VGE_LOCK(sc); 1490 1491 lim++; 1492 if (lim == VGE_RX_DESC_CNT) 1493 break; 1494 1495 } 1496 1497 /* Flush the RX DMA ring */ 1498 1499 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1500 sc->vge_ldata.vge_rx_list_map, 1501 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1502 1503 sc->vge_ldata.vge_rx_prodidx = i; 1504 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1505 1506 1507 return; 1508 } 1509 1510 static void 1511 vge_txeof(sc) 1512 struct vge_softc *sc; 1513 { 1514 struct ifnet *ifp; 1515 u_int32_t txstat; 1516 int idx; 1517 1518 ifp = sc->vge_ifp; 1519 idx = sc->vge_ldata.vge_tx_considx; 1520 1521 /* Invalidate the TX descriptor list */ 1522 1523 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1524 sc->vge_ldata.vge_tx_list_map, 1525 BUS_DMASYNC_POSTREAD); 1526 1527 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1528 1529 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1530 if (txstat & VGE_TDSTS_OWN) 1531 break; 1532 1533 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1534 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1535 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1536 sc->vge_ldata.vge_tx_dmamap[idx]); 1537 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1538 ifp->if_collisions++; 1539 if (txstat & VGE_TDSTS_TXERR) 1540 ifp->if_oerrors++; 1541 else 1542 ifp->if_opackets++; 1543 1544 sc->vge_ldata.vge_tx_free++; 1545 VGE_TX_DESC_INC(idx); 1546 } 1547 1548 /* No changes made to the TX ring, so no flush needed */ 1549 1550 if (idx != sc->vge_ldata.vge_tx_considx) { 1551 sc->vge_ldata.vge_tx_considx = idx; 1552 ifp->if_flags &= ~IFF_OACTIVE; 1553 ifp->if_timer = 0; 1554 } 1555 1556 /* 1557 * If not all descriptors have been released reaped yet, 1558 * reload the timer so that we will eventually get another 1559 * interrupt that will cause us to re-enter this routine. 1560 * This is done in case the transmitter has gone idle. 1561 */ 1562 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1563 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1564 } 1565 1566 return; 1567 } 1568 1569 static void 1570 vge_tick(xsc) 1571 void *xsc; 1572 { 1573 struct vge_softc *sc; 1574 struct ifnet *ifp; 1575 struct mii_data *mii; 1576 1577 sc = xsc; 1578 ifp = sc->vge_ifp; 1579 VGE_LOCK(sc); 1580 mii = device_get_softc(sc->vge_miibus); 1581 1582 mii_tick(mii); 1583 if (sc->vge_link) { 1584 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1585 sc->vge_link = 0; 1586 if_link_state_change(sc->vge_ifp, 1587 LINK_STATE_DOWN); 1588 } 1589 } else { 1590 if (mii->mii_media_status & IFM_ACTIVE && 1591 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1592 sc->vge_link = 1; 1593 if_link_state_change(sc->vge_ifp, 1594 LINK_STATE_UP); 1595 #if __FreeBSD_version < 502114 1596 if (ifp->if_snd.ifq_head != NULL) 1597 #else 1598 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599 #endif 1600 taskqueue_enqueue(taskqueue_swi, 1601 &sc->vge_txtask); 1602 } 1603 } 1604 1605 VGE_UNLOCK(sc); 1606 1607 return; 1608 } 1609 1610 #ifdef DEVICE_POLLING 1611 static void 1612 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1613 { 1614 struct vge_softc *sc = ifp->if_softc; 1615 1616 VGE_LOCK(sc); 1617 #ifdef IFCAP_POLLING 1618 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1619 ether_poll_deregister(ifp); 1620 cmd = POLL_DEREGISTER; 1621 } 1622 #endif 1623 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1624 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1625 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1626 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1627 goto done; 1628 } 1629 1630 sc->rxcycles = count; 1631 vge_rxeof(sc); 1632 vge_txeof(sc); 1633 1634 #if __FreeBSD_version < 502114 1635 if (ifp->if_snd.ifq_head != NULL) 1636 #else 1637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1638 #endif 1639 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1640 1641 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1642 u_int32_t status; 1643 status = CSR_READ_4(sc, VGE_ISR); 1644 if (status == 0xFFFFFFFF) 1645 goto done; 1646 if (status) 1647 CSR_WRITE_4(sc, VGE_ISR, status); 1648 1649 /* 1650 * XXX check behaviour on receiver stalls. 1651 */ 1652 1653 if (status & VGE_ISR_TXDMA_STALL || 1654 status & VGE_ISR_RXDMA_STALL) 1655 vge_init(sc); 1656 1657 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1658 vge_rxeof(sc); 1659 ifp->if_ierrors++; 1660 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1661 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1662 } 1663 } 1664 done: 1665 VGE_UNLOCK(sc); 1666 } 1667 #endif /* DEVICE_POLLING */ 1668 1669 static void 1670 vge_intr(arg) 1671 void *arg; 1672 { 1673 struct vge_softc *sc; 1674 struct ifnet *ifp; 1675 u_int32_t status; 1676 1677 sc = arg; 1678 1679 if (sc->suspended) { 1680 return; 1681 } 1682 1683 VGE_LOCK(sc); 1684 ifp = sc->vge_ifp; 1685 1686 if (!(ifp->if_flags & IFF_UP)) { 1687 VGE_UNLOCK(sc); 1688 return; 1689 } 1690 1691 #ifdef DEVICE_POLLING 1692 if (ifp->if_flags & IFF_POLLING) 1693 goto done; 1694 if ( 1695 #ifdef IFCAP_POLLING 1696 (ifp->if_capenable & IFCAP_POLLING) && 1697 #endif 1698 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1699 CSR_WRITE_4(sc, VGE_IMR, 0); 1700 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1701 vge_poll(ifp, 0, 1); 1702 goto done; 1703 } 1704 1705 #endif /* DEVICE_POLLING */ 1706 1707 /* Disable interrupts */ 1708 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1709 1710 for (;;) { 1711 1712 status = CSR_READ_4(sc, VGE_ISR); 1713 /* If the card has gone away the read returns 0xffff. */ 1714 if (status == 0xFFFFFFFF) 1715 break; 1716 1717 if (status) 1718 CSR_WRITE_4(sc, VGE_ISR, status); 1719 1720 if ((status & VGE_INTRS) == 0) 1721 break; 1722 1723 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1724 vge_rxeof(sc); 1725 1726 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1727 vge_rxeof(sc); 1728 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1729 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1730 } 1731 1732 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1733 vge_txeof(sc); 1734 1735 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1736 vge_init(sc); 1737 1738 if (status & VGE_ISR_LINKSTS) 1739 vge_tick(sc); 1740 } 1741 1742 /* Re-enable interrupts */ 1743 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1744 1745 #ifdef DEVICE_POLLING 1746 done: 1747 #endif 1748 VGE_UNLOCK(sc); 1749 1750 #if __FreeBSD_version < 502114 1751 if (ifp->if_snd.ifq_head != NULL) 1752 #else 1753 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1754 #endif 1755 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1756 1757 return; 1758 } 1759 1760 static int 1761 vge_encap(sc, m_head, idx) 1762 struct vge_softc *sc; 1763 struct mbuf *m_head; 1764 int idx; 1765 { 1766 struct mbuf *m_new = NULL; 1767 struct vge_dmaload_arg arg; 1768 bus_dmamap_t map; 1769 int error; 1770 struct m_tag *mtag; 1771 1772 if (sc->vge_ldata.vge_tx_free <= 2) 1773 return (EFBIG); 1774 1775 arg.vge_flags = 0; 1776 1777 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1778 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1779 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1780 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1781 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1782 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1783 1784 arg.sc = sc; 1785 arg.vge_idx = idx; 1786 arg.vge_m0 = m_head; 1787 arg.vge_maxsegs = VGE_TX_FRAGS; 1788 1789 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1790 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1791 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1792 1793 if (error && error != EFBIG) { 1794 printf("vge%d: can't map mbuf (error %d)\n", 1795 sc->vge_unit, error); 1796 return (ENOBUFS); 1797 } 1798 1799 /* Too many segments to map, coalesce into a single mbuf */ 1800 1801 if (error || arg.vge_maxsegs == 0) { 1802 m_new = m_defrag(m_head, M_DONTWAIT); 1803 if (m_new == NULL) 1804 return (1); 1805 else 1806 m_head = m_new; 1807 1808 arg.sc = sc; 1809 arg.vge_m0 = m_head; 1810 arg.vge_idx = idx; 1811 arg.vge_maxsegs = 1; 1812 1813 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1814 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1815 if (error) { 1816 printf("vge%d: can't map mbuf (error %d)\n", 1817 sc->vge_unit, error); 1818 return (EFBIG); 1819 } 1820 } 1821 1822 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1823 sc->vge_ldata.vge_tx_free--; 1824 1825 /* 1826 * Set up hardware VLAN tagging. 1827 */ 1828 1829 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1830 if (mtag != NULL) 1831 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1832 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1833 1834 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1835 1836 return (0); 1837 } 1838 1839 static void 1840 vge_tx_task(arg, npending) 1841 void *arg; 1842 int npending; 1843 { 1844 struct ifnet *ifp; 1845 1846 ifp = arg; 1847 vge_start(ifp); 1848 1849 return; 1850 } 1851 1852 /* 1853 * Main transmit routine. 1854 */ 1855 1856 static void 1857 vge_start(ifp) 1858 struct ifnet *ifp; 1859 { 1860 struct vge_softc *sc; 1861 struct mbuf *m_head = NULL; 1862 int idx, pidx = 0; 1863 1864 sc = ifp->if_softc; 1865 VGE_LOCK(sc); 1866 1867 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1868 VGE_UNLOCK(sc); 1869 return; 1870 } 1871 1872 #if __FreeBSD_version < 502114 1873 if (ifp->if_snd.ifq_head == NULL) { 1874 #else 1875 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1876 #endif 1877 VGE_UNLOCK(sc); 1878 return; 1879 } 1880 1881 idx = sc->vge_ldata.vge_tx_prodidx; 1882 1883 pidx = idx - 1; 1884 if (pidx < 0) 1885 pidx = VGE_TX_DESC_CNT - 1; 1886 1887 1888 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1889 #if __FreeBSD_version < 502114 1890 IF_DEQUEUE(&ifp->if_snd, m_head); 1891 #else 1892 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1893 #endif 1894 if (m_head == NULL) 1895 break; 1896 1897 if (vge_encap(sc, m_head, idx)) { 1898 #if __FreeBSD_version >= 502114 1899 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1900 #else 1901 IF_PREPEND(&ifp->if_snd, m_head); 1902 #endif 1903 ifp->if_flags |= IFF_OACTIVE; 1904 break; 1905 } 1906 1907 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1908 htole16(VGE_TXDESC_Q); 1909 1910 pidx = idx; 1911 VGE_TX_DESC_INC(idx); 1912 1913 /* 1914 * If there's a BPF listener, bounce a copy of this frame 1915 * to him. 1916 */ 1917 BPF_MTAP(ifp, m_head); 1918 } 1919 1920 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1921 VGE_UNLOCK(sc); 1922 return; 1923 } 1924 1925 /* Flush the TX descriptors */ 1926 1927 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1928 sc->vge_ldata.vge_tx_list_map, 1929 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1930 1931 /* Issue a transmit command. */ 1932 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1933 1934 sc->vge_ldata.vge_tx_prodidx = idx; 1935 1936 /* 1937 * Use the countdown timer for interrupt moderation. 1938 * 'TX done' interrupts are disabled. Instead, we reset the 1939 * countdown timer, which will begin counting until it hits 1940 * the value in the SSTIMER register, and then trigger an 1941 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1942 * the timer count is reloaded. Only when the transmitter 1943 * is idle will the timer hit 0 and an interrupt fire. 1944 */ 1945 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1946 1947 VGE_UNLOCK(sc); 1948 1949 /* 1950 * Set a timeout in case the chip goes out to lunch. 1951 */ 1952 ifp->if_timer = 5; 1953 1954 return; 1955 } 1956 1957 static void 1958 vge_init(xsc) 1959 void *xsc; 1960 { 1961 struct vge_softc *sc = xsc; 1962 struct ifnet *ifp = sc->vge_ifp; 1963 struct mii_data *mii; 1964 int i; 1965 1966 VGE_LOCK(sc); 1967 mii = device_get_softc(sc->vge_miibus); 1968 1969 /* 1970 * Cancel pending I/O and free all RX/TX buffers. 1971 */ 1972 vge_stop(sc); 1973 vge_reset(sc); 1974 1975 /* 1976 * Initialize the RX and TX descriptors and mbufs. 1977 */ 1978 1979 vge_rx_list_init(sc); 1980 vge_tx_list_init(sc); 1981 1982 /* Set our station address */ 1983 for (i = 0; i < ETHER_ADDR_LEN; i++) 1984 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]); 1985 1986 /* 1987 * Set receive FIFO threshold. Also allow transmission and 1988 * reception of VLAN tagged frames. 1989 */ 1990 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1991 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1992 1993 /* Set DMA burst length */ 1994 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1995 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1996 1997 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1998 1999 /* Set collision backoff algorithm */ 2000 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2001 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2002 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2003 2004 /* Disable LPSEL field in priority resolution */ 2005 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2006 2007 /* 2008 * Load the addresses of the DMA queues into the chip. 2009 * Note that we only use one transmit queue. 2010 */ 2011 2012 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2013 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2014 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2015 2016 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2017 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2018 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2019 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2020 2021 /* Enable and wake up the RX descriptor queue */ 2022 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2023 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2024 2025 /* Enable the TX descriptor queue */ 2026 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2027 2028 /* Set up the receive filter -- allow large frames for VLANs. */ 2029 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2030 2031 /* If we want promiscuous mode, set the allframes bit. */ 2032 if (ifp->if_flags & IFF_PROMISC) { 2033 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2034 } 2035 2036 /* Set capture broadcast bit to capture broadcast frames. */ 2037 if (ifp->if_flags & IFF_BROADCAST) { 2038 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2039 } 2040 2041 /* Set multicast bit to capture multicast frames. */ 2042 if (ifp->if_flags & IFF_MULTICAST) { 2043 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2044 } 2045 2046 /* Init the cam filter. */ 2047 vge_cam_clear(sc); 2048 2049 /* Init the multicast filter. */ 2050 vge_setmulti(sc); 2051 2052 /* Enable flow control */ 2053 2054 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2055 2056 /* Enable jumbo frame reception (if desired) */ 2057 2058 /* Start the MAC. */ 2059 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2060 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2061 CSR_WRITE_1(sc, VGE_CRS0, 2062 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2063 2064 /* 2065 * Configure one-shot timer for microsecond 2066 * resulution and load it for 500 usecs. 2067 */ 2068 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2069 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2070 2071 /* 2072 * Configure interrupt moderation for receive. Enable 2073 * the holdoff counter and load it, and set the RX 2074 * suppression count to the number of descriptors we 2075 * want to allow before triggering an interrupt. 2076 * The holdoff timer is in units of 20 usecs. 2077 */ 2078 2079 #ifdef notyet 2080 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2081 /* Select the interrupt holdoff timer page. */ 2082 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2083 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2084 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2085 2086 /* Enable use of the holdoff timer. */ 2087 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2088 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2089 2090 /* Select the RX suppression threshold page. */ 2091 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2092 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2093 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2094 2095 /* Restore the page select bits. */ 2096 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2097 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2098 #endif 2099 2100 #ifdef DEVICE_POLLING 2101 /* 2102 * Disable interrupts if we are polling. 2103 */ 2104 if (ifp->if_flags & IFF_POLLING) { 2105 CSR_WRITE_4(sc, VGE_IMR, 0); 2106 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2107 } else /* otherwise ... */ 2108 #endif /* DEVICE_POLLING */ 2109 { 2110 /* 2111 * Enable interrupts. 2112 */ 2113 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2114 CSR_WRITE_4(sc, VGE_ISR, 0); 2115 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2116 } 2117 2118 mii_mediachg(mii); 2119 2120 ifp->if_flags |= IFF_RUNNING; 2121 ifp->if_flags &= ~IFF_OACTIVE; 2122 2123 sc->vge_if_flags = 0; 2124 sc->vge_link = 0; 2125 2126 VGE_UNLOCK(sc); 2127 2128 return; 2129 } 2130 2131 /* 2132 * Set media options. 2133 */ 2134 static int 2135 vge_ifmedia_upd(ifp) 2136 struct ifnet *ifp; 2137 { 2138 struct vge_softc *sc; 2139 struct mii_data *mii; 2140 2141 sc = ifp->if_softc; 2142 mii = device_get_softc(sc->vge_miibus); 2143 mii_mediachg(mii); 2144 2145 return (0); 2146 } 2147 2148 /* 2149 * Report current media status. 2150 */ 2151 static void 2152 vge_ifmedia_sts(ifp, ifmr) 2153 struct ifnet *ifp; 2154 struct ifmediareq *ifmr; 2155 { 2156 struct vge_softc *sc; 2157 struct mii_data *mii; 2158 2159 sc = ifp->if_softc; 2160 mii = device_get_softc(sc->vge_miibus); 2161 2162 mii_pollstat(mii); 2163 ifmr->ifm_active = mii->mii_media_active; 2164 ifmr->ifm_status = mii->mii_media_status; 2165 2166 return; 2167 } 2168 2169 static void 2170 vge_miibus_statchg(dev) 2171 device_t dev; 2172 { 2173 struct vge_softc *sc; 2174 struct mii_data *mii; 2175 struct ifmedia_entry *ife; 2176 2177 sc = device_get_softc(dev); 2178 mii = device_get_softc(sc->vge_miibus); 2179 ife = mii->mii_media.ifm_cur; 2180 2181 /* 2182 * If the user manually selects a media mode, we need to turn 2183 * on the forced MAC mode bit in the DIAGCTL register. If the 2184 * user happens to choose a full duplex mode, we also need to 2185 * set the 'force full duplex' bit. This applies only to 2186 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2187 * mode is disabled, and in 1000baseT mode, full duplex is 2188 * always implied, so we turn on the forced mode bit but leave 2189 * the FDX bit cleared. 2190 */ 2191 2192 switch (IFM_SUBTYPE(ife->ifm_media)) { 2193 case IFM_AUTO: 2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2195 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2196 break; 2197 case IFM_1000_T: 2198 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2199 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2200 break; 2201 case IFM_100_TX: 2202 case IFM_10_T: 2203 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2204 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2205 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2206 } else { 2207 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2208 } 2209 break; 2210 default: 2211 device_printf(dev, "unknown media type: %x\n", 2212 IFM_SUBTYPE(ife->ifm_media)); 2213 break; 2214 } 2215 2216 return; 2217 } 2218 2219 static int 2220 vge_ioctl(ifp, command, data) 2221 struct ifnet *ifp; 2222 u_long command; 2223 caddr_t data; 2224 { 2225 struct vge_softc *sc = ifp->if_softc; 2226 struct ifreq *ifr = (struct ifreq *) data; 2227 struct mii_data *mii; 2228 int error = 0; 2229 2230 switch (command) { 2231 case SIOCSIFMTU: 2232 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2233 error = EINVAL; 2234 ifp->if_mtu = ifr->ifr_mtu; 2235 break; 2236 case SIOCSIFFLAGS: 2237 if (ifp->if_flags & IFF_UP) { 2238 if (ifp->if_flags & IFF_RUNNING && 2239 ifp->if_flags & IFF_PROMISC && 2240 !(sc->vge_if_flags & IFF_PROMISC)) { 2241 CSR_SETBIT_1(sc, VGE_RXCTL, 2242 VGE_RXCTL_RX_PROMISC); 2243 vge_setmulti(sc); 2244 } else if (ifp->if_flags & IFF_RUNNING && 2245 !(ifp->if_flags & IFF_PROMISC) && 2246 sc->vge_if_flags & IFF_PROMISC) { 2247 CSR_CLRBIT_1(sc, VGE_RXCTL, 2248 VGE_RXCTL_RX_PROMISC); 2249 vge_setmulti(sc); 2250 } else 2251 vge_init(sc); 2252 } else { 2253 if (ifp->if_flags & IFF_RUNNING) 2254 vge_stop(sc); 2255 } 2256 sc->vge_if_flags = ifp->if_flags; 2257 break; 2258 case SIOCADDMULTI: 2259 case SIOCDELMULTI: 2260 vge_setmulti(sc); 2261 break; 2262 case SIOCGIFMEDIA: 2263 case SIOCSIFMEDIA: 2264 mii = device_get_softc(sc->vge_miibus); 2265 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2266 break; 2267 case SIOCSIFCAP: 2268 #ifdef IFCAP_POLLING 2269 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2270 #else 2271 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2272 #endif 2273 ifp->if_capenable |= 2274 #ifdef IFCAP_POLLING 2275 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2276 #else 2277 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2278 #endif 2279 if (ifp->if_capenable & IFCAP_TXCSUM) 2280 ifp->if_hwassist = VGE_CSUM_FEATURES; 2281 else 2282 ifp->if_hwassist = 0; 2283 if (ifp->if_flags & IFF_RUNNING) 2284 vge_init(sc); 2285 break; 2286 default: 2287 error = ether_ioctl(ifp, command, data); 2288 break; 2289 } 2290 2291 return (error); 2292 } 2293 2294 static void 2295 vge_watchdog(ifp) 2296 struct ifnet *ifp; 2297 { 2298 struct vge_softc *sc; 2299 2300 sc = ifp->if_softc; 2301 VGE_LOCK(sc); 2302 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2303 ifp->if_oerrors++; 2304 2305 vge_txeof(sc); 2306 vge_rxeof(sc); 2307 2308 vge_init(sc); 2309 2310 VGE_UNLOCK(sc); 2311 2312 return; 2313 } 2314 2315 /* 2316 * Stop the adapter and free any mbufs allocated to the 2317 * RX and TX lists. 2318 */ 2319 static void 2320 vge_stop(sc) 2321 struct vge_softc *sc; 2322 { 2323 register int i; 2324 struct ifnet *ifp; 2325 2326 VGE_LOCK(sc); 2327 ifp = sc->vge_ifp; 2328 ifp->if_timer = 0; 2329 2330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2331 #ifdef DEVICE_POLLING 2332 ether_poll_deregister(ifp); 2333 #endif /* DEVICE_POLLING */ 2334 2335 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2336 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2337 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2338 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2339 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2340 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2341 2342 if (sc->vge_head != NULL) { 2343 m_freem(sc->vge_head); 2344 sc->vge_head = sc->vge_tail = NULL; 2345 } 2346 2347 /* Free the TX list buffers. */ 2348 2349 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2350 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2351 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2352 sc->vge_ldata.vge_tx_dmamap[i]); 2353 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2354 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2355 } 2356 } 2357 2358 /* Free the RX list buffers. */ 2359 2360 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2361 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2362 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2363 sc->vge_ldata.vge_rx_dmamap[i]); 2364 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2365 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2366 } 2367 } 2368 2369 VGE_UNLOCK(sc); 2370 2371 return; 2372 } 2373 2374 /* 2375 * Device suspend routine. Stop the interface and save some PCI 2376 * settings in case the BIOS doesn't restore them properly on 2377 * resume. 2378 */ 2379 static int 2380 vge_suspend(dev) 2381 device_t dev; 2382 { 2383 struct vge_softc *sc; 2384 2385 sc = device_get_softc(dev); 2386 2387 vge_stop(sc); 2388 2389 sc->suspended = 1; 2390 2391 return (0); 2392 } 2393 2394 /* 2395 * Device resume routine. Restore some PCI settings in case the BIOS 2396 * doesn't, re-enable busmastering, and restart the interface if 2397 * appropriate. 2398 */ 2399 static int 2400 vge_resume(dev) 2401 device_t dev; 2402 { 2403 struct vge_softc *sc; 2404 struct ifnet *ifp; 2405 2406 sc = device_get_softc(dev); 2407 ifp = sc->vge_ifp; 2408 2409 /* reenable busmastering */ 2410 pci_enable_busmaster(dev); 2411 pci_enable_io(dev, SYS_RES_MEMORY); 2412 2413 /* reinitialize interface if necessary */ 2414 if (ifp->if_flags & IFF_UP) 2415 vge_init(sc); 2416 2417 sc->suspended = 0; 2418 2419 return (0); 2420 } 2421 2422 /* 2423 * Stop all chip I/O so that the kernel's probe routines don't 2424 * get confused by errant DMAs when rebooting. 2425 */ 2426 static void 2427 vge_shutdown(dev) 2428 device_t dev; 2429 { 2430 struct vge_softc *sc; 2431 2432 sc = device_get_softc(dev); 2433 2434 vge_stop(sc); 2435 } 2436