1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #include <sys/param.h> 84 #include <sys/endian.h> 85 #include <sys/systm.h> 86 #include <sys/sockio.h> 87 #include <sys/mbuf.h> 88 #include <sys/malloc.h> 89 #include <sys/module.h> 90 #include <sys/kernel.h> 91 #include <sys/socket.h> 92 #include <sys/taskqueue.h> 93 94 #include <net/if.h> 95 #include <net/if_arp.h> 96 #include <net/ethernet.h> 97 #include <net/if_dl.h> 98 #include <net/if_media.h> 99 #include <net/if_vlan_var.h> 100 101 #include <net/bpf.h> 102 103 #include <machine/bus_pio.h> 104 #include <machine/bus_memio.h> 105 #include <machine/bus.h> 106 #include <machine/resource.h> 107 #include <sys/bus.h> 108 #include <sys/rman.h> 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 113 #include <dev/pci/pcireg.h> 114 #include <dev/pci/pcivar.h> 115 116 MODULE_DEPEND(vge, pci, 1, 1, 1); 117 MODULE_DEPEND(vge, ether, 1, 1, 1); 118 MODULE_DEPEND(vge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 #include <dev/vge/if_vgereg.h> 124 #include <dev/vge/if_vgevar.h> 125 126 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 127 128 /* 129 * Various supported device vendors/types and their names. 130 */ 131 static struct vge_type vge_devs[] = { 132 { VIA_VENDORID, VIA_DEVICEID_61XX, 133 "VIA Networking Gigabit Ethernet" }, 134 { 0, 0, NULL } 135 }; 136 137 static int vge_probe (device_t); 138 static int vge_attach (device_t); 139 static int vge_detach (device_t); 140 141 static int vge_encap (struct vge_softc *, struct mbuf *, int); 142 143 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 144 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 145 bus_size_t, int); 146 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 147 bus_size_t, int); 148 static int vge_allocmem (device_t, struct vge_softc *); 149 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 150 static int vge_rx_list_init (struct vge_softc *); 151 static int vge_tx_list_init (struct vge_softc *); 152 #ifdef VGE_FIXUP_RX 153 static __inline void vge_fixup_rx 154 (struct mbuf *); 155 #endif 156 static void vge_rxeof (struct vge_softc *); 157 static void vge_txeof (struct vge_softc *); 158 static void vge_intr (void *); 159 static void vge_tick (void *); 160 static void vge_tx_task (void *, int); 161 static void vge_start (struct ifnet *); 162 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 163 static void vge_init (void *); 164 static void vge_stop (struct vge_softc *); 165 static void vge_watchdog (struct ifnet *); 166 static int vge_suspend (device_t); 167 static int vge_resume (device_t); 168 static void vge_shutdown (device_t); 169 static int vge_ifmedia_upd (struct ifnet *); 170 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 171 172 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 173 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 174 175 static void vge_miipoll_start (struct vge_softc *); 176 static void vge_miipoll_stop (struct vge_softc *); 177 static int vge_miibus_readreg (device_t, int, int); 178 static int vge_miibus_writereg (device_t, int, int, int); 179 static void vge_miibus_statchg (device_t); 180 181 static void vge_cam_clear (struct vge_softc *); 182 static int vge_cam_set (struct vge_softc *, uint8_t *); 183 #if __FreeBSD_version < 502113 184 static uint32_t vge_mchash (uint8_t *); 185 #endif 186 static void vge_setmulti (struct vge_softc *); 187 static void vge_reset (struct vge_softc *); 188 189 #define VGE_PCI_LOIO 0x10 190 #define VGE_PCI_LOMEM 0x14 191 192 static device_method_t vge_methods[] = { 193 /* Device interface */ 194 DEVMETHOD(device_probe, vge_probe), 195 DEVMETHOD(device_attach, vge_attach), 196 DEVMETHOD(device_detach, vge_detach), 197 DEVMETHOD(device_suspend, vge_suspend), 198 DEVMETHOD(device_resume, vge_resume), 199 DEVMETHOD(device_shutdown, vge_shutdown), 200 201 /* bus interface */ 202 DEVMETHOD(bus_print_child, bus_generic_print_child), 203 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 204 205 /* MII interface */ 206 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 207 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 208 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 209 210 { 0, 0 } 211 }; 212 213 static driver_t vge_driver = { 214 "vge", 215 vge_methods, 216 sizeof(struct vge_softc) 217 }; 218 219 static devclass_t vge_devclass; 220 221 DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 222 DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 223 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 224 225 /* 226 * Read a word of data stored in the EEPROM at address 'addr.' 227 */ 228 static void 229 vge_eeprom_getword(sc, addr, dest) 230 struct vge_softc *sc; 231 int addr; 232 u_int16_t *dest; 233 { 234 register int i; 235 u_int16_t word = 0; 236 237 /* 238 * Enter EEPROM embedded programming mode. In order to 239 * access the EEPROM at all, we first have to set the 240 * EELOAD bit in the CHIPCFG2 register. 241 */ 242 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 243 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 244 245 /* Select the address of the word we want to read */ 246 CSR_WRITE_1(sc, VGE_EEADDR, addr); 247 248 /* Issue read command */ 249 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 250 251 /* Wait for the done bit to be set. */ 252 for (i = 0; i < VGE_TIMEOUT; i++) { 253 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 254 break; 255 } 256 257 if (i == VGE_TIMEOUT) { 258 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 259 *dest = 0; 260 return; 261 } 262 263 /* Read the result */ 264 word = CSR_READ_2(sc, VGE_EERDDAT); 265 266 /* Turn off EEPROM access mode. */ 267 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 268 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 269 270 *dest = word; 271 272 return; 273 } 274 275 /* 276 * Read a sequence of words from the EEPROM. 277 */ 278 static void 279 vge_read_eeprom(sc, dest, off, cnt, swap) 280 struct vge_softc *sc; 281 caddr_t dest; 282 int off; 283 int cnt; 284 int swap; 285 { 286 int i; 287 u_int16_t word = 0, *ptr; 288 289 for (i = 0; i < cnt; i++) { 290 vge_eeprom_getword(sc, off + i, &word); 291 ptr = (u_int16_t *)(dest + (i * 2)); 292 if (swap) 293 *ptr = ntohs(word); 294 else 295 *ptr = word; 296 } 297 } 298 299 static void 300 vge_miipoll_stop(sc) 301 struct vge_softc *sc; 302 { 303 int i; 304 305 CSR_WRITE_1(sc, VGE_MIICMD, 0); 306 307 for (i = 0; i < VGE_TIMEOUT; i++) { 308 DELAY(1); 309 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 310 break; 311 } 312 313 if (i == VGE_TIMEOUT) 314 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 315 316 return; 317 } 318 319 static void 320 vge_miipoll_start(sc) 321 struct vge_softc *sc; 322 { 323 int i; 324 325 /* First, make sure we're idle. */ 326 327 CSR_WRITE_1(sc, VGE_MIICMD, 0); 328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 329 330 for (i = 0; i < VGE_TIMEOUT; i++) { 331 DELAY(1); 332 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 333 break; 334 } 335 336 if (i == VGE_TIMEOUT) { 337 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 338 return; 339 } 340 341 /* Now enable auto poll mode. */ 342 343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 344 345 /* And make sure it started. */ 346 347 for (i = 0; i < VGE_TIMEOUT; i++) { 348 DELAY(1); 349 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 350 break; 351 } 352 353 if (i == VGE_TIMEOUT) 354 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 355 356 return; 357 } 358 359 static int 360 vge_miibus_readreg(dev, phy, reg) 361 device_t dev; 362 int phy, reg; 363 { 364 struct vge_softc *sc; 365 int i; 366 u_int16_t rval = 0; 367 368 sc = device_get_softc(dev); 369 370 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 371 return(0); 372 373 VGE_LOCK(sc); 374 vge_miipoll_stop(sc); 375 376 /* Specify the register we want to read. */ 377 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 378 379 /* Issue read command. */ 380 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 381 382 /* Wait for the read command bit to self-clear. */ 383 for (i = 0; i < VGE_TIMEOUT; i++) { 384 DELAY(1); 385 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 386 break; 387 } 388 389 if (i == VGE_TIMEOUT) 390 device_printf(sc->vge_dev, "MII read timed out\n"); 391 else 392 rval = CSR_READ_2(sc, VGE_MIIDATA); 393 394 vge_miipoll_start(sc); 395 VGE_UNLOCK(sc); 396 397 return (rval); 398 } 399 400 static int 401 vge_miibus_writereg(dev, phy, reg, data) 402 device_t dev; 403 int phy, reg, data; 404 { 405 struct vge_softc *sc; 406 int i, rval = 0; 407 408 sc = device_get_softc(dev); 409 410 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 411 return(0); 412 413 VGE_LOCK(sc); 414 vge_miipoll_stop(sc); 415 416 /* Specify the register we want to write. */ 417 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 418 419 /* Specify the data we want to write. */ 420 CSR_WRITE_2(sc, VGE_MIIDATA, data); 421 422 /* Issue write command. */ 423 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 424 425 /* Wait for the write command bit to self-clear. */ 426 for (i = 0; i < VGE_TIMEOUT; i++) { 427 DELAY(1); 428 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 429 break; 430 } 431 432 if (i == VGE_TIMEOUT) { 433 device_printf(sc->vge_dev, "MII write timed out\n"); 434 rval = EIO; 435 } 436 437 vge_miipoll_start(sc); 438 VGE_UNLOCK(sc); 439 440 return (rval); 441 } 442 443 static void 444 vge_cam_clear(sc) 445 struct vge_softc *sc; 446 { 447 int i; 448 449 /* 450 * Turn off all the mask bits. This tells the chip 451 * that none of the entries in the CAM filter are valid. 452 * desired entries will be enabled as we fill the filter in. 453 */ 454 455 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 456 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 457 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 458 for (i = 0; i < 8; i++) 459 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 460 461 /* Clear the VLAN filter too. */ 462 463 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 464 for (i = 0; i < 8; i++) 465 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 466 467 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 468 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 469 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 470 471 sc->vge_camidx = 0; 472 473 return; 474 } 475 476 static int 477 vge_cam_set(sc, addr) 478 struct vge_softc *sc; 479 uint8_t *addr; 480 { 481 int i, error = 0; 482 483 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 484 return(ENOSPC); 485 486 /* Select the CAM data page. */ 487 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 488 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 489 490 /* Set the filter entry we want to update and enable writing. */ 491 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 492 493 /* Write the address to the CAM registers */ 494 for (i = 0; i < ETHER_ADDR_LEN; i++) 495 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 496 497 /* Issue a write command. */ 498 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 499 500 /* Wake for it to clear. */ 501 for (i = 0; i < VGE_TIMEOUT; i++) { 502 DELAY(1); 503 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 504 break; 505 } 506 507 if (i == VGE_TIMEOUT) { 508 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 509 error = EIO; 510 goto fail; 511 } 512 513 /* Select the CAM mask page. */ 514 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 515 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 516 517 /* Set the mask bit that enables this filter. */ 518 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 519 1<<(sc->vge_camidx & 7)); 520 521 sc->vge_camidx++; 522 523 fail: 524 /* Turn off access to CAM. */ 525 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 526 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 527 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 528 529 return (error); 530 } 531 532 #if __FreeBSD_version < 502113 533 static uint32_t 534 vge_mchash(addr) 535 uint8_t *addr; 536 { 537 uint32_t crc, carry; 538 int idx, bit; 539 uint8_t data; 540 541 /* Compute CRC for the address value. */ 542 crc = 0xFFFFFFFF; /* initial value */ 543 544 for (idx = 0; idx < 6; idx++) { 545 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 546 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 547 crc <<= 1; 548 if (carry) 549 crc = (crc ^ 0x04c11db6) | carry; 550 } 551 } 552 553 return(crc); 554 } 555 #endif 556 557 /* 558 * Program the multicast filter. We use the 64-entry CAM filter 559 * for perfect filtering. If there's more than 64 multicast addresses, 560 * we use the hash filter insted. 561 */ 562 static void 563 vge_setmulti(sc) 564 struct vge_softc *sc; 565 { 566 struct ifnet *ifp; 567 int error = 0/*, h = 0*/; 568 struct ifmultiaddr *ifma; 569 u_int32_t h, hashes[2] = { 0, 0 }; 570 571 ifp = &sc->arpcom.ac_if; 572 573 /* First, zot all the multicast entries. */ 574 vge_cam_clear(sc); 575 CSR_WRITE_4(sc, VGE_MAR0, 0); 576 CSR_WRITE_4(sc, VGE_MAR1, 0); 577 578 /* 579 * If the user wants allmulti or promisc mode, enable reception 580 * of all multicast frames. 581 */ 582 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 583 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 584 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 585 return; 586 } 587 588 /* Now program new ones */ 589 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 590 if (ifma->ifma_addr->sa_family != AF_LINK) 591 continue; 592 error = vge_cam_set(sc, 593 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 594 if (error) 595 break; 596 } 597 598 /* If there were too many addresses, use the hash filter. */ 599 if (error) { 600 vge_cam_clear(sc); 601 602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 603 if (ifma->ifma_addr->sa_family != AF_LINK) 604 continue; 605 #if __FreeBSD_version < 502113 606 h = vge_mchash(LLADDR((struct sockaddr_dl *) 607 ifma->ifma_addr)) >> 26; 608 #else 609 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 611 #endif 612 if (h < 32) 613 hashes[0] |= (1 << h); 614 else 615 hashes[1] |= (1 << (h - 32)); 616 } 617 618 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 619 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 620 } 621 622 return; 623 } 624 625 static void 626 vge_reset(sc) 627 struct vge_softc *sc; 628 { 629 register int i; 630 631 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 632 633 for (i = 0; i < VGE_TIMEOUT; i++) { 634 DELAY(5); 635 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 636 break; 637 } 638 639 if (i == VGE_TIMEOUT) { 640 device_printf(sc->vge_dev, "soft reset timed out"); 641 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 642 DELAY(2000); 643 } 644 645 DELAY(5000); 646 647 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 648 649 for (i = 0; i < VGE_TIMEOUT; i++) { 650 DELAY(5); 651 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 652 break; 653 } 654 655 if (i == VGE_TIMEOUT) { 656 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 657 return; 658 } 659 660 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 661 662 return; 663 } 664 665 /* 666 * Probe for a VIA gigabit chip. Check the PCI vendor and device 667 * IDs against our list and return a device name if we find a match. 668 */ 669 static int 670 vge_probe(dev) 671 device_t dev; 672 { 673 struct vge_type *t; 674 struct vge_softc *sc; 675 676 t = vge_devs; 677 sc = device_get_softc(dev); 678 679 while (t->vge_name != NULL) { 680 if ((pci_get_vendor(dev) == t->vge_vid) && 681 (pci_get_device(dev) == t->vge_did)) { 682 device_set_desc(dev, t->vge_name); 683 return (0); 684 } 685 t++; 686 } 687 688 return (ENXIO); 689 } 690 691 static void 692 vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 693 void *arg; 694 bus_dma_segment_t *segs; 695 int nseg; 696 bus_size_t mapsize; 697 int error; 698 { 699 700 struct vge_dmaload_arg *ctx; 701 struct vge_rx_desc *d = NULL; 702 703 if (error) 704 return; 705 706 ctx = arg; 707 708 /* Signal error to caller if there's too many segments */ 709 if (nseg > ctx->vge_maxsegs) { 710 ctx->vge_maxsegs = 0; 711 return; 712 } 713 714 /* 715 * Map the segment array into descriptors. 716 */ 717 718 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 719 720 /* If this descriptor is still owned by the chip, bail. */ 721 722 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 723 device_printf(ctx->sc->vge_dev, 724 "tried to map busy descriptor\n"); 725 ctx->vge_maxsegs = 0; 726 return; 727 } 728 729 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 730 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 731 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 732 d->vge_sts = 0; 733 d->vge_ctl = 0; 734 735 ctx->vge_maxsegs = 1; 736 737 return; 738 } 739 740 static void 741 vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 742 void *arg; 743 bus_dma_segment_t *segs; 744 int nseg; 745 bus_size_t mapsize; 746 int error; 747 { 748 struct vge_dmaload_arg *ctx; 749 struct vge_tx_desc *d = NULL; 750 struct vge_tx_frag *f; 751 int i = 0; 752 753 if (error) 754 return; 755 756 ctx = arg; 757 758 /* Signal error to caller if there's too many segments */ 759 if (nseg > ctx->vge_maxsegs) { 760 ctx->vge_maxsegs = 0; 761 return; 762 } 763 764 /* Map the segment array into descriptors. */ 765 766 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 767 768 /* If this descriptor is still owned by the chip, bail. */ 769 770 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 771 ctx->vge_maxsegs = 0; 772 return; 773 } 774 775 for (i = 0; i < nseg; i++) { 776 f = &d->vge_frag[i]; 777 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 778 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 779 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 780 } 781 782 /* Argh. This chip does not autopad short frames */ 783 784 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 785 f = &d->vge_frag[i]; 786 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 787 ctx->vge_m0->m_pkthdr.len)); 788 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 789 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 790 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 791 i++; 792 } 793 794 /* 795 * When telling the chip how many segments there are, we 796 * must use nsegs + 1 instead of just nsegs. Darned if I 797 * know why. 798 */ 799 i++; 800 801 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 802 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 803 804 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 805 d->vge_ctl |= VGE_TDCTL_JUMBO; 806 807 ctx->vge_maxsegs = nseg; 808 809 return; 810 } 811 812 /* 813 * Map a single buffer address. 814 */ 815 816 static void 817 vge_dma_map_addr(arg, segs, nseg, error) 818 void *arg; 819 bus_dma_segment_t *segs; 820 int nseg; 821 int error; 822 { 823 bus_addr_t *addr; 824 825 if (error) 826 return; 827 828 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 829 addr = arg; 830 *addr = segs->ds_addr; 831 832 return; 833 } 834 835 static int 836 vge_allocmem(dev, sc) 837 device_t dev; 838 struct vge_softc *sc; 839 { 840 int error; 841 int nseg; 842 int i; 843 844 /* 845 * Allocate map for RX mbufs. 846 */ 847 nseg = 32; 848 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 849 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 850 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 851 NULL, NULL, &sc->vge_ldata.vge_mtag); 852 if (error) { 853 device_printf(dev, "could not allocate dma tag\n"); 854 return (ENOMEM); 855 } 856 857 /* 858 * Allocate map for TX descriptor list. 859 */ 860 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 861 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 862 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 863 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 864 if (error) { 865 device_printf(dev, "could not allocate dma tag\n"); 866 return (ENOMEM); 867 } 868 869 /* Allocate DMA'able memory for the TX ring */ 870 871 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 872 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 873 &sc->vge_ldata.vge_tx_list_map); 874 if (error) 875 return (ENOMEM); 876 877 /* Load the map for the TX ring. */ 878 879 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 880 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 881 VGE_TX_LIST_SZ, vge_dma_map_addr, 882 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 883 884 /* Create DMA maps for TX buffers */ 885 886 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 887 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 888 &sc->vge_ldata.vge_tx_dmamap[i]); 889 if (error) { 890 device_printf(dev, "can't create DMA map for TX\n"); 891 return (ENOMEM); 892 } 893 } 894 895 /* 896 * Allocate map for RX descriptor list. 897 */ 898 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 899 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 900 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 901 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 902 if (error) { 903 device_printf(dev, "could not allocate dma tag\n"); 904 return (ENOMEM); 905 } 906 907 /* Allocate DMA'able memory for the RX ring */ 908 909 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 910 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 911 &sc->vge_ldata.vge_rx_list_map); 912 if (error) 913 return (ENOMEM); 914 915 /* Load the map for the RX ring. */ 916 917 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 918 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 919 VGE_TX_LIST_SZ, vge_dma_map_addr, 920 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 921 922 /* Create DMA maps for RX buffers */ 923 924 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 925 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 926 &sc->vge_ldata.vge_rx_dmamap[i]); 927 if (error) { 928 device_printf(dev, "can't create DMA map for RX\n"); 929 return (ENOMEM); 930 } 931 } 932 933 return (0); 934 } 935 936 /* 937 * Attach the interface. Allocate softc structures, do ifmedia 938 * setup and ethernet/BPF attach. 939 */ 940 static int 941 vge_attach(dev) 942 device_t dev; 943 { 944 u_char eaddr[ETHER_ADDR_LEN]; 945 struct vge_softc *sc; 946 struct ifnet *ifp; 947 int unit, error = 0, rid; 948 949 sc = device_get_softc(dev); 950 unit = device_get_unit(dev); 951 sc->vge_dev = dev; 952 953 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 954 MTX_DEF | MTX_RECURSE); 955 /* 956 * Map control/status registers. 957 */ 958 pci_enable_busmaster(dev); 959 960 rid = VGE_PCI_LOMEM; 961 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 962 0, ~0, 1, RF_ACTIVE); 963 964 if (sc->vge_res == NULL) { 965 printf ("vge%d: couldn't map ports/memory\n", unit); 966 error = ENXIO; 967 goto fail; 968 } 969 970 sc->vge_btag = rman_get_bustag(sc->vge_res); 971 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 972 973 /* Allocate interrupt */ 974 rid = 0; 975 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 976 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 977 978 if (sc->vge_irq == NULL) { 979 printf("vge%d: couldn't map interrupt\n", unit); 980 error = ENXIO; 981 goto fail; 982 } 983 984 /* Reset the adapter. */ 985 vge_reset(sc); 986 987 /* 988 * Get station address from the EEPROM. 989 */ 990 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 991 992 sc->vge_unit = unit; 993 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 994 995 #if __FreeBSD_version < 502113 996 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 997 #endif 998 999 /* 1000 * Allocate the parent bus DMA tag appropriate for PCI. 1001 */ 1002 #define VGE_NSEG_NEW 32 1003 error = bus_dma_tag_create(NULL, /* parent */ 1004 1, 0, /* alignment, boundary */ 1005 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1006 BUS_SPACE_MAXADDR, /* highaddr */ 1007 NULL, NULL, /* filter, filterarg */ 1008 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1009 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1010 BUS_DMA_ALLOCNOW, /* flags */ 1011 NULL, NULL, /* lockfunc, lockarg */ 1012 &sc->vge_parent_tag); 1013 if (error) 1014 goto fail; 1015 1016 error = vge_allocmem(dev, sc); 1017 1018 if (error) 1019 goto fail; 1020 1021 /* Do MII setup */ 1022 if (mii_phy_probe(dev, &sc->vge_miibus, 1023 vge_ifmedia_upd, vge_ifmedia_sts)) { 1024 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1025 error = ENXIO; 1026 goto fail; 1027 } 1028 1029 ifp = &sc->arpcom.ac_if; 1030 ifp->if_softc = sc; 1031 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1032 ifp->if_mtu = ETHERMTU; 1033 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1034 ifp->if_ioctl = vge_ioctl; 1035 ifp->if_capabilities = IFCAP_VLAN_MTU; 1036 ifp->if_start = vge_start; 1037 ifp->if_hwassist = VGE_CSUM_FEATURES; 1038 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1039 #ifdef DEVICE_POLLING 1040 #ifdef IFCAP_POLLING 1041 ifp->if_capabilities |= IFCAP_POLLING; 1042 #endif 1043 #endif 1044 ifp->if_watchdog = vge_watchdog; 1045 ifp->if_init = vge_init; 1046 ifp->if_baudrate = 1000000000; 1047 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1048 ifp->if_capenable = ifp->if_capabilities; 1049 1050 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1051 1052 /* 1053 * Call MI attach routine. 1054 */ 1055 ether_ifattach(ifp, eaddr); 1056 1057 /* Hook interrupt last to avoid having to lock softc */ 1058 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1059 vge_intr, sc, &sc->vge_intrhand); 1060 1061 if (error) { 1062 printf("vge%d: couldn't set up irq\n", unit); 1063 ether_ifdetach(ifp); 1064 goto fail; 1065 } 1066 1067 fail: 1068 if (error) 1069 vge_detach(dev); 1070 1071 return (error); 1072 } 1073 1074 /* 1075 * Shutdown hardware and free up resources. This can be called any 1076 * time after the mutex has been initialized. It is called in both 1077 * the error case in attach and the normal detach case so it needs 1078 * to be careful about only freeing resources that have actually been 1079 * allocated. 1080 */ 1081 static int 1082 vge_detach(dev) 1083 device_t dev; 1084 { 1085 struct vge_softc *sc; 1086 struct ifnet *ifp; 1087 int i; 1088 1089 sc = device_get_softc(dev); 1090 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1091 ifp = &sc->arpcom.ac_if; 1092 1093 /* These should only be active if attach succeeded */ 1094 if (device_is_attached(dev)) { 1095 vge_stop(sc); 1096 /* 1097 * Force off the IFF_UP flag here, in case someone 1098 * still had a BPF descriptor attached to this 1099 * interface. If they do, ether_ifattach() will cause 1100 * the BPF code to try and clear the promisc mode 1101 * flag, which will bubble down to vge_ioctl(), 1102 * which will try to call vge_init() again. This will 1103 * turn the NIC back on and restart the MII ticker, 1104 * which will panic the system when the kernel tries 1105 * to invoke the vge_tick() function that isn't there 1106 * anymore. 1107 */ 1108 ifp->if_flags &= ~IFF_UP; 1109 ether_ifdetach(ifp); 1110 } 1111 if (sc->vge_miibus) 1112 device_delete_child(dev, sc->vge_miibus); 1113 bus_generic_detach(dev); 1114 1115 if (sc->vge_intrhand) 1116 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1117 if (sc->vge_irq) 1118 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1119 if (sc->vge_res) 1120 bus_release_resource(dev, SYS_RES_MEMORY, 1121 VGE_PCI_LOMEM, sc->vge_res); 1122 1123 /* Unload and free the RX DMA ring memory and map */ 1124 1125 if (sc->vge_ldata.vge_rx_list_tag) { 1126 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1127 sc->vge_ldata.vge_rx_list_map); 1128 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1129 sc->vge_ldata.vge_rx_list, 1130 sc->vge_ldata.vge_rx_list_map); 1131 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1132 } 1133 1134 /* Unload and free the TX DMA ring memory and map */ 1135 1136 if (sc->vge_ldata.vge_tx_list_tag) { 1137 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1138 sc->vge_ldata.vge_tx_list_map); 1139 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1140 sc->vge_ldata.vge_tx_list, 1141 sc->vge_ldata.vge_tx_list_map); 1142 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1143 } 1144 1145 /* Destroy all the RX and TX buffer maps */ 1146 1147 if (sc->vge_ldata.vge_mtag) { 1148 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1149 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1150 sc->vge_ldata.vge_tx_dmamap[i]); 1151 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1152 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1153 sc->vge_ldata.vge_rx_dmamap[i]); 1154 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1155 } 1156 1157 if (sc->vge_parent_tag) 1158 bus_dma_tag_destroy(sc->vge_parent_tag); 1159 1160 mtx_destroy(&sc->vge_mtx); 1161 1162 return (0); 1163 } 1164 1165 static int 1166 vge_newbuf(sc, idx, m) 1167 struct vge_softc *sc; 1168 int idx; 1169 struct mbuf *m; 1170 { 1171 struct vge_dmaload_arg arg; 1172 struct mbuf *n = NULL; 1173 int i, error; 1174 1175 if (m == NULL) { 1176 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1177 if (n == NULL) 1178 return (ENOBUFS); 1179 m = n; 1180 } else 1181 m->m_data = m->m_ext.ext_buf; 1182 1183 1184 #ifdef VGE_FIXUP_RX 1185 /* 1186 * This is part of an evil trick to deal with non-x86 platforms. 1187 * The VIA chip requires RX buffers to be aligned on 32-bit 1188 * boundaries, but that will hose non-x86 machines. To get around 1189 * this, we leave some empty space at the start of each buffer 1190 * and for non-x86 hosts, we copy the buffer back two bytes 1191 * to achieve word alignment. This is slightly more efficient 1192 * than allocating a new buffer, copying the contents, and 1193 * discarding the old buffer. 1194 */ 1195 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1196 m_adj(m, VGE_ETHER_ALIGN); 1197 #else 1198 m->m_len = m->m_pkthdr.len = MCLBYTES; 1199 #endif 1200 1201 arg.sc = sc; 1202 arg.vge_idx = idx; 1203 arg.vge_maxsegs = 1; 1204 arg.vge_flags = 0; 1205 1206 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1207 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1208 &arg, BUS_DMA_NOWAIT); 1209 if (error || arg.vge_maxsegs != 1) { 1210 if (n != NULL) 1211 m_freem(n); 1212 return (ENOMEM); 1213 } 1214 1215 /* 1216 * Note: the manual fails to document the fact that for 1217 * proper opration, the driver needs to replentish the RX 1218 * DMA ring 4 descriptors at a time (rather than one at a 1219 * time, like most chips). We can allocate the new buffers 1220 * but we should not set the OWN bits until we're ready 1221 * to hand back 4 of them in one shot. 1222 */ 1223 1224 #define VGE_RXCHUNK 4 1225 sc->vge_rx_consumed++; 1226 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1227 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1228 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1229 htole32(VGE_RDSTS_OWN); 1230 sc->vge_rx_consumed = 0; 1231 } 1232 1233 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1234 1235 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1236 sc->vge_ldata.vge_rx_dmamap[idx], 1237 BUS_DMASYNC_PREREAD); 1238 1239 return (0); 1240 } 1241 1242 static int 1243 vge_tx_list_init(sc) 1244 struct vge_softc *sc; 1245 { 1246 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1247 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1248 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1249 1250 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1251 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1252 sc->vge_ldata.vge_tx_prodidx = 0; 1253 sc->vge_ldata.vge_tx_considx = 0; 1254 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1255 1256 return (0); 1257 } 1258 1259 static int 1260 vge_rx_list_init(sc) 1261 struct vge_softc *sc; 1262 { 1263 int i; 1264 1265 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1266 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1267 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1268 1269 sc->vge_rx_consumed = 0; 1270 1271 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1272 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1273 return (ENOBUFS); 1274 } 1275 1276 /* Flush the RX descriptors */ 1277 1278 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1279 sc->vge_ldata.vge_rx_list_map, 1280 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1281 1282 sc->vge_ldata.vge_rx_prodidx = 0; 1283 sc->vge_rx_consumed = 0; 1284 sc->vge_head = sc->vge_tail = NULL; 1285 1286 return (0); 1287 } 1288 1289 #ifdef VGE_FIXUP_RX 1290 static __inline void 1291 vge_fixup_rx(m) 1292 struct mbuf *m; 1293 { 1294 int i; 1295 uint16_t *src, *dst; 1296 1297 src = mtod(m, uint16_t *); 1298 dst = src - 1; 1299 1300 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1301 *dst++ = *src++; 1302 1303 m->m_data -= ETHER_ALIGN; 1304 1305 return; 1306 } 1307 #endif 1308 1309 /* 1310 * RX handler. We support the reception of jumbo frames that have 1311 * been fragmented across multiple 2K mbuf cluster buffers. 1312 */ 1313 static void 1314 vge_rxeof(sc) 1315 struct vge_softc *sc; 1316 { 1317 struct mbuf *m; 1318 struct ifnet *ifp; 1319 int i, total_len; 1320 int lim = 0; 1321 struct vge_rx_desc *cur_rx; 1322 u_int32_t rxstat, rxctl; 1323 1324 VGE_LOCK_ASSERT(sc); 1325 ifp = &sc->arpcom.ac_if; 1326 i = sc->vge_ldata.vge_rx_prodidx; 1327 1328 /* Invalidate the descriptor memory */ 1329 1330 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1331 sc->vge_ldata.vge_rx_list_map, 1332 BUS_DMASYNC_POSTREAD); 1333 1334 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1335 1336 #ifdef DEVICE_POLLING 1337 if (ifp->if_flags & IFF_POLLING) { 1338 if (sc->rxcycles <= 0) 1339 break; 1340 sc->rxcycles--; 1341 } 1342 #endif /* DEVICE_POLLING */ 1343 1344 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1345 m = sc->vge_ldata.vge_rx_mbuf[i]; 1346 total_len = VGE_RXBYTES(cur_rx); 1347 rxstat = le32toh(cur_rx->vge_sts); 1348 rxctl = le32toh(cur_rx->vge_ctl); 1349 1350 /* Invalidate the RX mbuf and unload its map */ 1351 1352 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1353 sc->vge_ldata.vge_rx_dmamap[i], 1354 BUS_DMASYNC_POSTWRITE); 1355 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1356 sc->vge_ldata.vge_rx_dmamap[i]); 1357 1358 /* 1359 * If the 'start of frame' bit is set, this indicates 1360 * either the first fragment in a multi-fragment receive, 1361 * or an intermediate fragment. Either way, we want to 1362 * accumulate the buffers. 1363 */ 1364 if (rxstat & VGE_RXPKT_SOF) { 1365 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1366 if (sc->vge_head == NULL) 1367 sc->vge_head = sc->vge_tail = m; 1368 else { 1369 m->m_flags &= ~M_PKTHDR; 1370 sc->vge_tail->m_next = m; 1371 sc->vge_tail = m; 1372 } 1373 vge_newbuf(sc, i, NULL); 1374 VGE_RX_DESC_INC(i); 1375 continue; 1376 } 1377 1378 /* 1379 * Bad/error frames will have the RXOK bit cleared. 1380 * However, there's one error case we want to allow: 1381 * if a VLAN tagged frame arrives and the chip can't 1382 * match it against the CAM filter, it considers this 1383 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1384 * We don't want to drop the frame though: our VLAN 1385 * filtering is done in software. 1386 */ 1387 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1388 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1389 ifp->if_ierrors++; 1390 /* 1391 * If this is part of a multi-fragment packet, 1392 * discard all the pieces. 1393 */ 1394 if (sc->vge_head != NULL) { 1395 m_freem(sc->vge_head); 1396 sc->vge_head = sc->vge_tail = NULL; 1397 } 1398 vge_newbuf(sc, i, m); 1399 VGE_RX_DESC_INC(i); 1400 continue; 1401 } 1402 1403 /* 1404 * If allocating a replacement mbuf fails, 1405 * reload the current one. 1406 */ 1407 1408 if (vge_newbuf(sc, i, NULL)) { 1409 ifp->if_ierrors++; 1410 if (sc->vge_head != NULL) { 1411 m_freem(sc->vge_head); 1412 sc->vge_head = sc->vge_tail = NULL; 1413 } 1414 vge_newbuf(sc, i, m); 1415 VGE_RX_DESC_INC(i); 1416 continue; 1417 } 1418 1419 VGE_RX_DESC_INC(i); 1420 1421 if (sc->vge_head != NULL) { 1422 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1423 /* 1424 * Special case: if there's 4 bytes or less 1425 * in this buffer, the mbuf can be discarded: 1426 * the last 4 bytes is the CRC, which we don't 1427 * care about anyway. 1428 */ 1429 if (m->m_len <= ETHER_CRC_LEN) { 1430 sc->vge_tail->m_len -= 1431 (ETHER_CRC_LEN - m->m_len); 1432 m_freem(m); 1433 } else { 1434 m->m_len -= ETHER_CRC_LEN; 1435 m->m_flags &= ~M_PKTHDR; 1436 sc->vge_tail->m_next = m; 1437 } 1438 m = sc->vge_head; 1439 sc->vge_head = sc->vge_tail = NULL; 1440 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1441 } else 1442 m->m_pkthdr.len = m->m_len = 1443 (total_len - ETHER_CRC_LEN); 1444 1445 #ifdef VGE_FIXUP_RX 1446 vge_fixup_rx(m); 1447 #endif 1448 ifp->if_ipackets++; 1449 m->m_pkthdr.rcvif = ifp; 1450 1451 /* Do RX checksumming if enabled */ 1452 if (ifp->if_capenable & IFCAP_RXCSUM) { 1453 1454 /* Check IP header checksum */ 1455 if (rxctl & VGE_RDCTL_IPPKT) 1456 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1457 if (rxctl & VGE_RDCTL_IPCSUMOK) 1458 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1459 1460 /* Check TCP/UDP checksum */ 1461 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1462 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1463 m->m_pkthdr.csum_flags |= 1464 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1465 m->m_pkthdr.csum_data = 0xffff; 1466 } 1467 } 1468 1469 if (rxstat & VGE_RDSTS_VTAG) 1470 VLAN_INPUT_TAG(ifp, m, 1471 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1472 1473 VGE_UNLOCK(sc); 1474 (*ifp->if_input)(ifp, m); 1475 VGE_LOCK(sc); 1476 1477 lim++; 1478 if (lim == VGE_RX_DESC_CNT) 1479 break; 1480 1481 } 1482 1483 /* Flush the RX DMA ring */ 1484 1485 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1486 sc->vge_ldata.vge_rx_list_map, 1487 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1488 1489 sc->vge_ldata.vge_rx_prodidx = i; 1490 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1491 1492 1493 return; 1494 } 1495 1496 static void 1497 vge_txeof(sc) 1498 struct vge_softc *sc; 1499 { 1500 struct ifnet *ifp; 1501 u_int32_t txstat; 1502 int idx; 1503 1504 ifp = &sc->arpcom.ac_if; 1505 idx = sc->vge_ldata.vge_tx_considx; 1506 1507 /* Invalidate the TX descriptor list */ 1508 1509 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1510 sc->vge_ldata.vge_tx_list_map, 1511 BUS_DMASYNC_POSTREAD); 1512 1513 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1514 1515 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1516 if (txstat & VGE_TDSTS_OWN) 1517 break; 1518 1519 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1520 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1521 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1522 sc->vge_ldata.vge_tx_dmamap[idx]); 1523 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1524 ifp->if_collisions++; 1525 if (txstat & VGE_TDSTS_TXERR) 1526 ifp->if_oerrors++; 1527 else 1528 ifp->if_opackets++; 1529 1530 sc->vge_ldata.vge_tx_free++; 1531 VGE_TX_DESC_INC(idx); 1532 } 1533 1534 /* No changes made to the TX ring, so no flush needed */ 1535 1536 if (idx != sc->vge_ldata.vge_tx_considx) { 1537 sc->vge_ldata.vge_tx_considx = idx; 1538 ifp->if_flags &= ~IFF_OACTIVE; 1539 ifp->if_timer = 0; 1540 } 1541 1542 /* 1543 * If not all descriptors have been released reaped yet, 1544 * reload the timer so that we will eventually get another 1545 * interrupt that will cause us to re-enter this routine. 1546 * This is done in case the transmitter has gone idle. 1547 */ 1548 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1549 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1550 } 1551 1552 return; 1553 } 1554 1555 static void 1556 vge_tick(xsc) 1557 void *xsc; 1558 { 1559 struct vge_softc *sc; 1560 struct ifnet *ifp; 1561 struct mii_data *mii; 1562 1563 sc = xsc; 1564 ifp = &sc->arpcom.ac_if; 1565 VGE_LOCK(sc); 1566 mii = device_get_softc(sc->vge_miibus); 1567 1568 mii_tick(mii); 1569 if (sc->vge_link) { 1570 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1571 sc->vge_link = 0; 1572 if_link_state_change(&sc->arpcom.ac_if, 1573 LINK_STATE_UP); 1574 } 1575 } else { 1576 if (mii->mii_media_status & IFM_ACTIVE && 1577 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1578 sc->vge_link = 1; 1579 if_link_state_change(&sc->arpcom.ac_if, 1580 LINK_STATE_DOWN); 1581 #if __FreeBSD_version < 502114 1582 if (ifp->if_snd.ifq_head != NULL) 1583 #else 1584 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1585 #endif 1586 taskqueue_enqueue(taskqueue_swi, 1587 &sc->vge_txtask); 1588 } 1589 } 1590 1591 VGE_UNLOCK(sc); 1592 1593 return; 1594 } 1595 1596 #ifdef DEVICE_POLLING 1597 static void 1598 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1599 { 1600 struct vge_softc *sc = ifp->if_softc; 1601 1602 VGE_LOCK(sc); 1603 #ifdef IFCAP_POLLING 1604 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1605 ether_poll_deregister(ifp); 1606 cmd = POLL_DEREGISTER; 1607 } 1608 #endif 1609 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1610 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1611 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1612 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1613 goto done; 1614 } 1615 1616 sc->rxcycles = count; 1617 vge_rxeof(sc); 1618 vge_txeof(sc); 1619 1620 #if __FreeBSD_version < 502114 1621 if (ifp->if_snd.ifq_head != NULL) 1622 #else 1623 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1624 #endif 1625 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1626 1627 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1628 u_int32_t status; 1629 status = CSR_READ_4(sc, VGE_ISR); 1630 if (status == 0xFFFFFFFF) 1631 goto done; 1632 if (status) 1633 CSR_WRITE_4(sc, VGE_ISR, status); 1634 1635 /* 1636 * XXX check behaviour on receiver stalls. 1637 */ 1638 1639 if (status & VGE_ISR_TXDMA_STALL || 1640 status & VGE_ISR_RXDMA_STALL) 1641 vge_init(sc); 1642 1643 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1644 vge_rxeof(sc); 1645 ifp->if_ierrors++; 1646 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1647 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1648 } 1649 } 1650 done: 1651 VGE_UNLOCK(sc); 1652 } 1653 #endif /* DEVICE_POLLING */ 1654 1655 static void 1656 vge_intr(arg) 1657 void *arg; 1658 { 1659 struct vge_softc *sc; 1660 struct ifnet *ifp; 1661 u_int32_t status; 1662 1663 sc = arg; 1664 1665 if (sc->suspended) { 1666 return; 1667 } 1668 1669 VGE_LOCK(sc); 1670 ifp = &sc->arpcom.ac_if; 1671 1672 if (!(ifp->if_flags & IFF_UP)) { 1673 VGE_UNLOCK(sc); 1674 return; 1675 } 1676 1677 #ifdef DEVICE_POLLING 1678 if (ifp->if_flags & IFF_POLLING) 1679 goto done; 1680 if ( 1681 #ifdef IFCAP_POLLING 1682 (ifp->if_capenable & IFCAP_POLLING) && 1683 #endif 1684 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */ 1685 CSR_WRITE_4(sc, VGE_IMR, 0); 1686 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1687 vge_poll(ifp, 0, 1); 1688 goto done; 1689 } 1690 1691 #endif /* DEVICE_POLLING */ 1692 1693 /* Disable interrupts */ 1694 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1695 1696 for (;;) { 1697 1698 status = CSR_READ_4(sc, VGE_ISR); 1699 /* If the card has gone away the read returns 0xffff. */ 1700 if (status == 0xFFFFFFFF) 1701 break; 1702 1703 if (status) 1704 CSR_WRITE_4(sc, VGE_ISR, status); 1705 1706 if ((status & VGE_INTRS) == 0) 1707 break; 1708 1709 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1710 vge_rxeof(sc); 1711 1712 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1713 vge_rxeof(sc); 1714 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1715 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1716 } 1717 1718 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1719 vge_txeof(sc); 1720 1721 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1722 vge_init(sc); 1723 1724 if (status & VGE_ISR_LINKSTS) 1725 vge_tick(sc); 1726 } 1727 1728 /* Re-enable interrupts */ 1729 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1730 1731 #ifdef DEVICE_POLLING 1732 done: 1733 #endif 1734 VGE_UNLOCK(sc); 1735 1736 #if __FreeBSD_version < 502114 1737 if (ifp->if_snd.ifq_head != NULL) 1738 #else 1739 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1740 #endif 1741 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1742 1743 return; 1744 } 1745 1746 static int 1747 vge_encap(sc, m_head, idx) 1748 struct vge_softc *sc; 1749 struct mbuf *m_head; 1750 int idx; 1751 { 1752 struct mbuf *m_new = NULL; 1753 struct vge_dmaload_arg arg; 1754 bus_dmamap_t map; 1755 int error; 1756 struct m_tag *mtag; 1757 1758 if (sc->vge_ldata.vge_tx_free <= 2) 1759 return (EFBIG); 1760 1761 arg.vge_flags = 0; 1762 1763 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1764 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1765 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1766 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1767 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1768 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1769 1770 arg.sc = sc; 1771 arg.vge_idx = idx; 1772 arg.vge_m0 = m_head; 1773 arg.vge_maxsegs = VGE_TX_FRAGS; 1774 1775 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1776 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1777 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1778 1779 if (error && error != EFBIG) { 1780 printf("vge%d: can't map mbuf (error %d)\n", 1781 sc->vge_unit, error); 1782 return (ENOBUFS); 1783 } 1784 1785 /* Too many segments to map, coalesce into a single mbuf */ 1786 1787 if (error || arg.vge_maxsegs == 0) { 1788 m_new = m_defrag(m_head, M_DONTWAIT); 1789 if (m_new == NULL) 1790 return (1); 1791 else 1792 m_head = m_new; 1793 1794 arg.sc = sc; 1795 arg.vge_m0 = m_head; 1796 arg.vge_idx = idx; 1797 arg.vge_maxsegs = 1; 1798 1799 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1800 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1801 if (error) { 1802 printf("vge%d: can't map mbuf (error %d)\n", 1803 sc->vge_unit, error); 1804 return (EFBIG); 1805 } 1806 } 1807 1808 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1809 sc->vge_ldata.vge_tx_free--; 1810 1811 /* 1812 * Set up hardware VLAN tagging. 1813 */ 1814 1815 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1816 if (mtag != NULL) 1817 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1818 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1819 1820 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1821 1822 return (0); 1823 } 1824 1825 static void 1826 vge_tx_task(arg, npending) 1827 void *arg; 1828 int npending; 1829 { 1830 struct ifnet *ifp; 1831 1832 ifp = arg; 1833 vge_start(ifp); 1834 1835 return; 1836 } 1837 1838 /* 1839 * Main transmit routine. 1840 */ 1841 1842 static void 1843 vge_start(ifp) 1844 struct ifnet *ifp; 1845 { 1846 struct vge_softc *sc; 1847 struct mbuf *m_head = NULL; 1848 int idx, pidx = 0; 1849 1850 sc = ifp->if_softc; 1851 VGE_LOCK(sc); 1852 1853 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) { 1854 VGE_UNLOCK(sc); 1855 return; 1856 } 1857 1858 #if __FreeBSD_version < 502114 1859 if (ifp->if_snd.ifq_head == NULL) { 1860 #else 1861 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1862 #endif 1863 VGE_UNLOCK(sc); 1864 return; 1865 } 1866 1867 idx = sc->vge_ldata.vge_tx_prodidx; 1868 1869 pidx = idx - 1; 1870 if (pidx < 0) 1871 pidx = VGE_TX_DESC_CNT - 1; 1872 1873 1874 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1875 #if __FreeBSD_version < 502114 1876 IF_DEQUEUE(&ifp->if_snd, m_head); 1877 #else 1878 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1879 #endif 1880 if (m_head == NULL) 1881 break; 1882 1883 if (vge_encap(sc, m_head, idx)) { 1884 #if __FreeBSD_version >= 502114 1885 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1886 #else 1887 IF_PREPEND(&ifp->if_snd, m_head); 1888 #endif 1889 ifp->if_flags |= IFF_OACTIVE; 1890 break; 1891 } 1892 1893 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1894 htole16(VGE_TXDESC_Q); 1895 1896 pidx = idx; 1897 VGE_TX_DESC_INC(idx); 1898 1899 /* 1900 * If there's a BPF listener, bounce a copy of this frame 1901 * to him. 1902 */ 1903 BPF_MTAP(ifp, m_head); 1904 } 1905 1906 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1907 VGE_UNLOCK(sc); 1908 return; 1909 } 1910 1911 /* Flush the TX descriptors */ 1912 1913 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1914 sc->vge_ldata.vge_tx_list_map, 1915 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1916 1917 /* Issue a transmit command. */ 1918 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1919 1920 sc->vge_ldata.vge_tx_prodidx = idx; 1921 1922 /* 1923 * Use the countdown timer for interrupt moderation. 1924 * 'TX done' interrupts are disabled. Instead, we reset the 1925 * countdown timer, which will begin counting until it hits 1926 * the value in the SSTIMER register, and then trigger an 1927 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1928 * the timer count is reloaded. Only when the transmitter 1929 * is idle will the timer hit 0 and an interrupt fire. 1930 */ 1931 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1932 1933 VGE_UNLOCK(sc); 1934 1935 /* 1936 * Set a timeout in case the chip goes out to lunch. 1937 */ 1938 ifp->if_timer = 5; 1939 1940 return; 1941 } 1942 1943 static void 1944 vge_init(xsc) 1945 void *xsc; 1946 { 1947 struct vge_softc *sc = xsc; 1948 struct ifnet *ifp = &sc->arpcom.ac_if; 1949 struct mii_data *mii; 1950 int i; 1951 1952 VGE_LOCK(sc); 1953 mii = device_get_softc(sc->vge_miibus); 1954 1955 /* 1956 * Cancel pending I/O and free all RX/TX buffers. 1957 */ 1958 vge_stop(sc); 1959 vge_reset(sc); 1960 1961 /* 1962 * Initialize the RX and TX descriptors and mbufs. 1963 */ 1964 1965 vge_rx_list_init(sc); 1966 vge_tx_list_init(sc); 1967 1968 /* Set our station address */ 1969 for (i = 0; i < ETHER_ADDR_LEN; i++) 1970 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1971 1972 /* 1973 * Set receive FIFO threshold. Also allow transmission and 1974 * reception of VLAN tagged frames. 1975 */ 1976 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1977 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1978 1979 /* Set DMA burst length */ 1980 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1981 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1982 1983 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1984 1985 /* Set collision backoff algorithm */ 1986 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1987 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1988 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1989 1990 /* Disable LPSEL field in priority resolution */ 1991 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1992 1993 /* 1994 * Load the addresses of the DMA queues into the chip. 1995 * Note that we only use one transmit queue. 1996 */ 1997 1998 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1999 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2000 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2001 2002 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2003 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2004 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2005 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2006 2007 /* Enable and wake up the RX descriptor queue */ 2008 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2009 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2010 2011 /* Enable the TX descriptor queue */ 2012 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2013 2014 /* Set up the receive filter -- allow large frames for VLANs. */ 2015 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2016 2017 /* If we want promiscuous mode, set the allframes bit. */ 2018 if (ifp->if_flags & IFF_PROMISC) { 2019 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2020 } 2021 2022 /* Set capture broadcast bit to capture broadcast frames. */ 2023 if (ifp->if_flags & IFF_BROADCAST) { 2024 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2025 } 2026 2027 /* Set multicast bit to capture multicast frames. */ 2028 if (ifp->if_flags & IFF_MULTICAST) { 2029 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2030 } 2031 2032 /* Init the cam filter. */ 2033 vge_cam_clear(sc); 2034 2035 /* Init the multicast filter. */ 2036 vge_setmulti(sc); 2037 2038 /* Enable flow control */ 2039 2040 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2041 2042 /* Enable jumbo frame reception (if desired) */ 2043 2044 /* Start the MAC. */ 2045 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2046 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2047 CSR_WRITE_1(sc, VGE_CRS0, 2048 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2049 2050 /* 2051 * Configure one-shot timer for microsecond 2052 * resulution and load it for 500 usecs. 2053 */ 2054 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2055 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2056 2057 /* 2058 * Configure interrupt moderation for receive. Enable 2059 * the holdoff counter and load it, and set the RX 2060 * suppression count to the number of descriptors we 2061 * want to allow before triggering an interrupt. 2062 * The holdoff timer is in units of 20 usecs. 2063 */ 2064 2065 #ifdef notyet 2066 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2067 /* Select the interrupt holdoff timer page. */ 2068 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2069 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2070 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2071 2072 /* Enable use of the holdoff timer. */ 2073 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2074 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2075 2076 /* Select the RX suppression threshold page. */ 2077 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2078 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2079 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2080 2081 /* Restore the page select bits. */ 2082 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2083 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2084 #endif 2085 2086 #ifdef DEVICE_POLLING 2087 /* 2088 * Disable interrupts if we are polling. 2089 */ 2090 if (ifp->if_flags & IFF_POLLING) { 2091 CSR_WRITE_4(sc, VGE_IMR, 0); 2092 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2093 } else /* otherwise ... */ 2094 #endif /* DEVICE_POLLING */ 2095 { 2096 /* 2097 * Enable interrupts. 2098 */ 2099 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2100 CSR_WRITE_4(sc, VGE_ISR, 0); 2101 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2102 } 2103 2104 mii_mediachg(mii); 2105 2106 ifp->if_flags |= IFF_RUNNING; 2107 ifp->if_flags &= ~IFF_OACTIVE; 2108 2109 sc->vge_if_flags = 0; 2110 sc->vge_link = 0; 2111 2112 VGE_UNLOCK(sc); 2113 2114 return; 2115 } 2116 2117 /* 2118 * Set media options. 2119 */ 2120 static int 2121 vge_ifmedia_upd(ifp) 2122 struct ifnet *ifp; 2123 { 2124 struct vge_softc *sc; 2125 struct mii_data *mii; 2126 2127 sc = ifp->if_softc; 2128 mii = device_get_softc(sc->vge_miibus); 2129 mii_mediachg(mii); 2130 2131 return (0); 2132 } 2133 2134 /* 2135 * Report current media status. 2136 */ 2137 static void 2138 vge_ifmedia_sts(ifp, ifmr) 2139 struct ifnet *ifp; 2140 struct ifmediareq *ifmr; 2141 { 2142 struct vge_softc *sc; 2143 struct mii_data *mii; 2144 2145 sc = ifp->if_softc; 2146 mii = device_get_softc(sc->vge_miibus); 2147 2148 mii_pollstat(mii); 2149 ifmr->ifm_active = mii->mii_media_active; 2150 ifmr->ifm_status = mii->mii_media_status; 2151 2152 return; 2153 } 2154 2155 static void 2156 vge_miibus_statchg(dev) 2157 device_t dev; 2158 { 2159 struct vge_softc *sc; 2160 struct mii_data *mii; 2161 struct ifmedia_entry *ife; 2162 2163 sc = device_get_softc(dev); 2164 mii = device_get_softc(sc->vge_miibus); 2165 ife = mii->mii_media.ifm_cur; 2166 2167 /* 2168 * If the user manually selects a media mode, we need to turn 2169 * on the forced MAC mode bit in the DIAGCTL register. If the 2170 * user happens to choose a full duplex mode, we also need to 2171 * set the 'force full duplex' bit. This applies only to 2172 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2173 * mode is disabled, and in 1000baseT mode, full duplex is 2174 * always implied, so we turn on the forced mode bit but leave 2175 * the FDX bit cleared. 2176 */ 2177 2178 switch (IFM_SUBTYPE(ife->ifm_media)) { 2179 case IFM_AUTO: 2180 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2181 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2182 break; 2183 case IFM_1000_T: 2184 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2185 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2186 break; 2187 case IFM_100_TX: 2188 case IFM_10_T: 2189 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2190 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2191 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2192 } else { 2193 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2194 } 2195 break; 2196 default: 2197 device_printf(dev, "unknown media type: %x\n", 2198 IFM_SUBTYPE(ife->ifm_media)); 2199 break; 2200 } 2201 2202 return; 2203 } 2204 2205 static int 2206 vge_ioctl(ifp, command, data) 2207 struct ifnet *ifp; 2208 u_long command; 2209 caddr_t data; 2210 { 2211 struct vge_softc *sc = ifp->if_softc; 2212 struct ifreq *ifr = (struct ifreq *) data; 2213 struct mii_data *mii; 2214 int error = 0; 2215 2216 switch (command) { 2217 case SIOCSIFMTU: 2218 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2219 error = EINVAL; 2220 ifp->if_mtu = ifr->ifr_mtu; 2221 break; 2222 case SIOCSIFFLAGS: 2223 if (ifp->if_flags & IFF_UP) { 2224 if (ifp->if_flags & IFF_RUNNING && 2225 ifp->if_flags & IFF_PROMISC && 2226 !(sc->vge_if_flags & IFF_PROMISC)) { 2227 CSR_SETBIT_1(sc, VGE_RXCTL, 2228 VGE_RXCTL_RX_PROMISC); 2229 vge_setmulti(sc); 2230 } else if (ifp->if_flags & IFF_RUNNING && 2231 !(ifp->if_flags & IFF_PROMISC) && 2232 sc->vge_if_flags & IFF_PROMISC) { 2233 CSR_CLRBIT_1(sc, VGE_RXCTL, 2234 VGE_RXCTL_RX_PROMISC); 2235 vge_setmulti(sc); 2236 } else 2237 vge_init(sc); 2238 } else { 2239 if (ifp->if_flags & IFF_RUNNING) 2240 vge_stop(sc); 2241 } 2242 sc->vge_if_flags = ifp->if_flags; 2243 break; 2244 case SIOCADDMULTI: 2245 case SIOCDELMULTI: 2246 vge_setmulti(sc); 2247 break; 2248 case SIOCGIFMEDIA: 2249 case SIOCSIFMEDIA: 2250 mii = device_get_softc(sc->vge_miibus); 2251 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2252 break; 2253 case SIOCSIFCAP: 2254 #ifdef IFCAP_POLLING 2255 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING); 2256 #else 2257 ifp->if_capenable &= ~(IFCAP_HWCSUM); 2258 #endif 2259 ifp->if_capenable |= 2260 #ifdef IFCAP_POLLING 2261 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING); 2262 #else 2263 ifr->ifr_reqcap & (IFCAP_HWCSUM); 2264 #endif 2265 if (ifp->if_capenable & IFCAP_TXCSUM) 2266 ifp->if_hwassist = VGE_CSUM_FEATURES; 2267 else 2268 ifp->if_hwassist = 0; 2269 if (ifp->if_flags & IFF_RUNNING) 2270 vge_init(sc); 2271 break; 2272 default: 2273 error = ether_ioctl(ifp, command, data); 2274 break; 2275 } 2276 2277 return (error); 2278 } 2279 2280 static void 2281 vge_watchdog(ifp) 2282 struct ifnet *ifp; 2283 { 2284 struct vge_softc *sc; 2285 2286 sc = ifp->if_softc; 2287 VGE_LOCK(sc); 2288 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2289 ifp->if_oerrors++; 2290 2291 vge_txeof(sc); 2292 vge_rxeof(sc); 2293 2294 vge_init(sc); 2295 2296 VGE_UNLOCK(sc); 2297 2298 return; 2299 } 2300 2301 /* 2302 * Stop the adapter and free any mbufs allocated to the 2303 * RX and TX lists. 2304 */ 2305 static void 2306 vge_stop(sc) 2307 struct vge_softc *sc; 2308 { 2309 register int i; 2310 struct ifnet *ifp; 2311 2312 VGE_LOCK(sc); 2313 ifp = &sc->arpcom.ac_if; 2314 ifp->if_timer = 0; 2315 2316 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2317 #ifdef DEVICE_POLLING 2318 ether_poll_deregister(ifp); 2319 #endif /* DEVICE_POLLING */ 2320 2321 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2322 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2323 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2324 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2325 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2326 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2327 2328 if (sc->vge_head != NULL) { 2329 m_freem(sc->vge_head); 2330 sc->vge_head = sc->vge_tail = NULL; 2331 } 2332 2333 /* Free the TX list buffers. */ 2334 2335 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2336 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2337 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2338 sc->vge_ldata.vge_tx_dmamap[i]); 2339 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2340 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2341 } 2342 } 2343 2344 /* Free the RX list buffers. */ 2345 2346 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2347 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2348 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2349 sc->vge_ldata.vge_rx_dmamap[i]); 2350 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2351 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2352 } 2353 } 2354 2355 VGE_UNLOCK(sc); 2356 2357 return; 2358 } 2359 2360 /* 2361 * Device suspend routine. Stop the interface and save some PCI 2362 * settings in case the BIOS doesn't restore them properly on 2363 * resume. 2364 */ 2365 static int 2366 vge_suspend(dev) 2367 device_t dev; 2368 { 2369 struct vge_softc *sc; 2370 int i; 2371 2372 sc = device_get_softc(dev); 2373 2374 vge_stop(sc); 2375 2376 for (i = 0; i < 5; i++) 2377 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 2378 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 2379 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 2380 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 2381 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 2382 2383 sc->suspended = 1; 2384 2385 return (0); 2386 } 2387 2388 /* 2389 * Device resume routine. Restore some PCI settings in case the BIOS 2390 * doesn't, re-enable busmastering, and restart the interface if 2391 * appropriate. 2392 */ 2393 static int 2394 vge_resume(dev) 2395 device_t dev; 2396 { 2397 struct vge_softc *sc; 2398 struct ifnet *ifp; 2399 int i; 2400 2401 sc = device_get_softc(dev); 2402 ifp = &sc->arpcom.ac_if; 2403 2404 /* better way to do this? */ 2405 for (i = 0; i < 5; i++) 2406 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 2407 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 2408 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 2409 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 2410 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 2411 2412 /* reenable busmastering */ 2413 pci_enable_busmaster(dev); 2414 pci_enable_io(dev, SYS_RES_MEMORY); 2415 2416 /* reinitialize interface if necessary */ 2417 if (ifp->if_flags & IFF_UP) 2418 vge_init(sc); 2419 2420 sc->suspended = 0; 2421 2422 return (0); 2423 } 2424 2425 /* 2426 * Stop all chip I/O so that the kernel's probe routines don't 2427 * get confused by errant DMAs when rebooting. 2428 */ 2429 static void 2430 vge_shutdown(dev) 2431 device_t dev; 2432 { 2433 struct vge_softc *sc; 2434 2435 sc = device_get_softc(dev); 2436 2437 vge_stop(sc); 2438 } 2439