1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #ifdef HAVE_KERNEL_OPTION_HEADERS 84 #include "opt_device_polling.h" 85 #endif 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/module.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 97 #include <net/if.h> 98 #include <net/if_arp.h> 99 #include <net/ethernet.h> 100 #include <net/if_dl.h> 101 #include <net/if_media.h> 102 #include <net/if_types.h> 103 #include <net/if_vlan_var.h> 104 105 #include <net/bpf.h> 106 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <sys/bus.h> 110 #include <sys/rman.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 115 #include <dev/pci/pcireg.h> 116 #include <dev/pci/pcivar.h> 117 118 MODULE_DEPEND(vge, pci, 1, 1, 1); 119 MODULE_DEPEND(vge, ether, 1, 1, 1); 120 MODULE_DEPEND(vge, miibus, 1, 1, 1); 121 122 /* "device miibus" required. See GENERIC if you get errors here. */ 123 #include "miibus_if.h" 124 125 #include <dev/vge/if_vgereg.h> 126 #include <dev/vge/if_vgevar.h> 127 128 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129 130 /* 131 * Various supported device vendors/types and their names. 132 */ 133 static struct vge_type vge_devs[] = { 134 { VIA_VENDORID, VIA_DEVICEID_61XX, 135 "VIA Networking Gigabit Ethernet" }, 136 { 0, 0, NULL } 137 }; 138 139 static int vge_probe (device_t); 140 static int vge_attach (device_t); 141 static int vge_detach (device_t); 142 143 static int vge_encap (struct vge_softc *, struct mbuf *, int); 144 145 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 146 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 147 bus_size_t, int); 148 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 149 bus_size_t, int); 150 static int vge_allocmem (device_t, struct vge_softc *); 151 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 152 static int vge_rx_list_init (struct vge_softc *); 153 static int vge_tx_list_init (struct vge_softc *); 154 #ifdef VGE_FIXUP_RX 155 static __inline void vge_fixup_rx 156 (struct mbuf *); 157 #endif 158 static int vge_rxeof (struct vge_softc *); 159 static void vge_txeof (struct vge_softc *); 160 static void vge_intr (void *); 161 static void vge_tick (void *); 162 static void vge_start (struct ifnet *); 163 static void vge_start_locked (struct ifnet *); 164 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 165 static void vge_init (void *); 166 static void vge_init_locked (struct vge_softc *); 167 static void vge_stop (struct vge_softc *); 168 static void vge_watchdog (void *); 169 static int vge_suspend (device_t); 170 static int vge_resume (device_t); 171 static int vge_shutdown (device_t); 172 static int vge_ifmedia_upd (struct ifnet *); 173 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175 #ifdef VGE_EEPROM 176 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177 #endif 178 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180 static void vge_miipoll_start (struct vge_softc *); 181 static void vge_miipoll_stop (struct vge_softc *); 182 static int vge_miibus_readreg (device_t, int, int); 183 static int vge_miibus_writereg (device_t, int, int, int); 184 static void vge_miibus_statchg (device_t); 185 186 static void vge_cam_clear (struct vge_softc *); 187 static int vge_cam_set (struct vge_softc *, uint8_t *); 188 static void vge_setmulti (struct vge_softc *); 189 static void vge_reset (struct vge_softc *); 190 191 #define VGE_PCI_LOIO 0x10 192 #define VGE_PCI_LOMEM 0x14 193 194 static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213 }; 214 215 static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219 }; 220 221 static devclass_t vge_devclass; 222 223 DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226 #ifdef VGE_EEPROM 227 /* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230 static void 231 vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235 { 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275 } 276 #endif 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 #ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301 #else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304 #endif 305 } 306 307 static void 308 vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310 { 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325 } 326 327 static void 328 vge_miipoll_start(sc) 329 struct vge_softc *sc; 330 { 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365 } 366 367 static int 368 vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371 { 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK_ASSERT(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 404 return (rval); 405 } 406 407 static int 408 vge_miibus_writereg(dev, phy, reg, data) 409 device_t dev; 410 int phy, reg, data; 411 { 412 struct vge_softc *sc; 413 int i, rval = 0; 414 415 sc = device_get_softc(dev); 416 417 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 418 return(0); 419 420 VGE_LOCK_ASSERT(sc); 421 vge_miipoll_stop(sc); 422 423 /* Specify the register we want to write. */ 424 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 425 426 /* Specify the data we want to write. */ 427 CSR_WRITE_2(sc, VGE_MIIDATA, data); 428 429 /* Issue write command. */ 430 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 431 432 /* Wait for the write command bit to self-clear. */ 433 for (i = 0; i < VGE_TIMEOUT; i++) { 434 DELAY(1); 435 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 436 break; 437 } 438 439 if (i == VGE_TIMEOUT) { 440 device_printf(sc->vge_dev, "MII write timed out\n"); 441 rval = EIO; 442 } 443 444 vge_miipoll_start(sc); 445 446 return (rval); 447 } 448 449 static void 450 vge_cam_clear(sc) 451 struct vge_softc *sc; 452 { 453 int i; 454 455 /* 456 * Turn off all the mask bits. This tells the chip 457 * that none of the entries in the CAM filter are valid. 458 * desired entries will be enabled as we fill the filter in. 459 */ 460 461 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 462 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 463 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 464 for (i = 0; i < 8; i++) 465 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 466 467 /* Clear the VLAN filter too. */ 468 469 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 470 for (i = 0; i < 8; i++) 471 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 472 473 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 474 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 475 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 476 477 sc->vge_camidx = 0; 478 479 return; 480 } 481 482 static int 483 vge_cam_set(sc, addr) 484 struct vge_softc *sc; 485 uint8_t *addr; 486 { 487 int i, error = 0; 488 489 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 490 return(ENOSPC); 491 492 /* Select the CAM data page. */ 493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 495 496 /* Set the filter entry we want to update and enable writing. */ 497 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 498 499 /* Write the address to the CAM registers */ 500 for (i = 0; i < ETHER_ADDR_LEN; i++) 501 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 502 503 /* Issue a write command. */ 504 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 505 506 /* Wake for it to clear. */ 507 for (i = 0; i < VGE_TIMEOUT; i++) { 508 DELAY(1); 509 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 510 break; 511 } 512 513 if (i == VGE_TIMEOUT) { 514 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 515 error = EIO; 516 goto fail; 517 } 518 519 /* Select the CAM mask page. */ 520 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 521 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 522 523 /* Set the mask bit that enables this filter. */ 524 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 525 1<<(sc->vge_camidx & 7)); 526 527 sc->vge_camidx++; 528 529 fail: 530 /* Turn off access to CAM. */ 531 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 532 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 533 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 534 535 return (error); 536 } 537 538 /* 539 * Program the multicast filter. We use the 64-entry CAM filter 540 * for perfect filtering. If there's more than 64 multicast addresses, 541 * we use the hash filter insted. 542 */ 543 static void 544 vge_setmulti(sc) 545 struct vge_softc *sc; 546 { 547 struct ifnet *ifp; 548 int error = 0/*, h = 0*/; 549 struct ifmultiaddr *ifma; 550 u_int32_t h, hashes[2] = { 0, 0 }; 551 552 ifp = sc->vge_ifp; 553 554 /* First, zot all the multicast entries. */ 555 vge_cam_clear(sc); 556 CSR_WRITE_4(sc, VGE_MAR0, 0); 557 CSR_WRITE_4(sc, VGE_MAR1, 0); 558 559 /* 560 * If the user wants allmulti or promisc mode, enable reception 561 * of all multicast frames. 562 */ 563 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 564 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 565 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 566 return; 567 } 568 569 /* Now program new ones */ 570 if_maddr_rlock(ifp); 571 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 572 if (ifma->ifma_addr->sa_family != AF_LINK) 573 continue; 574 error = vge_cam_set(sc, 575 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 576 if (error) 577 break; 578 } 579 580 /* If there were too many addresses, use the hash filter. */ 581 if (error) { 582 vge_cam_clear(sc); 583 584 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 585 if (ifma->ifma_addr->sa_family != AF_LINK) 586 continue; 587 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 588 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 589 if (h < 32) 590 hashes[0] |= (1 << h); 591 else 592 hashes[1] |= (1 << (h - 32)); 593 } 594 595 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 596 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 597 } 598 if_maddr_runlock(ifp); 599 600 return; 601 } 602 603 static void 604 vge_reset(sc) 605 struct vge_softc *sc; 606 { 607 register int i; 608 609 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 610 611 for (i = 0; i < VGE_TIMEOUT; i++) { 612 DELAY(5); 613 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 614 break; 615 } 616 617 if (i == VGE_TIMEOUT) { 618 device_printf(sc->vge_dev, "soft reset timed out"); 619 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 620 DELAY(2000); 621 } 622 623 DELAY(5000); 624 625 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 626 627 for (i = 0; i < VGE_TIMEOUT; i++) { 628 DELAY(5); 629 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 630 break; 631 } 632 633 if (i == VGE_TIMEOUT) { 634 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 635 return; 636 } 637 638 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 639 640 return; 641 } 642 643 /* 644 * Probe for a VIA gigabit chip. Check the PCI vendor and device 645 * IDs against our list and return a device name if we find a match. 646 */ 647 static int 648 vge_probe(dev) 649 device_t dev; 650 { 651 struct vge_type *t; 652 653 t = vge_devs; 654 655 while (t->vge_name != NULL) { 656 if ((pci_get_vendor(dev) == t->vge_vid) && 657 (pci_get_device(dev) == t->vge_did)) { 658 device_set_desc(dev, t->vge_name); 659 return (BUS_PROBE_DEFAULT); 660 } 661 t++; 662 } 663 664 return (ENXIO); 665 } 666 667 static void 668 vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 669 void *arg; 670 bus_dma_segment_t *segs; 671 int nseg; 672 bus_size_t mapsize; 673 int error; 674 { 675 676 struct vge_dmaload_arg *ctx; 677 struct vge_rx_desc *d = NULL; 678 679 if (error) 680 return; 681 682 ctx = arg; 683 684 /* Signal error to caller if there's too many segments */ 685 if (nseg > ctx->vge_maxsegs) { 686 ctx->vge_maxsegs = 0; 687 return; 688 } 689 690 /* 691 * Map the segment array into descriptors. 692 */ 693 694 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 695 696 /* If this descriptor is still owned by the chip, bail. */ 697 698 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 699 device_printf(ctx->sc->vge_dev, 700 "tried to map busy descriptor\n"); 701 ctx->vge_maxsegs = 0; 702 return; 703 } 704 705 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 706 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 707 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 708 d->vge_sts = 0; 709 d->vge_ctl = 0; 710 711 ctx->vge_maxsegs = 1; 712 713 return; 714 } 715 716 static void 717 vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 718 void *arg; 719 bus_dma_segment_t *segs; 720 int nseg; 721 bus_size_t mapsize; 722 int error; 723 { 724 struct vge_dmaload_arg *ctx; 725 struct vge_tx_desc *d = NULL; 726 struct vge_tx_frag *f; 727 int i = 0; 728 729 if (error) 730 return; 731 732 ctx = arg; 733 734 /* Signal error to caller if there's too many segments */ 735 if (nseg > ctx->vge_maxsegs) { 736 ctx->vge_maxsegs = 0; 737 return; 738 } 739 740 /* Map the segment array into descriptors. */ 741 742 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 743 744 /* If this descriptor is still owned by the chip, bail. */ 745 746 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 747 ctx->vge_maxsegs = 0; 748 return; 749 } 750 751 for (i = 0; i < nseg; i++) { 752 f = &d->vge_frag[i]; 753 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 754 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 755 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 756 } 757 758 /* Argh. This chip does not autopad short frames */ 759 760 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 761 f = &d->vge_frag[i]; 762 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 763 ctx->vge_m0->m_pkthdr.len)); 764 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 765 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 766 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 767 i++; 768 } 769 770 /* 771 * When telling the chip how many segments there are, we 772 * must use nsegs + 1 instead of just nsegs. Darned if I 773 * know why. 774 */ 775 i++; 776 777 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 778 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 779 780 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 781 d->vge_ctl |= VGE_TDCTL_JUMBO; 782 783 ctx->vge_maxsegs = nseg; 784 785 return; 786 } 787 788 /* 789 * Map a single buffer address. 790 */ 791 792 static void 793 vge_dma_map_addr(arg, segs, nseg, error) 794 void *arg; 795 bus_dma_segment_t *segs; 796 int nseg; 797 int error; 798 { 799 bus_addr_t *addr; 800 801 if (error) 802 return; 803 804 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 805 addr = arg; 806 *addr = segs->ds_addr; 807 808 return; 809 } 810 811 static int 812 vge_allocmem(dev, sc) 813 device_t dev; 814 struct vge_softc *sc; 815 { 816 int error; 817 int nseg; 818 int i; 819 820 /* 821 * Allocate map for RX mbufs. 822 */ 823 nseg = 32; 824 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 825 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 826 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 827 NULL, NULL, &sc->vge_ldata.vge_mtag); 828 if (error) { 829 device_printf(dev, "could not allocate dma tag\n"); 830 return (ENOMEM); 831 } 832 833 /* 834 * Allocate map for TX descriptor list. 835 */ 836 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 837 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 838 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 839 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 840 if (error) { 841 device_printf(dev, "could not allocate dma tag\n"); 842 return (ENOMEM); 843 } 844 845 /* Allocate DMA'able memory for the TX ring */ 846 847 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 848 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 849 &sc->vge_ldata.vge_tx_list_map); 850 if (error) 851 return (ENOMEM); 852 853 /* Load the map for the TX ring. */ 854 855 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 856 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 857 VGE_TX_LIST_SZ, vge_dma_map_addr, 858 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 859 860 /* Create DMA maps for TX buffers */ 861 862 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 863 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 864 &sc->vge_ldata.vge_tx_dmamap[i]); 865 if (error) { 866 device_printf(dev, "can't create DMA map for TX\n"); 867 return (ENOMEM); 868 } 869 } 870 871 /* 872 * Allocate map for RX descriptor list. 873 */ 874 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 875 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 876 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 877 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 878 if (error) { 879 device_printf(dev, "could not allocate dma tag\n"); 880 return (ENOMEM); 881 } 882 883 /* Allocate DMA'able memory for the RX ring */ 884 885 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 886 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 887 &sc->vge_ldata.vge_rx_list_map); 888 if (error) 889 return (ENOMEM); 890 891 /* Load the map for the RX ring. */ 892 893 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 894 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 895 VGE_TX_LIST_SZ, vge_dma_map_addr, 896 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 897 898 /* Create DMA maps for RX buffers */ 899 900 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 901 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 902 &sc->vge_ldata.vge_rx_dmamap[i]); 903 if (error) { 904 device_printf(dev, "can't create DMA map for RX\n"); 905 return (ENOMEM); 906 } 907 } 908 909 return (0); 910 } 911 912 /* 913 * Attach the interface. Allocate softc structures, do ifmedia 914 * setup and ethernet/BPF attach. 915 */ 916 static int 917 vge_attach(dev) 918 device_t dev; 919 { 920 u_char eaddr[ETHER_ADDR_LEN]; 921 struct vge_softc *sc; 922 struct ifnet *ifp; 923 int unit, error = 0, rid; 924 925 sc = device_get_softc(dev); 926 unit = device_get_unit(dev); 927 sc->vge_dev = dev; 928 929 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 930 MTX_DEF); 931 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 932 933 /* 934 * Map control/status registers. 935 */ 936 pci_enable_busmaster(dev); 937 938 rid = VGE_PCI_LOMEM; 939 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 940 0, ~0, 1, RF_ACTIVE); 941 942 if (sc->vge_res == NULL) { 943 printf ("vge%d: couldn't map ports/memory\n", unit); 944 error = ENXIO; 945 goto fail; 946 } 947 948 /* Allocate interrupt */ 949 rid = 0; 950 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 951 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 952 953 if (sc->vge_irq == NULL) { 954 printf("vge%d: couldn't map interrupt\n", unit); 955 error = ENXIO; 956 goto fail; 957 } 958 959 /* Reset the adapter. */ 960 vge_reset(sc); 961 962 /* 963 * Get station address from the EEPROM. 964 */ 965 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 966 967 /* 968 * Allocate the parent bus DMA tag appropriate for PCI. 969 */ 970 #define VGE_NSEG_NEW 32 971 error = bus_dma_tag_create(NULL, /* parent */ 972 1, 0, /* alignment, boundary */ 973 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 974 BUS_SPACE_MAXADDR, /* highaddr */ 975 NULL, NULL, /* filter, filterarg */ 976 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 977 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 978 BUS_DMA_ALLOCNOW, /* flags */ 979 NULL, NULL, /* lockfunc, lockarg */ 980 &sc->vge_parent_tag); 981 if (error) 982 goto fail; 983 984 error = vge_allocmem(dev, sc); 985 986 if (error) 987 goto fail; 988 989 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 990 if (ifp == NULL) { 991 device_printf(dev, "can not if_alloc()\n"); 992 error = ENOSPC; 993 goto fail; 994 } 995 996 /* Do MII setup */ 997 if (mii_phy_probe(dev, &sc->vge_miibus, 998 vge_ifmedia_upd, vge_ifmedia_sts)) { 999 device_printf(dev, "MII without any phy!\n"); 1000 error = ENXIO; 1001 goto fail; 1002 } 1003 1004 ifp->if_softc = sc; 1005 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1006 ifp->if_mtu = ETHERMTU; 1007 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1008 ifp->if_ioctl = vge_ioctl; 1009 ifp->if_capabilities = IFCAP_VLAN_MTU; 1010 ifp->if_start = vge_start; 1011 ifp->if_hwassist = VGE_CSUM_FEATURES; 1012 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1013 ifp->if_capenable = ifp->if_capabilities; 1014 #ifdef DEVICE_POLLING 1015 ifp->if_capabilities |= IFCAP_POLLING; 1016 #endif 1017 ifp->if_init = vge_init; 1018 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1019 ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1020 IFQ_SET_READY(&ifp->if_snd); 1021 1022 /* 1023 * Call MI attach routine. 1024 */ 1025 ether_ifattach(ifp, eaddr); 1026 1027 /* Hook interrupt last to avoid having to lock softc */ 1028 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1029 NULL, vge_intr, sc, &sc->vge_intrhand); 1030 1031 if (error) { 1032 printf("vge%d: couldn't set up irq\n", unit); 1033 ether_ifdetach(ifp); 1034 goto fail; 1035 } 1036 1037 fail: 1038 if (error) 1039 vge_detach(dev); 1040 1041 return (error); 1042 } 1043 1044 /* 1045 * Shutdown hardware and free up resources. This can be called any 1046 * time after the mutex has been initialized. It is called in both 1047 * the error case in attach and the normal detach case so it needs 1048 * to be careful about only freeing resources that have actually been 1049 * allocated. 1050 */ 1051 static int 1052 vge_detach(dev) 1053 device_t dev; 1054 { 1055 struct vge_softc *sc; 1056 struct ifnet *ifp; 1057 int i; 1058 1059 sc = device_get_softc(dev); 1060 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1061 ifp = sc->vge_ifp; 1062 1063 #ifdef DEVICE_POLLING 1064 if (ifp->if_capenable & IFCAP_POLLING) 1065 ether_poll_deregister(ifp); 1066 #endif 1067 1068 /* These should only be active if attach succeeded */ 1069 if (device_is_attached(dev)) { 1070 ether_ifdetach(ifp); 1071 VGE_LOCK(sc); 1072 vge_stop(sc); 1073 VGE_UNLOCK(sc); 1074 callout_drain(&sc->vge_watchdog); 1075 } 1076 if (sc->vge_miibus) 1077 device_delete_child(dev, sc->vge_miibus); 1078 bus_generic_detach(dev); 1079 1080 if (sc->vge_intrhand) 1081 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1082 if (sc->vge_irq) 1083 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1084 if (sc->vge_res) 1085 bus_release_resource(dev, SYS_RES_MEMORY, 1086 VGE_PCI_LOMEM, sc->vge_res); 1087 if (ifp) 1088 if_free(ifp); 1089 1090 /* Unload and free the RX DMA ring memory and map */ 1091 1092 if (sc->vge_ldata.vge_rx_list_tag) { 1093 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1094 sc->vge_ldata.vge_rx_list_map); 1095 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1096 sc->vge_ldata.vge_rx_list, 1097 sc->vge_ldata.vge_rx_list_map); 1098 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1099 } 1100 1101 /* Unload and free the TX DMA ring memory and map */ 1102 1103 if (sc->vge_ldata.vge_tx_list_tag) { 1104 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1105 sc->vge_ldata.vge_tx_list_map); 1106 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1107 sc->vge_ldata.vge_tx_list, 1108 sc->vge_ldata.vge_tx_list_map); 1109 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1110 } 1111 1112 /* Destroy all the RX and TX buffer maps */ 1113 1114 if (sc->vge_ldata.vge_mtag) { 1115 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1116 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1117 sc->vge_ldata.vge_tx_dmamap[i]); 1118 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1119 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1120 sc->vge_ldata.vge_rx_dmamap[i]); 1121 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1122 } 1123 1124 if (sc->vge_parent_tag) 1125 bus_dma_tag_destroy(sc->vge_parent_tag); 1126 1127 mtx_destroy(&sc->vge_mtx); 1128 1129 return (0); 1130 } 1131 1132 static int 1133 vge_newbuf(sc, idx, m) 1134 struct vge_softc *sc; 1135 int idx; 1136 struct mbuf *m; 1137 { 1138 struct vge_dmaload_arg arg; 1139 struct mbuf *n = NULL; 1140 int i, error; 1141 1142 if (m == NULL) { 1143 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1144 if (n == NULL) 1145 return (ENOBUFS); 1146 m = n; 1147 } else 1148 m->m_data = m->m_ext.ext_buf; 1149 1150 1151 #ifdef VGE_FIXUP_RX 1152 /* 1153 * This is part of an evil trick to deal with non-x86 platforms. 1154 * The VIA chip requires RX buffers to be aligned on 32-bit 1155 * boundaries, but that will hose non-x86 machines. To get around 1156 * this, we leave some empty space at the start of each buffer 1157 * and for non-x86 hosts, we copy the buffer back two bytes 1158 * to achieve word alignment. This is slightly more efficient 1159 * than allocating a new buffer, copying the contents, and 1160 * discarding the old buffer. 1161 */ 1162 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1163 m_adj(m, VGE_ETHER_ALIGN); 1164 #else 1165 m->m_len = m->m_pkthdr.len = MCLBYTES; 1166 #endif 1167 1168 arg.sc = sc; 1169 arg.vge_idx = idx; 1170 arg.vge_maxsegs = 1; 1171 arg.vge_flags = 0; 1172 1173 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1174 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1175 &arg, BUS_DMA_NOWAIT); 1176 if (error || arg.vge_maxsegs != 1) { 1177 if (n != NULL) 1178 m_freem(n); 1179 return (ENOMEM); 1180 } 1181 1182 /* 1183 * Note: the manual fails to document the fact that for 1184 * proper opration, the driver needs to replentish the RX 1185 * DMA ring 4 descriptors at a time (rather than one at a 1186 * time, like most chips). We can allocate the new buffers 1187 * but we should not set the OWN bits until we're ready 1188 * to hand back 4 of them in one shot. 1189 */ 1190 1191 #define VGE_RXCHUNK 4 1192 sc->vge_rx_consumed++; 1193 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1194 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1195 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1196 htole32(VGE_RDSTS_OWN); 1197 sc->vge_rx_consumed = 0; 1198 } 1199 1200 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1201 1202 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1203 sc->vge_ldata.vge_rx_dmamap[idx], 1204 BUS_DMASYNC_PREREAD); 1205 1206 return (0); 1207 } 1208 1209 static int 1210 vge_tx_list_init(sc) 1211 struct vge_softc *sc; 1212 { 1213 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1214 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1215 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1216 1217 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1218 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1219 sc->vge_ldata.vge_tx_prodidx = 0; 1220 sc->vge_ldata.vge_tx_considx = 0; 1221 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1222 1223 return (0); 1224 } 1225 1226 static int 1227 vge_rx_list_init(sc) 1228 struct vge_softc *sc; 1229 { 1230 int i; 1231 1232 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1233 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1234 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1235 1236 sc->vge_rx_consumed = 0; 1237 1238 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1239 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1240 return (ENOBUFS); 1241 } 1242 1243 /* Flush the RX descriptors */ 1244 1245 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1246 sc->vge_ldata.vge_rx_list_map, 1247 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1248 1249 sc->vge_ldata.vge_rx_prodidx = 0; 1250 sc->vge_rx_consumed = 0; 1251 sc->vge_head = sc->vge_tail = NULL; 1252 1253 return (0); 1254 } 1255 1256 #ifdef VGE_FIXUP_RX 1257 static __inline void 1258 vge_fixup_rx(m) 1259 struct mbuf *m; 1260 { 1261 int i; 1262 uint16_t *src, *dst; 1263 1264 src = mtod(m, uint16_t *); 1265 dst = src - 1; 1266 1267 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1268 *dst++ = *src++; 1269 1270 m->m_data -= ETHER_ALIGN; 1271 1272 return; 1273 } 1274 #endif 1275 1276 /* 1277 * RX handler. We support the reception of jumbo frames that have 1278 * been fragmented across multiple 2K mbuf cluster buffers. 1279 */ 1280 static int 1281 vge_rxeof(sc) 1282 struct vge_softc *sc; 1283 { 1284 struct mbuf *m; 1285 struct ifnet *ifp; 1286 int i, total_len; 1287 int lim = 0; 1288 struct vge_rx_desc *cur_rx; 1289 u_int32_t rxstat, rxctl; 1290 1291 VGE_LOCK_ASSERT(sc); 1292 ifp = sc->vge_ifp; 1293 i = sc->vge_ldata.vge_rx_prodidx; 1294 1295 /* Invalidate the descriptor memory */ 1296 1297 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1298 sc->vge_ldata.vge_rx_list_map, 1299 BUS_DMASYNC_POSTREAD); 1300 1301 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1302 1303 #ifdef DEVICE_POLLING 1304 if (ifp->if_capenable & IFCAP_POLLING) { 1305 if (sc->rxcycles <= 0) 1306 break; 1307 sc->rxcycles--; 1308 } 1309 #endif 1310 1311 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1312 m = sc->vge_ldata.vge_rx_mbuf[i]; 1313 total_len = VGE_RXBYTES(cur_rx); 1314 rxstat = le32toh(cur_rx->vge_sts); 1315 rxctl = le32toh(cur_rx->vge_ctl); 1316 1317 /* Invalidate the RX mbuf and unload its map */ 1318 1319 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1320 sc->vge_ldata.vge_rx_dmamap[i], 1321 BUS_DMASYNC_POSTWRITE); 1322 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1323 sc->vge_ldata.vge_rx_dmamap[i]); 1324 1325 /* 1326 * If the 'start of frame' bit is set, this indicates 1327 * either the first fragment in a multi-fragment receive, 1328 * or an intermediate fragment. Either way, we want to 1329 * accumulate the buffers. 1330 */ 1331 if (rxstat & VGE_RXPKT_SOF) { 1332 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1333 if (sc->vge_head == NULL) 1334 sc->vge_head = sc->vge_tail = m; 1335 else { 1336 m->m_flags &= ~M_PKTHDR; 1337 sc->vge_tail->m_next = m; 1338 sc->vge_tail = m; 1339 } 1340 vge_newbuf(sc, i, NULL); 1341 VGE_RX_DESC_INC(i); 1342 continue; 1343 } 1344 1345 /* 1346 * Bad/error frames will have the RXOK bit cleared. 1347 * However, there's one error case we want to allow: 1348 * if a VLAN tagged frame arrives and the chip can't 1349 * match it against the CAM filter, it considers this 1350 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1351 * We don't want to drop the frame though: our VLAN 1352 * filtering is done in software. 1353 */ 1354 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1355 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1356 ifp->if_ierrors++; 1357 /* 1358 * If this is part of a multi-fragment packet, 1359 * discard all the pieces. 1360 */ 1361 if (sc->vge_head != NULL) { 1362 m_freem(sc->vge_head); 1363 sc->vge_head = sc->vge_tail = NULL; 1364 } 1365 vge_newbuf(sc, i, m); 1366 VGE_RX_DESC_INC(i); 1367 continue; 1368 } 1369 1370 /* 1371 * If allocating a replacement mbuf fails, 1372 * reload the current one. 1373 */ 1374 1375 if (vge_newbuf(sc, i, NULL)) { 1376 ifp->if_ierrors++; 1377 if (sc->vge_head != NULL) { 1378 m_freem(sc->vge_head); 1379 sc->vge_head = sc->vge_tail = NULL; 1380 } 1381 vge_newbuf(sc, i, m); 1382 VGE_RX_DESC_INC(i); 1383 continue; 1384 } 1385 1386 VGE_RX_DESC_INC(i); 1387 1388 if (sc->vge_head != NULL) { 1389 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1390 /* 1391 * Special case: if there's 4 bytes or less 1392 * in this buffer, the mbuf can be discarded: 1393 * the last 4 bytes is the CRC, which we don't 1394 * care about anyway. 1395 */ 1396 if (m->m_len <= ETHER_CRC_LEN) { 1397 sc->vge_tail->m_len -= 1398 (ETHER_CRC_LEN - m->m_len); 1399 m_freem(m); 1400 } else { 1401 m->m_len -= ETHER_CRC_LEN; 1402 m->m_flags &= ~M_PKTHDR; 1403 sc->vge_tail->m_next = m; 1404 } 1405 m = sc->vge_head; 1406 sc->vge_head = sc->vge_tail = NULL; 1407 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1408 } else 1409 m->m_pkthdr.len = m->m_len = 1410 (total_len - ETHER_CRC_LEN); 1411 1412 #ifdef VGE_FIXUP_RX 1413 vge_fixup_rx(m); 1414 #endif 1415 ifp->if_ipackets++; 1416 m->m_pkthdr.rcvif = ifp; 1417 1418 /* Do RX checksumming if enabled */ 1419 if (ifp->if_capenable & IFCAP_RXCSUM) { 1420 1421 /* Check IP header checksum */ 1422 if (rxctl & VGE_RDCTL_IPPKT) 1423 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1424 if (rxctl & VGE_RDCTL_IPCSUMOK) 1425 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1426 1427 /* Check TCP/UDP checksum */ 1428 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1429 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1430 m->m_pkthdr.csum_flags |= 1431 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1432 m->m_pkthdr.csum_data = 0xffff; 1433 } 1434 } 1435 1436 if (rxstat & VGE_RDSTS_VTAG) { 1437 /* 1438 * The 32-bit rxctl register is stored in little-endian. 1439 * However, the 16-bit vlan tag is stored in big-endian, 1440 * so we have to byte swap it. 1441 */ 1442 m->m_pkthdr.ether_vtag = 1443 bswap16(rxctl & VGE_RDCTL_VLANID); 1444 m->m_flags |= M_VLANTAG; 1445 } 1446 1447 VGE_UNLOCK(sc); 1448 (*ifp->if_input)(ifp, m); 1449 VGE_LOCK(sc); 1450 1451 lim++; 1452 if (lim == VGE_RX_DESC_CNT) 1453 break; 1454 1455 } 1456 1457 /* Flush the RX DMA ring */ 1458 1459 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1460 sc->vge_ldata.vge_rx_list_map, 1461 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1462 1463 sc->vge_ldata.vge_rx_prodidx = i; 1464 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1465 1466 1467 return (lim); 1468 } 1469 1470 static void 1471 vge_txeof(sc) 1472 struct vge_softc *sc; 1473 { 1474 struct ifnet *ifp; 1475 u_int32_t txstat; 1476 int idx; 1477 1478 ifp = sc->vge_ifp; 1479 idx = sc->vge_ldata.vge_tx_considx; 1480 1481 /* Invalidate the TX descriptor list */ 1482 1483 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1484 sc->vge_ldata.vge_tx_list_map, 1485 BUS_DMASYNC_POSTREAD); 1486 1487 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1488 1489 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1490 if (txstat & VGE_TDSTS_OWN) 1491 break; 1492 1493 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1494 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1495 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1496 sc->vge_ldata.vge_tx_dmamap[idx]); 1497 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1498 ifp->if_collisions++; 1499 if (txstat & VGE_TDSTS_TXERR) 1500 ifp->if_oerrors++; 1501 else 1502 ifp->if_opackets++; 1503 1504 sc->vge_ldata.vge_tx_free++; 1505 VGE_TX_DESC_INC(idx); 1506 } 1507 1508 /* No changes made to the TX ring, so no flush needed */ 1509 1510 if (idx != sc->vge_ldata.vge_tx_considx) { 1511 sc->vge_ldata.vge_tx_considx = idx; 1512 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1513 sc->vge_timer = 0; 1514 } 1515 1516 /* 1517 * If not all descriptors have been released reaped yet, 1518 * reload the timer so that we will eventually get another 1519 * interrupt that will cause us to re-enter this routine. 1520 * This is done in case the transmitter has gone idle. 1521 */ 1522 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1523 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1524 } 1525 1526 return; 1527 } 1528 1529 static void 1530 vge_tick(xsc) 1531 void *xsc; 1532 { 1533 struct vge_softc *sc; 1534 struct ifnet *ifp; 1535 struct mii_data *mii; 1536 1537 sc = xsc; 1538 ifp = sc->vge_ifp; 1539 VGE_LOCK_ASSERT(sc); 1540 mii = device_get_softc(sc->vge_miibus); 1541 1542 mii_tick(mii); 1543 if (sc->vge_link) { 1544 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1545 sc->vge_link = 0; 1546 if_link_state_change(sc->vge_ifp, 1547 LINK_STATE_DOWN); 1548 } 1549 } else { 1550 if (mii->mii_media_status & IFM_ACTIVE && 1551 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1552 sc->vge_link = 1; 1553 if_link_state_change(sc->vge_ifp, 1554 LINK_STATE_UP); 1555 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1556 vge_start_locked(ifp); 1557 } 1558 } 1559 1560 return; 1561 } 1562 1563 #ifdef DEVICE_POLLING 1564 static int 1565 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1566 { 1567 struct vge_softc *sc = ifp->if_softc; 1568 int rx_npkts = 0; 1569 1570 VGE_LOCK(sc); 1571 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1572 goto done; 1573 1574 sc->rxcycles = count; 1575 rx_npkts = vge_rxeof(sc); 1576 vge_txeof(sc); 1577 1578 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1579 vge_start_locked(ifp); 1580 1581 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1582 u_int32_t status; 1583 status = CSR_READ_4(sc, VGE_ISR); 1584 if (status == 0xFFFFFFFF) 1585 goto done; 1586 if (status) 1587 CSR_WRITE_4(sc, VGE_ISR, status); 1588 1589 /* 1590 * XXX check behaviour on receiver stalls. 1591 */ 1592 1593 if (status & VGE_ISR_TXDMA_STALL || 1594 status & VGE_ISR_RXDMA_STALL) 1595 vge_init_locked(sc); 1596 1597 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1598 vge_rxeof(sc); 1599 ifp->if_ierrors++; 1600 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1601 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1602 } 1603 } 1604 done: 1605 VGE_UNLOCK(sc); 1606 return (rx_npkts); 1607 } 1608 #endif /* DEVICE_POLLING */ 1609 1610 static void 1611 vge_intr(arg) 1612 void *arg; 1613 { 1614 struct vge_softc *sc; 1615 struct ifnet *ifp; 1616 u_int32_t status; 1617 1618 sc = arg; 1619 1620 if (sc->suspended) { 1621 return; 1622 } 1623 1624 VGE_LOCK(sc); 1625 ifp = sc->vge_ifp; 1626 1627 if (!(ifp->if_flags & IFF_UP)) { 1628 VGE_UNLOCK(sc); 1629 return; 1630 } 1631 1632 #ifdef DEVICE_POLLING 1633 if (ifp->if_capenable & IFCAP_POLLING) { 1634 VGE_UNLOCK(sc); 1635 return; 1636 } 1637 #endif 1638 1639 /* Disable interrupts */ 1640 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1641 1642 for (;;) { 1643 1644 status = CSR_READ_4(sc, VGE_ISR); 1645 /* If the card has gone away the read returns 0xffff. */ 1646 if (status == 0xFFFFFFFF) 1647 break; 1648 1649 if (status) 1650 CSR_WRITE_4(sc, VGE_ISR, status); 1651 1652 if ((status & VGE_INTRS) == 0) 1653 break; 1654 1655 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1656 vge_rxeof(sc); 1657 1658 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1659 vge_rxeof(sc); 1660 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1661 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1662 } 1663 1664 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1665 vge_txeof(sc); 1666 1667 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1668 vge_init_locked(sc); 1669 1670 if (status & VGE_ISR_LINKSTS) 1671 vge_tick(sc); 1672 } 1673 1674 /* Re-enable interrupts */ 1675 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1676 1677 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1678 vge_start_locked(ifp); 1679 1680 VGE_UNLOCK(sc); 1681 1682 return; 1683 } 1684 1685 static int 1686 vge_encap(sc, m_head, idx) 1687 struct vge_softc *sc; 1688 struct mbuf *m_head; 1689 int idx; 1690 { 1691 struct mbuf *m_new = NULL; 1692 struct vge_dmaload_arg arg; 1693 bus_dmamap_t map; 1694 int error; 1695 1696 if (sc->vge_ldata.vge_tx_free <= 2) 1697 return (EFBIG); 1698 1699 arg.vge_flags = 0; 1700 1701 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1702 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1703 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1704 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1705 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1706 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1707 1708 arg.sc = sc; 1709 arg.vge_idx = idx; 1710 arg.vge_m0 = m_head; 1711 arg.vge_maxsegs = VGE_TX_FRAGS; 1712 1713 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1714 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1715 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1716 1717 if (error && error != EFBIG) { 1718 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", error); 1719 return (ENOBUFS); 1720 } 1721 1722 /* Too many segments to map, coalesce into a single mbuf */ 1723 1724 if (error || arg.vge_maxsegs == 0) { 1725 m_new = m_defrag(m_head, M_DONTWAIT); 1726 if (m_new == NULL) 1727 return (1); 1728 else 1729 m_head = m_new; 1730 1731 arg.sc = sc; 1732 arg.vge_m0 = m_head; 1733 arg.vge_idx = idx; 1734 arg.vge_maxsegs = 1; 1735 1736 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1737 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1738 if (error) { 1739 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", 1740 error); 1741 return (EFBIG); 1742 } 1743 } 1744 1745 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1746 sc->vge_ldata.vge_tx_free--; 1747 1748 /* 1749 * Set up hardware VLAN tagging. 1750 */ 1751 1752 if (m_head->m_flags & M_VLANTAG) 1753 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1754 htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1755 1756 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1757 1758 return (0); 1759 } 1760 1761 /* 1762 * Main transmit routine. 1763 */ 1764 1765 static void 1766 vge_start(ifp) 1767 struct ifnet *ifp; 1768 { 1769 struct vge_softc *sc; 1770 1771 sc = ifp->if_softc; 1772 VGE_LOCK(sc); 1773 vge_start_locked(ifp); 1774 VGE_UNLOCK(sc); 1775 } 1776 1777 static void 1778 vge_start_locked(ifp) 1779 struct ifnet *ifp; 1780 { 1781 struct vge_softc *sc; 1782 struct mbuf *m_head = NULL; 1783 int idx, pidx = 0; 1784 1785 sc = ifp->if_softc; 1786 VGE_LOCK_ASSERT(sc); 1787 1788 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) 1789 return; 1790 1791 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1792 return; 1793 1794 idx = sc->vge_ldata.vge_tx_prodidx; 1795 1796 pidx = idx - 1; 1797 if (pidx < 0) 1798 pidx = VGE_TX_DESC_CNT - 1; 1799 1800 1801 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1802 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1803 if (m_head == NULL) 1804 break; 1805 1806 if (vge_encap(sc, m_head, idx)) { 1807 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1808 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1809 break; 1810 } 1811 1812 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1813 htole16(VGE_TXDESC_Q); 1814 1815 pidx = idx; 1816 VGE_TX_DESC_INC(idx); 1817 1818 /* 1819 * If there's a BPF listener, bounce a copy of this frame 1820 * to him. 1821 */ 1822 ETHER_BPF_MTAP(ifp, m_head); 1823 } 1824 1825 if (idx == sc->vge_ldata.vge_tx_prodidx) 1826 return; 1827 1828 /* Flush the TX descriptors */ 1829 1830 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1831 sc->vge_ldata.vge_tx_list_map, 1832 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1833 1834 /* Issue a transmit command. */ 1835 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1836 1837 sc->vge_ldata.vge_tx_prodidx = idx; 1838 1839 /* 1840 * Use the countdown timer for interrupt moderation. 1841 * 'TX done' interrupts are disabled. Instead, we reset the 1842 * countdown timer, which will begin counting until it hits 1843 * the value in the SSTIMER register, and then trigger an 1844 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1845 * the timer count is reloaded. Only when the transmitter 1846 * is idle will the timer hit 0 and an interrupt fire. 1847 */ 1848 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1849 1850 /* 1851 * Set a timeout in case the chip goes out to lunch. 1852 */ 1853 sc->vge_timer = 5; 1854 1855 return; 1856 } 1857 1858 static void 1859 vge_init(xsc) 1860 void *xsc; 1861 { 1862 struct vge_softc *sc = xsc; 1863 1864 VGE_LOCK(sc); 1865 vge_init_locked(sc); 1866 VGE_UNLOCK(sc); 1867 } 1868 1869 static void 1870 vge_init_locked(struct vge_softc *sc) 1871 { 1872 struct ifnet *ifp = sc->vge_ifp; 1873 struct mii_data *mii; 1874 int i; 1875 1876 VGE_LOCK_ASSERT(sc); 1877 mii = device_get_softc(sc->vge_miibus); 1878 1879 /* 1880 * Cancel pending I/O and free all RX/TX buffers. 1881 */ 1882 vge_stop(sc); 1883 vge_reset(sc); 1884 1885 /* 1886 * Initialize the RX and TX descriptors and mbufs. 1887 */ 1888 1889 vge_rx_list_init(sc); 1890 vge_tx_list_init(sc); 1891 1892 /* Set our station address */ 1893 for (i = 0; i < ETHER_ADDR_LEN; i++) 1894 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1895 1896 /* 1897 * Set receive FIFO threshold. Also allow transmission and 1898 * reception of VLAN tagged frames. 1899 */ 1900 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1901 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1902 1903 /* Set DMA burst length */ 1904 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1905 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1906 1907 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1908 1909 /* Set collision backoff algorithm */ 1910 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1911 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1912 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1913 1914 /* Disable LPSEL field in priority resolution */ 1915 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1916 1917 /* 1918 * Load the addresses of the DMA queues into the chip. 1919 * Note that we only use one transmit queue. 1920 */ 1921 1922 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1923 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1924 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1925 1926 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1927 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1928 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1929 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1930 1931 /* Enable and wake up the RX descriptor queue */ 1932 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1933 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1934 1935 /* Enable the TX descriptor queue */ 1936 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1937 1938 /* Set up the receive filter -- allow large frames for VLANs. */ 1939 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1940 1941 /* If we want promiscuous mode, set the allframes bit. */ 1942 if (ifp->if_flags & IFF_PROMISC) { 1943 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1944 } 1945 1946 /* Set capture broadcast bit to capture broadcast frames. */ 1947 if (ifp->if_flags & IFF_BROADCAST) { 1948 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1949 } 1950 1951 /* Set multicast bit to capture multicast frames. */ 1952 if (ifp->if_flags & IFF_MULTICAST) { 1953 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1954 } 1955 1956 /* Init the cam filter. */ 1957 vge_cam_clear(sc); 1958 1959 /* Init the multicast filter. */ 1960 vge_setmulti(sc); 1961 1962 /* Enable flow control */ 1963 1964 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1965 1966 /* Enable jumbo frame reception (if desired) */ 1967 1968 /* Start the MAC. */ 1969 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1970 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1971 CSR_WRITE_1(sc, VGE_CRS0, 1972 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1973 1974 /* 1975 * Configure one-shot timer for microsecond 1976 * resulution and load it for 500 usecs. 1977 */ 1978 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1979 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1980 1981 /* 1982 * Configure interrupt moderation for receive. Enable 1983 * the holdoff counter and load it, and set the RX 1984 * suppression count to the number of descriptors we 1985 * want to allow before triggering an interrupt. 1986 * The holdoff timer is in units of 20 usecs. 1987 */ 1988 1989 #ifdef notyet 1990 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1991 /* Select the interrupt holdoff timer page. */ 1992 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1993 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1994 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1995 1996 /* Enable use of the holdoff timer. */ 1997 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1998 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1999 2000 /* Select the RX suppression threshold page. */ 2001 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2002 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2003 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2004 2005 /* Restore the page select bits. */ 2006 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2007 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2008 #endif 2009 2010 #ifdef DEVICE_POLLING 2011 /* 2012 * Disable interrupts if we are polling. 2013 */ 2014 if (ifp->if_capenable & IFCAP_POLLING) { 2015 CSR_WRITE_4(sc, VGE_IMR, 0); 2016 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2017 } else /* otherwise ... */ 2018 #endif 2019 { 2020 /* 2021 * Enable interrupts. 2022 */ 2023 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2024 CSR_WRITE_4(sc, VGE_ISR, 0); 2025 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2026 } 2027 2028 mii_mediachg(mii); 2029 2030 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2031 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2032 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2033 2034 sc->vge_if_flags = 0; 2035 sc->vge_link = 0; 2036 2037 return; 2038 } 2039 2040 /* 2041 * Set media options. 2042 */ 2043 static int 2044 vge_ifmedia_upd(ifp) 2045 struct ifnet *ifp; 2046 { 2047 struct vge_softc *sc; 2048 struct mii_data *mii; 2049 2050 sc = ifp->if_softc; 2051 VGE_LOCK(sc); 2052 mii = device_get_softc(sc->vge_miibus); 2053 mii_mediachg(mii); 2054 VGE_UNLOCK(sc); 2055 2056 return (0); 2057 } 2058 2059 /* 2060 * Report current media status. 2061 */ 2062 static void 2063 vge_ifmedia_sts(ifp, ifmr) 2064 struct ifnet *ifp; 2065 struct ifmediareq *ifmr; 2066 { 2067 struct vge_softc *sc; 2068 struct mii_data *mii; 2069 2070 sc = ifp->if_softc; 2071 mii = device_get_softc(sc->vge_miibus); 2072 2073 VGE_LOCK(sc); 2074 mii_pollstat(mii); 2075 VGE_UNLOCK(sc); 2076 ifmr->ifm_active = mii->mii_media_active; 2077 ifmr->ifm_status = mii->mii_media_status; 2078 2079 return; 2080 } 2081 2082 static void 2083 vge_miibus_statchg(dev) 2084 device_t dev; 2085 { 2086 struct vge_softc *sc; 2087 struct mii_data *mii; 2088 struct ifmedia_entry *ife; 2089 2090 sc = device_get_softc(dev); 2091 mii = device_get_softc(sc->vge_miibus); 2092 ife = mii->mii_media.ifm_cur; 2093 2094 /* 2095 * If the user manually selects a media mode, we need to turn 2096 * on the forced MAC mode bit in the DIAGCTL register. If the 2097 * user happens to choose a full duplex mode, we also need to 2098 * set the 'force full duplex' bit. This applies only to 2099 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2100 * mode is disabled, and in 1000baseT mode, full duplex is 2101 * always implied, so we turn on the forced mode bit but leave 2102 * the FDX bit cleared. 2103 */ 2104 2105 switch (IFM_SUBTYPE(ife->ifm_media)) { 2106 case IFM_AUTO: 2107 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2108 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2109 break; 2110 case IFM_1000_T: 2111 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2112 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2113 break; 2114 case IFM_100_TX: 2115 case IFM_10_T: 2116 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2117 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2118 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2119 } else { 2120 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2121 } 2122 break; 2123 default: 2124 device_printf(dev, "unknown media type: %x\n", 2125 IFM_SUBTYPE(ife->ifm_media)); 2126 break; 2127 } 2128 2129 return; 2130 } 2131 2132 static int 2133 vge_ioctl(ifp, command, data) 2134 struct ifnet *ifp; 2135 u_long command; 2136 caddr_t data; 2137 { 2138 struct vge_softc *sc = ifp->if_softc; 2139 struct ifreq *ifr = (struct ifreq *) data; 2140 struct mii_data *mii; 2141 int error = 0; 2142 2143 switch (command) { 2144 case SIOCSIFMTU: 2145 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2146 error = EINVAL; 2147 ifp->if_mtu = ifr->ifr_mtu; 2148 break; 2149 case SIOCSIFFLAGS: 2150 VGE_LOCK(sc); 2151 if (ifp->if_flags & IFF_UP) { 2152 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2153 ifp->if_flags & IFF_PROMISC && 2154 !(sc->vge_if_flags & IFF_PROMISC)) { 2155 CSR_SETBIT_1(sc, VGE_RXCTL, 2156 VGE_RXCTL_RX_PROMISC); 2157 vge_setmulti(sc); 2158 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2159 !(ifp->if_flags & IFF_PROMISC) && 2160 sc->vge_if_flags & IFF_PROMISC) { 2161 CSR_CLRBIT_1(sc, VGE_RXCTL, 2162 VGE_RXCTL_RX_PROMISC); 2163 vge_setmulti(sc); 2164 } else 2165 vge_init_locked(sc); 2166 } else { 2167 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2168 vge_stop(sc); 2169 } 2170 sc->vge_if_flags = ifp->if_flags; 2171 VGE_UNLOCK(sc); 2172 break; 2173 case SIOCADDMULTI: 2174 case SIOCDELMULTI: 2175 VGE_LOCK(sc); 2176 vge_setmulti(sc); 2177 VGE_UNLOCK(sc); 2178 break; 2179 case SIOCGIFMEDIA: 2180 case SIOCSIFMEDIA: 2181 mii = device_get_softc(sc->vge_miibus); 2182 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2183 break; 2184 case SIOCSIFCAP: 2185 { 2186 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2187 #ifdef DEVICE_POLLING 2188 if (mask & IFCAP_POLLING) { 2189 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2190 error = ether_poll_register(vge_poll, ifp); 2191 if (error) 2192 return(error); 2193 VGE_LOCK(sc); 2194 /* Disable interrupts */ 2195 CSR_WRITE_4(sc, VGE_IMR, 0); 2196 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2197 ifp->if_capenable |= IFCAP_POLLING; 2198 VGE_UNLOCK(sc); 2199 } else { 2200 error = ether_poll_deregister(ifp); 2201 /* Enable interrupts. */ 2202 VGE_LOCK(sc); 2203 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2204 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2205 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2206 ifp->if_capenable &= ~IFCAP_POLLING; 2207 VGE_UNLOCK(sc); 2208 } 2209 } 2210 #endif /* DEVICE_POLLING */ 2211 VGE_LOCK(sc); 2212 if ((mask & IFCAP_TXCSUM) != 0 && 2213 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2214 ifp->if_capenable ^= IFCAP_TXCSUM; 2215 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2216 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2217 else 2218 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2219 } 2220 if ((mask & IFCAP_RXCSUM) != 0 && 2221 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2222 ifp->if_capenable ^= IFCAP_RXCSUM; 2223 VGE_UNLOCK(sc); 2224 } 2225 break; 2226 default: 2227 error = ether_ioctl(ifp, command, data); 2228 break; 2229 } 2230 2231 return (error); 2232 } 2233 2234 static void 2235 vge_watchdog(void *arg) 2236 { 2237 struct vge_softc *sc; 2238 struct ifnet *ifp; 2239 2240 sc = arg; 2241 VGE_LOCK_ASSERT(sc); 2242 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2243 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2244 return; 2245 2246 ifp = sc->vge_ifp; 2247 if_printf(ifp, "watchdog timeout\n"); 2248 ifp->if_oerrors++; 2249 2250 vge_txeof(sc); 2251 vge_rxeof(sc); 2252 2253 vge_init_locked(sc); 2254 2255 return; 2256 } 2257 2258 /* 2259 * Stop the adapter and free any mbufs allocated to the 2260 * RX and TX lists. 2261 */ 2262 static void 2263 vge_stop(sc) 2264 struct vge_softc *sc; 2265 { 2266 register int i; 2267 struct ifnet *ifp; 2268 2269 VGE_LOCK_ASSERT(sc); 2270 ifp = sc->vge_ifp; 2271 sc->vge_timer = 0; 2272 callout_stop(&sc->vge_watchdog); 2273 2274 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2275 2276 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2277 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2278 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2279 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2280 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2281 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2282 2283 if (sc->vge_head != NULL) { 2284 m_freem(sc->vge_head); 2285 sc->vge_head = sc->vge_tail = NULL; 2286 } 2287 2288 /* Free the TX list buffers. */ 2289 2290 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2291 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2292 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2293 sc->vge_ldata.vge_tx_dmamap[i]); 2294 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2295 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2296 } 2297 } 2298 2299 /* Free the RX list buffers. */ 2300 2301 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2302 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2303 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2304 sc->vge_ldata.vge_rx_dmamap[i]); 2305 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2306 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2307 } 2308 } 2309 2310 return; 2311 } 2312 2313 /* 2314 * Device suspend routine. Stop the interface and save some PCI 2315 * settings in case the BIOS doesn't restore them properly on 2316 * resume. 2317 */ 2318 static int 2319 vge_suspend(dev) 2320 device_t dev; 2321 { 2322 struct vge_softc *sc; 2323 2324 sc = device_get_softc(dev); 2325 2326 VGE_LOCK(sc); 2327 vge_stop(sc); 2328 2329 sc->suspended = 1; 2330 VGE_UNLOCK(sc); 2331 2332 return (0); 2333 } 2334 2335 /* 2336 * Device resume routine. Restore some PCI settings in case the BIOS 2337 * doesn't, re-enable busmastering, and restart the interface if 2338 * appropriate. 2339 */ 2340 static int 2341 vge_resume(dev) 2342 device_t dev; 2343 { 2344 struct vge_softc *sc; 2345 struct ifnet *ifp; 2346 2347 sc = device_get_softc(dev); 2348 ifp = sc->vge_ifp; 2349 2350 /* reenable busmastering */ 2351 pci_enable_busmaster(dev); 2352 pci_enable_io(dev, SYS_RES_MEMORY); 2353 2354 /* reinitialize interface if necessary */ 2355 VGE_LOCK(sc); 2356 if (ifp->if_flags & IFF_UP) 2357 vge_init_locked(sc); 2358 2359 sc->suspended = 0; 2360 VGE_UNLOCK(sc); 2361 2362 return (0); 2363 } 2364 2365 /* 2366 * Stop all chip I/O so that the kernel's probe routines don't 2367 * get confused by errant DMAs when rebooting. 2368 */ 2369 static int 2370 vge_shutdown(dev) 2371 device_t dev; 2372 { 2373 struct vge_softc *sc; 2374 2375 sc = device_get_softc(dev); 2376 2377 VGE_LOCK(sc); 2378 vge_stop(sc); 2379 VGE_UNLOCK(sc); 2380 2381 return (0); 2382 } 2383