1 /*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44 /* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83 #ifdef HAVE_KERNEL_OPTION_HEADERS 84 #include "opt_device_polling.h" 85 #endif 86 87 #include <sys/param.h> 88 #include <sys/endian.h> 89 #include <sys/systm.h> 90 #include <sys/sockio.h> 91 #include <sys/mbuf.h> 92 #include <sys/malloc.h> 93 #include <sys/module.h> 94 #include <sys/kernel.h> 95 #include <sys/socket.h> 96 #include <sys/taskqueue.h> 97 98 #include <net/if.h> 99 #include <net/if_arp.h> 100 #include <net/ethernet.h> 101 #include <net/if_dl.h> 102 #include <net/if_media.h> 103 #include <net/if_types.h> 104 #include <net/if_vlan_var.h> 105 106 #include <net/bpf.h> 107 108 #include <machine/bus.h> 109 #include <machine/resource.h> 110 #include <sys/bus.h> 111 #include <sys/rman.h> 112 113 #include <dev/mii/mii.h> 114 #include <dev/mii/miivar.h> 115 116 #include <dev/pci/pcireg.h> 117 #include <dev/pci/pcivar.h> 118 119 MODULE_DEPEND(vge, pci, 1, 1, 1); 120 MODULE_DEPEND(vge, ether, 1, 1, 1); 121 MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123 /* "device miibus" required. See GENERIC if you get errors here. */ 124 #include "miibus_if.h" 125 126 #include <dev/vge/if_vgereg.h> 127 #include <dev/vge/if_vgevar.h> 128 129 #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131 /* 132 * Various supported device vendors/types and their names. 133 */ 134 static struct vge_type vge_devs[] = { 135 { VIA_VENDORID, VIA_DEVICEID_61XX, 136 "VIA Networking Gigabit Ethernet" }, 137 { 0, 0, NULL } 138 }; 139 140 static int vge_probe (device_t); 141 static int vge_attach (device_t); 142 static int vge_detach (device_t); 143 144 static int vge_encap (struct vge_softc *, struct mbuf *, int); 145 146 static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 147 static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 148 bus_size_t, int); 149 static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 150 bus_size_t, int); 151 static int vge_allocmem (device_t, struct vge_softc *); 152 static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 153 static int vge_rx_list_init (struct vge_softc *); 154 static int vge_tx_list_init (struct vge_softc *); 155 #ifdef VGE_FIXUP_RX 156 static __inline void vge_fixup_rx 157 (struct mbuf *); 158 #endif 159 static void vge_rxeof (struct vge_softc *); 160 static void vge_txeof (struct vge_softc *); 161 static void vge_intr (void *); 162 static void vge_tick (void *); 163 static void vge_tx_task (void *, int); 164 static void vge_start (struct ifnet *); 165 static int vge_ioctl (struct ifnet *, u_long, caddr_t); 166 static void vge_init (void *); 167 static void vge_stop (struct vge_softc *); 168 static void vge_watchdog (struct ifnet *); 169 static int vge_suspend (device_t); 170 static int vge_resume (device_t); 171 static int vge_shutdown (device_t); 172 static int vge_ifmedia_upd (struct ifnet *); 173 static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175 #ifdef VGE_EEPROM 176 static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177 #endif 178 static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180 static void vge_miipoll_start (struct vge_softc *); 181 static void vge_miipoll_stop (struct vge_softc *); 182 static int vge_miibus_readreg (device_t, int, int); 183 static int vge_miibus_writereg (device_t, int, int, int); 184 static void vge_miibus_statchg (device_t); 185 186 static void vge_cam_clear (struct vge_softc *); 187 static int vge_cam_set (struct vge_softc *, uint8_t *); 188 static void vge_setmulti (struct vge_softc *); 189 static void vge_reset (struct vge_softc *); 190 191 #define VGE_PCI_LOIO 0x10 192 #define VGE_PCI_LOMEM 0x14 193 194 static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213 }; 214 215 static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219 }; 220 221 static devclass_t vge_devclass; 222 223 DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224 DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226 #ifdef VGE_EEPROM 227 /* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230 static void 231 vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235 { 236 register int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275 } 276 #endif 277 278 /* 279 * Read a sequence of words from the EEPROM. 280 */ 281 static void 282 vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288 { 289 int i; 290 #ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301 #else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304 #endif 305 } 306 307 static void 308 vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310 { 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325 } 326 327 static void 328 vge_miipoll_start(sc) 329 struct vge_softc *sc; 330 { 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365 } 366 367 static int 368 vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371 { 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 VGE_LOCK(sc); 382 vge_miipoll_stop(sc); 383 384 /* Specify the register we want to read. */ 385 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 386 387 /* Issue read command. */ 388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 389 390 /* Wait for the read command bit to self-clear. */ 391 for (i = 0; i < VGE_TIMEOUT; i++) { 392 DELAY(1); 393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 394 break; 395 } 396 397 if (i == VGE_TIMEOUT) 398 device_printf(sc->vge_dev, "MII read timed out\n"); 399 else 400 rval = CSR_READ_2(sc, VGE_MIIDATA); 401 402 vge_miipoll_start(sc); 403 VGE_UNLOCK(sc); 404 405 return (rval); 406 } 407 408 static int 409 vge_miibus_writereg(dev, phy, reg, data) 410 device_t dev; 411 int phy, reg, data; 412 { 413 struct vge_softc *sc; 414 int i, rval = 0; 415 416 sc = device_get_softc(dev); 417 418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 419 return(0); 420 421 VGE_LOCK(sc); 422 vge_miipoll_stop(sc); 423 424 /* Specify the register we want to write. */ 425 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 426 427 /* Specify the data we want to write. */ 428 CSR_WRITE_2(sc, VGE_MIIDATA, data); 429 430 /* Issue write command. */ 431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 432 433 /* Wait for the write command bit to self-clear. */ 434 for (i = 0; i < VGE_TIMEOUT; i++) { 435 DELAY(1); 436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 437 break; 438 } 439 440 if (i == VGE_TIMEOUT) { 441 device_printf(sc->vge_dev, "MII write timed out\n"); 442 rval = EIO; 443 } 444 445 vge_miipoll_start(sc); 446 VGE_UNLOCK(sc); 447 448 return (rval); 449 } 450 451 static void 452 vge_cam_clear(sc) 453 struct vge_softc *sc; 454 { 455 int i; 456 457 /* 458 * Turn off all the mask bits. This tells the chip 459 * that none of the entries in the CAM filter are valid. 460 * desired entries will be enabled as we fill the filter in. 461 */ 462 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 466 for (i = 0; i < 8; i++) 467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 468 469 /* Clear the VLAN filter too. */ 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 472 for (i = 0; i < 8; i++) 473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 478 479 sc->vge_camidx = 0; 480 481 return; 482 } 483 484 static int 485 vge_cam_set(sc, addr) 486 struct vge_softc *sc; 487 uint8_t *addr; 488 { 489 int i, error = 0; 490 491 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 492 return(ENOSPC); 493 494 /* Select the CAM data page. */ 495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 497 498 /* Set the filter entry we want to update and enable writing. */ 499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 500 501 /* Write the address to the CAM registers */ 502 for (i = 0; i < ETHER_ADDR_LEN; i++) 503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 504 505 /* Issue a write command. */ 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 507 508 /* Wake for it to clear. */ 509 for (i = 0; i < VGE_TIMEOUT; i++) { 510 DELAY(1); 511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 512 break; 513 } 514 515 if (i == VGE_TIMEOUT) { 516 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 517 error = EIO; 518 goto fail; 519 } 520 521 /* Select the CAM mask page. */ 522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 524 525 /* Set the mask bit that enables this filter. */ 526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 527 1<<(sc->vge_camidx & 7)); 528 529 sc->vge_camidx++; 530 531 fail: 532 /* Turn off access to CAM. */ 533 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 536 537 return (error); 538 } 539 540 /* 541 * Program the multicast filter. We use the 64-entry CAM filter 542 * for perfect filtering. If there's more than 64 multicast addresses, 543 * we use the hash filter insted. 544 */ 545 static void 546 vge_setmulti(sc) 547 struct vge_softc *sc; 548 { 549 struct ifnet *ifp; 550 int error = 0/*, h = 0*/; 551 struct ifmultiaddr *ifma; 552 u_int32_t h, hashes[2] = { 0, 0 }; 553 554 ifp = sc->vge_ifp; 555 556 /* First, zot all the multicast entries. */ 557 vge_cam_clear(sc); 558 CSR_WRITE_4(sc, VGE_MAR0, 0); 559 CSR_WRITE_4(sc, VGE_MAR1, 0); 560 561 /* 562 * If the user wants allmulti or promisc mode, enable reception 563 * of all multicast frames. 564 */ 565 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 566 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 567 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 568 return; 569 } 570 571 /* Now program new ones */ 572 IF_ADDR_LOCK(ifp); 573 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 574 if (ifma->ifma_addr->sa_family != AF_LINK) 575 continue; 576 error = vge_cam_set(sc, 577 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 578 if (error) 579 break; 580 } 581 582 /* If there were too many addresses, use the hash filter. */ 583 if (error) { 584 vge_cam_clear(sc); 585 586 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 587 if (ifma->ifma_addr->sa_family != AF_LINK) 588 continue; 589 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 590 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 591 if (h < 32) 592 hashes[0] |= (1 << h); 593 else 594 hashes[1] |= (1 << (h - 32)); 595 } 596 597 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 598 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 599 } 600 IF_ADDR_UNLOCK(ifp); 601 602 return; 603 } 604 605 static void 606 vge_reset(sc) 607 struct vge_softc *sc; 608 { 609 register int i; 610 611 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 612 613 for (i = 0; i < VGE_TIMEOUT; i++) { 614 DELAY(5); 615 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 616 break; 617 } 618 619 if (i == VGE_TIMEOUT) { 620 device_printf(sc->vge_dev, "soft reset timed out"); 621 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 622 DELAY(2000); 623 } 624 625 DELAY(5000); 626 627 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 628 629 for (i = 0; i < VGE_TIMEOUT; i++) { 630 DELAY(5); 631 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 632 break; 633 } 634 635 if (i == VGE_TIMEOUT) { 636 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 637 return; 638 } 639 640 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 641 642 return; 643 } 644 645 /* 646 * Probe for a VIA gigabit chip. Check the PCI vendor and device 647 * IDs against our list and return a device name if we find a match. 648 */ 649 static int 650 vge_probe(dev) 651 device_t dev; 652 { 653 struct vge_type *t; 654 655 t = vge_devs; 656 657 while (t->vge_name != NULL) { 658 if ((pci_get_vendor(dev) == t->vge_vid) && 659 (pci_get_device(dev) == t->vge_did)) { 660 device_set_desc(dev, t->vge_name); 661 return (BUS_PROBE_DEFAULT); 662 } 663 t++; 664 } 665 666 return (ENXIO); 667 } 668 669 static void 670 vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 671 void *arg; 672 bus_dma_segment_t *segs; 673 int nseg; 674 bus_size_t mapsize; 675 int error; 676 { 677 678 struct vge_dmaload_arg *ctx; 679 struct vge_rx_desc *d = NULL; 680 681 if (error) 682 return; 683 684 ctx = arg; 685 686 /* Signal error to caller if there's too many segments */ 687 if (nseg > ctx->vge_maxsegs) { 688 ctx->vge_maxsegs = 0; 689 return; 690 } 691 692 /* 693 * Map the segment array into descriptors. 694 */ 695 696 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 697 698 /* If this descriptor is still owned by the chip, bail. */ 699 700 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 701 device_printf(ctx->sc->vge_dev, 702 "tried to map busy descriptor\n"); 703 ctx->vge_maxsegs = 0; 704 return; 705 } 706 707 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 708 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 709 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 710 d->vge_sts = 0; 711 d->vge_ctl = 0; 712 713 ctx->vge_maxsegs = 1; 714 715 return; 716 } 717 718 static void 719 vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 720 void *arg; 721 bus_dma_segment_t *segs; 722 int nseg; 723 bus_size_t mapsize; 724 int error; 725 { 726 struct vge_dmaload_arg *ctx; 727 struct vge_tx_desc *d = NULL; 728 struct vge_tx_frag *f; 729 int i = 0; 730 731 if (error) 732 return; 733 734 ctx = arg; 735 736 /* Signal error to caller if there's too many segments */ 737 if (nseg > ctx->vge_maxsegs) { 738 ctx->vge_maxsegs = 0; 739 return; 740 } 741 742 /* Map the segment array into descriptors. */ 743 744 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 745 746 /* If this descriptor is still owned by the chip, bail. */ 747 748 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 749 ctx->vge_maxsegs = 0; 750 return; 751 } 752 753 for (i = 0; i < nseg; i++) { 754 f = &d->vge_frag[i]; 755 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 756 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 757 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 758 } 759 760 /* Argh. This chip does not autopad short frames */ 761 762 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 763 f = &d->vge_frag[i]; 764 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 765 ctx->vge_m0->m_pkthdr.len)); 766 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 767 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 768 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 769 i++; 770 } 771 772 /* 773 * When telling the chip how many segments there are, we 774 * must use nsegs + 1 instead of just nsegs. Darned if I 775 * know why. 776 */ 777 i++; 778 779 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 780 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 781 782 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 783 d->vge_ctl |= VGE_TDCTL_JUMBO; 784 785 ctx->vge_maxsegs = nseg; 786 787 return; 788 } 789 790 /* 791 * Map a single buffer address. 792 */ 793 794 static void 795 vge_dma_map_addr(arg, segs, nseg, error) 796 void *arg; 797 bus_dma_segment_t *segs; 798 int nseg; 799 int error; 800 { 801 bus_addr_t *addr; 802 803 if (error) 804 return; 805 806 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 807 addr = arg; 808 *addr = segs->ds_addr; 809 810 return; 811 } 812 813 static int 814 vge_allocmem(dev, sc) 815 device_t dev; 816 struct vge_softc *sc; 817 { 818 int error; 819 int nseg; 820 int i; 821 822 /* 823 * Allocate map for RX mbufs. 824 */ 825 nseg = 32; 826 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 827 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 828 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 829 NULL, NULL, &sc->vge_ldata.vge_mtag); 830 if (error) { 831 device_printf(dev, "could not allocate dma tag\n"); 832 return (ENOMEM); 833 } 834 835 /* 836 * Allocate map for TX descriptor list. 837 */ 838 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 839 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 840 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 841 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 842 if (error) { 843 device_printf(dev, "could not allocate dma tag\n"); 844 return (ENOMEM); 845 } 846 847 /* Allocate DMA'able memory for the TX ring */ 848 849 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 850 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 851 &sc->vge_ldata.vge_tx_list_map); 852 if (error) 853 return (ENOMEM); 854 855 /* Load the map for the TX ring. */ 856 857 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 858 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 859 VGE_TX_LIST_SZ, vge_dma_map_addr, 860 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 861 862 /* Create DMA maps for TX buffers */ 863 864 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 865 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 866 &sc->vge_ldata.vge_tx_dmamap[i]); 867 if (error) { 868 device_printf(dev, "can't create DMA map for TX\n"); 869 return (ENOMEM); 870 } 871 } 872 873 /* 874 * Allocate map for RX descriptor list. 875 */ 876 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 877 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 878 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 879 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 880 if (error) { 881 device_printf(dev, "could not allocate dma tag\n"); 882 return (ENOMEM); 883 } 884 885 /* Allocate DMA'able memory for the RX ring */ 886 887 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 888 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 889 &sc->vge_ldata.vge_rx_list_map); 890 if (error) 891 return (ENOMEM); 892 893 /* Load the map for the RX ring. */ 894 895 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 896 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 897 VGE_TX_LIST_SZ, vge_dma_map_addr, 898 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 899 900 /* Create DMA maps for RX buffers */ 901 902 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 903 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 904 &sc->vge_ldata.vge_rx_dmamap[i]); 905 if (error) { 906 device_printf(dev, "can't create DMA map for RX\n"); 907 return (ENOMEM); 908 } 909 } 910 911 return (0); 912 } 913 914 /* 915 * Attach the interface. Allocate softc structures, do ifmedia 916 * setup and ethernet/BPF attach. 917 */ 918 static int 919 vge_attach(dev) 920 device_t dev; 921 { 922 u_char eaddr[ETHER_ADDR_LEN]; 923 struct vge_softc *sc; 924 struct ifnet *ifp; 925 int unit, error = 0, rid; 926 927 sc = device_get_softc(dev); 928 unit = device_get_unit(dev); 929 sc->vge_dev = dev; 930 931 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 932 MTX_DEF | MTX_RECURSE); 933 /* 934 * Map control/status registers. 935 */ 936 pci_enable_busmaster(dev); 937 938 rid = VGE_PCI_LOMEM; 939 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 940 0, ~0, 1, RF_ACTIVE); 941 942 if (sc->vge_res == NULL) { 943 printf ("vge%d: couldn't map ports/memory\n", unit); 944 error = ENXIO; 945 goto fail; 946 } 947 948 sc->vge_btag = rman_get_bustag(sc->vge_res); 949 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 950 951 /* Allocate interrupt */ 952 rid = 0; 953 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 954 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 955 956 if (sc->vge_irq == NULL) { 957 printf("vge%d: couldn't map interrupt\n", unit); 958 error = ENXIO; 959 goto fail; 960 } 961 962 /* Reset the adapter. */ 963 vge_reset(sc); 964 965 /* 966 * Get station address from the EEPROM. 967 */ 968 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 969 970 sc->vge_unit = unit; 971 972 /* 973 * Allocate the parent bus DMA tag appropriate for PCI. 974 */ 975 #define VGE_NSEG_NEW 32 976 error = bus_dma_tag_create(NULL, /* parent */ 977 1, 0, /* alignment, boundary */ 978 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 979 BUS_SPACE_MAXADDR, /* highaddr */ 980 NULL, NULL, /* filter, filterarg */ 981 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 982 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 983 BUS_DMA_ALLOCNOW, /* flags */ 984 NULL, NULL, /* lockfunc, lockarg */ 985 &sc->vge_parent_tag); 986 if (error) 987 goto fail; 988 989 error = vge_allocmem(dev, sc); 990 991 if (error) 992 goto fail; 993 994 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 995 if (ifp == NULL) { 996 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 997 error = ENOSPC; 998 goto fail; 999 } 1000 1001 /* Do MII setup */ 1002 if (mii_phy_probe(dev, &sc->vge_miibus, 1003 vge_ifmedia_upd, vge_ifmedia_sts)) { 1004 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1005 error = ENXIO; 1006 goto fail; 1007 } 1008 1009 ifp->if_softc = sc; 1010 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1011 ifp->if_mtu = ETHERMTU; 1012 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1013 ifp->if_ioctl = vge_ioctl; 1014 ifp->if_capabilities = IFCAP_VLAN_MTU; 1015 ifp->if_start = vge_start; 1016 ifp->if_hwassist = VGE_CSUM_FEATURES; 1017 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1018 ifp->if_capenable = ifp->if_capabilities; 1019 #ifdef DEVICE_POLLING 1020 ifp->if_capabilities |= IFCAP_POLLING; 1021 #endif 1022 ifp->if_watchdog = vge_watchdog; 1023 ifp->if_init = vge_init; 1024 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1025 ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1026 IFQ_SET_READY(&ifp->if_snd); 1027 1028 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1029 1030 /* 1031 * Call MI attach routine. 1032 */ 1033 ether_ifattach(ifp, eaddr); 1034 1035 /* Hook interrupt last to avoid having to lock softc */ 1036 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1037 NULL, vge_intr, sc, &sc->vge_intrhand); 1038 1039 if (error) { 1040 printf("vge%d: couldn't set up irq\n", unit); 1041 ether_ifdetach(ifp); 1042 goto fail; 1043 } 1044 1045 fail: 1046 if (error) 1047 vge_detach(dev); 1048 1049 return (error); 1050 } 1051 1052 /* 1053 * Shutdown hardware and free up resources. This can be called any 1054 * time after the mutex has been initialized. It is called in both 1055 * the error case in attach and the normal detach case so it needs 1056 * to be careful about only freeing resources that have actually been 1057 * allocated. 1058 */ 1059 static int 1060 vge_detach(dev) 1061 device_t dev; 1062 { 1063 struct vge_softc *sc; 1064 struct ifnet *ifp; 1065 int i; 1066 1067 sc = device_get_softc(dev); 1068 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1069 ifp = sc->vge_ifp; 1070 1071 #ifdef DEVICE_POLLING 1072 if (ifp->if_capenable & IFCAP_POLLING) 1073 ether_poll_deregister(ifp); 1074 #endif 1075 1076 /* These should only be active if attach succeeded */ 1077 if (device_is_attached(dev)) { 1078 vge_stop(sc); 1079 /* 1080 * Force off the IFF_UP flag here, in case someone 1081 * still had a BPF descriptor attached to this 1082 * interface. If they do, ether_ifattach() will cause 1083 * the BPF code to try and clear the promisc mode 1084 * flag, which will bubble down to vge_ioctl(), 1085 * which will try to call vge_init() again. This will 1086 * turn the NIC back on and restart the MII ticker, 1087 * which will panic the system when the kernel tries 1088 * to invoke the vge_tick() function that isn't there 1089 * anymore. 1090 */ 1091 ifp->if_flags &= ~IFF_UP; 1092 ether_ifdetach(ifp); 1093 } 1094 if (sc->vge_miibus) 1095 device_delete_child(dev, sc->vge_miibus); 1096 bus_generic_detach(dev); 1097 1098 if (sc->vge_intrhand) 1099 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1100 if (sc->vge_irq) 1101 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1102 if (sc->vge_res) 1103 bus_release_resource(dev, SYS_RES_MEMORY, 1104 VGE_PCI_LOMEM, sc->vge_res); 1105 if (ifp) 1106 if_free(ifp); 1107 1108 /* Unload and free the RX DMA ring memory and map */ 1109 1110 if (sc->vge_ldata.vge_rx_list_tag) { 1111 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1112 sc->vge_ldata.vge_rx_list_map); 1113 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1114 sc->vge_ldata.vge_rx_list, 1115 sc->vge_ldata.vge_rx_list_map); 1116 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1117 } 1118 1119 /* Unload and free the TX DMA ring memory and map */ 1120 1121 if (sc->vge_ldata.vge_tx_list_tag) { 1122 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1123 sc->vge_ldata.vge_tx_list_map); 1124 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1125 sc->vge_ldata.vge_tx_list, 1126 sc->vge_ldata.vge_tx_list_map); 1127 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1128 } 1129 1130 /* Destroy all the RX and TX buffer maps */ 1131 1132 if (sc->vge_ldata.vge_mtag) { 1133 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1134 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1135 sc->vge_ldata.vge_tx_dmamap[i]); 1136 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1137 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1138 sc->vge_ldata.vge_rx_dmamap[i]); 1139 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1140 } 1141 1142 if (sc->vge_parent_tag) 1143 bus_dma_tag_destroy(sc->vge_parent_tag); 1144 1145 mtx_destroy(&sc->vge_mtx); 1146 1147 return (0); 1148 } 1149 1150 static int 1151 vge_newbuf(sc, idx, m) 1152 struct vge_softc *sc; 1153 int idx; 1154 struct mbuf *m; 1155 { 1156 struct vge_dmaload_arg arg; 1157 struct mbuf *n = NULL; 1158 int i, error; 1159 1160 if (m == NULL) { 1161 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1162 if (n == NULL) 1163 return (ENOBUFS); 1164 m = n; 1165 } else 1166 m->m_data = m->m_ext.ext_buf; 1167 1168 1169 #ifdef VGE_FIXUP_RX 1170 /* 1171 * This is part of an evil trick to deal with non-x86 platforms. 1172 * The VIA chip requires RX buffers to be aligned on 32-bit 1173 * boundaries, but that will hose non-x86 machines. To get around 1174 * this, we leave some empty space at the start of each buffer 1175 * and for non-x86 hosts, we copy the buffer back two bytes 1176 * to achieve word alignment. This is slightly more efficient 1177 * than allocating a new buffer, copying the contents, and 1178 * discarding the old buffer. 1179 */ 1180 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1181 m_adj(m, VGE_ETHER_ALIGN); 1182 #else 1183 m->m_len = m->m_pkthdr.len = MCLBYTES; 1184 #endif 1185 1186 arg.sc = sc; 1187 arg.vge_idx = idx; 1188 arg.vge_maxsegs = 1; 1189 arg.vge_flags = 0; 1190 1191 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1192 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1193 &arg, BUS_DMA_NOWAIT); 1194 if (error || arg.vge_maxsegs != 1) { 1195 if (n != NULL) 1196 m_freem(n); 1197 return (ENOMEM); 1198 } 1199 1200 /* 1201 * Note: the manual fails to document the fact that for 1202 * proper opration, the driver needs to replentish the RX 1203 * DMA ring 4 descriptors at a time (rather than one at a 1204 * time, like most chips). We can allocate the new buffers 1205 * but we should not set the OWN bits until we're ready 1206 * to hand back 4 of them in one shot. 1207 */ 1208 1209 #define VGE_RXCHUNK 4 1210 sc->vge_rx_consumed++; 1211 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1212 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1213 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1214 htole32(VGE_RDSTS_OWN); 1215 sc->vge_rx_consumed = 0; 1216 } 1217 1218 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1219 1220 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1221 sc->vge_ldata.vge_rx_dmamap[idx], 1222 BUS_DMASYNC_PREREAD); 1223 1224 return (0); 1225 } 1226 1227 static int 1228 vge_tx_list_init(sc) 1229 struct vge_softc *sc; 1230 { 1231 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1232 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1233 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1234 1235 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1236 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1237 sc->vge_ldata.vge_tx_prodidx = 0; 1238 sc->vge_ldata.vge_tx_considx = 0; 1239 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1240 1241 return (0); 1242 } 1243 1244 static int 1245 vge_rx_list_init(sc) 1246 struct vge_softc *sc; 1247 { 1248 int i; 1249 1250 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1251 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1252 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1253 1254 sc->vge_rx_consumed = 0; 1255 1256 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1257 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1258 return (ENOBUFS); 1259 } 1260 1261 /* Flush the RX descriptors */ 1262 1263 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1264 sc->vge_ldata.vge_rx_list_map, 1265 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1266 1267 sc->vge_ldata.vge_rx_prodidx = 0; 1268 sc->vge_rx_consumed = 0; 1269 sc->vge_head = sc->vge_tail = NULL; 1270 1271 return (0); 1272 } 1273 1274 #ifdef VGE_FIXUP_RX 1275 static __inline void 1276 vge_fixup_rx(m) 1277 struct mbuf *m; 1278 { 1279 int i; 1280 uint16_t *src, *dst; 1281 1282 src = mtod(m, uint16_t *); 1283 dst = src - 1; 1284 1285 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1286 *dst++ = *src++; 1287 1288 m->m_data -= ETHER_ALIGN; 1289 1290 return; 1291 } 1292 #endif 1293 1294 /* 1295 * RX handler. We support the reception of jumbo frames that have 1296 * been fragmented across multiple 2K mbuf cluster buffers. 1297 */ 1298 static void 1299 vge_rxeof(sc) 1300 struct vge_softc *sc; 1301 { 1302 struct mbuf *m; 1303 struct ifnet *ifp; 1304 int i, total_len; 1305 int lim = 0; 1306 struct vge_rx_desc *cur_rx; 1307 u_int32_t rxstat, rxctl; 1308 1309 VGE_LOCK_ASSERT(sc); 1310 ifp = sc->vge_ifp; 1311 i = sc->vge_ldata.vge_rx_prodidx; 1312 1313 /* Invalidate the descriptor memory */ 1314 1315 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1316 sc->vge_ldata.vge_rx_list_map, 1317 BUS_DMASYNC_POSTREAD); 1318 1319 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1320 1321 #ifdef DEVICE_POLLING 1322 if (ifp->if_capenable & IFCAP_POLLING) { 1323 if (sc->rxcycles <= 0) 1324 break; 1325 sc->rxcycles--; 1326 } 1327 #endif 1328 1329 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1330 m = sc->vge_ldata.vge_rx_mbuf[i]; 1331 total_len = VGE_RXBYTES(cur_rx); 1332 rxstat = le32toh(cur_rx->vge_sts); 1333 rxctl = le32toh(cur_rx->vge_ctl); 1334 1335 /* Invalidate the RX mbuf and unload its map */ 1336 1337 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1338 sc->vge_ldata.vge_rx_dmamap[i], 1339 BUS_DMASYNC_POSTWRITE); 1340 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1341 sc->vge_ldata.vge_rx_dmamap[i]); 1342 1343 /* 1344 * If the 'start of frame' bit is set, this indicates 1345 * either the first fragment in a multi-fragment receive, 1346 * or an intermediate fragment. Either way, we want to 1347 * accumulate the buffers. 1348 */ 1349 if (rxstat & VGE_RXPKT_SOF) { 1350 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1351 if (sc->vge_head == NULL) 1352 sc->vge_head = sc->vge_tail = m; 1353 else { 1354 m->m_flags &= ~M_PKTHDR; 1355 sc->vge_tail->m_next = m; 1356 sc->vge_tail = m; 1357 } 1358 vge_newbuf(sc, i, NULL); 1359 VGE_RX_DESC_INC(i); 1360 continue; 1361 } 1362 1363 /* 1364 * Bad/error frames will have the RXOK bit cleared. 1365 * However, there's one error case we want to allow: 1366 * if a VLAN tagged frame arrives and the chip can't 1367 * match it against the CAM filter, it considers this 1368 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1369 * We don't want to drop the frame though: our VLAN 1370 * filtering is done in software. 1371 */ 1372 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1373 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1374 ifp->if_ierrors++; 1375 /* 1376 * If this is part of a multi-fragment packet, 1377 * discard all the pieces. 1378 */ 1379 if (sc->vge_head != NULL) { 1380 m_freem(sc->vge_head); 1381 sc->vge_head = sc->vge_tail = NULL; 1382 } 1383 vge_newbuf(sc, i, m); 1384 VGE_RX_DESC_INC(i); 1385 continue; 1386 } 1387 1388 /* 1389 * If allocating a replacement mbuf fails, 1390 * reload the current one. 1391 */ 1392 1393 if (vge_newbuf(sc, i, NULL)) { 1394 ifp->if_ierrors++; 1395 if (sc->vge_head != NULL) { 1396 m_freem(sc->vge_head); 1397 sc->vge_head = sc->vge_tail = NULL; 1398 } 1399 vge_newbuf(sc, i, m); 1400 VGE_RX_DESC_INC(i); 1401 continue; 1402 } 1403 1404 VGE_RX_DESC_INC(i); 1405 1406 if (sc->vge_head != NULL) { 1407 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1408 /* 1409 * Special case: if there's 4 bytes or less 1410 * in this buffer, the mbuf can be discarded: 1411 * the last 4 bytes is the CRC, which we don't 1412 * care about anyway. 1413 */ 1414 if (m->m_len <= ETHER_CRC_LEN) { 1415 sc->vge_tail->m_len -= 1416 (ETHER_CRC_LEN - m->m_len); 1417 m_freem(m); 1418 } else { 1419 m->m_len -= ETHER_CRC_LEN; 1420 m->m_flags &= ~M_PKTHDR; 1421 sc->vge_tail->m_next = m; 1422 } 1423 m = sc->vge_head; 1424 sc->vge_head = sc->vge_tail = NULL; 1425 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1426 } else 1427 m->m_pkthdr.len = m->m_len = 1428 (total_len - ETHER_CRC_LEN); 1429 1430 #ifdef VGE_FIXUP_RX 1431 vge_fixup_rx(m); 1432 #endif 1433 ifp->if_ipackets++; 1434 m->m_pkthdr.rcvif = ifp; 1435 1436 /* Do RX checksumming if enabled */ 1437 if (ifp->if_capenable & IFCAP_RXCSUM) { 1438 1439 /* Check IP header checksum */ 1440 if (rxctl & VGE_RDCTL_IPPKT) 1441 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1442 if (rxctl & VGE_RDCTL_IPCSUMOK) 1443 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1444 1445 /* Check TCP/UDP checksum */ 1446 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1447 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1448 m->m_pkthdr.csum_flags |= 1449 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1450 m->m_pkthdr.csum_data = 0xffff; 1451 } 1452 } 1453 1454 if (rxstat & VGE_RDSTS_VTAG) { 1455 /* 1456 * The 32-bit rxctl register is stored in little-endian. 1457 * However, the 16-bit vlan tag is stored in big-endian, 1458 * so we have to byte swap it. 1459 */ 1460 m->m_pkthdr.ether_vtag = 1461 bswap16(rxctl & VGE_RDCTL_VLANID); 1462 m->m_flags |= M_VLANTAG; 1463 } 1464 1465 VGE_UNLOCK(sc); 1466 (*ifp->if_input)(ifp, m); 1467 VGE_LOCK(sc); 1468 1469 lim++; 1470 if (lim == VGE_RX_DESC_CNT) 1471 break; 1472 1473 } 1474 1475 /* Flush the RX DMA ring */ 1476 1477 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1478 sc->vge_ldata.vge_rx_list_map, 1479 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1480 1481 sc->vge_ldata.vge_rx_prodidx = i; 1482 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1483 1484 1485 return; 1486 } 1487 1488 static void 1489 vge_txeof(sc) 1490 struct vge_softc *sc; 1491 { 1492 struct ifnet *ifp; 1493 u_int32_t txstat; 1494 int idx; 1495 1496 ifp = sc->vge_ifp; 1497 idx = sc->vge_ldata.vge_tx_considx; 1498 1499 /* Invalidate the TX descriptor list */ 1500 1501 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1502 sc->vge_ldata.vge_tx_list_map, 1503 BUS_DMASYNC_POSTREAD); 1504 1505 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1506 1507 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1508 if (txstat & VGE_TDSTS_OWN) 1509 break; 1510 1511 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1512 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1513 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1514 sc->vge_ldata.vge_tx_dmamap[idx]); 1515 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1516 ifp->if_collisions++; 1517 if (txstat & VGE_TDSTS_TXERR) 1518 ifp->if_oerrors++; 1519 else 1520 ifp->if_opackets++; 1521 1522 sc->vge_ldata.vge_tx_free++; 1523 VGE_TX_DESC_INC(idx); 1524 } 1525 1526 /* No changes made to the TX ring, so no flush needed */ 1527 1528 if (idx != sc->vge_ldata.vge_tx_considx) { 1529 sc->vge_ldata.vge_tx_considx = idx; 1530 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1531 ifp->if_timer = 0; 1532 } 1533 1534 /* 1535 * If not all descriptors have been released reaped yet, 1536 * reload the timer so that we will eventually get another 1537 * interrupt that will cause us to re-enter this routine. 1538 * This is done in case the transmitter has gone idle. 1539 */ 1540 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1541 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1542 } 1543 1544 return; 1545 } 1546 1547 static void 1548 vge_tick(xsc) 1549 void *xsc; 1550 { 1551 struct vge_softc *sc; 1552 struct ifnet *ifp; 1553 struct mii_data *mii; 1554 1555 sc = xsc; 1556 ifp = sc->vge_ifp; 1557 VGE_LOCK(sc); 1558 mii = device_get_softc(sc->vge_miibus); 1559 1560 mii_tick(mii); 1561 if (sc->vge_link) { 1562 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1563 sc->vge_link = 0; 1564 if_link_state_change(sc->vge_ifp, 1565 LINK_STATE_DOWN); 1566 } 1567 } else { 1568 if (mii->mii_media_status & IFM_ACTIVE && 1569 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1570 sc->vge_link = 1; 1571 if_link_state_change(sc->vge_ifp, 1572 LINK_STATE_UP); 1573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1574 taskqueue_enqueue(taskqueue_swi, 1575 &sc->vge_txtask); 1576 } 1577 } 1578 1579 VGE_UNLOCK(sc); 1580 1581 return; 1582 } 1583 1584 #ifdef DEVICE_POLLING 1585 static void 1586 vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1587 { 1588 struct vge_softc *sc = ifp->if_softc; 1589 1590 VGE_LOCK(sc); 1591 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1592 goto done; 1593 1594 sc->rxcycles = count; 1595 vge_rxeof(sc); 1596 vge_txeof(sc); 1597 1598 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1599 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1600 1601 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1602 u_int32_t status; 1603 status = CSR_READ_4(sc, VGE_ISR); 1604 if (status == 0xFFFFFFFF) 1605 goto done; 1606 if (status) 1607 CSR_WRITE_4(sc, VGE_ISR, status); 1608 1609 /* 1610 * XXX check behaviour on receiver stalls. 1611 */ 1612 1613 if (status & VGE_ISR_TXDMA_STALL || 1614 status & VGE_ISR_RXDMA_STALL) 1615 vge_init(sc); 1616 1617 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1618 vge_rxeof(sc); 1619 ifp->if_ierrors++; 1620 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1621 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1622 } 1623 } 1624 done: 1625 VGE_UNLOCK(sc); 1626 } 1627 #endif /* DEVICE_POLLING */ 1628 1629 static void 1630 vge_intr(arg) 1631 void *arg; 1632 { 1633 struct vge_softc *sc; 1634 struct ifnet *ifp; 1635 u_int32_t status; 1636 1637 sc = arg; 1638 1639 if (sc->suspended) { 1640 return; 1641 } 1642 1643 VGE_LOCK(sc); 1644 ifp = sc->vge_ifp; 1645 1646 if (!(ifp->if_flags & IFF_UP)) { 1647 VGE_UNLOCK(sc); 1648 return; 1649 } 1650 1651 #ifdef DEVICE_POLLING 1652 if (ifp->if_capenable & IFCAP_POLLING) { 1653 VGE_UNLOCK(sc); 1654 return; 1655 } 1656 #endif 1657 1658 /* Disable interrupts */ 1659 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1660 1661 for (;;) { 1662 1663 status = CSR_READ_4(sc, VGE_ISR); 1664 /* If the card has gone away the read returns 0xffff. */ 1665 if (status == 0xFFFFFFFF) 1666 break; 1667 1668 if (status) 1669 CSR_WRITE_4(sc, VGE_ISR, status); 1670 1671 if ((status & VGE_INTRS) == 0) 1672 break; 1673 1674 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1675 vge_rxeof(sc); 1676 1677 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1678 vge_rxeof(sc); 1679 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1680 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1681 } 1682 1683 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1684 vge_txeof(sc); 1685 1686 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1687 vge_init(sc); 1688 1689 if (status & VGE_ISR_LINKSTS) 1690 vge_tick(sc); 1691 } 1692 1693 /* Re-enable interrupts */ 1694 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1695 1696 VGE_UNLOCK(sc); 1697 1698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1699 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1700 1701 return; 1702 } 1703 1704 static int 1705 vge_encap(sc, m_head, idx) 1706 struct vge_softc *sc; 1707 struct mbuf *m_head; 1708 int idx; 1709 { 1710 struct mbuf *m_new = NULL; 1711 struct vge_dmaload_arg arg; 1712 bus_dmamap_t map; 1713 int error; 1714 1715 if (sc->vge_ldata.vge_tx_free <= 2) 1716 return (EFBIG); 1717 1718 arg.vge_flags = 0; 1719 1720 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1721 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1722 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1723 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1724 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1725 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1726 1727 arg.sc = sc; 1728 arg.vge_idx = idx; 1729 arg.vge_m0 = m_head; 1730 arg.vge_maxsegs = VGE_TX_FRAGS; 1731 1732 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1733 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1734 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1735 1736 if (error && error != EFBIG) { 1737 printf("vge%d: can't map mbuf (error %d)\n", 1738 sc->vge_unit, error); 1739 return (ENOBUFS); 1740 } 1741 1742 /* Too many segments to map, coalesce into a single mbuf */ 1743 1744 if (error || arg.vge_maxsegs == 0) { 1745 m_new = m_defrag(m_head, M_DONTWAIT); 1746 if (m_new == NULL) 1747 return (1); 1748 else 1749 m_head = m_new; 1750 1751 arg.sc = sc; 1752 arg.vge_m0 = m_head; 1753 arg.vge_idx = idx; 1754 arg.vge_maxsegs = 1; 1755 1756 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1757 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1758 if (error) { 1759 printf("vge%d: can't map mbuf (error %d)\n", 1760 sc->vge_unit, error); 1761 return (EFBIG); 1762 } 1763 } 1764 1765 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1766 sc->vge_ldata.vge_tx_free--; 1767 1768 /* 1769 * Set up hardware VLAN tagging. 1770 */ 1771 1772 if (m_head->m_flags & M_VLANTAG) 1773 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1774 htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1775 1776 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1777 1778 return (0); 1779 } 1780 1781 static void 1782 vge_tx_task(arg, npending) 1783 void *arg; 1784 int npending; 1785 { 1786 struct ifnet *ifp; 1787 1788 ifp = arg; 1789 vge_start(ifp); 1790 1791 return; 1792 } 1793 1794 /* 1795 * Main transmit routine. 1796 */ 1797 1798 static void 1799 vge_start(ifp) 1800 struct ifnet *ifp; 1801 { 1802 struct vge_softc *sc; 1803 struct mbuf *m_head = NULL; 1804 int idx, pidx = 0; 1805 1806 sc = ifp->if_softc; 1807 VGE_LOCK(sc); 1808 1809 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1810 VGE_UNLOCK(sc); 1811 return; 1812 } 1813 1814 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1815 VGE_UNLOCK(sc); 1816 return; 1817 } 1818 1819 idx = sc->vge_ldata.vge_tx_prodidx; 1820 1821 pidx = idx - 1; 1822 if (pidx < 0) 1823 pidx = VGE_TX_DESC_CNT - 1; 1824 1825 1826 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1827 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1828 if (m_head == NULL) 1829 break; 1830 1831 if (vge_encap(sc, m_head, idx)) { 1832 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1833 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1834 break; 1835 } 1836 1837 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1838 htole16(VGE_TXDESC_Q); 1839 1840 pidx = idx; 1841 VGE_TX_DESC_INC(idx); 1842 1843 /* 1844 * If there's a BPF listener, bounce a copy of this frame 1845 * to him. 1846 */ 1847 ETHER_BPF_MTAP(ifp, m_head); 1848 } 1849 1850 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1851 VGE_UNLOCK(sc); 1852 return; 1853 } 1854 1855 /* Flush the TX descriptors */ 1856 1857 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1858 sc->vge_ldata.vge_tx_list_map, 1859 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1860 1861 /* Issue a transmit command. */ 1862 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1863 1864 sc->vge_ldata.vge_tx_prodidx = idx; 1865 1866 /* 1867 * Use the countdown timer for interrupt moderation. 1868 * 'TX done' interrupts are disabled. Instead, we reset the 1869 * countdown timer, which will begin counting until it hits 1870 * the value in the SSTIMER register, and then trigger an 1871 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1872 * the timer count is reloaded. Only when the transmitter 1873 * is idle will the timer hit 0 and an interrupt fire. 1874 */ 1875 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1876 1877 VGE_UNLOCK(sc); 1878 1879 /* 1880 * Set a timeout in case the chip goes out to lunch. 1881 */ 1882 ifp->if_timer = 5; 1883 1884 return; 1885 } 1886 1887 static void 1888 vge_init(xsc) 1889 void *xsc; 1890 { 1891 struct vge_softc *sc = xsc; 1892 struct ifnet *ifp = sc->vge_ifp; 1893 struct mii_data *mii; 1894 int i; 1895 1896 VGE_LOCK(sc); 1897 mii = device_get_softc(sc->vge_miibus); 1898 1899 /* 1900 * Cancel pending I/O and free all RX/TX buffers. 1901 */ 1902 vge_stop(sc); 1903 vge_reset(sc); 1904 1905 /* 1906 * Initialize the RX and TX descriptors and mbufs. 1907 */ 1908 1909 vge_rx_list_init(sc); 1910 vge_tx_list_init(sc); 1911 1912 /* Set our station address */ 1913 for (i = 0; i < ETHER_ADDR_LEN; i++) 1914 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1915 1916 /* 1917 * Set receive FIFO threshold. Also allow transmission and 1918 * reception of VLAN tagged frames. 1919 */ 1920 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1921 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1922 1923 /* Set DMA burst length */ 1924 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1925 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1926 1927 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1928 1929 /* Set collision backoff algorithm */ 1930 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1931 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1932 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1933 1934 /* Disable LPSEL field in priority resolution */ 1935 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1936 1937 /* 1938 * Load the addresses of the DMA queues into the chip. 1939 * Note that we only use one transmit queue. 1940 */ 1941 1942 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1943 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1944 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1945 1946 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1947 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1948 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1949 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1950 1951 /* Enable and wake up the RX descriptor queue */ 1952 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1953 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1954 1955 /* Enable the TX descriptor queue */ 1956 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1957 1958 /* Set up the receive filter -- allow large frames for VLANs. */ 1959 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1960 1961 /* If we want promiscuous mode, set the allframes bit. */ 1962 if (ifp->if_flags & IFF_PROMISC) { 1963 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1964 } 1965 1966 /* Set capture broadcast bit to capture broadcast frames. */ 1967 if (ifp->if_flags & IFF_BROADCAST) { 1968 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1969 } 1970 1971 /* Set multicast bit to capture multicast frames. */ 1972 if (ifp->if_flags & IFF_MULTICAST) { 1973 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1974 } 1975 1976 /* Init the cam filter. */ 1977 vge_cam_clear(sc); 1978 1979 /* Init the multicast filter. */ 1980 vge_setmulti(sc); 1981 1982 /* Enable flow control */ 1983 1984 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1985 1986 /* Enable jumbo frame reception (if desired) */ 1987 1988 /* Start the MAC. */ 1989 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1990 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1991 CSR_WRITE_1(sc, VGE_CRS0, 1992 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1993 1994 /* 1995 * Configure one-shot timer for microsecond 1996 * resulution and load it for 500 usecs. 1997 */ 1998 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1999 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2000 2001 /* 2002 * Configure interrupt moderation for receive. Enable 2003 * the holdoff counter and load it, and set the RX 2004 * suppression count to the number of descriptors we 2005 * want to allow before triggering an interrupt. 2006 * The holdoff timer is in units of 20 usecs. 2007 */ 2008 2009 #ifdef notyet 2010 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2011 /* Select the interrupt holdoff timer page. */ 2012 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2013 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2014 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2015 2016 /* Enable use of the holdoff timer. */ 2017 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2018 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2019 2020 /* Select the RX suppression threshold page. */ 2021 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2022 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2023 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2024 2025 /* Restore the page select bits. */ 2026 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2027 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2028 #endif 2029 2030 #ifdef DEVICE_POLLING 2031 /* 2032 * Disable interrupts if we are polling. 2033 */ 2034 if (ifp->if_capenable & IFCAP_POLLING) { 2035 CSR_WRITE_4(sc, VGE_IMR, 0); 2036 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2037 } else /* otherwise ... */ 2038 #endif 2039 { 2040 /* 2041 * Enable interrupts. 2042 */ 2043 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2044 CSR_WRITE_4(sc, VGE_ISR, 0); 2045 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2046 } 2047 2048 mii_mediachg(mii); 2049 2050 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2051 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2052 2053 sc->vge_if_flags = 0; 2054 sc->vge_link = 0; 2055 2056 VGE_UNLOCK(sc); 2057 2058 return; 2059 } 2060 2061 /* 2062 * Set media options. 2063 */ 2064 static int 2065 vge_ifmedia_upd(ifp) 2066 struct ifnet *ifp; 2067 { 2068 struct vge_softc *sc; 2069 struct mii_data *mii; 2070 2071 sc = ifp->if_softc; 2072 VGE_LOCK(sc); 2073 mii = device_get_softc(sc->vge_miibus); 2074 mii_mediachg(mii); 2075 VGE_UNLOCK(sc); 2076 2077 return (0); 2078 } 2079 2080 /* 2081 * Report current media status. 2082 */ 2083 static void 2084 vge_ifmedia_sts(ifp, ifmr) 2085 struct ifnet *ifp; 2086 struct ifmediareq *ifmr; 2087 { 2088 struct vge_softc *sc; 2089 struct mii_data *mii; 2090 2091 sc = ifp->if_softc; 2092 mii = device_get_softc(sc->vge_miibus); 2093 2094 mii_pollstat(mii); 2095 ifmr->ifm_active = mii->mii_media_active; 2096 ifmr->ifm_status = mii->mii_media_status; 2097 2098 return; 2099 } 2100 2101 static void 2102 vge_miibus_statchg(dev) 2103 device_t dev; 2104 { 2105 struct vge_softc *sc; 2106 struct mii_data *mii; 2107 struct ifmedia_entry *ife; 2108 2109 sc = device_get_softc(dev); 2110 mii = device_get_softc(sc->vge_miibus); 2111 ife = mii->mii_media.ifm_cur; 2112 2113 /* 2114 * If the user manually selects a media mode, we need to turn 2115 * on the forced MAC mode bit in the DIAGCTL register. If the 2116 * user happens to choose a full duplex mode, we also need to 2117 * set the 'force full duplex' bit. This applies only to 2118 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2119 * mode is disabled, and in 1000baseT mode, full duplex is 2120 * always implied, so we turn on the forced mode bit but leave 2121 * the FDX bit cleared. 2122 */ 2123 2124 switch (IFM_SUBTYPE(ife->ifm_media)) { 2125 case IFM_AUTO: 2126 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2127 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2128 break; 2129 case IFM_1000_T: 2130 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2131 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2132 break; 2133 case IFM_100_TX: 2134 case IFM_10_T: 2135 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2136 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2137 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2138 } else { 2139 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2140 } 2141 break; 2142 default: 2143 device_printf(dev, "unknown media type: %x\n", 2144 IFM_SUBTYPE(ife->ifm_media)); 2145 break; 2146 } 2147 2148 return; 2149 } 2150 2151 static int 2152 vge_ioctl(ifp, command, data) 2153 struct ifnet *ifp; 2154 u_long command; 2155 caddr_t data; 2156 { 2157 struct vge_softc *sc = ifp->if_softc; 2158 struct ifreq *ifr = (struct ifreq *) data; 2159 struct mii_data *mii; 2160 int error = 0; 2161 2162 switch (command) { 2163 case SIOCSIFMTU: 2164 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2165 error = EINVAL; 2166 ifp->if_mtu = ifr->ifr_mtu; 2167 break; 2168 case SIOCSIFFLAGS: 2169 if (ifp->if_flags & IFF_UP) { 2170 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2171 ifp->if_flags & IFF_PROMISC && 2172 !(sc->vge_if_flags & IFF_PROMISC)) { 2173 CSR_SETBIT_1(sc, VGE_RXCTL, 2174 VGE_RXCTL_RX_PROMISC); 2175 vge_setmulti(sc); 2176 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2177 !(ifp->if_flags & IFF_PROMISC) && 2178 sc->vge_if_flags & IFF_PROMISC) { 2179 CSR_CLRBIT_1(sc, VGE_RXCTL, 2180 VGE_RXCTL_RX_PROMISC); 2181 vge_setmulti(sc); 2182 } else 2183 vge_init(sc); 2184 } else { 2185 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2186 vge_stop(sc); 2187 } 2188 sc->vge_if_flags = ifp->if_flags; 2189 break; 2190 case SIOCADDMULTI: 2191 case SIOCDELMULTI: 2192 vge_setmulti(sc); 2193 break; 2194 case SIOCGIFMEDIA: 2195 case SIOCSIFMEDIA: 2196 mii = device_get_softc(sc->vge_miibus); 2197 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2198 break; 2199 case SIOCSIFCAP: 2200 { 2201 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2202 #ifdef DEVICE_POLLING 2203 if (mask & IFCAP_POLLING) { 2204 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2205 error = ether_poll_register(vge_poll, ifp); 2206 if (error) 2207 return(error); 2208 VGE_LOCK(sc); 2209 /* Disable interrupts */ 2210 CSR_WRITE_4(sc, VGE_IMR, 0); 2211 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2212 ifp->if_capenable |= IFCAP_POLLING; 2213 VGE_UNLOCK(sc); 2214 } else { 2215 error = ether_poll_deregister(ifp); 2216 /* Enable interrupts. */ 2217 VGE_LOCK(sc); 2218 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2219 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2220 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2221 ifp->if_capenable &= ~IFCAP_POLLING; 2222 VGE_UNLOCK(sc); 2223 } 2224 } 2225 #endif /* DEVICE_POLLING */ 2226 if ((mask & IFCAP_TXCSUM) != 0 && 2227 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2228 ifp->if_capenable ^= IFCAP_TXCSUM; 2229 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2230 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2231 else 2232 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2233 } 2234 if ((mask & IFCAP_RXCSUM) != 0 && 2235 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2236 ifp->if_capenable ^= IFCAP_RXCSUM; 2237 } 2238 break; 2239 default: 2240 error = ether_ioctl(ifp, command, data); 2241 break; 2242 } 2243 2244 return (error); 2245 } 2246 2247 static void 2248 vge_watchdog(ifp) 2249 struct ifnet *ifp; 2250 { 2251 struct vge_softc *sc; 2252 2253 sc = ifp->if_softc; 2254 VGE_LOCK(sc); 2255 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2256 ifp->if_oerrors++; 2257 2258 vge_txeof(sc); 2259 vge_rxeof(sc); 2260 2261 vge_init(sc); 2262 2263 VGE_UNLOCK(sc); 2264 2265 return; 2266 } 2267 2268 /* 2269 * Stop the adapter and free any mbufs allocated to the 2270 * RX and TX lists. 2271 */ 2272 static void 2273 vge_stop(sc) 2274 struct vge_softc *sc; 2275 { 2276 register int i; 2277 struct ifnet *ifp; 2278 2279 VGE_LOCK(sc); 2280 ifp = sc->vge_ifp; 2281 ifp->if_timer = 0; 2282 2283 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2284 2285 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2286 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2287 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2288 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2289 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2290 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2291 2292 if (sc->vge_head != NULL) { 2293 m_freem(sc->vge_head); 2294 sc->vge_head = sc->vge_tail = NULL; 2295 } 2296 2297 /* Free the TX list buffers. */ 2298 2299 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2300 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2301 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2302 sc->vge_ldata.vge_tx_dmamap[i]); 2303 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2304 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2305 } 2306 } 2307 2308 /* Free the RX list buffers. */ 2309 2310 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2311 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2312 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2313 sc->vge_ldata.vge_rx_dmamap[i]); 2314 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2315 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2316 } 2317 } 2318 2319 VGE_UNLOCK(sc); 2320 2321 return; 2322 } 2323 2324 /* 2325 * Device suspend routine. Stop the interface and save some PCI 2326 * settings in case the BIOS doesn't restore them properly on 2327 * resume. 2328 */ 2329 static int 2330 vge_suspend(dev) 2331 device_t dev; 2332 { 2333 struct vge_softc *sc; 2334 2335 sc = device_get_softc(dev); 2336 2337 vge_stop(sc); 2338 2339 sc->suspended = 1; 2340 2341 return (0); 2342 } 2343 2344 /* 2345 * Device resume routine. Restore some PCI settings in case the BIOS 2346 * doesn't, re-enable busmastering, and restart the interface if 2347 * appropriate. 2348 */ 2349 static int 2350 vge_resume(dev) 2351 device_t dev; 2352 { 2353 struct vge_softc *sc; 2354 struct ifnet *ifp; 2355 2356 sc = device_get_softc(dev); 2357 ifp = sc->vge_ifp; 2358 2359 /* reenable busmastering */ 2360 pci_enable_busmaster(dev); 2361 pci_enable_io(dev, SYS_RES_MEMORY); 2362 2363 /* reinitialize interface if necessary */ 2364 if (ifp->if_flags & IFF_UP) 2365 vge_init(sc); 2366 2367 sc->suspended = 0; 2368 2369 return (0); 2370 } 2371 2372 /* 2373 * Stop all chip I/O so that the kernel's probe routines don't 2374 * get confused by errant DMAs when rebooting. 2375 */ 2376 static int 2377 vge_shutdown(dev) 2378 device_t dev; 2379 { 2380 struct vge_softc *sc; 2381 2382 sc = device_get_softc(dev); 2383 2384 vge_stop(sc); 2385 2386 return (0); 2387 } 2388