1098ca2bdSWarner Losh /*- 2a07bd003SBill Paul * Copyright (c) 2004 3a07bd003SBill Paul * Bill Paul <wpaul@windriver.com>. All rights reserved. 4a07bd003SBill Paul * 5a07bd003SBill Paul * Redistribution and use in source and binary forms, with or without 6a07bd003SBill Paul * modification, are permitted provided that the following conditions 7a07bd003SBill Paul * are met: 8a07bd003SBill Paul * 1. Redistributions of source code must retain the above copyright 9a07bd003SBill Paul * notice, this list of conditions and the following disclaimer. 10a07bd003SBill Paul * 2. Redistributions in binary form must reproduce the above copyright 11a07bd003SBill Paul * notice, this list of conditions and the following disclaimer in the 12a07bd003SBill Paul * documentation and/or other materials provided with the distribution. 13a07bd003SBill Paul * 3. All advertising materials mentioning features or use of this software 14a07bd003SBill Paul * must display the following acknowledgement: 15a07bd003SBill Paul * This product includes software developed by Bill Paul. 16a07bd003SBill Paul * 4. Neither the name of the author nor the names of any co-contributors 17a07bd003SBill Paul * may be used to endorse or promote products derived from this software 18a07bd003SBill Paul * without specific prior written permission. 19a07bd003SBill Paul * 20a07bd003SBill Paul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21a07bd003SBill Paul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22a07bd003SBill Paul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23a07bd003SBill Paul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24a07bd003SBill Paul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25a07bd003SBill Paul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26a07bd003SBill Paul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27a07bd003SBill Paul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28a07bd003SBill Paul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29a07bd003SBill Paul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30a07bd003SBill Paul * THE POSSIBILITY OF SUCH DAMAGE. 31a07bd003SBill Paul */ 32a07bd003SBill Paul 33a07bd003SBill Paul #include <sys/cdefs.h> 34a07bd003SBill Paul __FBSDID("$FreeBSD$"); 35a07bd003SBill Paul 36a07bd003SBill Paul /* 37a07bd003SBill Paul * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38a07bd003SBill Paul * 39a07bd003SBill Paul * Written by Bill Paul <wpaul@windriver.com> 40a07bd003SBill Paul * Senior Networking Software Engineer 41a07bd003SBill Paul * Wind River Systems 42a07bd003SBill Paul */ 43a07bd003SBill Paul 44a07bd003SBill Paul /* 45a07bd003SBill Paul * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46a07bd003SBill Paul * combines a tri-speed ethernet MAC and PHY, with the following 47a07bd003SBill Paul * features: 48a07bd003SBill Paul * 49a07bd003SBill Paul * o Jumbo frame support up to 16K 50a07bd003SBill Paul * o Transmit and receive flow control 51a07bd003SBill Paul * o IPv4 checksum offload 52a07bd003SBill Paul * o VLAN tag insertion and stripping 53a07bd003SBill Paul * o TCP large send 54a07bd003SBill Paul * o 64-bit multicast hash table filter 55a07bd003SBill Paul * o 64 entry CAM filter 56a07bd003SBill Paul * o 16K RX FIFO and 48K TX FIFO memory 57a07bd003SBill Paul * o Interrupt moderation 58a07bd003SBill Paul * 59a07bd003SBill Paul * The VT6122 supports up to four transmit DMA queues. The descriptors 60a07bd003SBill Paul * in the transmit ring can address up to 7 data fragments; frames which 61a07bd003SBill Paul * span more than 7 data buffers must be coalesced, but in general the 62a07bd003SBill Paul * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63a07bd003SBill Paul * long. The receive descriptors address only a single buffer. 64a07bd003SBill Paul * 65a07bd003SBill Paul * There are two peculiar design issues with the VT6122. One is that 66a07bd003SBill Paul * receive data buffers must be aligned on a 32-bit boundary. This is 67a07bd003SBill Paul * not a problem where the VT6122 is used as a LOM device in x86-based 68a07bd003SBill Paul * systems, but on architectures that generate unaligned access traps, we 69a07bd003SBill Paul * have to do some copying. 70a07bd003SBill Paul * 71a07bd003SBill Paul * The other issue has to do with the way 64-bit addresses are handled. 72a07bd003SBill Paul * The DMA descriptors only allow you to specify 48 bits of addressing 73a07bd003SBill Paul * information. The remaining 16 bits are specified using one of the 74a07bd003SBill Paul * I/O registers. If you only have a 32-bit system, then this isn't 75a07bd003SBill Paul * an issue, but if you have a 64-bit system and more than 4GB of 76a07bd003SBill Paul * memory, you must have to make sure your network data buffers reside 77a07bd003SBill Paul * in the same 48-bit 'segment.' 78a07bd003SBill Paul * 79a07bd003SBill Paul * Special thanks to Ryan Fu at VIA Networking for providing documentation 80a07bd003SBill Paul * and sample NICs for testing. 81a07bd003SBill Paul */ 82a07bd003SBill Paul 83f0796cd2SGleb Smirnoff #ifdef HAVE_KERNEL_OPTION_HEADERS 84f0796cd2SGleb Smirnoff #include "opt_device_polling.h" 85f0796cd2SGleb Smirnoff #endif 86f0796cd2SGleb Smirnoff 87a07bd003SBill Paul #include <sys/param.h> 88a07bd003SBill Paul #include <sys/endian.h> 89a07bd003SBill Paul #include <sys/systm.h> 90a07bd003SBill Paul #include <sys/sockio.h> 91a07bd003SBill Paul #include <sys/mbuf.h> 92a07bd003SBill Paul #include <sys/malloc.h> 93a07bd003SBill Paul #include <sys/module.h> 94a07bd003SBill Paul #include <sys/kernel.h> 95a07bd003SBill Paul #include <sys/socket.h> 967129fb20SPyun YongHyeon #include <sys/sysctl.h> 97a07bd003SBill Paul 98a07bd003SBill Paul #include <net/if.h> 99a07bd003SBill Paul #include <net/if_arp.h> 100a07bd003SBill Paul #include <net/ethernet.h> 101a07bd003SBill Paul #include <net/if_dl.h> 102a07bd003SBill Paul #include <net/if_media.h> 103fc74a9f9SBrooks Davis #include <net/if_types.h> 104a07bd003SBill Paul #include <net/if_vlan_var.h> 105a07bd003SBill Paul 106a07bd003SBill Paul #include <net/bpf.h> 107a07bd003SBill Paul 108a07bd003SBill Paul #include <machine/bus.h> 109a07bd003SBill Paul #include <machine/resource.h> 110a07bd003SBill Paul #include <sys/bus.h> 111a07bd003SBill Paul #include <sys/rman.h> 112a07bd003SBill Paul 113a07bd003SBill Paul #include <dev/mii/mii.h> 114a07bd003SBill Paul #include <dev/mii/miivar.h> 115a07bd003SBill Paul 116a07bd003SBill Paul #include <dev/pci/pcireg.h> 117a07bd003SBill Paul #include <dev/pci/pcivar.h> 118a07bd003SBill Paul 119a07bd003SBill Paul MODULE_DEPEND(vge, pci, 1, 1, 1); 120a07bd003SBill Paul MODULE_DEPEND(vge, ether, 1, 1, 1); 121a07bd003SBill Paul MODULE_DEPEND(vge, miibus, 1, 1, 1); 122a07bd003SBill Paul 1237b279558SWarner Losh /* "device miibus" required. See GENERIC if you get errors here. */ 124a07bd003SBill Paul #include "miibus_if.h" 125a07bd003SBill Paul 126a07bd003SBill Paul #include <dev/vge/if_vgereg.h> 127a07bd003SBill Paul #include <dev/vge/if_vgevar.h> 128a07bd003SBill Paul 129a07bd003SBill Paul #define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130a07bd003SBill Paul 1315957cc2aSPyun YongHyeon /* Tunables */ 1325957cc2aSPyun YongHyeon static int msi_disable = 0; 1335957cc2aSPyun YongHyeon TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 1345957cc2aSPyun YongHyeon 135a07bd003SBill Paul /* 1367129fb20SPyun YongHyeon * The SQE error counter of MIB seems to report bogus value. 1377129fb20SPyun YongHyeon * Vendor's workaround does not seem to work on PCIe based 1387129fb20SPyun YongHyeon * controllers. Disable it until we find better workaround. 1397129fb20SPyun YongHyeon */ 1407129fb20SPyun YongHyeon #undef VGE_ENABLE_SQEERR 1417129fb20SPyun YongHyeon 1427129fb20SPyun YongHyeon /* 143a07bd003SBill Paul * Various supported device vendors/types and their names. 144a07bd003SBill Paul */ 145a07bd003SBill Paul static struct vge_type vge_devs[] = { 146a07bd003SBill Paul { VIA_VENDORID, VIA_DEVICEID_61XX, 147a07bd003SBill Paul "VIA Networking Gigabit Ethernet" }, 148a07bd003SBill Paul { 0, 0, NULL } 149a07bd003SBill Paul }; 150a07bd003SBill Paul 151a07bd003SBill Paul static int vge_attach(device_t); 152a07bd003SBill Paul static int vge_detach(device_t); 153e4027c49SPyun YongHyeon static int vge_probe(device_t); 154a07bd003SBill Paul static int vge_resume(device_t); 1556a087a87SPyun YongHyeon static int vge_shutdown(device_t); 156e4027c49SPyun YongHyeon static int vge_suspend(device_t); 157a07bd003SBill Paul 158a07bd003SBill Paul static void vge_cam_clear(struct vge_softc *); 159a07bd003SBill Paul static int vge_cam_set(struct vge_softc *, uint8_t *); 160e4027c49SPyun YongHyeon static void vge_discard_rxbuf(struct vge_softc *, int); 161e4027c49SPyun YongHyeon static int vge_dma_alloc(struct vge_softc *); 162e4027c49SPyun YongHyeon static void vge_dma_free(struct vge_softc *); 163e4027c49SPyun YongHyeon static void vge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 164e4027c49SPyun YongHyeon #ifdef VGE_EEPROM 165e4027c49SPyun YongHyeon static void vge_eeprom_getword(struct vge_softc *, int, uint16_t *); 166e4027c49SPyun YongHyeon #endif 167e4027c49SPyun YongHyeon static int vge_encap(struct vge_softc *, struct mbuf **); 168e4027c49SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 169e4027c49SPyun YongHyeon static __inline void 170e4027c49SPyun YongHyeon vge_fixup_rx(struct mbuf *); 171e4027c49SPyun YongHyeon #endif 172e4027c49SPyun YongHyeon static void vge_freebufs(struct vge_softc *); 173e4027c49SPyun YongHyeon static void vge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 174e4027c49SPyun YongHyeon static int vge_ifmedia_upd(struct ifnet *); 175e4027c49SPyun YongHyeon static void vge_init(void *); 176e4027c49SPyun YongHyeon static void vge_init_locked(struct vge_softc *); 177e4027c49SPyun YongHyeon static void vge_intr(void *); 178e4027c49SPyun YongHyeon static int vge_ioctl(struct ifnet *, u_long, caddr_t); 179e7b2d9b8SPyun YongHyeon static void vge_link_statchg(void *); 180e4027c49SPyun YongHyeon static int vge_miibus_readreg(device_t, int, int); 181e4027c49SPyun YongHyeon static void vge_miibus_statchg(device_t); 182e4027c49SPyun YongHyeon static int vge_miibus_writereg(device_t, int, int, int); 183e4027c49SPyun YongHyeon static void vge_miipoll_start(struct vge_softc *); 184e4027c49SPyun YongHyeon static void vge_miipoll_stop(struct vge_softc *); 185e4027c49SPyun YongHyeon static int vge_newbuf(struct vge_softc *, int); 186e4027c49SPyun YongHyeon static void vge_read_eeprom(struct vge_softc *, caddr_t, int, int, int); 187a07bd003SBill Paul static void vge_reset(struct vge_softc *); 188e4027c49SPyun YongHyeon static int vge_rx_list_init(struct vge_softc *); 189e4027c49SPyun YongHyeon static int vge_rxeof(struct vge_softc *, int); 1905f07fd19SPyun YongHyeon static void vge_rxfilter(struct vge_softc *); 19138aa43c5SPyun YongHyeon static void vge_setvlan(struct vge_softc *); 192e4027c49SPyun YongHyeon static void vge_start(struct ifnet *); 193e4027c49SPyun YongHyeon static void vge_start_locked(struct ifnet *); 1947129fb20SPyun YongHyeon static void vge_stats_clear(struct vge_softc *); 1957129fb20SPyun YongHyeon static void vge_stats_update(struct vge_softc *); 196e4027c49SPyun YongHyeon static void vge_stop(struct vge_softc *); 1977129fb20SPyun YongHyeon static void vge_sysctl_node(struct vge_softc *); 198e4027c49SPyun YongHyeon static int vge_tx_list_init(struct vge_softc *); 199e4027c49SPyun YongHyeon static void vge_txeof(struct vge_softc *); 200e4027c49SPyun YongHyeon static void vge_watchdog(void *); 201a07bd003SBill Paul 202a07bd003SBill Paul static device_method_t vge_methods[] = { 203a07bd003SBill Paul /* Device interface */ 204a07bd003SBill Paul DEVMETHOD(device_probe, vge_probe), 205a07bd003SBill Paul DEVMETHOD(device_attach, vge_attach), 206a07bd003SBill Paul DEVMETHOD(device_detach, vge_detach), 207a07bd003SBill Paul DEVMETHOD(device_suspend, vge_suspend), 208a07bd003SBill Paul DEVMETHOD(device_resume, vge_resume), 209a07bd003SBill Paul DEVMETHOD(device_shutdown, vge_shutdown), 210a07bd003SBill Paul 211a07bd003SBill Paul /* bus interface */ 212a07bd003SBill Paul DEVMETHOD(bus_print_child, bus_generic_print_child), 213a07bd003SBill Paul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 214a07bd003SBill Paul 215a07bd003SBill Paul /* MII interface */ 216a07bd003SBill Paul DEVMETHOD(miibus_readreg, vge_miibus_readreg), 217a07bd003SBill Paul DEVMETHOD(miibus_writereg, vge_miibus_writereg), 218a07bd003SBill Paul DEVMETHOD(miibus_statchg, vge_miibus_statchg), 219a07bd003SBill Paul 220a07bd003SBill Paul { 0, 0 } 221a07bd003SBill Paul }; 222a07bd003SBill Paul 223a07bd003SBill Paul static driver_t vge_driver = { 224a07bd003SBill Paul "vge", 225a07bd003SBill Paul vge_methods, 226a07bd003SBill Paul sizeof(struct vge_softc) 227a07bd003SBill Paul }; 228a07bd003SBill Paul 229a07bd003SBill Paul static devclass_t vge_devclass; 230a07bd003SBill Paul 231a07bd003SBill Paul DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 232a07bd003SBill Paul DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 233a07bd003SBill Paul 234bb74e5f6SBill Paul #ifdef VGE_EEPROM 235a07bd003SBill Paul /* 236a07bd003SBill Paul * Read a word of data stored in the EEPROM at address 'addr.' 237a07bd003SBill Paul */ 238a07bd003SBill Paul static void 239c3c74c61SPyun YongHyeon vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 240a07bd003SBill Paul { 241b534dcd5SPyun YongHyeon int i; 242c3c74c61SPyun YongHyeon uint16_t word = 0; 243a07bd003SBill Paul 244a07bd003SBill Paul /* 245a07bd003SBill Paul * Enter EEPROM embedded programming mode. In order to 246a07bd003SBill Paul * access the EEPROM at all, we first have to set the 247a07bd003SBill Paul * EELOAD bit in the CHIPCFG2 register. 248a07bd003SBill Paul */ 249a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 250a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 251a07bd003SBill Paul 252a07bd003SBill Paul /* Select the address of the word we want to read */ 253a07bd003SBill Paul CSR_WRITE_1(sc, VGE_EEADDR, addr); 254a07bd003SBill Paul 255a07bd003SBill Paul /* Issue read command */ 256a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 257a07bd003SBill Paul 258a07bd003SBill Paul /* Wait for the done bit to be set. */ 259a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 260a07bd003SBill Paul if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 261a07bd003SBill Paul break; 262a07bd003SBill Paul } 263a07bd003SBill Paul 264a07bd003SBill Paul if (i == VGE_TIMEOUT) { 265a07bd003SBill Paul device_printf(sc->vge_dev, "EEPROM read timed out\n"); 266a07bd003SBill Paul *dest = 0; 267a07bd003SBill Paul return; 268a07bd003SBill Paul } 269a07bd003SBill Paul 270a07bd003SBill Paul /* Read the result */ 271a07bd003SBill Paul word = CSR_READ_2(sc, VGE_EERDDAT); 272a07bd003SBill Paul 273a07bd003SBill Paul /* Turn off EEPROM access mode. */ 274a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 275a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 276a07bd003SBill Paul 277a07bd003SBill Paul *dest = word; 278a07bd003SBill Paul } 279bb74e5f6SBill Paul #endif 280a07bd003SBill Paul 281a07bd003SBill Paul /* 282a07bd003SBill Paul * Read a sequence of words from the EEPROM. 283a07bd003SBill Paul */ 284a07bd003SBill Paul static void 2856afe22a8SPyun YongHyeon vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 286a07bd003SBill Paul { 287a07bd003SBill Paul int i; 288bb74e5f6SBill Paul #ifdef VGE_EEPROM 289c3c74c61SPyun YongHyeon uint16_t word = 0, *ptr; 290a07bd003SBill Paul 291a07bd003SBill Paul for (i = 0; i < cnt; i++) { 292a07bd003SBill Paul vge_eeprom_getword(sc, off + i, &word); 293c3c74c61SPyun YongHyeon ptr = (uint16_t *)(dest + (i * 2)); 294a07bd003SBill Paul if (swap) 295a07bd003SBill Paul *ptr = ntohs(word); 296a07bd003SBill Paul else 297a07bd003SBill Paul *ptr = word; 298a07bd003SBill Paul } 299bb74e5f6SBill Paul #else 300bb74e5f6SBill Paul for (i = 0; i < ETHER_ADDR_LEN; i++) 301bb74e5f6SBill Paul dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 302bb74e5f6SBill Paul #endif 303a07bd003SBill Paul } 304a07bd003SBill Paul 305a07bd003SBill Paul static void 3066afe22a8SPyun YongHyeon vge_miipoll_stop(struct vge_softc *sc) 307a07bd003SBill Paul { 308a07bd003SBill Paul int i; 309a07bd003SBill Paul 310a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIICMD, 0); 311a07bd003SBill Paul 312a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 313a07bd003SBill Paul DELAY(1); 314a07bd003SBill Paul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 315a07bd003SBill Paul break; 316a07bd003SBill Paul } 317a07bd003SBill Paul 318a07bd003SBill Paul if (i == VGE_TIMEOUT) 319a07bd003SBill Paul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 320a07bd003SBill Paul } 321a07bd003SBill Paul 322a07bd003SBill Paul static void 3236afe22a8SPyun YongHyeon vge_miipoll_start(struct vge_softc *sc) 324a07bd003SBill Paul { 325a07bd003SBill Paul int i; 326a07bd003SBill Paul 327a07bd003SBill Paul /* First, make sure we're idle. */ 328a07bd003SBill Paul 329a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIICMD, 0); 330a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 331a07bd003SBill Paul 332a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 333a07bd003SBill Paul DELAY(1); 334a07bd003SBill Paul if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 335a07bd003SBill Paul break; 336a07bd003SBill Paul } 337a07bd003SBill Paul 338a07bd003SBill Paul if (i == VGE_TIMEOUT) { 339a07bd003SBill Paul device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 340a07bd003SBill Paul return; 341a07bd003SBill Paul } 342a07bd003SBill Paul 343a07bd003SBill Paul /* Now enable auto poll mode. */ 344a07bd003SBill Paul 345a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 346a07bd003SBill Paul 347a07bd003SBill Paul /* And make sure it started. */ 348a07bd003SBill Paul 349a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 350a07bd003SBill Paul DELAY(1); 351a07bd003SBill Paul if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 352a07bd003SBill Paul break; 353a07bd003SBill Paul } 354a07bd003SBill Paul 355a07bd003SBill Paul if (i == VGE_TIMEOUT) 356a07bd003SBill Paul device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 357a07bd003SBill Paul } 358a07bd003SBill Paul 359a07bd003SBill Paul static int 3606afe22a8SPyun YongHyeon vge_miibus_readreg(device_t dev, int phy, int reg) 361a07bd003SBill Paul { 362a07bd003SBill Paul struct vge_softc *sc; 363a07bd003SBill Paul int i; 364c3c74c61SPyun YongHyeon uint16_t rval = 0; 365a07bd003SBill Paul 366a07bd003SBill Paul sc = device_get_softc(dev); 367a07bd003SBill Paul 368643e9ee9SPyun YongHyeon if (phy != sc->vge_phyaddr) 369a07bd003SBill Paul return (0); 370a07bd003SBill Paul 371a07bd003SBill Paul vge_miipoll_stop(sc); 372a07bd003SBill Paul 373a07bd003SBill Paul /* Specify the register we want to read. */ 374a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 375a07bd003SBill Paul 376a07bd003SBill Paul /* Issue read command. */ 377a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 378a07bd003SBill Paul 379a07bd003SBill Paul /* Wait for the read command bit to self-clear. */ 380a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 381a07bd003SBill Paul DELAY(1); 382a07bd003SBill Paul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 383a07bd003SBill Paul break; 384a07bd003SBill Paul } 385a07bd003SBill Paul 386a07bd003SBill Paul if (i == VGE_TIMEOUT) 387a07bd003SBill Paul device_printf(sc->vge_dev, "MII read timed out\n"); 388a07bd003SBill Paul else 389a07bd003SBill Paul rval = CSR_READ_2(sc, VGE_MIIDATA); 390a07bd003SBill Paul 391a07bd003SBill Paul vge_miipoll_start(sc); 392a07bd003SBill Paul 393a07bd003SBill Paul return (rval); 394a07bd003SBill Paul } 395a07bd003SBill Paul 396a07bd003SBill Paul static int 3976afe22a8SPyun YongHyeon vge_miibus_writereg(device_t dev, int phy, int reg, int data) 398a07bd003SBill Paul { 399a07bd003SBill Paul struct vge_softc *sc; 400a07bd003SBill Paul int i, rval = 0; 401a07bd003SBill Paul 402a07bd003SBill Paul sc = device_get_softc(dev); 403a07bd003SBill Paul 404643e9ee9SPyun YongHyeon if (phy != sc->vge_phyaddr) 405a07bd003SBill Paul return (0); 406a07bd003SBill Paul 407a07bd003SBill Paul vge_miipoll_stop(sc); 408a07bd003SBill Paul 409a07bd003SBill Paul /* Specify the register we want to write. */ 410a07bd003SBill Paul CSR_WRITE_1(sc, VGE_MIIADDR, reg); 411a07bd003SBill Paul 412a07bd003SBill Paul /* Specify the data we want to write. */ 413a07bd003SBill Paul CSR_WRITE_2(sc, VGE_MIIDATA, data); 414a07bd003SBill Paul 415a07bd003SBill Paul /* Issue write command. */ 416a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 417a07bd003SBill Paul 418a07bd003SBill Paul /* Wait for the write command bit to self-clear. */ 419a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 420a07bd003SBill Paul DELAY(1); 421a07bd003SBill Paul if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 422a07bd003SBill Paul break; 423a07bd003SBill Paul } 424a07bd003SBill Paul 425a07bd003SBill Paul if (i == VGE_TIMEOUT) { 426a07bd003SBill Paul device_printf(sc->vge_dev, "MII write timed out\n"); 427a07bd003SBill Paul rval = EIO; 428a07bd003SBill Paul } 429a07bd003SBill Paul 430a07bd003SBill Paul vge_miipoll_start(sc); 431a07bd003SBill Paul 432a07bd003SBill Paul return (rval); 433a07bd003SBill Paul } 434a07bd003SBill Paul 435a07bd003SBill Paul static void 4366afe22a8SPyun YongHyeon vge_cam_clear(struct vge_softc *sc) 437a07bd003SBill Paul { 438a07bd003SBill Paul int i; 439a07bd003SBill Paul 440a07bd003SBill Paul /* 441a07bd003SBill Paul * Turn off all the mask bits. This tells the chip 442a07bd003SBill Paul * that none of the entries in the CAM filter are valid. 443a07bd003SBill Paul * desired entries will be enabled as we fill the filter in. 444a07bd003SBill Paul */ 445a07bd003SBill Paul 446a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 447a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 448a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 449a07bd003SBill Paul for (i = 0; i < 8; i++) 450a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 451a07bd003SBill Paul 452a07bd003SBill Paul /* Clear the VLAN filter too. */ 453a07bd003SBill Paul 454a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 455a07bd003SBill Paul for (i = 0; i < 8; i++) 456a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 457a07bd003SBill Paul 458a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 459a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 460a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 461a07bd003SBill Paul 462a07bd003SBill Paul sc->vge_camidx = 0; 463a07bd003SBill Paul } 464a07bd003SBill Paul 465a07bd003SBill Paul static int 4666afe22a8SPyun YongHyeon vge_cam_set(struct vge_softc *sc, uint8_t *addr) 467a07bd003SBill Paul { 468a07bd003SBill Paul int i, error = 0; 469a07bd003SBill Paul 470a07bd003SBill Paul if (sc->vge_camidx == VGE_CAM_MAXADDRS) 471a07bd003SBill Paul return (ENOSPC); 472a07bd003SBill Paul 473a07bd003SBill Paul /* Select the CAM data page. */ 474a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 475a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 476a07bd003SBill Paul 477a07bd003SBill Paul /* Set the filter entry we want to update and enable writing. */ 478a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 479a07bd003SBill Paul 480a07bd003SBill Paul /* Write the address to the CAM registers */ 481a07bd003SBill Paul for (i = 0; i < ETHER_ADDR_LEN; i++) 482a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 483a07bd003SBill Paul 484a07bd003SBill Paul /* Issue a write command. */ 485a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 486a07bd003SBill Paul 487a07bd003SBill Paul /* Wake for it to clear. */ 488a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 489a07bd003SBill Paul DELAY(1); 490a07bd003SBill Paul if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 491a07bd003SBill Paul break; 492a07bd003SBill Paul } 493a07bd003SBill Paul 494a07bd003SBill Paul if (i == VGE_TIMEOUT) { 495a07bd003SBill Paul device_printf(sc->vge_dev, "setting CAM filter failed\n"); 496a07bd003SBill Paul error = EIO; 497a07bd003SBill Paul goto fail; 498a07bd003SBill Paul } 499a07bd003SBill Paul 500a07bd003SBill Paul /* Select the CAM mask page. */ 501a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 502a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 503a07bd003SBill Paul 504a07bd003SBill Paul /* Set the mask bit that enables this filter. */ 505a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 506a07bd003SBill Paul 1<<(sc->vge_camidx & 7)); 507a07bd003SBill Paul 508a07bd003SBill Paul sc->vge_camidx++; 509a07bd003SBill Paul 510a07bd003SBill Paul fail: 511a07bd003SBill Paul /* Turn off access to CAM. */ 512a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CAMADDR, 0); 513a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 514a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 515a07bd003SBill Paul 516a07bd003SBill Paul return (error); 517a07bd003SBill Paul } 518a07bd003SBill Paul 51938aa43c5SPyun YongHyeon static void 52038aa43c5SPyun YongHyeon vge_setvlan(struct vge_softc *sc) 52138aa43c5SPyun YongHyeon { 52238aa43c5SPyun YongHyeon struct ifnet *ifp; 52338aa43c5SPyun YongHyeon uint8_t cfg; 52438aa43c5SPyun YongHyeon 52538aa43c5SPyun YongHyeon VGE_LOCK_ASSERT(sc); 52638aa43c5SPyun YongHyeon 52738aa43c5SPyun YongHyeon ifp = sc->vge_ifp; 52838aa43c5SPyun YongHyeon cfg = CSR_READ_1(sc, VGE_RXCFG); 52938aa43c5SPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 53038aa43c5SPyun YongHyeon cfg |= VGE_VTAG_OPT2; 53138aa43c5SPyun YongHyeon else 53238aa43c5SPyun YongHyeon cfg &= ~VGE_VTAG_OPT2; 53338aa43c5SPyun YongHyeon CSR_WRITE_1(sc, VGE_RXCFG, cfg); 53438aa43c5SPyun YongHyeon } 53538aa43c5SPyun YongHyeon 536a07bd003SBill Paul /* 537a07bd003SBill Paul * Program the multicast filter. We use the 64-entry CAM filter 538a07bd003SBill Paul * for perfect filtering. If there's more than 64 multicast addresses, 5398170b243SPyun YongHyeon * we use the hash filter instead. 540a07bd003SBill Paul */ 541a07bd003SBill Paul static void 5425f07fd19SPyun YongHyeon vge_rxfilter(struct vge_softc *sc) 543a07bd003SBill Paul { 544a07bd003SBill Paul struct ifnet *ifp; 545a07bd003SBill Paul struct ifmultiaddr *ifma; 5465f07fd19SPyun YongHyeon uint32_t h, hashes[2]; 5475f07fd19SPyun YongHyeon uint8_t rxcfg; 5485f07fd19SPyun YongHyeon int error = 0; 549a07bd003SBill Paul 550410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 551410f4c60SPyun YongHyeon 552a07bd003SBill Paul /* First, zot all the multicast entries. */ 5535f07fd19SPyun YongHyeon hashes[0] = 0; 5545f07fd19SPyun YongHyeon hashes[1] = 0; 555a07bd003SBill Paul 5565f07fd19SPyun YongHyeon rxcfg = CSR_READ_1(sc, VGE_RXCTL); 5575f07fd19SPyun YongHyeon rxcfg &= ~(VGE_RXCTL_RX_MCAST | VGE_RXCTL_RX_BCAST | 5585f07fd19SPyun YongHyeon VGE_RXCTL_RX_PROMISC); 559a07bd003SBill Paul /* 5605f07fd19SPyun YongHyeon * Always allow VLAN oversized frames and frames for 5615f07fd19SPyun YongHyeon * this host. 562a07bd003SBill Paul */ 5635f07fd19SPyun YongHyeon rxcfg |= VGE_RXCTL_RX_GIANT | VGE_RXCTL_RX_UCAST; 5645f07fd19SPyun YongHyeon 5655f07fd19SPyun YongHyeon ifp = sc->vge_ifp; 5665f07fd19SPyun YongHyeon if ((ifp->if_flags & IFF_BROADCAST) != 0) 5675f07fd19SPyun YongHyeon rxcfg |= VGE_RXCTL_RX_BCAST; 5685f07fd19SPyun YongHyeon if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5695f07fd19SPyun YongHyeon if ((ifp->if_flags & IFF_PROMISC) != 0) 5705f07fd19SPyun YongHyeon rxcfg |= VGE_RXCTL_RX_PROMISC; 5715f07fd19SPyun YongHyeon if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 5725f07fd19SPyun YongHyeon hashes[0] = 0xFFFFFFFF; 5735f07fd19SPyun YongHyeon hashes[1] = 0xFFFFFFFF; 5745f07fd19SPyun YongHyeon } 5755f07fd19SPyun YongHyeon goto done; 576a07bd003SBill Paul } 577a07bd003SBill Paul 5785f07fd19SPyun YongHyeon vge_cam_clear(sc); 579a07bd003SBill Paul /* Now program new ones */ 580eb956cd0SRobert Watson if_maddr_rlock(ifp); 581a07bd003SBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 582a07bd003SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 583a07bd003SBill Paul continue; 584a07bd003SBill Paul error = vge_cam_set(sc, 585a07bd003SBill Paul LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 586a07bd003SBill Paul if (error) 587a07bd003SBill Paul break; 588a07bd003SBill Paul } 589a07bd003SBill Paul 590a07bd003SBill Paul /* If there were too many addresses, use the hash filter. */ 591a07bd003SBill Paul if (error) { 592a07bd003SBill Paul vge_cam_clear(sc); 593a07bd003SBill Paul 594a07bd003SBill Paul TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 595a07bd003SBill Paul if (ifma->ifma_addr->sa_family != AF_LINK) 596a07bd003SBill Paul continue; 597a07bd003SBill Paul h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 598a07bd003SBill Paul ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 599a07bd003SBill Paul if (h < 32) 600a07bd003SBill Paul hashes[0] |= (1 << h); 601a07bd003SBill Paul else 602a07bd003SBill Paul hashes[1] |= (1 << (h - 32)); 603a07bd003SBill Paul } 604a07bd003SBill Paul } 605eb956cd0SRobert Watson if_maddr_runlock(ifp); 6065f07fd19SPyun YongHyeon 6075f07fd19SPyun YongHyeon done: 6085f07fd19SPyun YongHyeon if (hashes[0] != 0 || hashes[1] != 0) 6095f07fd19SPyun YongHyeon rxcfg |= VGE_RXCTL_RX_MCAST; 6105f07fd19SPyun YongHyeon CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 6115f07fd19SPyun YongHyeon CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 6125f07fd19SPyun YongHyeon CSR_WRITE_1(sc, VGE_RXCTL, rxcfg); 613a07bd003SBill Paul } 614a07bd003SBill Paul 615a07bd003SBill Paul static void 6166afe22a8SPyun YongHyeon vge_reset(struct vge_softc *sc) 617a07bd003SBill Paul { 618b534dcd5SPyun YongHyeon int i; 619a07bd003SBill Paul 620a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 621a07bd003SBill Paul 622a07bd003SBill Paul for (i = 0; i < VGE_TIMEOUT; i++) { 623a07bd003SBill Paul DELAY(5); 624a07bd003SBill Paul if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 625a07bd003SBill Paul break; 626a07bd003SBill Paul } 627a07bd003SBill Paul 628a07bd003SBill Paul if (i == VGE_TIMEOUT) { 62920c3cb15SPyun YongHyeon device_printf(sc->vge_dev, "soft reset timed out\n"); 630a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 631a07bd003SBill Paul DELAY(2000); 632a07bd003SBill Paul } 633a07bd003SBill Paul 634a07bd003SBill Paul DELAY(5000); 635a07bd003SBill Paul } 636a07bd003SBill Paul 637a07bd003SBill Paul /* 638a07bd003SBill Paul * Probe for a VIA gigabit chip. Check the PCI vendor and device 639a07bd003SBill Paul * IDs against our list and return a device name if we find a match. 640a07bd003SBill Paul */ 641a07bd003SBill Paul static int 6426afe22a8SPyun YongHyeon vge_probe(device_t dev) 643a07bd003SBill Paul { 644a07bd003SBill Paul struct vge_type *t; 645a07bd003SBill Paul 646a07bd003SBill Paul t = vge_devs; 647a07bd003SBill Paul 648a07bd003SBill Paul while (t->vge_name != NULL) { 649a07bd003SBill Paul if ((pci_get_vendor(dev) == t->vge_vid) && 650a07bd003SBill Paul (pci_get_device(dev) == t->vge_did)) { 651a07bd003SBill Paul device_set_desc(dev, t->vge_name); 6522ece8174SWarner Losh return (BUS_PROBE_DEFAULT); 653a07bd003SBill Paul } 654a07bd003SBill Paul t++; 655a07bd003SBill Paul } 656a07bd003SBill Paul 657a07bd003SBill Paul return (ENXIO); 658a07bd003SBill Paul } 659a07bd003SBill Paul 660a07bd003SBill Paul /* 661a07bd003SBill Paul * Map a single buffer address. 662a07bd003SBill Paul */ 663a07bd003SBill Paul 664410f4c60SPyun YongHyeon struct vge_dmamap_arg { 665410f4c60SPyun YongHyeon bus_addr_t vge_busaddr; 666410f4c60SPyun YongHyeon }; 667410f4c60SPyun YongHyeon 668a07bd003SBill Paul static void 6696afe22a8SPyun YongHyeon vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 670a07bd003SBill Paul { 671410f4c60SPyun YongHyeon struct vge_dmamap_arg *ctx; 672a07bd003SBill Paul 673410f4c60SPyun YongHyeon if (error != 0) 674a07bd003SBill Paul return; 675a07bd003SBill Paul 676410f4c60SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 677a07bd003SBill Paul 678410f4c60SPyun YongHyeon ctx = (struct vge_dmamap_arg *)arg; 679410f4c60SPyun YongHyeon ctx->vge_busaddr = segs[0].ds_addr; 680a07bd003SBill Paul } 681a07bd003SBill Paul 682a07bd003SBill Paul static int 6836afe22a8SPyun YongHyeon vge_dma_alloc(struct vge_softc *sc) 684a07bd003SBill Paul { 685410f4c60SPyun YongHyeon struct vge_dmamap_arg ctx; 686410f4c60SPyun YongHyeon struct vge_txdesc *txd; 687410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 688410f4c60SPyun YongHyeon bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 689410f4c60SPyun YongHyeon int error, i; 690410f4c60SPyun YongHyeon 691410f4c60SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR; 692410f4c60SPyun YongHyeon 693410f4c60SPyun YongHyeon again: 694410f4c60SPyun YongHyeon /* Create parent ring tag. */ 695410f4c60SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 696410f4c60SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 697410f4c60SPyun YongHyeon lowaddr, /* lowaddr */ 698410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 699410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 700410f4c60SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 701410f4c60SPyun YongHyeon 0, /* nsegments */ 702410f4c60SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 703410f4c60SPyun YongHyeon 0, /* flags */ 704410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 705410f4c60SPyun YongHyeon &sc->vge_cdata.vge_ring_tag); 706410f4c60SPyun YongHyeon if (error != 0) { 707410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 708410f4c60SPyun YongHyeon "could not create parent DMA tag.\n"); 709410f4c60SPyun YongHyeon goto fail; 710410f4c60SPyun YongHyeon } 711410f4c60SPyun YongHyeon 712410f4c60SPyun YongHyeon /* Create tag for Tx ring. */ 713410f4c60SPyun YongHyeon error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 714410f4c60SPyun YongHyeon VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 715410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 716410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 717410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 718410f4c60SPyun YongHyeon VGE_TX_LIST_SZ, /* maxsize */ 719410f4c60SPyun YongHyeon 1, /* nsegments */ 720410f4c60SPyun YongHyeon VGE_TX_LIST_SZ, /* maxsegsize */ 721410f4c60SPyun YongHyeon 0, /* flags */ 722410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 723410f4c60SPyun YongHyeon &sc->vge_cdata.vge_tx_ring_tag); 724410f4c60SPyun YongHyeon if (error != 0) { 725410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 726410f4c60SPyun YongHyeon "could not allocate Tx ring DMA tag.\n"); 727410f4c60SPyun YongHyeon goto fail; 728410f4c60SPyun YongHyeon } 729410f4c60SPyun YongHyeon 730410f4c60SPyun YongHyeon /* Create tag for Rx ring. */ 731410f4c60SPyun YongHyeon error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 732410f4c60SPyun YongHyeon VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 733410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 734410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 735410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 736410f4c60SPyun YongHyeon VGE_RX_LIST_SZ, /* maxsize */ 737410f4c60SPyun YongHyeon 1, /* nsegments */ 738410f4c60SPyun YongHyeon VGE_RX_LIST_SZ, /* maxsegsize */ 739410f4c60SPyun YongHyeon 0, /* flags */ 740410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 741410f4c60SPyun YongHyeon &sc->vge_cdata.vge_rx_ring_tag); 742410f4c60SPyun YongHyeon if (error != 0) { 743410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 744410f4c60SPyun YongHyeon "could not allocate Rx ring DMA tag.\n"); 745410f4c60SPyun YongHyeon goto fail; 746410f4c60SPyun YongHyeon } 747410f4c60SPyun YongHyeon 748410f4c60SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 749410f4c60SPyun YongHyeon error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 750410f4c60SPyun YongHyeon (void **)&sc->vge_rdata.vge_tx_ring, 751410f4c60SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 752410f4c60SPyun YongHyeon &sc->vge_cdata.vge_tx_ring_map); 753410f4c60SPyun YongHyeon if (error != 0) { 754410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 755410f4c60SPyun YongHyeon "could not allocate DMA'able memory for Tx ring.\n"); 756410f4c60SPyun YongHyeon goto fail; 757410f4c60SPyun YongHyeon } 758410f4c60SPyun YongHyeon 759410f4c60SPyun YongHyeon ctx.vge_busaddr = 0; 760410f4c60SPyun YongHyeon error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 761410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 762410f4c60SPyun YongHyeon VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 763410f4c60SPyun YongHyeon if (error != 0 || ctx.vge_busaddr == 0) { 764410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 765410f4c60SPyun YongHyeon "could not load DMA'able memory for Tx ring.\n"); 766410f4c60SPyun YongHyeon goto fail; 767410f4c60SPyun YongHyeon } 768410f4c60SPyun YongHyeon sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 769410f4c60SPyun YongHyeon 770410f4c60SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 771410f4c60SPyun YongHyeon error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 772410f4c60SPyun YongHyeon (void **)&sc->vge_rdata.vge_rx_ring, 773410f4c60SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 774410f4c60SPyun YongHyeon &sc->vge_cdata.vge_rx_ring_map); 775410f4c60SPyun YongHyeon if (error != 0) { 776410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 777410f4c60SPyun YongHyeon "could not allocate DMA'able memory for Rx ring.\n"); 778410f4c60SPyun YongHyeon goto fail; 779410f4c60SPyun YongHyeon } 780410f4c60SPyun YongHyeon 781410f4c60SPyun YongHyeon ctx.vge_busaddr = 0; 782410f4c60SPyun YongHyeon error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 783410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 784410f4c60SPyun YongHyeon VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 785410f4c60SPyun YongHyeon if (error != 0 || ctx.vge_busaddr == 0) { 786410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 787410f4c60SPyun YongHyeon "could not load DMA'able memory for Rx ring.\n"); 788410f4c60SPyun YongHyeon goto fail; 789410f4c60SPyun YongHyeon } 790410f4c60SPyun YongHyeon sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 791410f4c60SPyun YongHyeon 792410f4c60SPyun YongHyeon /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 793410f4c60SPyun YongHyeon tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 794410f4c60SPyun YongHyeon rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 795410f4c60SPyun YongHyeon if ((VGE_ADDR_HI(tx_ring_end) != 796410f4c60SPyun YongHyeon VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 797410f4c60SPyun YongHyeon (VGE_ADDR_HI(rx_ring_end) != 798410f4c60SPyun YongHyeon VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 799410f4c60SPyun YongHyeon VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 800410f4c60SPyun YongHyeon device_printf(sc->vge_dev, "4GB boundary crossed, " 801410f4c60SPyun YongHyeon "switching to 32bit DMA address mode.\n"); 802410f4c60SPyun YongHyeon vge_dma_free(sc); 803410f4c60SPyun YongHyeon /* Limit DMA address space to 32bit and try again. */ 804410f4c60SPyun YongHyeon lowaddr = BUS_SPACE_MAXADDR_32BIT; 805410f4c60SPyun YongHyeon goto again; 806410f4c60SPyun YongHyeon } 807410f4c60SPyun YongHyeon 808410f4c60SPyun YongHyeon /* Create parent buffer tag. */ 809410f4c60SPyun YongHyeon error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 810410f4c60SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 811410f4c60SPyun YongHyeon VGE_BUF_DMA_MAXADDR, /* lowaddr */ 812410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 813410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 814410f4c60SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 815410f4c60SPyun YongHyeon 0, /* nsegments */ 816410f4c60SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 817410f4c60SPyun YongHyeon 0, /* flags */ 818410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 819410f4c60SPyun YongHyeon &sc->vge_cdata.vge_buffer_tag); 820410f4c60SPyun YongHyeon if (error != 0) { 821410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 822410f4c60SPyun YongHyeon "could not create parent buffer DMA tag.\n"); 823410f4c60SPyun YongHyeon goto fail; 824410f4c60SPyun YongHyeon } 825410f4c60SPyun YongHyeon 826410f4c60SPyun YongHyeon /* Create tag for Tx buffers. */ 827410f4c60SPyun YongHyeon error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 828410f4c60SPyun YongHyeon 1, 0, /* algnmnt, boundary */ 829410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 830410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 831410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 832410f4c60SPyun YongHyeon MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 833410f4c60SPyun YongHyeon VGE_MAXTXSEGS, /* nsegments */ 834410f4c60SPyun YongHyeon MCLBYTES, /* maxsegsize */ 835410f4c60SPyun YongHyeon 0, /* flags */ 836410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 837410f4c60SPyun YongHyeon &sc->vge_cdata.vge_tx_tag); 838410f4c60SPyun YongHyeon if (error != 0) { 839410f4c60SPyun YongHyeon device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 840410f4c60SPyun YongHyeon goto fail; 841410f4c60SPyun YongHyeon } 842410f4c60SPyun YongHyeon 843410f4c60SPyun YongHyeon /* Create tag for Rx buffers. */ 844410f4c60SPyun YongHyeon error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 845410f4c60SPyun YongHyeon VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 846410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 847410f4c60SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 848410f4c60SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 849410f4c60SPyun YongHyeon MCLBYTES, /* maxsize */ 850410f4c60SPyun YongHyeon 1, /* nsegments */ 851410f4c60SPyun YongHyeon MCLBYTES, /* maxsegsize */ 852410f4c60SPyun YongHyeon 0, /* flags */ 853410f4c60SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 854410f4c60SPyun YongHyeon &sc->vge_cdata.vge_rx_tag); 855410f4c60SPyun YongHyeon if (error != 0) { 856410f4c60SPyun YongHyeon device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 857410f4c60SPyun YongHyeon goto fail; 858410f4c60SPyun YongHyeon } 859410f4c60SPyun YongHyeon 860410f4c60SPyun YongHyeon /* Create DMA maps for Tx buffers. */ 861410f4c60SPyun YongHyeon for (i = 0; i < VGE_TX_DESC_CNT; i++) { 862410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[i]; 863410f4c60SPyun YongHyeon txd->tx_m = NULL; 864410f4c60SPyun YongHyeon txd->tx_dmamap = NULL; 865410f4c60SPyun YongHyeon error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 866410f4c60SPyun YongHyeon &txd->tx_dmamap); 867410f4c60SPyun YongHyeon if (error != 0) { 868410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 869410f4c60SPyun YongHyeon "could not create Tx dmamap.\n"); 870410f4c60SPyun YongHyeon goto fail; 871410f4c60SPyun YongHyeon } 872410f4c60SPyun YongHyeon } 873410f4c60SPyun YongHyeon /* Create DMA maps for Rx buffers. */ 874410f4c60SPyun YongHyeon if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 875410f4c60SPyun YongHyeon &sc->vge_cdata.vge_rx_sparemap)) != 0) { 876410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 877410f4c60SPyun YongHyeon "could not create spare Rx dmamap.\n"); 878410f4c60SPyun YongHyeon goto fail; 879410f4c60SPyun YongHyeon } 880410f4c60SPyun YongHyeon for (i = 0; i < VGE_RX_DESC_CNT; i++) { 881410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[i]; 882410f4c60SPyun YongHyeon rxd->rx_m = NULL; 883410f4c60SPyun YongHyeon rxd->rx_dmamap = NULL; 884410f4c60SPyun YongHyeon error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 885410f4c60SPyun YongHyeon &rxd->rx_dmamap); 886410f4c60SPyun YongHyeon if (error != 0) { 887410f4c60SPyun YongHyeon device_printf(sc->vge_dev, 888410f4c60SPyun YongHyeon "could not create Rx dmamap.\n"); 889410f4c60SPyun YongHyeon goto fail; 890410f4c60SPyun YongHyeon } 891410f4c60SPyun YongHyeon } 892410f4c60SPyun YongHyeon 893410f4c60SPyun YongHyeon fail: 894410f4c60SPyun YongHyeon return (error); 895410f4c60SPyun YongHyeon } 896410f4c60SPyun YongHyeon 897410f4c60SPyun YongHyeon static void 8986afe22a8SPyun YongHyeon vge_dma_free(struct vge_softc *sc) 899410f4c60SPyun YongHyeon { 900410f4c60SPyun YongHyeon struct vge_txdesc *txd; 901410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 902a07bd003SBill Paul int i; 903a07bd003SBill Paul 904410f4c60SPyun YongHyeon /* Tx ring. */ 905410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 906410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_ring_map) 907410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 908410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map); 909410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_ring_map && 910410f4c60SPyun YongHyeon sc->vge_rdata.vge_tx_ring) 911410f4c60SPyun YongHyeon bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 912410f4c60SPyun YongHyeon sc->vge_rdata.vge_tx_ring, 913410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map); 914410f4c60SPyun YongHyeon sc->vge_rdata.vge_tx_ring = NULL; 915410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map = NULL; 916410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 917410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_tag = NULL; 918a07bd003SBill Paul } 919410f4c60SPyun YongHyeon /* Rx ring. */ 920410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 921410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_ring_map) 922410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 923410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map); 924410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_ring_map && 925410f4c60SPyun YongHyeon sc->vge_rdata.vge_rx_ring) 926410f4c60SPyun YongHyeon bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 927410f4c60SPyun YongHyeon sc->vge_rdata.vge_rx_ring, 928410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map); 929410f4c60SPyun YongHyeon sc->vge_rdata.vge_rx_ring = NULL; 930410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map = NULL; 931410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 932410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_tag = NULL; 933a07bd003SBill Paul } 934410f4c60SPyun YongHyeon /* Tx buffers. */ 935410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_tag != NULL) { 936a07bd003SBill Paul for (i = 0; i < VGE_TX_DESC_CNT; i++) { 937410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[i]; 938410f4c60SPyun YongHyeon if (txd->tx_dmamap != NULL) { 939410f4c60SPyun YongHyeon bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 940410f4c60SPyun YongHyeon txd->tx_dmamap); 941410f4c60SPyun YongHyeon txd->tx_dmamap = NULL; 942a07bd003SBill Paul } 943a07bd003SBill Paul } 944410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 945410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_tag = NULL; 946a07bd003SBill Paul } 947410f4c60SPyun YongHyeon /* Rx buffers. */ 948410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_tag != NULL) { 949a07bd003SBill Paul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 950410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[i]; 951410f4c60SPyun YongHyeon if (rxd->rx_dmamap != NULL) { 952410f4c60SPyun YongHyeon bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 953410f4c60SPyun YongHyeon rxd->rx_dmamap); 954410f4c60SPyun YongHyeon rxd->rx_dmamap = NULL; 955a07bd003SBill Paul } 956a07bd003SBill Paul } 957410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_sparemap != NULL) { 958410f4c60SPyun YongHyeon bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 959410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_sparemap); 960410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_sparemap = NULL; 961410f4c60SPyun YongHyeon } 962410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 963410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_tag = NULL; 964410f4c60SPyun YongHyeon } 965a07bd003SBill Paul 966410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_buffer_tag != NULL) { 967410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 968410f4c60SPyun YongHyeon sc->vge_cdata.vge_buffer_tag = NULL; 969410f4c60SPyun YongHyeon } 970410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_ring_tag != NULL) { 971410f4c60SPyun YongHyeon bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 972410f4c60SPyun YongHyeon sc->vge_cdata.vge_ring_tag = NULL; 973410f4c60SPyun YongHyeon } 974a07bd003SBill Paul } 975a07bd003SBill Paul 976a07bd003SBill Paul /* 977a07bd003SBill Paul * Attach the interface. Allocate softc structures, do ifmedia 978a07bd003SBill Paul * setup and ethernet/BPF attach. 979a07bd003SBill Paul */ 980a07bd003SBill Paul static int 9816afe22a8SPyun YongHyeon vge_attach(device_t dev) 982a07bd003SBill Paul { 983a07bd003SBill Paul u_char eaddr[ETHER_ADDR_LEN]; 984a07bd003SBill Paul struct vge_softc *sc; 985a07bd003SBill Paul struct ifnet *ifp; 98620c3cb15SPyun YongHyeon int error = 0, cap, i, msic, rid; 987a07bd003SBill Paul 988a07bd003SBill Paul sc = device_get_softc(dev); 989a07bd003SBill Paul sc->vge_dev = dev; 990a07bd003SBill Paul 991a07bd003SBill Paul mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 99267e1dfa7SJohn Baldwin MTX_DEF); 99367e1dfa7SJohn Baldwin callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 99467e1dfa7SJohn Baldwin 995a07bd003SBill Paul /* 996a07bd003SBill Paul * Map control/status registers. 997a07bd003SBill Paul */ 998a07bd003SBill Paul pci_enable_busmaster(dev); 999a07bd003SBill Paul 10004baee897SPyun YongHyeon rid = PCIR_BAR(1); 10018b3433dcSPyun YongHyeon sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 10028b3433dcSPyun YongHyeon RF_ACTIVE); 1003a07bd003SBill Paul 1004a07bd003SBill Paul if (sc->vge_res == NULL) { 1005481402e1SPyun YongHyeon device_printf(dev, "couldn't map ports/memory\n"); 1006a07bd003SBill Paul error = ENXIO; 1007a07bd003SBill Paul goto fail; 1008a07bd003SBill Paul } 1009a07bd003SBill Paul 1010643e9ee9SPyun YongHyeon if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 1011643e9ee9SPyun YongHyeon sc->vge_flags |= VGE_FLAG_PCIE; 1012643e9ee9SPyun YongHyeon sc->vge_expcap = cap; 1013643e9ee9SPyun YongHyeon } 10145957cc2aSPyun YongHyeon rid = 0; 10155957cc2aSPyun YongHyeon msic = pci_msi_count(dev); 10165957cc2aSPyun YongHyeon if (msi_disable == 0 && msic > 0) { 10175957cc2aSPyun YongHyeon msic = 1; 10185957cc2aSPyun YongHyeon if (pci_alloc_msi(dev, &msic) == 0) { 10195957cc2aSPyun YongHyeon if (msic == 1) { 10205957cc2aSPyun YongHyeon sc->vge_flags |= VGE_FLAG_MSI; 10215957cc2aSPyun YongHyeon device_printf(dev, "Using %d MSI message\n", 10225957cc2aSPyun YongHyeon msic); 10235957cc2aSPyun YongHyeon rid = 1; 10245957cc2aSPyun YongHyeon } else 10255957cc2aSPyun YongHyeon pci_release_msi(dev); 10265957cc2aSPyun YongHyeon } 10275957cc2aSPyun YongHyeon } 1028643e9ee9SPyun YongHyeon 1029a07bd003SBill Paul /* Allocate interrupt */ 10308b3433dcSPyun YongHyeon sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 10315957cc2aSPyun YongHyeon ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 1032a07bd003SBill Paul if (sc->vge_irq == NULL) { 1033481402e1SPyun YongHyeon device_printf(dev, "couldn't map interrupt\n"); 1034a07bd003SBill Paul error = ENXIO; 1035a07bd003SBill Paul goto fail; 1036a07bd003SBill Paul } 1037a07bd003SBill Paul 1038a07bd003SBill Paul /* Reset the adapter. */ 1039a07bd003SBill Paul vge_reset(sc); 104020c3cb15SPyun YongHyeon /* Reload EEPROM. */ 104120c3cb15SPyun YongHyeon CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 104220c3cb15SPyun YongHyeon for (i = 0; i < VGE_TIMEOUT; i++) { 104320c3cb15SPyun YongHyeon DELAY(5); 104420c3cb15SPyun YongHyeon if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 104520c3cb15SPyun YongHyeon break; 104620c3cb15SPyun YongHyeon } 104720c3cb15SPyun YongHyeon if (i == VGE_TIMEOUT) 104820c3cb15SPyun YongHyeon device_printf(dev, "EEPROM reload timed out\n"); 104920c3cb15SPyun YongHyeon /* 105020c3cb15SPyun YongHyeon * Clear PACPI as EEPROM reload will set the bit. Otherwise 105120c3cb15SPyun YongHyeon * MAC will receive magic packet which in turn confuses 105220c3cb15SPyun YongHyeon * controller. 105320c3cb15SPyun YongHyeon */ 105420c3cb15SPyun YongHyeon CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1055a07bd003SBill Paul 1056a07bd003SBill Paul /* 1057a07bd003SBill Paul * Get station address from the EEPROM. 1058a07bd003SBill Paul */ 1059a07bd003SBill Paul vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1060643e9ee9SPyun YongHyeon /* 1061643e9ee9SPyun YongHyeon * Save configured PHY address. 1062643e9ee9SPyun YongHyeon * It seems the PHY address of PCIe controllers just 1063643e9ee9SPyun YongHyeon * reflects media jump strapping status so we assume the 1064643e9ee9SPyun YongHyeon * internal PHY address of PCIe controller is at 1. 1065643e9ee9SPyun YongHyeon */ 1066643e9ee9SPyun YongHyeon if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1067643e9ee9SPyun YongHyeon sc->vge_phyaddr = 1; 1068643e9ee9SPyun YongHyeon else 1069643e9ee9SPyun YongHyeon sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1070643e9ee9SPyun YongHyeon VGE_MIICFG_PHYADDR; 10717129fb20SPyun YongHyeon vge_sysctl_node(sc); 1072410f4c60SPyun YongHyeon error = vge_dma_alloc(sc); 1073a07bd003SBill Paul if (error) 1074a07bd003SBill Paul goto fail; 1075a07bd003SBill Paul 1076cd036ec1SBrooks Davis ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1077cd036ec1SBrooks Davis if (ifp == NULL) { 1078f1b21184SJohn Baldwin device_printf(dev, "can not if_alloc()\n"); 1079cd036ec1SBrooks Davis error = ENOSPC; 1080cd036ec1SBrooks Davis goto fail; 1081cd036ec1SBrooks Davis } 1082cd036ec1SBrooks Davis 1083a07bd003SBill Paul /* Do MII setup */ 1084a07bd003SBill Paul if (mii_phy_probe(dev, &sc->vge_miibus, 1085a07bd003SBill Paul vge_ifmedia_upd, vge_ifmedia_sts)) { 1086f1b21184SJohn Baldwin device_printf(dev, "MII without any phy!\n"); 1087a07bd003SBill Paul error = ENXIO; 1088a07bd003SBill Paul goto fail; 1089a07bd003SBill Paul } 1090a07bd003SBill Paul 1091a07bd003SBill Paul ifp->if_softc = sc; 1092a07bd003SBill Paul if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1093a07bd003SBill Paul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1094a07bd003SBill Paul ifp->if_ioctl = vge_ioctl; 1095a07bd003SBill Paul ifp->if_capabilities = IFCAP_VLAN_MTU; 1096a07bd003SBill Paul ifp->if_start = vge_start; 1097a07bd003SBill Paul ifp->if_hwassist = VGE_CSUM_FEATURES; 109838aa43c5SPyun YongHyeon ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | 109938aa43c5SPyun YongHyeon IFCAP_VLAN_HWTAGGING; 110040929967SGleb Smirnoff ifp->if_capenable = ifp->if_capabilities; 1101a07bd003SBill Paul #ifdef DEVICE_POLLING 1102a07bd003SBill Paul ifp->if_capabilities |= IFCAP_POLLING; 1103a07bd003SBill Paul #endif 1104a07bd003SBill Paul ifp->if_init = vge_init; 1105623fa718SPyun YongHyeon IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); 1106623fa718SPyun YongHyeon ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; 110799baad9dSChristian Brueffer IFQ_SET_READY(&ifp->if_snd); 1108a07bd003SBill Paul 1109a07bd003SBill Paul /* 1110a07bd003SBill Paul * Call MI attach routine. 1111a07bd003SBill Paul */ 1112a07bd003SBill Paul ether_ifattach(ifp, eaddr); 1113a07bd003SBill Paul 11140c003e99SPyun YongHyeon /* Tell the upper layer(s) we support long frames. */ 11150c003e99SPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 11160c003e99SPyun YongHyeon 1117a07bd003SBill Paul /* Hook interrupt last to avoid having to lock softc */ 1118a07bd003SBill Paul error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1119ef544f63SPaolo Pisati NULL, vge_intr, sc, &sc->vge_intrhand); 1120a07bd003SBill Paul 1121a07bd003SBill Paul if (error) { 1122481402e1SPyun YongHyeon device_printf(dev, "couldn't set up irq\n"); 1123a07bd003SBill Paul ether_ifdetach(ifp); 1124a07bd003SBill Paul goto fail; 1125a07bd003SBill Paul } 1126a07bd003SBill Paul 1127a07bd003SBill Paul fail: 1128a07bd003SBill Paul if (error) 1129a07bd003SBill Paul vge_detach(dev); 1130a07bd003SBill Paul 1131a07bd003SBill Paul return (error); 1132a07bd003SBill Paul } 1133a07bd003SBill Paul 1134a07bd003SBill Paul /* 1135a07bd003SBill Paul * Shutdown hardware and free up resources. This can be called any 1136a07bd003SBill Paul * time after the mutex has been initialized. It is called in both 1137a07bd003SBill Paul * the error case in attach and the normal detach case so it needs 1138a07bd003SBill Paul * to be careful about only freeing resources that have actually been 1139a07bd003SBill Paul * allocated. 1140a07bd003SBill Paul */ 1141a07bd003SBill Paul static int 11426afe22a8SPyun YongHyeon vge_detach(device_t dev) 1143a07bd003SBill Paul { 1144a07bd003SBill Paul struct vge_softc *sc; 1145a07bd003SBill Paul struct ifnet *ifp; 1146a07bd003SBill Paul 1147a07bd003SBill Paul sc = device_get_softc(dev); 1148a07bd003SBill Paul KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1149fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 1150a07bd003SBill Paul 115140929967SGleb Smirnoff #ifdef DEVICE_POLLING 115240929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) 115340929967SGleb Smirnoff ether_poll_deregister(ifp); 115440929967SGleb Smirnoff #endif 115540929967SGleb Smirnoff 1156a07bd003SBill Paul /* These should only be active if attach succeeded */ 1157a07bd003SBill Paul if (device_is_attached(dev)) { 1158a07bd003SBill Paul ether_ifdetach(ifp); 115967e1dfa7SJohn Baldwin VGE_LOCK(sc); 116067e1dfa7SJohn Baldwin vge_stop(sc); 116167e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 116267e1dfa7SJohn Baldwin callout_drain(&sc->vge_watchdog); 1163a07bd003SBill Paul } 1164a07bd003SBill Paul if (sc->vge_miibus) 1165a07bd003SBill Paul device_delete_child(dev, sc->vge_miibus); 1166a07bd003SBill Paul bus_generic_detach(dev); 1167a07bd003SBill Paul 1168a07bd003SBill Paul if (sc->vge_intrhand) 1169a07bd003SBill Paul bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1170a07bd003SBill Paul if (sc->vge_irq) 11715957cc2aSPyun YongHyeon bus_release_resource(dev, SYS_RES_IRQ, 11725957cc2aSPyun YongHyeon sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 11735957cc2aSPyun YongHyeon if (sc->vge_flags & VGE_FLAG_MSI) 11745957cc2aSPyun YongHyeon pci_release_msi(dev); 1175a07bd003SBill Paul if (sc->vge_res) 1176a07bd003SBill Paul bus_release_resource(dev, SYS_RES_MEMORY, 11774baee897SPyun YongHyeon PCIR_BAR(1), sc->vge_res); 1178ad4f426eSWarner Losh if (ifp) 1179ad4f426eSWarner Losh if_free(ifp); 1180a07bd003SBill Paul 1181410f4c60SPyun YongHyeon vge_dma_free(sc); 1182a07bd003SBill Paul mtx_destroy(&sc->vge_mtx); 1183a07bd003SBill Paul 1184a07bd003SBill Paul return (0); 1185a07bd003SBill Paul } 1186a07bd003SBill Paul 1187410f4c60SPyun YongHyeon static void 11886afe22a8SPyun YongHyeon vge_discard_rxbuf(struct vge_softc *sc, int prod) 1189a07bd003SBill Paul { 1190410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 1191410f4c60SPyun YongHyeon int i; 1192a07bd003SBill Paul 1193410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1194410f4c60SPyun YongHyeon rxd->rx_desc->vge_sts = 0; 1195410f4c60SPyun YongHyeon rxd->rx_desc->vge_ctl = 0; 1196a07bd003SBill Paul 1197a07bd003SBill Paul /* 1198410f4c60SPyun YongHyeon * Note: the manual fails to document the fact that for 1199410f4c60SPyun YongHyeon * proper opration, the driver needs to replentish the RX 1200410f4c60SPyun YongHyeon * DMA ring 4 descriptors at a time (rather than one at a 1201410f4c60SPyun YongHyeon * time, like most chips). We can allocate the new buffers 1202410f4c60SPyun YongHyeon * but we should not set the OWN bits until we're ready 1203410f4c60SPyun YongHyeon * to hand back 4 of them in one shot. 1204a07bd003SBill Paul */ 1205410f4c60SPyun YongHyeon if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1206410f4c60SPyun YongHyeon for (i = VGE_RXCHUNK; i > 0; i--) { 1207410f4c60SPyun YongHyeon rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1208410f4c60SPyun YongHyeon rxd = rxd->rxd_prev; 1209a07bd003SBill Paul } 1210410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1211410f4c60SPyun YongHyeon } 1212410f4c60SPyun YongHyeon } 1213410f4c60SPyun YongHyeon 1214410f4c60SPyun YongHyeon static int 12156afe22a8SPyun YongHyeon vge_newbuf(struct vge_softc *sc, int prod) 1216410f4c60SPyun YongHyeon { 1217410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 1218410f4c60SPyun YongHyeon struct mbuf *m; 1219410f4c60SPyun YongHyeon bus_dma_segment_t segs[1]; 1220410f4c60SPyun YongHyeon bus_dmamap_t map; 1221410f4c60SPyun YongHyeon int i, nsegs; 1222410f4c60SPyun YongHyeon 1223410f4c60SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1224410f4c60SPyun YongHyeon if (m == NULL) 1225410f4c60SPyun YongHyeon return (ENOBUFS); 1226410f4c60SPyun YongHyeon /* 1227410f4c60SPyun YongHyeon * This is part of an evil trick to deal with strict-alignment 1228410f4c60SPyun YongHyeon * architectures. The VIA chip requires RX buffers to be aligned 1229410f4c60SPyun YongHyeon * on 32-bit boundaries, but that will hose strict-alignment 1230410f4c60SPyun YongHyeon * architectures. To get around this, we leave some empty space 1231410f4c60SPyun YongHyeon * at the start of each buffer and for non-strict-alignment hosts, 1232410f4c60SPyun YongHyeon * we copy the buffer back two bytes to achieve word alignment. 1233410f4c60SPyun YongHyeon * This is slightly more efficient than allocating a new buffer, 1234410f4c60SPyun YongHyeon * copying the contents, and discarding the old buffer. 1235410f4c60SPyun YongHyeon */ 1236410f4c60SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 1237410f4c60SPyun YongHyeon m_adj(m, VGE_RX_BUF_ALIGN); 1238410f4c60SPyun YongHyeon 1239410f4c60SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1240410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1241410f4c60SPyun YongHyeon m_freem(m); 1242410f4c60SPyun YongHyeon return (ENOBUFS); 1243410f4c60SPyun YongHyeon } 1244410f4c60SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1245410f4c60SPyun YongHyeon 1246410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1247410f4c60SPyun YongHyeon if (rxd->rx_m != NULL) { 1248410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1249410f4c60SPyun YongHyeon BUS_DMASYNC_POSTREAD); 1250410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1251410f4c60SPyun YongHyeon } 1252410f4c60SPyun YongHyeon map = rxd->rx_dmamap; 1253410f4c60SPyun YongHyeon rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1254410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_sparemap = map; 1255410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1256410f4c60SPyun YongHyeon BUS_DMASYNC_PREREAD); 1257410f4c60SPyun YongHyeon rxd->rx_m = m; 1258410f4c60SPyun YongHyeon 1259410f4c60SPyun YongHyeon rxd->rx_desc->vge_sts = 0; 1260410f4c60SPyun YongHyeon rxd->rx_desc->vge_ctl = 0; 1261410f4c60SPyun YongHyeon rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1262410f4c60SPyun YongHyeon rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1263410f4c60SPyun YongHyeon (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1264a07bd003SBill Paul 1265a07bd003SBill Paul /* 1266a07bd003SBill Paul * Note: the manual fails to document the fact that for 12678170b243SPyun YongHyeon * proper operation, the driver needs to replenish the RX 1268a07bd003SBill Paul * DMA ring 4 descriptors at a time (rather than one at a 1269a07bd003SBill Paul * time, like most chips). We can allocate the new buffers 1270a07bd003SBill Paul * but we should not set the OWN bits until we're ready 1271a07bd003SBill Paul * to hand back 4 of them in one shot. 1272a07bd003SBill Paul */ 1273410f4c60SPyun YongHyeon if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1274410f4c60SPyun YongHyeon for (i = VGE_RXCHUNK; i > 0; i--) { 1275410f4c60SPyun YongHyeon rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1276410f4c60SPyun YongHyeon rxd = rxd->rxd_prev; 1277a07bd003SBill Paul } 1278410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1279410f4c60SPyun YongHyeon } 1280a07bd003SBill Paul 1281a07bd003SBill Paul return (0); 1282a07bd003SBill Paul } 1283a07bd003SBill Paul 1284a07bd003SBill Paul static int 12856afe22a8SPyun YongHyeon vge_tx_list_init(struct vge_softc *sc) 1286a07bd003SBill Paul { 1287410f4c60SPyun YongHyeon struct vge_ring_data *rd; 1288410f4c60SPyun YongHyeon struct vge_txdesc *txd; 1289410f4c60SPyun YongHyeon int i; 1290a07bd003SBill Paul 1291410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 1292410f4c60SPyun YongHyeon 1293410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_prodidx = 0; 1294410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_considx = 0; 1295410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_cnt = 0; 1296410f4c60SPyun YongHyeon 1297410f4c60SPyun YongHyeon rd = &sc->vge_rdata; 1298410f4c60SPyun YongHyeon bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1299410f4c60SPyun YongHyeon for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1300410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[i]; 1301410f4c60SPyun YongHyeon txd->tx_m = NULL; 1302410f4c60SPyun YongHyeon txd->tx_desc = &rd->vge_tx_ring[i]; 1303410f4c60SPyun YongHyeon } 1304410f4c60SPyun YongHyeon 1305410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1306410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map, 1307410f4c60SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1308a07bd003SBill Paul 1309a07bd003SBill Paul return (0); 1310a07bd003SBill Paul } 1311a07bd003SBill Paul 1312a07bd003SBill Paul static int 13136afe22a8SPyun YongHyeon vge_rx_list_init(struct vge_softc *sc) 1314a07bd003SBill Paul { 1315410f4c60SPyun YongHyeon struct vge_ring_data *rd; 1316410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 1317a07bd003SBill Paul int i; 1318a07bd003SBill Paul 1319410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 1320a07bd003SBill Paul 1321410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_prodidx = 0; 1322410f4c60SPyun YongHyeon sc->vge_cdata.vge_head = NULL; 1323410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail = NULL; 1324410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit = 0; 1325a07bd003SBill Paul 1326410f4c60SPyun YongHyeon rd = &sc->vge_rdata; 1327410f4c60SPyun YongHyeon bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1328a07bd003SBill Paul for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1329410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[i]; 1330410f4c60SPyun YongHyeon rxd->rx_m = NULL; 1331410f4c60SPyun YongHyeon rxd->rx_desc = &rd->vge_rx_ring[i]; 1332410f4c60SPyun YongHyeon if (i == 0) 1333410f4c60SPyun YongHyeon rxd->rxd_prev = 1334410f4c60SPyun YongHyeon &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1335410f4c60SPyun YongHyeon else 1336410f4c60SPyun YongHyeon rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1337410f4c60SPyun YongHyeon if (vge_newbuf(sc, i) != 0) 1338a07bd003SBill Paul return (ENOBUFS); 1339a07bd003SBill Paul } 1340a07bd003SBill Paul 1341410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1342410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map, 1343410f4c60SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1344a07bd003SBill Paul 1345410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit = 0; 1346a07bd003SBill Paul 1347a07bd003SBill Paul return (0); 1348a07bd003SBill Paul } 1349a07bd003SBill Paul 1350410f4c60SPyun YongHyeon static void 13516afe22a8SPyun YongHyeon vge_freebufs(struct vge_softc *sc) 1352410f4c60SPyun YongHyeon { 1353410f4c60SPyun YongHyeon struct vge_txdesc *txd; 1354410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 1355410f4c60SPyun YongHyeon struct ifnet *ifp; 1356410f4c60SPyun YongHyeon int i; 1357410f4c60SPyun YongHyeon 1358410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 1359410f4c60SPyun YongHyeon 1360410f4c60SPyun YongHyeon ifp = sc->vge_ifp; 1361410f4c60SPyun YongHyeon /* 1362410f4c60SPyun YongHyeon * Free RX and TX mbufs still in the queues. 1363410f4c60SPyun YongHyeon */ 1364410f4c60SPyun YongHyeon for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1365410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[i]; 1366410f4c60SPyun YongHyeon if (rxd->rx_m != NULL) { 1367410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1368410f4c60SPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1369410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1370410f4c60SPyun YongHyeon rxd->rx_dmamap); 1371410f4c60SPyun YongHyeon m_freem(rxd->rx_m); 1372410f4c60SPyun YongHyeon rxd->rx_m = NULL; 1373410f4c60SPyun YongHyeon } 1374410f4c60SPyun YongHyeon } 1375410f4c60SPyun YongHyeon 1376410f4c60SPyun YongHyeon for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1377410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[i]; 1378410f4c60SPyun YongHyeon if (txd->tx_m != NULL) { 1379410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1380410f4c60SPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1381410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1382410f4c60SPyun YongHyeon txd->tx_dmamap); 1383410f4c60SPyun YongHyeon m_freem(txd->tx_m); 1384410f4c60SPyun YongHyeon txd->tx_m = NULL; 1385410f4c60SPyun YongHyeon ifp->if_oerrors++; 1386410f4c60SPyun YongHyeon } 1387410f4c60SPyun YongHyeon } 1388410f4c60SPyun YongHyeon } 1389410f4c60SPyun YongHyeon 1390410f4c60SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 1391a07bd003SBill Paul static __inline void 13926afe22a8SPyun YongHyeon vge_fixup_rx(struct mbuf *m) 1393a07bd003SBill Paul { 1394a07bd003SBill Paul int i; 1395a07bd003SBill Paul uint16_t *src, *dst; 1396a07bd003SBill Paul 1397a07bd003SBill Paul src = mtod(m, uint16_t *); 1398a07bd003SBill Paul dst = src - 1; 1399a07bd003SBill Paul 1400a07bd003SBill Paul for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1401a07bd003SBill Paul *dst++ = *src++; 1402a07bd003SBill Paul 1403a07bd003SBill Paul m->m_data -= ETHER_ALIGN; 1404a07bd003SBill Paul } 1405a07bd003SBill Paul #endif 1406a07bd003SBill Paul 1407a07bd003SBill Paul /* 1408a07bd003SBill Paul * RX handler. We support the reception of jumbo frames that have 1409a07bd003SBill Paul * been fragmented across multiple 2K mbuf cluster buffers. 1410a07bd003SBill Paul */ 14111abcdbd1SAttilio Rao static int 14126afe22a8SPyun YongHyeon vge_rxeof(struct vge_softc *sc, int count) 1413a07bd003SBill Paul { 1414a07bd003SBill Paul struct mbuf *m; 1415a07bd003SBill Paul struct ifnet *ifp; 1416410f4c60SPyun YongHyeon int prod, prog, total_len; 1417410f4c60SPyun YongHyeon struct vge_rxdesc *rxd; 1418a07bd003SBill Paul struct vge_rx_desc *cur_rx; 1419410f4c60SPyun YongHyeon uint32_t rxstat, rxctl; 1420a07bd003SBill Paul 1421a07bd003SBill Paul VGE_LOCK_ASSERT(sc); 1422410f4c60SPyun YongHyeon 1423fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 1424a07bd003SBill Paul 1425410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1426410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map, 1427410f4c60SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1428a07bd003SBill Paul 1429410f4c60SPyun YongHyeon prod = sc->vge_cdata.vge_rx_prodidx; 1430410f4c60SPyun YongHyeon for (prog = 0; count > 0 && 1431410f4c60SPyun YongHyeon (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1432410f4c60SPyun YongHyeon VGE_RX_DESC_INC(prod)) { 1433410f4c60SPyun YongHyeon cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1434a07bd003SBill Paul rxstat = le32toh(cur_rx->vge_sts); 1435410f4c60SPyun YongHyeon if ((rxstat & VGE_RDSTS_OWN) != 0) 1436410f4c60SPyun YongHyeon break; 1437410f4c60SPyun YongHyeon count--; 1438410f4c60SPyun YongHyeon prog++; 1439a07bd003SBill Paul rxctl = le32toh(cur_rx->vge_ctl); 1440410f4c60SPyun YongHyeon total_len = VGE_RXBYTES(rxstat); 1441410f4c60SPyun YongHyeon rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1442410f4c60SPyun YongHyeon m = rxd->rx_m; 1443a07bd003SBill Paul 1444a07bd003SBill Paul /* 1445a07bd003SBill Paul * If the 'start of frame' bit is set, this indicates 1446a07bd003SBill Paul * either the first fragment in a multi-fragment receive, 1447a07bd003SBill Paul * or an intermediate fragment. Either way, we want to 1448a07bd003SBill Paul * accumulate the buffers. 1449a07bd003SBill Paul */ 1450410f4c60SPyun YongHyeon if ((rxstat & VGE_RXPKT_SOF) != 0) { 1451410f4c60SPyun YongHyeon if (vge_newbuf(sc, prod) != 0) { 1452410f4c60SPyun YongHyeon ifp->if_iqdrops++; 1453410f4c60SPyun YongHyeon VGE_CHAIN_RESET(sc); 1454410f4c60SPyun YongHyeon vge_discard_rxbuf(sc, prod); 1455410f4c60SPyun YongHyeon continue; 1456a07bd003SBill Paul } 1457410f4c60SPyun YongHyeon m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1458410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_head == NULL) { 1459410f4c60SPyun YongHyeon sc->vge_cdata.vge_head = m; 1460410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail = m; 1461410f4c60SPyun YongHyeon } else { 1462410f4c60SPyun YongHyeon m->m_flags &= ~M_PKTHDR; 1463410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail->m_next = m; 1464410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail = m; 1465410f4c60SPyun YongHyeon } 1466a07bd003SBill Paul continue; 1467a07bd003SBill Paul } 1468a07bd003SBill Paul 1469a07bd003SBill Paul /* 1470a07bd003SBill Paul * Bad/error frames will have the RXOK bit cleared. 1471a07bd003SBill Paul * However, there's one error case we want to allow: 1472a07bd003SBill Paul * if a VLAN tagged frame arrives and the chip can't 1473a07bd003SBill Paul * match it against the CAM filter, it considers this 1474a07bd003SBill Paul * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1475a07bd003SBill Paul * We don't want to drop the frame though: our VLAN 1476a07bd003SBill Paul * filtering is done in software. 1477410f4c60SPyun YongHyeon * We also want to receive bad-checksummed frames and 1478410f4c60SPyun YongHyeon * and frames with bad-length. 1479a07bd003SBill Paul */ 1480410f4c60SPyun YongHyeon if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1481410f4c60SPyun YongHyeon (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1482410f4c60SPyun YongHyeon VGE_RDSTS_CSUMERR)) == 0) { 1483a07bd003SBill Paul ifp->if_ierrors++; 1484a07bd003SBill Paul /* 1485a07bd003SBill Paul * If this is part of a multi-fragment packet, 1486a07bd003SBill Paul * discard all the pieces. 1487a07bd003SBill Paul */ 1488410f4c60SPyun YongHyeon VGE_CHAIN_RESET(sc); 1489410f4c60SPyun YongHyeon vge_discard_rxbuf(sc, prod); 1490a07bd003SBill Paul continue; 1491a07bd003SBill Paul } 1492a07bd003SBill Paul 1493410f4c60SPyun YongHyeon if (vge_newbuf(sc, prod) != 0) { 1494410f4c60SPyun YongHyeon ifp->if_iqdrops++; 1495410f4c60SPyun YongHyeon VGE_CHAIN_RESET(sc); 1496410f4c60SPyun YongHyeon vge_discard_rxbuf(sc, prod); 1497a07bd003SBill Paul continue; 1498a07bd003SBill Paul } 1499a07bd003SBill Paul 1500410f4c60SPyun YongHyeon /* Chain received mbufs. */ 1501410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_head != NULL) { 1502410f4c60SPyun YongHyeon m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1503a07bd003SBill Paul /* 1504a07bd003SBill Paul * Special case: if there's 4 bytes or less 1505a07bd003SBill Paul * in this buffer, the mbuf can be discarded: 1506a07bd003SBill Paul * the last 4 bytes is the CRC, which we don't 1507a07bd003SBill Paul * care about anyway. 1508a07bd003SBill Paul */ 1509a07bd003SBill Paul if (m->m_len <= ETHER_CRC_LEN) { 1510410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail->m_len -= 1511a07bd003SBill Paul (ETHER_CRC_LEN - m->m_len); 1512a07bd003SBill Paul m_freem(m); 1513a07bd003SBill Paul } else { 1514a07bd003SBill Paul m->m_len -= ETHER_CRC_LEN; 1515a07bd003SBill Paul m->m_flags &= ~M_PKTHDR; 1516410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail->m_next = m; 1517a07bd003SBill Paul } 1518410f4c60SPyun YongHyeon m = sc->vge_cdata.vge_head; 1519410f4c60SPyun YongHyeon m->m_flags |= M_PKTHDR; 1520a07bd003SBill Paul m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1521410f4c60SPyun YongHyeon } else { 1522410f4c60SPyun YongHyeon m->m_flags |= M_PKTHDR; 1523a07bd003SBill Paul m->m_pkthdr.len = m->m_len = 1524a07bd003SBill Paul (total_len - ETHER_CRC_LEN); 1525410f4c60SPyun YongHyeon } 1526a07bd003SBill Paul 1527410f4c60SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT 1528a07bd003SBill Paul vge_fixup_rx(m); 1529a07bd003SBill Paul #endif 1530a07bd003SBill Paul m->m_pkthdr.rcvif = ifp; 1531a07bd003SBill Paul 1532a07bd003SBill Paul /* Do RX checksumming if enabled */ 1533410f4c60SPyun YongHyeon if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1534410f4c60SPyun YongHyeon (rxctl & VGE_RDCTL_FRAG) == 0) { 1535a07bd003SBill Paul /* Check IP header checksum */ 1536410f4c60SPyun YongHyeon if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1537a07bd003SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1538410f4c60SPyun YongHyeon if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1539a07bd003SBill Paul m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1540a07bd003SBill Paul 1541a07bd003SBill Paul /* Check TCP/UDP checksum */ 1542a07bd003SBill Paul if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1543a07bd003SBill Paul rxctl & VGE_RDCTL_PROTOCSUMOK) { 1544a07bd003SBill Paul m->m_pkthdr.csum_flags |= 1545a07bd003SBill Paul CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1546a07bd003SBill Paul m->m_pkthdr.csum_data = 0xffff; 1547a07bd003SBill Paul } 1548a07bd003SBill Paul } 1549a07bd003SBill Paul 1550410f4c60SPyun YongHyeon if ((rxstat & VGE_RDSTS_VTAG) != 0) { 155103eab9f7SRuslan Ermilov /* 155203eab9f7SRuslan Ermilov * The 32-bit rxctl register is stored in little-endian. 155303eab9f7SRuslan Ermilov * However, the 16-bit vlan tag is stored in big-endian, 155403eab9f7SRuslan Ermilov * so we have to byte swap it. 155503eab9f7SRuslan Ermilov */ 155678ba57b9SAndre Oppermann m->m_pkthdr.ether_vtag = 155703eab9f7SRuslan Ermilov bswap16(rxctl & VGE_RDCTL_VLANID); 155878ba57b9SAndre Oppermann m->m_flags |= M_VLANTAG; 1559d147662cSGleb Smirnoff } 1560a07bd003SBill Paul 1561a07bd003SBill Paul VGE_UNLOCK(sc); 1562a07bd003SBill Paul (*ifp->if_input)(ifp, m); 1563a07bd003SBill Paul VGE_LOCK(sc); 1564410f4c60SPyun YongHyeon sc->vge_cdata.vge_head = NULL; 1565410f4c60SPyun YongHyeon sc->vge_cdata.vge_tail = NULL; 1566a07bd003SBill Paul } 1567a07bd003SBill Paul 1568410f4c60SPyun YongHyeon if (prog > 0) { 1569410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_prodidx = prod; 1570410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1571410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_ring_map, 1572410f4c60SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1573410f4c60SPyun YongHyeon /* Update residue counter. */ 1574410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_rx_commit != 0) { 1575410f4c60SPyun YongHyeon CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1576410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit); 1577410f4c60SPyun YongHyeon sc->vge_cdata.vge_rx_commit = 0; 1578410f4c60SPyun YongHyeon } 1579410f4c60SPyun YongHyeon } 1580410f4c60SPyun YongHyeon return (prog); 1581a07bd003SBill Paul } 1582a07bd003SBill Paul 1583a07bd003SBill Paul static void 15846afe22a8SPyun YongHyeon vge_txeof(struct vge_softc *sc) 1585a07bd003SBill Paul { 1586a07bd003SBill Paul struct ifnet *ifp; 1587410f4c60SPyun YongHyeon struct vge_tx_desc *cur_tx; 1588410f4c60SPyun YongHyeon struct vge_txdesc *txd; 1589410f4c60SPyun YongHyeon uint32_t txstat; 1590410f4c60SPyun YongHyeon int cons, prod; 1591410f4c60SPyun YongHyeon 1592410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 1593a07bd003SBill Paul 1594fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 1595a07bd003SBill Paul 1596410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_cnt == 0) 1597410f4c60SPyun YongHyeon return; 1598a07bd003SBill Paul 1599410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1600410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map, 1601410f4c60SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1602a07bd003SBill Paul 1603410f4c60SPyun YongHyeon /* 1604410f4c60SPyun YongHyeon * Go through our tx list and free mbufs for those 1605410f4c60SPyun YongHyeon * frames that have been transmitted. 1606410f4c60SPyun YongHyeon */ 1607410f4c60SPyun YongHyeon cons = sc->vge_cdata.vge_tx_considx; 1608410f4c60SPyun YongHyeon prod = sc->vge_cdata.vge_tx_prodidx; 1609410f4c60SPyun YongHyeon for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1610410f4c60SPyun YongHyeon cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1611410f4c60SPyun YongHyeon txstat = le32toh(cur_tx->vge_sts); 1612410f4c60SPyun YongHyeon if ((txstat & VGE_TDSTS_OWN) != 0) 1613a07bd003SBill Paul break; 1614410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_cnt--; 161513f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1616410f4c60SPyun YongHyeon 1617410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[cons]; 1618410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1619410f4c60SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 1620410f4c60SPyun YongHyeon bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1621410f4c60SPyun YongHyeon 1622410f4c60SPyun YongHyeon KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1623410f4c60SPyun YongHyeon __func__)); 1624410f4c60SPyun YongHyeon m_freem(txd->tx_m); 1625410f4c60SPyun YongHyeon txd->tx_m = NULL; 1626420d0abfSPyun YongHyeon txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1627a07bd003SBill Paul } 1628420d0abfSPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1629420d0abfSPyun YongHyeon sc->vge_cdata.vge_tx_ring_map, 1630420d0abfSPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1631410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_considx = cons; 1632410f4c60SPyun YongHyeon if (sc->vge_cdata.vge_tx_cnt == 0) 1633410f4c60SPyun YongHyeon sc->vge_timer = 0; 1634410f4c60SPyun YongHyeon else { 1635a07bd003SBill Paul /* 1636a07bd003SBill Paul * If not all descriptors have been released reaped yet, 1637a07bd003SBill Paul * reload the timer so that we will eventually get another 1638a07bd003SBill Paul * interrupt that will cause us to re-enter this routine. 1639a07bd003SBill Paul * This is done in case the transmitter has gone idle. 1640a07bd003SBill Paul */ 1641a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1642a07bd003SBill Paul } 1643a07bd003SBill Paul } 1644a07bd003SBill Paul 1645a07bd003SBill Paul static void 1646e7b2d9b8SPyun YongHyeon vge_link_statchg(void *xsc) 1647a07bd003SBill Paul { 1648a07bd003SBill Paul struct vge_softc *sc; 1649a07bd003SBill Paul struct ifnet *ifp; 1650a07bd003SBill Paul struct mii_data *mii; 1651a07bd003SBill Paul 1652a07bd003SBill Paul sc = xsc; 1653fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 165467e1dfa7SJohn Baldwin VGE_LOCK_ASSERT(sc); 1655a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 1656a07bd003SBill Paul 1657e7b2d9b8SPyun YongHyeon mii_pollstat(mii); 16584d7235ddSPyun YongHyeon if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { 1659a07bd003SBill Paul if (!(mii->mii_media_status & IFM_ACTIVE)) { 16604d7235ddSPyun YongHyeon sc->vge_flags &= ~VGE_FLAG_LINK; 1661fc74a9f9SBrooks Davis if_link_state_change(sc->vge_ifp, 166242559cd2SBill Paul LINK_STATE_DOWN); 1663a07bd003SBill Paul } 1664a07bd003SBill Paul } else { 1665a07bd003SBill Paul if (mii->mii_media_status & IFM_ACTIVE && 1666a07bd003SBill Paul IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 16674d7235ddSPyun YongHyeon sc->vge_flags |= VGE_FLAG_LINK; 1668fc74a9f9SBrooks Davis if_link_state_change(sc->vge_ifp, 166942559cd2SBill Paul LINK_STATE_UP); 1670a07bd003SBill Paul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 167167e1dfa7SJohn Baldwin vge_start_locked(ifp); 1672a07bd003SBill Paul } 1673a07bd003SBill Paul } 1674a07bd003SBill Paul } 1675a07bd003SBill Paul 1676a07bd003SBill Paul #ifdef DEVICE_POLLING 16771abcdbd1SAttilio Rao static int 1678a07bd003SBill Paul vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1679a07bd003SBill Paul { 1680a07bd003SBill Paul struct vge_softc *sc = ifp->if_softc; 16811abcdbd1SAttilio Rao int rx_npkts = 0; 1682a07bd003SBill Paul 1683a07bd003SBill Paul VGE_LOCK(sc); 168440929967SGleb Smirnoff if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1685a07bd003SBill Paul goto done; 1686a07bd003SBill Paul 1687410f4c60SPyun YongHyeon rx_npkts = vge_rxeof(sc, count); 1688a07bd003SBill Paul vge_txeof(sc); 1689a07bd003SBill Paul 1690a07bd003SBill Paul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 169167e1dfa7SJohn Baldwin vge_start_locked(ifp); 1692a07bd003SBill Paul 1693a07bd003SBill Paul if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1694c3c74c61SPyun YongHyeon uint32_t status; 1695a07bd003SBill Paul status = CSR_READ_4(sc, VGE_ISR); 1696a07bd003SBill Paul if (status == 0xFFFFFFFF) 1697a07bd003SBill Paul goto done; 1698a07bd003SBill Paul if (status) 1699a07bd003SBill Paul CSR_WRITE_4(sc, VGE_ISR, status); 1700a07bd003SBill Paul 1701a07bd003SBill Paul /* 1702a07bd003SBill Paul * XXX check behaviour on receiver stalls. 1703a07bd003SBill Paul */ 1704a07bd003SBill Paul 1705a07bd003SBill Paul if (status & VGE_ISR_TXDMA_STALL || 1706410f4c60SPyun YongHyeon status & VGE_ISR_RXDMA_STALL) { 1707410f4c60SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 170867e1dfa7SJohn Baldwin vge_init_locked(sc); 1709410f4c60SPyun YongHyeon } 1710a07bd003SBill Paul 1711a07bd003SBill Paul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1712410f4c60SPyun YongHyeon vge_rxeof(sc, count); 1713a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1714a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1715a07bd003SBill Paul } 1716a07bd003SBill Paul } 1717a07bd003SBill Paul done: 1718a07bd003SBill Paul VGE_UNLOCK(sc); 17191abcdbd1SAttilio Rao return (rx_npkts); 1720a07bd003SBill Paul } 1721a07bd003SBill Paul #endif /* DEVICE_POLLING */ 1722a07bd003SBill Paul 1723a07bd003SBill Paul static void 17246afe22a8SPyun YongHyeon vge_intr(void *arg) 1725a07bd003SBill Paul { 1726a07bd003SBill Paul struct vge_softc *sc; 1727a07bd003SBill Paul struct ifnet *ifp; 1728c3c74c61SPyun YongHyeon uint32_t status; 1729a07bd003SBill Paul 1730a07bd003SBill Paul sc = arg; 1731a07bd003SBill Paul 1732a07bd003SBill Paul if (sc->suspended) { 1733a07bd003SBill Paul return; 1734a07bd003SBill Paul } 1735a07bd003SBill Paul 1736a07bd003SBill Paul VGE_LOCK(sc); 1737fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 1738a07bd003SBill Paul 1739a07bd003SBill Paul if (!(ifp->if_flags & IFF_UP)) { 1740a07bd003SBill Paul VGE_UNLOCK(sc); 1741a07bd003SBill Paul return; 1742a07bd003SBill Paul } 1743a07bd003SBill Paul 1744a07bd003SBill Paul #ifdef DEVICE_POLLING 174540929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 174640929967SGleb Smirnoff VGE_UNLOCK(sc); 174740929967SGleb Smirnoff return; 1748a07bd003SBill Paul } 174940929967SGleb Smirnoff #endif 1750a07bd003SBill Paul 1751a07bd003SBill Paul /* Disable interrupts */ 1752a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1753a07bd003SBill Paul 1754a07bd003SBill Paul for (;;) { 1755a07bd003SBill Paul 1756a07bd003SBill Paul status = CSR_READ_4(sc, VGE_ISR); 1757a07bd003SBill Paul /* If the card has gone away the read returns 0xffff. */ 1758a07bd003SBill Paul if (status == 0xFFFFFFFF) 1759a07bd003SBill Paul break; 1760a07bd003SBill Paul 1761a07bd003SBill Paul if (status) 1762a07bd003SBill Paul CSR_WRITE_4(sc, VGE_ISR, status); 1763a07bd003SBill Paul 1764a07bd003SBill Paul if ((status & VGE_INTRS) == 0) 1765a07bd003SBill Paul break; 1766a07bd003SBill Paul 1767a07bd003SBill Paul if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1768410f4c60SPyun YongHyeon vge_rxeof(sc, VGE_RX_DESC_CNT); 1769a07bd003SBill Paul 1770a07bd003SBill Paul if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1771410f4c60SPyun YongHyeon vge_rxeof(sc, VGE_RX_DESC_CNT); 1772a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1773a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1774a07bd003SBill Paul } 1775a07bd003SBill Paul 1776a07bd003SBill Paul if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1777a07bd003SBill Paul vge_txeof(sc); 1778a07bd003SBill Paul 1779410f4c60SPyun YongHyeon if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1780410f4c60SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 178167e1dfa7SJohn Baldwin vge_init_locked(sc); 1782410f4c60SPyun YongHyeon } 1783a07bd003SBill Paul 1784a07bd003SBill Paul if (status & VGE_ISR_LINKSTS) 1785e7b2d9b8SPyun YongHyeon vge_link_statchg(sc); 1786a07bd003SBill Paul } 1787a07bd003SBill Paul 1788a07bd003SBill Paul /* Re-enable interrupts */ 1789a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1790a07bd003SBill Paul 1791a07bd003SBill Paul if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 179267e1dfa7SJohn Baldwin vge_start_locked(ifp); 179367e1dfa7SJohn Baldwin 179467e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 1795a07bd003SBill Paul } 1796a07bd003SBill Paul 1797a07bd003SBill Paul static int 17986afe22a8SPyun YongHyeon vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1799a07bd003SBill Paul { 1800410f4c60SPyun YongHyeon struct vge_txdesc *txd; 1801410f4c60SPyun YongHyeon struct vge_tx_frag *frag; 1802410f4c60SPyun YongHyeon struct mbuf *m; 1803410f4c60SPyun YongHyeon bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1804410f4c60SPyun YongHyeon int error, i, nsegs, padlen; 1805410f4c60SPyun YongHyeon uint32_t cflags; 1806a07bd003SBill Paul 1807410f4c60SPyun YongHyeon VGE_LOCK_ASSERT(sc); 1808a07bd003SBill Paul 1809410f4c60SPyun YongHyeon M_ASSERTPKTHDR((*m_head)); 1810a07bd003SBill Paul 1811410f4c60SPyun YongHyeon /* Argh. This chip does not autopad short frames. */ 1812410f4c60SPyun YongHyeon if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1813410f4c60SPyun YongHyeon m = *m_head; 1814410f4c60SPyun YongHyeon padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1815410f4c60SPyun YongHyeon if (M_WRITABLE(m) == 0) { 1816410f4c60SPyun YongHyeon /* Get a writable copy. */ 1817410f4c60SPyun YongHyeon m = m_dup(*m_head, M_DONTWAIT); 1818410f4c60SPyun YongHyeon m_freem(*m_head); 1819410f4c60SPyun YongHyeon if (m == NULL) { 1820410f4c60SPyun YongHyeon *m_head = NULL; 1821a07bd003SBill Paul return (ENOBUFS); 1822a07bd003SBill Paul } 1823410f4c60SPyun YongHyeon *m_head = m; 1824410f4c60SPyun YongHyeon } 1825410f4c60SPyun YongHyeon if (M_TRAILINGSPACE(m) < padlen) { 1826410f4c60SPyun YongHyeon m = m_defrag(m, M_DONTWAIT); 1827410f4c60SPyun YongHyeon if (m == NULL) { 1828410f4c60SPyun YongHyeon m_freem(*m_head); 1829410f4c60SPyun YongHyeon *m_head = NULL; 1830410f4c60SPyun YongHyeon return (ENOBUFS); 1831a07bd003SBill Paul } 1832a07bd003SBill Paul } 1833410f4c60SPyun YongHyeon /* 1834410f4c60SPyun YongHyeon * Manually pad short frames, and zero the pad space 1835410f4c60SPyun YongHyeon * to avoid leaking data. 1836410f4c60SPyun YongHyeon */ 1837410f4c60SPyun YongHyeon bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1838410f4c60SPyun YongHyeon m->m_pkthdr.len += padlen; 1839410f4c60SPyun YongHyeon m->m_len = m->m_pkthdr.len; 1840410f4c60SPyun YongHyeon *m_head = m; 1841410f4c60SPyun YongHyeon } 1842a07bd003SBill Paul 1843410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1844410f4c60SPyun YongHyeon 1845410f4c60SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1846410f4c60SPyun YongHyeon txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1847410f4c60SPyun YongHyeon if (error == EFBIG) { 1848410f4c60SPyun YongHyeon m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1849410f4c60SPyun YongHyeon if (m == NULL) { 1850410f4c60SPyun YongHyeon m_freem(*m_head); 1851410f4c60SPyun YongHyeon *m_head = NULL; 1852410f4c60SPyun YongHyeon return (ENOMEM); 1853410f4c60SPyun YongHyeon } 1854410f4c60SPyun YongHyeon *m_head = m; 1855410f4c60SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1856410f4c60SPyun YongHyeon txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1857410f4c60SPyun YongHyeon if (error != 0) { 1858410f4c60SPyun YongHyeon m_freem(*m_head); 1859410f4c60SPyun YongHyeon *m_head = NULL; 1860410f4c60SPyun YongHyeon return (error); 1861410f4c60SPyun YongHyeon } 1862410f4c60SPyun YongHyeon } else if (error != 0) 1863410f4c60SPyun YongHyeon return (error); 1864410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1865410f4c60SPyun YongHyeon BUS_DMASYNC_PREWRITE); 1866410f4c60SPyun YongHyeon 1867410f4c60SPyun YongHyeon m = *m_head; 1868410f4c60SPyun YongHyeon cflags = 0; 1869410f4c60SPyun YongHyeon 1870410f4c60SPyun YongHyeon /* Configure checksum offload. */ 1871410f4c60SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1872410f4c60SPyun YongHyeon cflags |= VGE_TDCTL_IPCSUM; 1873410f4c60SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1874410f4c60SPyun YongHyeon cflags |= VGE_TDCTL_TCPCSUM; 1875410f4c60SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1876410f4c60SPyun YongHyeon cflags |= VGE_TDCTL_UDPCSUM; 1877410f4c60SPyun YongHyeon 1878410f4c60SPyun YongHyeon /* Configure VLAN. */ 1879410f4c60SPyun YongHyeon if ((m->m_flags & M_VLANTAG) != 0) 1880410f4c60SPyun YongHyeon cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1881410f4c60SPyun YongHyeon txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1882410f4c60SPyun YongHyeon /* 1883410f4c60SPyun YongHyeon * XXX 1884410f4c60SPyun YongHyeon * Velocity family seems to support TSO but no information 1885410f4c60SPyun YongHyeon * for MSS configuration is available. Also the number of 1886410f4c60SPyun YongHyeon * fragments supported by a descriptor is too small to hold 1887410f4c60SPyun YongHyeon * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1888410f4c60SPyun YongHyeon * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1889410f4c60SPyun YongHyeon * longer chain of buffers but no additional information is 1890410f4c60SPyun YongHyeon * available. 1891410f4c60SPyun YongHyeon * 1892410f4c60SPyun YongHyeon * When telling the chip how many segments there are, we 1893410f4c60SPyun YongHyeon * must use nsegs + 1 instead of just nsegs. Darned if I 1894410f4c60SPyun YongHyeon * know why. This also means we can't use the last fragment 1895410f4c60SPyun YongHyeon * field of Tx descriptor. 1896410f4c60SPyun YongHyeon */ 1897410f4c60SPyun YongHyeon txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1898410f4c60SPyun YongHyeon VGE_TD_LS_NORM); 1899410f4c60SPyun YongHyeon for (i = 0; i < nsegs; i++) { 1900410f4c60SPyun YongHyeon frag = &txd->tx_desc->vge_frag[i]; 1901410f4c60SPyun YongHyeon frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1902410f4c60SPyun YongHyeon frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1903410f4c60SPyun YongHyeon (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1904410f4c60SPyun YongHyeon } 1905410f4c60SPyun YongHyeon 1906410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_cnt++; 1907410f4c60SPyun YongHyeon VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1908a07bd003SBill Paul 1909a07bd003SBill Paul /* 1910410f4c60SPyun YongHyeon * Finally request interrupt and give the first descriptor 1911410f4c60SPyun YongHyeon * ownership to hardware. 1912a07bd003SBill Paul */ 1913410f4c60SPyun YongHyeon txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1914410f4c60SPyun YongHyeon txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1915410f4c60SPyun YongHyeon txd->tx_m = m; 1916a07bd003SBill Paul 1917a07bd003SBill Paul return (0); 1918a07bd003SBill Paul } 1919a07bd003SBill Paul 1920a07bd003SBill Paul /* 1921a07bd003SBill Paul * Main transmit routine. 1922a07bd003SBill Paul */ 1923a07bd003SBill Paul 1924a07bd003SBill Paul static void 19256afe22a8SPyun YongHyeon vge_start(struct ifnet *ifp) 1926a07bd003SBill Paul { 1927a07bd003SBill Paul struct vge_softc *sc; 192867e1dfa7SJohn Baldwin 192967e1dfa7SJohn Baldwin sc = ifp->if_softc; 193067e1dfa7SJohn Baldwin VGE_LOCK(sc); 193167e1dfa7SJohn Baldwin vge_start_locked(ifp); 193267e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 193367e1dfa7SJohn Baldwin } 193467e1dfa7SJohn Baldwin 1935410f4c60SPyun YongHyeon 193667e1dfa7SJohn Baldwin static void 19376afe22a8SPyun YongHyeon vge_start_locked(struct ifnet *ifp) 193867e1dfa7SJohn Baldwin { 193967e1dfa7SJohn Baldwin struct vge_softc *sc; 1940410f4c60SPyun YongHyeon struct vge_txdesc *txd; 1941410f4c60SPyun YongHyeon struct mbuf *m_head; 1942410f4c60SPyun YongHyeon int enq, idx; 1943a07bd003SBill Paul 1944a07bd003SBill Paul sc = ifp->if_softc; 1945410f4c60SPyun YongHyeon 194667e1dfa7SJohn Baldwin VGE_LOCK_ASSERT(sc); 1947a07bd003SBill Paul 19484d7235ddSPyun YongHyeon if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1949410f4c60SPyun YongHyeon (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1950410f4c60SPyun YongHyeon IFF_DRV_RUNNING) 1951a07bd003SBill Paul return; 1952a07bd003SBill Paul 1953410f4c60SPyun YongHyeon idx = sc->vge_cdata.vge_tx_prodidx; 1954410f4c60SPyun YongHyeon VGE_TX_DESC_DEC(idx); 1955410f4c60SPyun YongHyeon for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1956410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1957a07bd003SBill Paul IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1958a07bd003SBill Paul if (m_head == NULL) 1959a07bd003SBill Paul break; 1960410f4c60SPyun YongHyeon /* 1961410f4c60SPyun YongHyeon * Pack the data into the transmit ring. If we 1962410f4c60SPyun YongHyeon * don't have room, set the OACTIVE flag and wait 1963410f4c60SPyun YongHyeon * for the NIC to drain the ring. 1964410f4c60SPyun YongHyeon */ 1965410f4c60SPyun YongHyeon if (vge_encap(sc, &m_head)) { 1966410f4c60SPyun YongHyeon if (m_head == NULL) 1967410f4c60SPyun YongHyeon break; 1968a07bd003SBill Paul IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 196913f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1970a07bd003SBill Paul break; 1971a07bd003SBill Paul } 1972a07bd003SBill Paul 1973410f4c60SPyun YongHyeon txd = &sc->vge_cdata.vge_txdesc[idx]; 1974410f4c60SPyun YongHyeon txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1975a07bd003SBill Paul VGE_TX_DESC_INC(idx); 1976a07bd003SBill Paul 1977410f4c60SPyun YongHyeon enq++; 1978a07bd003SBill Paul /* 1979a07bd003SBill Paul * If there's a BPF listener, bounce a copy of this frame 1980a07bd003SBill Paul * to him. 1981a07bd003SBill Paul */ 198259a0d28bSChristian S.J. Peron ETHER_BPF_MTAP(ifp, m_head); 1983a07bd003SBill Paul } 1984a07bd003SBill Paul 1985410f4c60SPyun YongHyeon if (enq > 0) { 1986410f4c60SPyun YongHyeon bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1987410f4c60SPyun YongHyeon sc->vge_cdata.vge_tx_ring_map, 1988410f4c60SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1989a07bd003SBill Paul /* Issue a transmit command. */ 1990a07bd003SBill Paul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1991a07bd003SBill Paul /* 1992a07bd003SBill Paul * Use the countdown timer for interrupt moderation. 1993a07bd003SBill Paul * 'TX done' interrupts are disabled. Instead, we reset the 1994a07bd003SBill Paul * countdown timer, which will begin counting until it hits 1995a07bd003SBill Paul * the value in the SSTIMER register, and then trigger an 1996a07bd003SBill Paul * interrupt. Each time we set the TIMER0_ENABLE bit, the 1997a07bd003SBill Paul * the timer count is reloaded. Only when the transmitter 1998a07bd003SBill Paul * is idle will the timer hit 0 and an interrupt fire. 1999a07bd003SBill Paul */ 2000a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 2001a07bd003SBill Paul 2002a07bd003SBill Paul /* 2003a07bd003SBill Paul * Set a timeout in case the chip goes out to lunch. 2004a07bd003SBill Paul */ 200567e1dfa7SJohn Baldwin sc->vge_timer = 5; 2006410f4c60SPyun YongHyeon } 2007a07bd003SBill Paul } 2008a07bd003SBill Paul 2009a07bd003SBill Paul static void 20106afe22a8SPyun YongHyeon vge_init(void *xsc) 2011a07bd003SBill Paul { 2012a07bd003SBill Paul struct vge_softc *sc = xsc; 201367e1dfa7SJohn Baldwin 201467e1dfa7SJohn Baldwin VGE_LOCK(sc); 201567e1dfa7SJohn Baldwin vge_init_locked(sc); 201667e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 201767e1dfa7SJohn Baldwin } 201867e1dfa7SJohn Baldwin 201967e1dfa7SJohn Baldwin static void 202067e1dfa7SJohn Baldwin vge_init_locked(struct vge_softc *sc) 202167e1dfa7SJohn Baldwin { 2022fc74a9f9SBrooks Davis struct ifnet *ifp = sc->vge_ifp; 2023a07bd003SBill Paul struct mii_data *mii; 2024410f4c60SPyun YongHyeon int error, i; 2025a07bd003SBill Paul 202667e1dfa7SJohn Baldwin VGE_LOCK_ASSERT(sc); 2027a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 2028a07bd003SBill Paul 2029410f4c60SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2030410f4c60SPyun YongHyeon return; 2031410f4c60SPyun YongHyeon 2032a07bd003SBill Paul /* 2033a07bd003SBill Paul * Cancel pending I/O and free all RX/TX buffers. 2034a07bd003SBill Paul */ 2035a07bd003SBill Paul vge_stop(sc); 2036a07bd003SBill Paul vge_reset(sc); 2037a07bd003SBill Paul 2038a07bd003SBill Paul /* 2039a07bd003SBill Paul * Initialize the RX and TX descriptors and mbufs. 2040a07bd003SBill Paul */ 2041a07bd003SBill Paul 2042410f4c60SPyun YongHyeon error = vge_rx_list_init(sc); 2043410f4c60SPyun YongHyeon if (error != 0) { 2044410f4c60SPyun YongHyeon device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2045410f4c60SPyun YongHyeon return; 2046410f4c60SPyun YongHyeon } 2047a07bd003SBill Paul vge_tx_list_init(sc); 20487129fb20SPyun YongHyeon /* Clear MAC statistics. */ 20497129fb20SPyun YongHyeon vge_stats_clear(sc); 2050a07bd003SBill Paul /* Set our station address */ 2051a07bd003SBill Paul for (i = 0; i < ETHER_ADDR_LEN; i++) 20524a0d6638SRuslan Ermilov CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 2053a07bd003SBill Paul 2054a07bd003SBill Paul /* 2055a07bd003SBill Paul * Set receive FIFO threshold. Also allow transmission and 2056a07bd003SBill Paul * reception of VLAN tagged frames. 2057a07bd003SBill Paul */ 2058a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 205938aa43c5SPyun YongHyeon CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 2060a07bd003SBill Paul 2061a07bd003SBill Paul /* Set DMA burst length */ 2062a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2063a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2064a07bd003SBill Paul 2065a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2066a07bd003SBill Paul 2067a07bd003SBill Paul /* Set collision backoff algorithm */ 2068a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2069a07bd003SBill Paul VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2070a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2071a07bd003SBill Paul 2072a07bd003SBill Paul /* Disable LPSEL field in priority resolution */ 2073a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2074a07bd003SBill Paul 2075a07bd003SBill Paul /* 2076a07bd003SBill Paul * Load the addresses of the DMA queues into the chip. 2077a07bd003SBill Paul * Note that we only use one transmit queue. 2078a07bd003SBill Paul */ 2079a07bd003SBill Paul 2080410f4c60SPyun YongHyeon CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2081410f4c60SPyun YongHyeon VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2082a07bd003SBill Paul CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2083410f4c60SPyun YongHyeon VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2084a07bd003SBill Paul CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2085a07bd003SBill Paul 2086a07bd003SBill Paul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2087410f4c60SPyun YongHyeon VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2088a07bd003SBill Paul CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2089a07bd003SBill Paul CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2090a07bd003SBill Paul 2091a07bd003SBill Paul /* Enable and wake up the RX descriptor queue */ 2092a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2093a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2094a07bd003SBill Paul 2095a07bd003SBill Paul /* Enable the TX descriptor queue */ 2096a07bd003SBill Paul CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2097a07bd003SBill Paul 2098a07bd003SBill Paul /* Init the cam filter. */ 2099a07bd003SBill Paul vge_cam_clear(sc); 2100a07bd003SBill Paul 21015f07fd19SPyun YongHyeon /* Set up receiver filter. */ 21025f07fd19SPyun YongHyeon vge_rxfilter(sc); 210338aa43c5SPyun YongHyeon vge_setvlan(sc); 2104a07bd003SBill Paul 2105a07bd003SBill Paul /* Enable flow control */ 2106a07bd003SBill Paul 2107a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2108a07bd003SBill Paul 2109a07bd003SBill Paul /* Enable jumbo frame reception (if desired) */ 2110a07bd003SBill Paul 2111a07bd003SBill Paul /* Start the MAC. */ 2112a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2113a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2114a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS0, 2115a07bd003SBill Paul VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2116a07bd003SBill Paul 2117a07bd003SBill Paul /* 2118a07bd003SBill Paul * Configure one-shot timer for microsecond 21198170b243SPyun YongHyeon * resolution and load it for 500 usecs. 2120a07bd003SBill Paul */ 2121a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2122a07bd003SBill Paul CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2123a07bd003SBill Paul 2124a07bd003SBill Paul /* 2125a07bd003SBill Paul * Configure interrupt moderation for receive. Enable 2126a07bd003SBill Paul * the holdoff counter and load it, and set the RX 2127a07bd003SBill Paul * suppression count to the number of descriptors we 2128a07bd003SBill Paul * want to allow before triggering an interrupt. 2129a07bd003SBill Paul * The holdoff timer is in units of 20 usecs. 2130a07bd003SBill Paul */ 2131a07bd003SBill Paul 2132a07bd003SBill Paul #ifdef notyet 2133a07bd003SBill Paul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2134a07bd003SBill Paul /* Select the interrupt holdoff timer page. */ 2135a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2136a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2137a07bd003SBill Paul CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2138a07bd003SBill Paul 2139a07bd003SBill Paul /* Enable use of the holdoff timer. */ 2140a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2141a07bd003SBill Paul CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2142a07bd003SBill Paul 2143a07bd003SBill Paul /* Select the RX suppression threshold page. */ 2144a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2145a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2146a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2147a07bd003SBill Paul 2148a07bd003SBill Paul /* Restore the page select bits. */ 2149a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2150a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2151a07bd003SBill Paul #endif 2152a07bd003SBill Paul 2153a07bd003SBill Paul #ifdef DEVICE_POLLING 2154a07bd003SBill Paul /* 2155a07bd003SBill Paul * Disable interrupts if we are polling. 2156a07bd003SBill Paul */ 215740929967SGleb Smirnoff if (ifp->if_capenable & IFCAP_POLLING) { 2158a07bd003SBill Paul CSR_WRITE_4(sc, VGE_IMR, 0); 2159a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2160a07bd003SBill Paul } else /* otherwise ... */ 216140929967SGleb Smirnoff #endif 2162a07bd003SBill Paul { 2163a07bd003SBill Paul /* 2164a07bd003SBill Paul * Enable interrupts. 2165a07bd003SBill Paul */ 2166a07bd003SBill Paul CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2167a07bd003SBill Paul CSR_WRITE_4(sc, VGE_ISR, 0); 2168a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2169a07bd003SBill Paul } 2170a07bd003SBill Paul 21714d7235ddSPyun YongHyeon sc->vge_flags &= ~VGE_FLAG_LINK; 2172a07bd003SBill Paul mii_mediachg(mii); 2173a07bd003SBill Paul 217413f4c340SRobert Watson ifp->if_drv_flags |= IFF_DRV_RUNNING; 217513f4c340SRobert Watson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 217667e1dfa7SJohn Baldwin callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2177a07bd003SBill Paul } 2178a07bd003SBill Paul 2179a07bd003SBill Paul /* 2180a07bd003SBill Paul * Set media options. 2181a07bd003SBill Paul */ 2182a07bd003SBill Paul static int 21836afe22a8SPyun YongHyeon vge_ifmedia_upd(struct ifnet *ifp) 2184a07bd003SBill Paul { 2185a07bd003SBill Paul struct vge_softc *sc; 2186a07bd003SBill Paul struct mii_data *mii; 21876f530983SPyun YongHyeon int error; 2188a07bd003SBill Paul 2189a07bd003SBill Paul sc = ifp->if_softc; 2190592777f6SMichael Reifenberger VGE_LOCK(sc); 2191a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 21926f530983SPyun YongHyeon error = mii_mediachg(mii); 2193592777f6SMichael Reifenberger VGE_UNLOCK(sc); 2194a07bd003SBill Paul 21956f530983SPyun YongHyeon return (error); 2196a07bd003SBill Paul } 2197a07bd003SBill Paul 2198a07bd003SBill Paul /* 2199a07bd003SBill Paul * Report current media status. 2200a07bd003SBill Paul */ 2201a07bd003SBill Paul static void 22026afe22a8SPyun YongHyeon vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2203a07bd003SBill Paul { 2204a07bd003SBill Paul struct vge_softc *sc; 2205a07bd003SBill Paul struct mii_data *mii; 2206a07bd003SBill Paul 2207a07bd003SBill Paul sc = ifp->if_softc; 2208a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 2209a07bd003SBill Paul 221067e1dfa7SJohn Baldwin VGE_LOCK(sc); 22115f26dcd8SPyun YongHyeon if ((ifp->if_flags & IFF_UP) == 0) { 22125f26dcd8SPyun YongHyeon VGE_UNLOCK(sc); 22135f26dcd8SPyun YongHyeon return; 22145f26dcd8SPyun YongHyeon } 2215a07bd003SBill Paul mii_pollstat(mii); 221667e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 2217a07bd003SBill Paul ifmr->ifm_active = mii->mii_media_active; 2218a07bd003SBill Paul ifmr->ifm_status = mii->mii_media_status; 2219a07bd003SBill Paul } 2220a07bd003SBill Paul 2221a07bd003SBill Paul static void 22226afe22a8SPyun YongHyeon vge_miibus_statchg(device_t dev) 2223a07bd003SBill Paul { 2224a07bd003SBill Paul struct vge_softc *sc; 2225a07bd003SBill Paul struct mii_data *mii; 2226a07bd003SBill Paul struct ifmedia_entry *ife; 2227a07bd003SBill Paul 2228a07bd003SBill Paul sc = device_get_softc(dev); 2229a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 2230a07bd003SBill Paul ife = mii->mii_media.ifm_cur; 2231a07bd003SBill Paul 2232a07bd003SBill Paul /* 2233a07bd003SBill Paul * If the user manually selects a media mode, we need to turn 2234a07bd003SBill Paul * on the forced MAC mode bit in the DIAGCTL register. If the 2235a07bd003SBill Paul * user happens to choose a full duplex mode, we also need to 2236a07bd003SBill Paul * set the 'force full duplex' bit. This applies only to 2237a07bd003SBill Paul * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2238a07bd003SBill Paul * mode is disabled, and in 1000baseT mode, full duplex is 2239a07bd003SBill Paul * always implied, so we turn on the forced mode bit but leave 2240a07bd003SBill Paul * the FDX bit cleared. 2241a07bd003SBill Paul */ 2242a07bd003SBill Paul 2243a07bd003SBill Paul switch (IFM_SUBTYPE(ife->ifm_media)) { 2244a07bd003SBill Paul case IFM_AUTO: 2245a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2246a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2247a07bd003SBill Paul break; 2248a07bd003SBill Paul case IFM_1000_T: 2249a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2250a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2251a07bd003SBill Paul break; 2252a07bd003SBill Paul case IFM_100_TX: 2253a07bd003SBill Paul case IFM_10_T: 2254a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2255a07bd003SBill Paul if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2256a07bd003SBill Paul CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2257a07bd003SBill Paul } else { 2258a07bd003SBill Paul CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2259a07bd003SBill Paul } 2260a07bd003SBill Paul break; 2261a07bd003SBill Paul default: 2262a07bd003SBill Paul device_printf(dev, "unknown media type: %x\n", 2263a07bd003SBill Paul IFM_SUBTYPE(ife->ifm_media)); 2264a07bd003SBill Paul break; 2265a07bd003SBill Paul } 2266a07bd003SBill Paul } 2267a07bd003SBill Paul 2268a07bd003SBill Paul static int 22696afe22a8SPyun YongHyeon vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2270a07bd003SBill Paul { 2271a07bd003SBill Paul struct vge_softc *sc = ifp->if_softc; 2272a07bd003SBill Paul struct ifreq *ifr = (struct ifreq *) data; 2273a07bd003SBill Paul struct mii_data *mii; 227438aa43c5SPyun YongHyeon int error = 0, mask; 2275a07bd003SBill Paul 2276a07bd003SBill Paul switch (command) { 2277a07bd003SBill Paul case SIOCSIFMTU: 2278a07bd003SBill Paul if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2279a07bd003SBill Paul error = EINVAL; 2280a07bd003SBill Paul ifp->if_mtu = ifr->ifr_mtu; 2281a07bd003SBill Paul break; 2282a07bd003SBill Paul case SIOCSIFFLAGS: 228367e1dfa7SJohn Baldwin VGE_LOCK(sc); 22845f07fd19SPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 22855f07fd19SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 22865f07fd19SPyun YongHyeon ((ifp->if_flags ^ sc->vge_if_flags) & 22875f07fd19SPyun YongHyeon (IFF_PROMISC | IFF_ALLMULTI)) != 0) 22885f07fd19SPyun YongHyeon vge_rxfilter(sc); 22895f07fd19SPyun YongHyeon else 229067e1dfa7SJohn Baldwin vge_init_locked(sc); 22915f07fd19SPyun YongHyeon } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2292a07bd003SBill Paul vge_stop(sc); 2293a07bd003SBill Paul sc->vge_if_flags = ifp->if_flags; 229467e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 2295a07bd003SBill Paul break; 2296a07bd003SBill Paul case SIOCADDMULTI: 2297a07bd003SBill Paul case SIOCDELMULTI: 229867e1dfa7SJohn Baldwin VGE_LOCK(sc); 2299410f4c60SPyun YongHyeon if (ifp->if_drv_flags & IFF_DRV_RUNNING) 23005f07fd19SPyun YongHyeon vge_rxfilter(sc); 230167e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 2302a07bd003SBill Paul break; 2303a07bd003SBill Paul case SIOCGIFMEDIA: 2304a07bd003SBill Paul case SIOCSIFMEDIA: 2305a07bd003SBill Paul mii = device_get_softc(sc->vge_miibus); 2306a07bd003SBill Paul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2307a07bd003SBill Paul break; 2308a07bd003SBill Paul case SIOCSIFCAP: 230938aa43c5SPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 231040929967SGleb Smirnoff #ifdef DEVICE_POLLING 231140929967SGleb Smirnoff if (mask & IFCAP_POLLING) { 231240929967SGleb Smirnoff if (ifr->ifr_reqcap & IFCAP_POLLING) { 231340929967SGleb Smirnoff error = ether_poll_register(vge_poll, ifp); 231440929967SGleb Smirnoff if (error) 231540929967SGleb Smirnoff return (error); 231640929967SGleb Smirnoff VGE_LOCK(sc); 231740929967SGleb Smirnoff /* Disable interrupts */ 231840929967SGleb Smirnoff CSR_WRITE_4(sc, VGE_IMR, 0); 231940929967SGleb Smirnoff CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 232040929967SGleb Smirnoff ifp->if_capenable |= IFCAP_POLLING; 232140929967SGleb Smirnoff VGE_UNLOCK(sc); 232240929967SGleb Smirnoff } else { 232340929967SGleb Smirnoff error = ether_poll_deregister(ifp); 232440929967SGleb Smirnoff /* Enable interrupts. */ 232540929967SGleb Smirnoff VGE_LOCK(sc); 232640929967SGleb Smirnoff CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 232740929967SGleb Smirnoff CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 232840929967SGleb Smirnoff CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 232940929967SGleb Smirnoff ifp->if_capenable &= ~IFCAP_POLLING; 233040929967SGleb Smirnoff VGE_UNLOCK(sc); 233140929967SGleb Smirnoff } 233240929967SGleb Smirnoff } 233340929967SGleb Smirnoff #endif /* DEVICE_POLLING */ 233467e1dfa7SJohn Baldwin VGE_LOCK(sc); 233520f9ef43SPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0 && 233620f9ef43SPyun YongHyeon (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 233720f9ef43SPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 233820f9ef43SPyun YongHyeon if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 233920f9ef43SPyun YongHyeon ifp->if_hwassist |= VGE_CSUM_FEATURES; 2340a07bd003SBill Paul else 234120f9ef43SPyun YongHyeon ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 234240929967SGleb Smirnoff } 234320f9ef43SPyun YongHyeon if ((mask & IFCAP_RXCSUM) != 0 && 234420f9ef43SPyun YongHyeon (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 234520f9ef43SPyun YongHyeon ifp->if_capenable ^= IFCAP_RXCSUM; 234638aa43c5SPyun YongHyeon if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 234738aa43c5SPyun YongHyeon (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 234838aa43c5SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 234938aa43c5SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 235038aa43c5SPyun YongHyeon (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 235138aa43c5SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 235238aa43c5SPyun YongHyeon vge_setvlan(sc); 235340929967SGleb Smirnoff } 235438aa43c5SPyun YongHyeon VGE_UNLOCK(sc); 235538aa43c5SPyun YongHyeon VLAN_CAPABILITIES(ifp); 2356a07bd003SBill Paul break; 2357a07bd003SBill Paul default: 2358a07bd003SBill Paul error = ether_ioctl(ifp, command, data); 2359a07bd003SBill Paul break; 2360a07bd003SBill Paul } 2361a07bd003SBill Paul 2362a07bd003SBill Paul return (error); 2363a07bd003SBill Paul } 2364a07bd003SBill Paul 2365a07bd003SBill Paul static void 236667e1dfa7SJohn Baldwin vge_watchdog(void *arg) 2367a07bd003SBill Paul { 2368a07bd003SBill Paul struct vge_softc *sc; 236967e1dfa7SJohn Baldwin struct ifnet *ifp; 2370a07bd003SBill Paul 237167e1dfa7SJohn Baldwin sc = arg; 237267e1dfa7SJohn Baldwin VGE_LOCK_ASSERT(sc); 23737129fb20SPyun YongHyeon vge_stats_update(sc); 237467e1dfa7SJohn Baldwin callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 237567e1dfa7SJohn Baldwin if (sc->vge_timer == 0 || --sc->vge_timer > 0) 237667e1dfa7SJohn Baldwin return; 237767e1dfa7SJohn Baldwin 237867e1dfa7SJohn Baldwin ifp = sc->vge_ifp; 2379f1b21184SJohn Baldwin if_printf(ifp, "watchdog timeout\n"); 2380a07bd003SBill Paul ifp->if_oerrors++; 2381a07bd003SBill Paul 2382a07bd003SBill Paul vge_txeof(sc); 2383410f4c60SPyun YongHyeon vge_rxeof(sc, VGE_RX_DESC_CNT); 2384a07bd003SBill Paul 2385410f4c60SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 238667e1dfa7SJohn Baldwin vge_init_locked(sc); 2387a07bd003SBill Paul } 2388a07bd003SBill Paul 2389a07bd003SBill Paul /* 2390a07bd003SBill Paul * Stop the adapter and free any mbufs allocated to the 2391a07bd003SBill Paul * RX and TX lists. 2392a07bd003SBill Paul */ 2393a07bd003SBill Paul static void 23946afe22a8SPyun YongHyeon vge_stop(struct vge_softc *sc) 2395a07bd003SBill Paul { 2396a07bd003SBill Paul struct ifnet *ifp; 2397a07bd003SBill Paul 239867e1dfa7SJohn Baldwin VGE_LOCK_ASSERT(sc); 2399fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 240067e1dfa7SJohn Baldwin sc->vge_timer = 0; 240167e1dfa7SJohn Baldwin callout_stop(&sc->vge_watchdog); 2402a07bd003SBill Paul 240313f4c340SRobert Watson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2404a07bd003SBill Paul 2405a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2406a07bd003SBill Paul CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2407a07bd003SBill Paul CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2408a07bd003SBill Paul CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2409a07bd003SBill Paul CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2410a07bd003SBill Paul CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2411a07bd003SBill Paul 24127129fb20SPyun YongHyeon vge_stats_update(sc); 2413410f4c60SPyun YongHyeon VGE_CHAIN_RESET(sc); 2414410f4c60SPyun YongHyeon vge_txeof(sc); 2415410f4c60SPyun YongHyeon vge_freebufs(sc); 2416a07bd003SBill Paul } 2417a07bd003SBill Paul 2418a07bd003SBill Paul /* 2419a07bd003SBill Paul * Device suspend routine. Stop the interface and save some PCI 2420a07bd003SBill Paul * settings in case the BIOS doesn't restore them properly on 2421a07bd003SBill Paul * resume. 2422a07bd003SBill Paul */ 2423a07bd003SBill Paul static int 24246afe22a8SPyun YongHyeon vge_suspend(device_t dev) 2425a07bd003SBill Paul { 2426a07bd003SBill Paul struct vge_softc *sc; 2427a07bd003SBill Paul 2428a07bd003SBill Paul sc = device_get_softc(dev); 2429a07bd003SBill Paul 243067e1dfa7SJohn Baldwin VGE_LOCK(sc); 2431a07bd003SBill Paul vge_stop(sc); 2432a07bd003SBill Paul 2433a07bd003SBill Paul sc->suspended = 1; 243467e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 2435a07bd003SBill Paul 2436a07bd003SBill Paul return (0); 2437a07bd003SBill Paul } 2438a07bd003SBill Paul 2439a07bd003SBill Paul /* 2440a07bd003SBill Paul * Device resume routine. Restore some PCI settings in case the BIOS 2441a07bd003SBill Paul * doesn't, re-enable busmastering, and restart the interface if 2442a07bd003SBill Paul * appropriate. 2443a07bd003SBill Paul */ 2444a07bd003SBill Paul static int 24456afe22a8SPyun YongHyeon vge_resume(device_t dev) 2446a07bd003SBill Paul { 2447a07bd003SBill Paul struct vge_softc *sc; 2448a07bd003SBill Paul struct ifnet *ifp; 2449a07bd003SBill Paul 2450a07bd003SBill Paul sc = device_get_softc(dev); 2451fc74a9f9SBrooks Davis ifp = sc->vge_ifp; 2452a07bd003SBill Paul 2453a07bd003SBill Paul /* reenable busmastering */ 2454a07bd003SBill Paul pci_enable_busmaster(dev); 2455a07bd003SBill Paul pci_enable_io(dev, SYS_RES_MEMORY); 2456a07bd003SBill Paul 2457a07bd003SBill Paul /* reinitialize interface if necessary */ 245867e1dfa7SJohn Baldwin VGE_LOCK(sc); 2459410f4c60SPyun YongHyeon if (ifp->if_flags & IFF_UP) { 2460410f4c60SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 246167e1dfa7SJohn Baldwin vge_init_locked(sc); 2462410f4c60SPyun YongHyeon } 2463a07bd003SBill Paul sc->suspended = 0; 246467e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 2465a07bd003SBill Paul 2466a07bd003SBill Paul return (0); 2467a07bd003SBill Paul } 2468a07bd003SBill Paul 2469a07bd003SBill Paul /* 2470a07bd003SBill Paul * Stop all chip I/O so that the kernel's probe routines don't 2471a07bd003SBill Paul * get confused by errant DMAs when rebooting. 2472a07bd003SBill Paul */ 24736a087a87SPyun YongHyeon static int 24746afe22a8SPyun YongHyeon vge_shutdown(device_t dev) 2475a07bd003SBill Paul { 2476a07bd003SBill Paul struct vge_softc *sc; 2477a07bd003SBill Paul 2478a07bd003SBill Paul sc = device_get_softc(dev); 2479a07bd003SBill Paul 248067e1dfa7SJohn Baldwin VGE_LOCK(sc); 2481a07bd003SBill Paul vge_stop(sc); 248267e1dfa7SJohn Baldwin VGE_UNLOCK(sc); 24836a087a87SPyun YongHyeon 24846a087a87SPyun YongHyeon return (0); 2485a07bd003SBill Paul } 24867129fb20SPyun YongHyeon 24877129fb20SPyun YongHyeon #define VGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 24887129fb20SPyun YongHyeon SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 24897129fb20SPyun YongHyeon 24907129fb20SPyun YongHyeon static void 24917129fb20SPyun YongHyeon vge_sysctl_node(struct vge_softc *sc) 24927129fb20SPyun YongHyeon { 24937129fb20SPyun YongHyeon struct sysctl_ctx_list *ctx; 24947129fb20SPyun YongHyeon struct sysctl_oid_list *child, *parent; 24957129fb20SPyun YongHyeon struct sysctl_oid *tree; 24967129fb20SPyun YongHyeon struct vge_hw_stats *stats; 24977129fb20SPyun YongHyeon 24987129fb20SPyun YongHyeon stats = &sc->vge_stats; 24997129fb20SPyun YongHyeon ctx = device_get_sysctl_ctx(sc->vge_dev); 25007129fb20SPyun YongHyeon child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->vge_dev)); 25017129fb20SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 25027129fb20SPyun YongHyeon NULL, "VGE statistics"); 25037129fb20SPyun YongHyeon parent = SYSCTL_CHILDREN(tree); 25047129fb20SPyun YongHyeon 25057129fb20SPyun YongHyeon /* Rx statistics. */ 25067129fb20SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 25077129fb20SPyun YongHyeon NULL, "RX MAC statistics"); 25087129fb20SPyun YongHyeon child = SYSCTL_CHILDREN(tree); 25097129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames", 25107129fb20SPyun YongHyeon &stats->rx_frames, "frames"); 25117129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 25127129fb20SPyun YongHyeon &stats->rx_good_frames, "Good frames"); 25137129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 25147129fb20SPyun YongHyeon &stats->rx_fifo_oflows, "FIFO overflows"); 25157129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "runts", 25167129fb20SPyun YongHyeon &stats->rx_runts, "Too short frames"); 25177129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "runts_errs", 25187129fb20SPyun YongHyeon &stats->rx_runts_errs, "Too short frames with errors"); 25197129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 25207129fb20SPyun YongHyeon &stats->rx_pkts_64, "64 bytes frames"); 25217129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 25227129fb20SPyun YongHyeon &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 25237129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 25247129fb20SPyun YongHyeon &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 25257129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 25267129fb20SPyun YongHyeon &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 25277129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 25287129fb20SPyun YongHyeon &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 25297129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 25307129fb20SPyun YongHyeon &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 25317129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 25327129fb20SPyun YongHyeon &stats->rx_pkts_1519_max, "1519 to max frames"); 25337129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max_errs", 25347129fb20SPyun YongHyeon &stats->rx_pkts_1519_max_errs, "1519 to max frames with error"); 25357129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 25367129fb20SPyun YongHyeon &stats->rx_jumbos, "Jumbo frames"); 25377129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", 25387129fb20SPyun YongHyeon &stats->rx_crcerrs, "CRC errors"); 25397129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 25407129fb20SPyun YongHyeon &stats->rx_pause_frames, "CRC errors"); 25417129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 25427129fb20SPyun YongHyeon &stats->rx_alignerrs, "Alignment errors"); 25437129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "nobufs", 25447129fb20SPyun YongHyeon &stats->rx_nobufs, "Frames with no buffer event"); 25457129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 25467129fb20SPyun YongHyeon &stats->rx_symerrs, "Frames with symbol errors"); 25477129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 25487129fb20SPyun YongHyeon &stats->rx_lenerrs, "Frames with length mismatched"); 25497129fb20SPyun YongHyeon 25507129fb20SPyun YongHyeon /* Tx statistics. */ 25517129fb20SPyun YongHyeon tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 25527129fb20SPyun YongHyeon NULL, "TX MAC statistics"); 25537129fb20SPyun YongHyeon child = SYSCTL_CHILDREN(tree); 25547129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 25557129fb20SPyun YongHyeon &stats->tx_good_frames, "Good frames"); 25567129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 25577129fb20SPyun YongHyeon &stats->tx_pkts_64, "64 bytes frames"); 25587129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 25597129fb20SPyun YongHyeon &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 25607129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 25617129fb20SPyun YongHyeon &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 25627129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 25637129fb20SPyun YongHyeon &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 25647129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 25657129fb20SPyun YongHyeon &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 25667129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 25677129fb20SPyun YongHyeon &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 25687129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "frames_jumbo", 25697129fb20SPyun YongHyeon &stats->tx_jumbos, "Jumbo frames"); 25707129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "colls", 25717129fb20SPyun YongHyeon &stats->tx_colls, "Collisions"); 25727129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 25737129fb20SPyun YongHyeon &stats->tx_latecolls, "Late collisions"); 25747129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 25757129fb20SPyun YongHyeon &stats->tx_pause, "Pause frames"); 25767129fb20SPyun YongHyeon #ifdef VGE_ENABLE_SQEERR 25777129fb20SPyun YongHyeon VGE_SYSCTL_STAT_ADD32(ctx, child, "sqeerrs", 25787129fb20SPyun YongHyeon &stats->tx_sqeerrs, "SQE errors"); 25797129fb20SPyun YongHyeon #endif 25807129fb20SPyun YongHyeon /* Clear MAC statistics. */ 25817129fb20SPyun YongHyeon vge_stats_clear(sc); 25827129fb20SPyun YongHyeon } 25837129fb20SPyun YongHyeon 25847129fb20SPyun YongHyeon #undef VGE_SYSCTL_STAT_ADD32 25857129fb20SPyun YongHyeon 25867129fb20SPyun YongHyeon static void 25877129fb20SPyun YongHyeon vge_stats_clear(struct vge_softc *sc) 25887129fb20SPyun YongHyeon { 25897129fb20SPyun YongHyeon int i; 25907129fb20SPyun YongHyeon 25917129fb20SPyun YongHyeon VGE_LOCK_ASSERT(sc); 25927129fb20SPyun YongHyeon 25937129fb20SPyun YongHyeon CSR_WRITE_1(sc, VGE_MIBCSR, 25947129fb20SPyun YongHyeon CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FREEZE); 25957129fb20SPyun YongHyeon CSR_WRITE_1(sc, VGE_MIBCSR, 25967129fb20SPyun YongHyeon CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_CLR); 25977129fb20SPyun YongHyeon for (i = VGE_TIMEOUT; i > 0; i--) { 25987129fb20SPyun YongHyeon DELAY(1); 25997129fb20SPyun YongHyeon if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_CLR) == 0) 26007129fb20SPyun YongHyeon break; 26017129fb20SPyun YongHyeon } 26027129fb20SPyun YongHyeon if (i == 0) 26037129fb20SPyun YongHyeon device_printf(sc->vge_dev, "MIB clear timed out!\n"); 26047129fb20SPyun YongHyeon CSR_WRITE_1(sc, VGE_MIBCSR, CSR_READ_1(sc, VGE_MIBCSR) & 26057129fb20SPyun YongHyeon ~VGE_MIBCSR_FREEZE); 26067129fb20SPyun YongHyeon } 26077129fb20SPyun YongHyeon 26087129fb20SPyun YongHyeon static void 26097129fb20SPyun YongHyeon vge_stats_update(struct vge_softc *sc) 26107129fb20SPyun YongHyeon { 26117129fb20SPyun YongHyeon struct vge_hw_stats *stats; 26127129fb20SPyun YongHyeon struct ifnet *ifp; 26137129fb20SPyun YongHyeon uint32_t mib[VGE_MIB_CNT], val; 26147129fb20SPyun YongHyeon int i; 26157129fb20SPyun YongHyeon 26167129fb20SPyun YongHyeon VGE_LOCK_ASSERT(sc); 26177129fb20SPyun YongHyeon 26187129fb20SPyun YongHyeon stats = &sc->vge_stats; 26197129fb20SPyun YongHyeon ifp = sc->vge_ifp; 26207129fb20SPyun YongHyeon 26217129fb20SPyun YongHyeon CSR_WRITE_1(sc, VGE_MIBCSR, 26227129fb20SPyun YongHyeon CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_FLUSH); 26237129fb20SPyun YongHyeon for (i = VGE_TIMEOUT; i > 0; i--) { 26247129fb20SPyun YongHyeon DELAY(1); 26257129fb20SPyun YongHyeon if ((CSR_READ_1(sc, VGE_MIBCSR) & VGE_MIBCSR_FLUSH) == 0) 26267129fb20SPyun YongHyeon break; 26277129fb20SPyun YongHyeon } 26287129fb20SPyun YongHyeon if (i == 0) { 26297129fb20SPyun YongHyeon device_printf(sc->vge_dev, "MIB counter dump timed out!\n"); 26307129fb20SPyun YongHyeon vge_stats_clear(sc); 26317129fb20SPyun YongHyeon return; 26327129fb20SPyun YongHyeon } 26337129fb20SPyun YongHyeon 26347129fb20SPyun YongHyeon bzero(mib, sizeof(mib)); 26357129fb20SPyun YongHyeon reset_idx: 26367129fb20SPyun YongHyeon /* Set MIB read index to 0. */ 26377129fb20SPyun YongHyeon CSR_WRITE_1(sc, VGE_MIBCSR, 26387129fb20SPyun YongHyeon CSR_READ_1(sc, VGE_MIBCSR) | VGE_MIBCSR_RINI); 26397129fb20SPyun YongHyeon for (i = 0; i < VGE_MIB_CNT; i++) { 26407129fb20SPyun YongHyeon val = CSR_READ_4(sc, VGE_MIBDATA); 26417129fb20SPyun YongHyeon if (i != VGE_MIB_DATA_IDX(val)) { 26427129fb20SPyun YongHyeon /* Reading interrupted. */ 26437129fb20SPyun YongHyeon goto reset_idx; 26447129fb20SPyun YongHyeon } 26457129fb20SPyun YongHyeon mib[i] = val & VGE_MIB_DATA_MASK; 26467129fb20SPyun YongHyeon } 26477129fb20SPyun YongHyeon 26487129fb20SPyun YongHyeon /* Rx stats. */ 26497129fb20SPyun YongHyeon stats->rx_frames += mib[VGE_MIB_RX_FRAMES]; 26507129fb20SPyun YongHyeon stats->rx_good_frames += mib[VGE_MIB_RX_GOOD_FRAMES]; 26517129fb20SPyun YongHyeon stats->rx_fifo_oflows += mib[VGE_MIB_RX_FIFO_OVERRUNS]; 26527129fb20SPyun YongHyeon stats->rx_runts += mib[VGE_MIB_RX_RUNTS]; 26537129fb20SPyun YongHyeon stats->rx_runts_errs += mib[VGE_MIB_RX_RUNTS_ERRS]; 26547129fb20SPyun YongHyeon stats->rx_pkts_64 += mib[VGE_MIB_RX_PKTS_64]; 26557129fb20SPyun YongHyeon stats->rx_pkts_65_127 += mib[VGE_MIB_RX_PKTS_65_127]; 26567129fb20SPyun YongHyeon stats->rx_pkts_128_255 += mib[VGE_MIB_RX_PKTS_128_255]; 26577129fb20SPyun YongHyeon stats->rx_pkts_256_511 += mib[VGE_MIB_RX_PKTS_256_511]; 26587129fb20SPyun YongHyeon stats->rx_pkts_512_1023 += mib[VGE_MIB_RX_PKTS_512_1023]; 26597129fb20SPyun YongHyeon stats->rx_pkts_1024_1518 += mib[VGE_MIB_RX_PKTS_1024_1518]; 26607129fb20SPyun YongHyeon stats->rx_pkts_1519_max += mib[VGE_MIB_RX_PKTS_1519_MAX]; 26617129fb20SPyun YongHyeon stats->rx_pkts_1519_max_errs += mib[VGE_MIB_RX_PKTS_1519_MAX_ERRS]; 26627129fb20SPyun YongHyeon stats->rx_jumbos += mib[VGE_MIB_RX_JUMBOS]; 26637129fb20SPyun YongHyeon stats->rx_crcerrs += mib[VGE_MIB_RX_CRCERRS]; 26647129fb20SPyun YongHyeon stats->rx_pause_frames += mib[VGE_MIB_RX_PAUSE]; 26657129fb20SPyun YongHyeon stats->rx_alignerrs += mib[VGE_MIB_RX_ALIGNERRS]; 26667129fb20SPyun YongHyeon stats->rx_nobufs += mib[VGE_MIB_RX_NOBUFS]; 26677129fb20SPyun YongHyeon stats->rx_symerrs += mib[VGE_MIB_RX_SYMERRS]; 26687129fb20SPyun YongHyeon stats->rx_lenerrs += mib[VGE_MIB_RX_LENERRS]; 26697129fb20SPyun YongHyeon 26707129fb20SPyun YongHyeon /* Tx stats. */ 26717129fb20SPyun YongHyeon stats->tx_good_frames += mib[VGE_MIB_TX_GOOD_FRAMES]; 26727129fb20SPyun YongHyeon stats->tx_pkts_64 += mib[VGE_MIB_TX_PKTS_64]; 26737129fb20SPyun YongHyeon stats->tx_pkts_65_127 += mib[VGE_MIB_TX_PKTS_65_127]; 26747129fb20SPyun YongHyeon stats->tx_pkts_128_255 += mib[VGE_MIB_TX_PKTS_128_255]; 26757129fb20SPyun YongHyeon stats->tx_pkts_256_511 += mib[VGE_MIB_TX_PKTS_256_511]; 26767129fb20SPyun YongHyeon stats->tx_pkts_512_1023 += mib[VGE_MIB_TX_PKTS_512_1023]; 26777129fb20SPyun YongHyeon stats->tx_pkts_1024_1518 += mib[VGE_MIB_TX_PKTS_1024_1518]; 26787129fb20SPyun YongHyeon stats->tx_jumbos += mib[VGE_MIB_TX_JUMBOS]; 26797129fb20SPyun YongHyeon stats->tx_colls += mib[VGE_MIB_TX_COLLS]; 26807129fb20SPyun YongHyeon stats->tx_pause += mib[VGE_MIB_TX_PAUSE]; 26817129fb20SPyun YongHyeon #ifdef VGE_ENABLE_SQEERR 26827129fb20SPyun YongHyeon stats->tx_sqeerrs += mib[VGE_MIB_TX_SQEERRS]; 26837129fb20SPyun YongHyeon #endif 26847129fb20SPyun YongHyeon stats->tx_latecolls += mib[VGE_MIB_TX_LATECOLLS]; 26857129fb20SPyun YongHyeon 26867129fb20SPyun YongHyeon /* Update counters in ifnet. */ 26877129fb20SPyun YongHyeon ifp->if_opackets += mib[VGE_MIB_TX_GOOD_FRAMES]; 26887129fb20SPyun YongHyeon 26897129fb20SPyun YongHyeon ifp->if_collisions += mib[VGE_MIB_TX_COLLS] + 26907129fb20SPyun YongHyeon mib[VGE_MIB_TX_LATECOLLS]; 26917129fb20SPyun YongHyeon 26927129fb20SPyun YongHyeon ifp->if_oerrors += mib[VGE_MIB_TX_COLLS] + 26937129fb20SPyun YongHyeon mib[VGE_MIB_TX_LATECOLLS]; 26947129fb20SPyun YongHyeon 26957129fb20SPyun YongHyeon ifp->if_ipackets += mib[VGE_MIB_RX_GOOD_FRAMES]; 26967129fb20SPyun YongHyeon 26977129fb20SPyun YongHyeon ifp->if_ierrors += mib[VGE_MIB_RX_FIFO_OVERRUNS] + 26987129fb20SPyun YongHyeon mib[VGE_MIB_RX_RUNTS] + 26997129fb20SPyun YongHyeon mib[VGE_MIB_RX_RUNTS_ERRS] + 27007129fb20SPyun YongHyeon mib[VGE_MIB_RX_CRCERRS] + 27017129fb20SPyun YongHyeon mib[VGE_MIB_RX_ALIGNERRS] + 27027129fb20SPyun YongHyeon mib[VGE_MIB_RX_NOBUFS] + 27037129fb20SPyun YongHyeon mib[VGE_MIB_RX_SYMERRS] + 27047129fb20SPyun YongHyeon mib[VGE_MIB_RX_LENERRS]; 27057129fb20SPyun YongHyeon } 2706