1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 20 #include "opt_wlan.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/sysctl.h> 25 #include <sys/lock.h> 26 #include <sys/mutex.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kdb.h> 36 37 #include <net/if.h> 38 #include <net/if_var.h> 39 #include <net/if_arp.h> 40 #include <net/ethernet.h> 41 #include <net/if_dl.h> 42 #include <net/if_media.h> 43 #include <net/if_types.h> 44 45 #ifdef INET 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 #include <netinet/in_var.h> 49 #include <netinet/if_ether.h> 50 #include <netinet/ip.h> 51 #endif 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_regdomain.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include "usbdevs.h" 60 61 #include <dev/usb/wlan/if_urtwreg.h> 62 #include <dev/usb/wlan/if_urtwvar.h> 63 64 /* copy some rate indices from if_rtwn_ridx.h */ 65 #define URTW_RIDX_CCK5 2 66 #define URTW_RIDX_CCK11 3 67 #define URTW_RIDX_OFDM6 4 68 #define URTW_RIDX_OFDM24 8 69 70 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 71 #ifdef URTW_DEBUG 72 int urtw_debug = 0; 73 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 74 "control debugging printfs"); 75 enum { 76 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 77 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 78 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 79 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 80 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 81 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 82 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 83 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 84 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 85 URTW_DEBUG_ANY = 0xffffffff 86 }; 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 if (sc->sc_debug & (m)) \ 89 printf(fmt, __VA_ARGS__); \ 90 } while (0) 91 #else 92 #define DPRINTF(sc, m, fmt, ...) do { \ 93 (void) sc; \ 94 } while (0) 95 #endif 96 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 97 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 98 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 99 100 /* recognized device vendors/products */ 101 #define urtw_lookup(v, p) \ 102 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 103 #define URTW_DEV_B(v,p) \ 104 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 105 #define URTW_DEV_L(v,p) \ 106 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 107 #define URTW_REV_RTL8187B 0 108 #define URTW_REV_RTL8187L 1 109 static const STRUCT_USB_HOST_ID urtw_devs[] = { 110 URTW_DEV_B(NETGEAR, WG111V3), 111 URTW_DEV_B(REALTEK, RTL8187B_0), 112 URTW_DEV_B(REALTEK, RTL8187B_1), 113 URTW_DEV_B(REALTEK, RTL8187B_2), 114 URTW_DEV_B(SITECOMEU, WL168V4), 115 URTW_DEV_L(ASUS, P5B_WIFI), 116 URTW_DEV_L(BELKIN, F5D7050E), 117 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 118 URTW_DEV_L(NETGEAR, WG111V2), 119 URTW_DEV_L(REALTEK, RTL8187), 120 URTW_DEV_L(SITECOMEU, WL168V1), 121 URTW_DEV_L(SURECOM, EP9001G2A), 122 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 124 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 125 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 126 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 127 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 128 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 129 #undef URTW_DEV_L 130 #undef URTW_DEV_B 131 }; 132 133 #define urtw_read8_m(sc, val, data) do { \ 134 error = urtw_read8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_write8_m(sc, val, data) do { \ 139 error = urtw_write8_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_read16_m(sc, val, data) do { \ 144 error = urtw_read16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_write16_m(sc, val, data) do { \ 149 error = urtw_write16_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_read32_m(sc, val, data) do { \ 154 error = urtw_read32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_write32_m(sc, val, data) do { \ 159 error = urtw_write32_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 164 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 169 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 #define urtw_8225_write(sc, val, data) do { \ 174 error = urtw_8225_write_c(sc, val, data); \ 175 if (error != 0) \ 176 goto fail; \ 177 } while (0) 178 179 struct urtw_pair { 180 uint32_t reg; 181 uint32_t val; 182 }; 183 184 static uint8_t urtw_8225_agc[] = { 185 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 186 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 187 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 188 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 189 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 190 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 191 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 192 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 193 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 194 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 195 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 196 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 197 }; 198 199 static uint8_t urtw_8225z2_agc[] = { 200 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 201 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 202 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 203 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 204 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 205 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 206 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 207 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 208 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 209 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 210 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 211 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 212 }; 213 214 static uint32_t urtw_8225_channel[] = { 215 0x0000, /* dummy channel 0 */ 216 0x085c, /* 1 */ 217 0x08dc, /* 2 */ 218 0x095c, /* 3 */ 219 0x09dc, /* 4 */ 220 0x0a5c, /* 5 */ 221 0x0adc, /* 6 */ 222 0x0b5c, /* 7 */ 223 0x0bdc, /* 8 */ 224 0x0c5c, /* 9 */ 225 0x0cdc, /* 10 */ 226 0x0d5c, /* 11 */ 227 0x0ddc, /* 12 */ 228 0x0e5c, /* 13 */ 229 0x0f72, /* 14 */ 230 }; 231 232 static uint8_t urtw_8225_gain[] = { 233 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 234 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 235 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 236 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 237 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 238 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 239 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 240 }; 241 242 static struct urtw_pair urtw_8225_rf_part1[] = { 243 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 244 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 245 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 246 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 247 }; 248 249 static struct urtw_pair urtw_8225_rf_part2[] = { 250 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 251 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 252 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 253 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 254 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 255 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 256 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 257 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 258 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 259 { 0x27, 0x88 } 260 }; 261 262 static struct urtw_pair urtw_8225_rf_part3[] = { 263 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 264 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 265 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 266 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 267 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 268 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 269 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 270 }; 271 272 static uint16_t urtw_8225_rxgain[] = { 273 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 274 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 275 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 276 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 277 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 278 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 279 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 280 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 281 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 282 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 283 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 284 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 285 }; 286 287 static uint8_t urtw_8225_threshold[] = { 288 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 289 }; 290 291 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 292 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 293 }; 294 295 static uint8_t urtw_8225_txpwr_cck[] = { 296 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 297 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 298 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 299 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 300 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 301 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 302 }; 303 304 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 305 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 306 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 307 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 308 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 309 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 310 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 311 }; 312 313 static uint8_t urtw_8225_txpwr_ofdm[]={ 314 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 315 }; 316 317 static uint8_t urtw_8225v2_gain_bg[]={ 318 0x23, 0x15, 0xa5, /* -82-1dbm */ 319 0x23, 0x15, 0xb5, /* -82-2dbm */ 320 0x23, 0x15, 0xc5, /* -82-3dbm */ 321 0x33, 0x15, 0xc5, /* -78dbm */ 322 0x43, 0x15, 0xc5, /* -74dbm */ 323 0x53, 0x15, 0xc5, /* -70dbm */ 324 0x63, 0x15, 0xc5, /* -66dbm */ 325 }; 326 327 static struct urtw_pair urtw_8225v2_rf_part1[] = { 328 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 329 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 330 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 331 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 332 }; 333 334 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 335 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 336 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 337 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 338 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 339 }; 340 341 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 342 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 343 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 344 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 345 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 346 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 347 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 348 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 349 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 350 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 351 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 352 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 353 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 354 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 355 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 356 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 357 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 358 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 359 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 360 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 361 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 362 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 363 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 364 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 365 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 366 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 367 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 368 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 369 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 370 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 371 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 372 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 373 }; 374 375 static struct urtw_pair urtw_8225v2_rf_part2[] = { 376 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 377 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 378 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 379 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 380 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 381 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 382 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 383 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 384 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 385 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 386 }; 387 388 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 389 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 390 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 391 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 392 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 393 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 394 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 395 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 396 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 397 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 398 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 399 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 400 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 401 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 402 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 403 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 404 }; 405 406 static struct urtw_pair urtw_8225v2_rf_part3[] = { 407 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 408 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 409 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 410 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 411 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 412 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 413 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 414 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 415 }; 416 417 static uint16_t urtw_8225v2_rxgain[] = { 418 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 419 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 420 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 421 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 422 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 423 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 424 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 425 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 426 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 427 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 428 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 429 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 430 }; 431 432 static uint16_t urtw_8225v2b_rxgain[] = { 433 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 434 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 435 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 436 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 437 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 438 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 439 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 440 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 441 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 442 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 443 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 444 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 445 }; 446 447 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 448 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 449 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 450 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 451 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 452 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 453 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 454 }; 455 456 static uint8_t urtw_8225v2_txpwr_cck[] = { 457 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 458 }; 459 460 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 461 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 462 }; 463 464 static uint8_t urtw_8225v2b_txpwr_cck[] = { 465 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 466 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 467 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 468 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 469 }; 470 471 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 472 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 474 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 475 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 476 }; 477 478 static struct urtw_pair urtw_ratetable[] = { 479 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 480 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 481 { 96, 10 }, { 108, 11 } 482 }; 483 484 #if 0 485 static const uint8_t urtw_8187b_reg_table[][3] = { 486 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 487 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 488 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 489 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 490 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 491 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 492 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 493 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 494 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 495 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 496 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 497 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 498 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 499 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 500 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 501 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 502 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 503 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 504 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 505 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 506 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 507 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 508 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 509 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 510 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 511 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 512 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 513 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 514 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 515 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 516 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 517 }; 518 #endif 519 520 static usb_callback_t urtw_bulk_rx_callback; 521 static usb_callback_t urtw_bulk_tx_callback; 522 static usb_callback_t urtw_bulk_tx_status_callback; 523 524 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 525 [URTW_8187B_BULK_RX] = { 526 .type = UE_BULK, 527 .endpoint = 0x83, 528 .direction = UE_DIR_IN, 529 .bufsize = MCLBYTES, 530 .flags = { 531 .ext_buffer = 1, 532 .pipe_bof = 1, 533 .short_xfer_ok = 1 534 }, 535 .callback = urtw_bulk_rx_callback 536 }, 537 [URTW_8187B_BULK_TX_STATUS] = { 538 .type = UE_BULK, 539 .endpoint = 0x89, 540 .direction = UE_DIR_IN, 541 .bufsize = sizeof(uint64_t), 542 .flags = { 543 .pipe_bof = 1, 544 .short_xfer_ok = 1 545 }, 546 .callback = urtw_bulk_tx_status_callback 547 }, 548 [URTW_8187B_BULK_TX_BE] = { 549 .type = UE_BULK, 550 .endpoint = URTW_8187B_TXPIPE_BE, 551 .direction = UE_DIR_OUT, 552 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 553 .flags = { 554 .force_short_xfer = 1, 555 .pipe_bof = 1, 556 }, 557 .callback = urtw_bulk_tx_callback, 558 .timeout = URTW_DATA_TIMEOUT 559 }, 560 [URTW_8187B_BULK_TX_BK] = { 561 .type = UE_BULK, 562 .endpoint = URTW_8187B_TXPIPE_BK, 563 .direction = UE_DIR_OUT, 564 .bufsize = URTW_TX_MAXSIZE, 565 .flags = { 566 .ext_buffer = 1, 567 .force_short_xfer = 1, 568 .pipe_bof = 1, 569 }, 570 .callback = urtw_bulk_tx_callback, 571 .timeout = URTW_DATA_TIMEOUT 572 }, 573 [URTW_8187B_BULK_TX_VI] = { 574 .type = UE_BULK, 575 .endpoint = URTW_8187B_TXPIPE_VI, 576 .direction = UE_DIR_OUT, 577 .bufsize = URTW_TX_MAXSIZE, 578 .flags = { 579 .ext_buffer = 1, 580 .force_short_xfer = 1, 581 .pipe_bof = 1, 582 }, 583 .callback = urtw_bulk_tx_callback, 584 .timeout = URTW_DATA_TIMEOUT 585 }, 586 [URTW_8187B_BULK_TX_VO] = { 587 .type = UE_BULK, 588 .endpoint = URTW_8187B_TXPIPE_VO, 589 .direction = UE_DIR_OUT, 590 .bufsize = URTW_TX_MAXSIZE, 591 .flags = { 592 .ext_buffer = 1, 593 .force_short_xfer = 1, 594 .pipe_bof = 1, 595 }, 596 .callback = urtw_bulk_tx_callback, 597 .timeout = URTW_DATA_TIMEOUT 598 }, 599 [URTW_8187B_BULK_TX_EP12] = { 600 .type = UE_BULK, 601 .endpoint = 0xc, 602 .direction = UE_DIR_OUT, 603 .bufsize = URTW_TX_MAXSIZE, 604 .flags = { 605 .ext_buffer = 1, 606 .force_short_xfer = 1, 607 .pipe_bof = 1, 608 }, 609 .callback = urtw_bulk_tx_callback, 610 .timeout = URTW_DATA_TIMEOUT 611 } 612 }; 613 614 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 615 [URTW_8187L_BULK_RX] = { 616 .type = UE_BULK, 617 .endpoint = 0x81, 618 .direction = UE_DIR_IN, 619 .bufsize = MCLBYTES, 620 .flags = { 621 .ext_buffer = 1, 622 .pipe_bof = 1, 623 .short_xfer_ok = 1 624 }, 625 .callback = urtw_bulk_rx_callback 626 }, 627 [URTW_8187L_BULK_TX_LOW] = { 628 .type = UE_BULK, 629 .endpoint = 0x2, 630 .direction = UE_DIR_OUT, 631 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 632 .flags = { 633 .force_short_xfer = 1, 634 .pipe_bof = 1, 635 }, 636 .callback = urtw_bulk_tx_callback, 637 .timeout = URTW_DATA_TIMEOUT 638 }, 639 [URTW_8187L_BULK_TX_NORMAL] = { 640 .type = UE_BULK, 641 .endpoint = 0x3, 642 .direction = UE_DIR_OUT, 643 .bufsize = URTW_TX_MAXSIZE, 644 .flags = { 645 .ext_buffer = 1, 646 .force_short_xfer = 1, 647 .pipe_bof = 1, 648 }, 649 .callback = urtw_bulk_tx_callback, 650 .timeout = URTW_DATA_TIMEOUT 651 }, 652 }; 653 654 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 655 const char [IFNAMSIZ], int, enum ieee80211_opmode, 656 int, const uint8_t [IEEE80211_ADDR_LEN], 657 const uint8_t [IEEE80211_ADDR_LEN]); 658 static void urtw_vap_delete(struct ieee80211vap *); 659 static void urtw_init(struct urtw_softc *); 660 static void urtw_stop(struct urtw_softc *); 661 static void urtw_parent(struct ieee80211com *); 662 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 663 static void urtw_start(struct urtw_softc *); 664 static int urtw_alloc_rx_data_list(struct urtw_softc *); 665 static int urtw_alloc_tx_data_list(struct urtw_softc *); 666 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 667 const struct ieee80211_bpf_params *); 668 static void urtw_scan_start(struct ieee80211com *); 669 static void urtw_scan_end(struct ieee80211com *); 670 static void urtw_getradiocaps(struct ieee80211com *, int, int *, 671 struct ieee80211_channel[]); 672 static void urtw_set_channel(struct ieee80211com *); 673 static void urtw_update_promisc(struct ieee80211com *); 674 static void urtw_update_mcast(struct ieee80211com *); 675 static int urtw_tx_start(struct urtw_softc *, 676 struct ieee80211_node *, struct mbuf *, 677 struct urtw_data *, int); 678 static int urtw_newstate(struct ieee80211vap *, 679 enum ieee80211_state, int); 680 static void urtw_led_ch(void *); 681 static void urtw_ledtask(void *, int); 682 static void urtw_watchdog(void *); 683 static void urtw_set_multi(void *); 684 static int urtw_isbmode(uint16_t); 685 static uint16_t urtw_rtl2rate(uint32_t); 686 static usb_error_t urtw_set_rate(struct urtw_softc *); 687 static usb_error_t urtw_update_msr(struct urtw_softc *); 688 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 689 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 690 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 691 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 692 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 693 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 694 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 695 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 696 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 697 int); 698 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 699 uint32_t *); 700 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 701 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 702 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 703 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 704 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 705 static usb_error_t urtw_led_init(struct urtw_softc *); 706 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 707 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 708 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 709 uint32_t); 710 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 711 uint8_t, uint32_t); 712 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 713 uint32_t); 714 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 715 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 716 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 717 uint16_t); 718 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 719 uint16_t *); 720 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 721 uint32_t *); 722 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 723 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 724 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 725 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 726 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 727 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 728 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 729 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 730 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 731 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 732 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 733 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 734 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 735 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 736 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 737 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 738 static usb_error_t urtw_intr_enable(struct urtw_softc *); 739 static usb_error_t urtw_intr_disable(struct urtw_softc *); 740 static usb_error_t urtw_reset(struct urtw_softc *); 741 static usb_error_t urtw_led_on(struct urtw_softc *, int); 742 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 743 static usb_error_t urtw_led_blink(struct urtw_softc *); 744 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 745 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 746 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 747 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 748 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 749 static usb_error_t urtw_rx_enable(struct urtw_softc *); 750 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 751 static void urtw_free_tx_data_list(struct urtw_softc *); 752 static void urtw_free_rx_data_list(struct urtw_softc *); 753 static void urtw_free_data_list(struct urtw_softc *, 754 struct urtw_data data[], int, int); 755 static usb_error_t urtw_adapter_start(struct urtw_softc *); 756 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 757 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 758 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 759 static usb_error_t urtw_do_request(struct urtw_softc *, 760 struct usb_device_request *, void *); 761 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 762 static usb_error_t urtw_led_off(struct urtw_softc *, int); 763 static void urtw_abort_xfers(struct urtw_softc *); 764 static struct urtw_data * 765 urtw_getbuf(struct urtw_softc *sc); 766 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 767 uint8_t); 768 static void urtw_updateslot(struct ieee80211com *); 769 static void urtw_updateslottask(void *, int); 770 static void urtw_sysctl_node(struct urtw_softc *); 771 772 static int 773 urtw_match(device_t dev) 774 { 775 struct usb_attach_arg *uaa = device_get_ivars(dev); 776 777 if (uaa->usb_mode != USB_MODE_HOST) 778 return (ENXIO); 779 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 780 return (ENXIO); 781 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 782 return (ENXIO); 783 784 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 785 } 786 787 static int 788 urtw_attach(device_t dev) 789 { 790 const struct usb_config *setup_start; 791 int ret = ENXIO; 792 struct urtw_softc *sc = device_get_softc(dev); 793 struct usb_attach_arg *uaa = device_get_ivars(dev); 794 struct ieee80211com *ic = &sc->sc_ic; 795 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 796 uint16_t n_setup; 797 uint32_t data; 798 usb_error_t error; 799 800 device_set_usb_desc(dev); 801 802 sc->sc_dev = dev; 803 sc->sc_udev = uaa->device; 804 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 805 sc->sc_flags |= URTW_RTL8187B; 806 #ifdef URTW_DEBUG 807 sc->sc_debug = urtw_debug; 808 #endif 809 810 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 811 MTX_DEF); 812 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 813 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 814 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 815 callout_init(&sc->sc_watchdog_ch, 0); 816 mbufq_init(&sc->sc_snd, ifqmaxlen); 817 818 if (sc->sc_flags & URTW_RTL8187B) { 819 setup_start = urtw_8187b_usbconfig; 820 n_setup = URTW_8187B_N_XFERS; 821 } else { 822 setup_start = urtw_8187l_usbconfig; 823 n_setup = URTW_8187L_N_XFERS; 824 } 825 826 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 827 setup_start, n_setup, sc, &sc->sc_mtx); 828 if (error) { 829 device_printf(dev, "could not allocate USB transfers, " 830 "err=%s\n", usbd_errstr(error)); 831 ret = ENXIO; 832 goto fail0; 833 } 834 835 if (sc->sc_flags & URTW_RTL8187B) { 836 sc->sc_tx_dma_buf = 837 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 838 URTW_8187B_BULK_TX_BE], 0); 839 } else { 840 sc->sc_tx_dma_buf = 841 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 842 URTW_8187L_BULK_TX_LOW], 0); 843 } 844 845 URTW_LOCK(sc); 846 847 urtw_read32_m(sc, URTW_RX, &data); 848 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 849 URTW_EEPROM_93C46; 850 851 error = urtw_get_rfchip(sc); 852 if (error != 0) 853 goto fail; 854 error = urtw_get_macaddr(sc); 855 if (error != 0) 856 goto fail; 857 error = urtw_get_txpwr(sc); 858 if (error != 0) 859 goto fail; 860 error = urtw_led_init(sc); 861 if (error != 0) 862 goto fail; 863 864 URTW_UNLOCK(sc); 865 866 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 867 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 868 sc->sc_currate = URTW_RIDX_CCK11; 869 sc->sc_preamble_mode = urtw_preamble_mode; 870 871 ic->ic_softc = sc; 872 ic->ic_name = device_get_nameunit(dev); 873 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 874 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 875 876 /* set device capabilities */ 877 ic->ic_caps = 878 IEEE80211_C_STA | /* station mode */ 879 IEEE80211_C_MONITOR | /* monitor mode supported */ 880 IEEE80211_C_TXPMGT | /* tx power management */ 881 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 882 IEEE80211_C_SHSLOT | /* short slot time supported */ 883 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 884 IEEE80211_C_WPA; /* 802.11i */ 885 886 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 887 888 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 889 ic->ic_channels); 890 891 ieee80211_ifattach(ic); 892 ic->ic_raw_xmit = urtw_raw_xmit; 893 ic->ic_scan_start = urtw_scan_start; 894 ic->ic_scan_end = urtw_scan_end; 895 ic->ic_getradiocaps = urtw_getradiocaps; 896 ic->ic_set_channel = urtw_set_channel; 897 ic->ic_updateslot = urtw_updateslot; 898 ic->ic_vap_create = urtw_vap_create; 899 ic->ic_vap_delete = urtw_vap_delete; 900 ic->ic_update_promisc = urtw_update_promisc; 901 ic->ic_update_mcast = urtw_update_mcast; 902 ic->ic_parent = urtw_parent; 903 ic->ic_transmit = urtw_transmit; 904 905 ieee80211_radiotap_attach(ic, 906 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 907 URTW_TX_RADIOTAP_PRESENT, 908 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 909 URTW_RX_RADIOTAP_PRESENT); 910 911 urtw_sysctl_node(sc); 912 913 if (bootverbose) 914 ieee80211_announce(ic); 915 return (0); 916 917 fail: 918 URTW_UNLOCK(sc); 919 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 920 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 921 fail0: 922 return (ret); 923 } 924 925 static int 926 urtw_detach(device_t dev) 927 { 928 struct urtw_softc *sc = device_get_softc(dev); 929 struct ieee80211com *ic = &sc->sc_ic; 930 unsigned int x; 931 unsigned int n_xfers; 932 933 /* Prevent further ioctls */ 934 URTW_LOCK(sc); 935 sc->sc_flags |= URTW_DETACHED; 936 urtw_stop(sc); 937 URTW_UNLOCK(sc); 938 939 ieee80211_draintask(ic, &sc->sc_updateslot_task); 940 ieee80211_draintask(ic, &sc->sc_led_task); 941 942 usb_callout_drain(&sc->sc_led_ch); 943 callout_drain(&sc->sc_watchdog_ch); 944 945 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 946 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 947 948 /* prevent further allocations from RX/TX data lists */ 949 URTW_LOCK(sc); 950 STAILQ_INIT(&sc->sc_tx_active); 951 STAILQ_INIT(&sc->sc_tx_inactive); 952 STAILQ_INIT(&sc->sc_tx_pending); 953 954 STAILQ_INIT(&sc->sc_rx_active); 955 STAILQ_INIT(&sc->sc_rx_inactive); 956 URTW_UNLOCK(sc); 957 958 /* drain USB transfers */ 959 for (x = 0; x != n_xfers; x++) 960 usbd_transfer_drain(sc->sc_xfer[x]); 961 962 /* free data buffers */ 963 URTW_LOCK(sc); 964 urtw_free_tx_data_list(sc); 965 urtw_free_rx_data_list(sc); 966 URTW_UNLOCK(sc); 967 968 /* free USB transfers and some data buffers */ 969 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 970 971 ieee80211_ifdetach(ic); 972 mbufq_drain(&sc->sc_snd); 973 mtx_destroy(&sc->sc_mtx); 974 return (0); 975 } 976 977 static void 978 urtw_free_tx_data_list(struct urtw_softc *sc) 979 { 980 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 981 } 982 983 static void 984 urtw_free_rx_data_list(struct urtw_softc *sc) 985 { 986 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 987 } 988 989 static void 990 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 991 int fillmbuf) 992 { 993 int i; 994 995 for (i = 0; i < ndata; i++) { 996 struct urtw_data *dp = &data[i]; 997 998 if (fillmbuf == 1) { 999 if (dp->m != NULL) { 1000 m_freem(dp->m); 1001 dp->m = NULL; 1002 dp->buf = NULL; 1003 } 1004 } else { 1005 dp->buf = NULL; 1006 } 1007 if (dp->ni != NULL) { 1008 ieee80211_free_node(dp->ni); 1009 dp->ni = NULL; 1010 } 1011 } 1012 } 1013 1014 static struct ieee80211vap * 1015 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1016 enum ieee80211_opmode opmode, int flags, 1017 const uint8_t bssid[IEEE80211_ADDR_LEN], 1018 const uint8_t mac[IEEE80211_ADDR_LEN]) 1019 { 1020 struct urtw_vap *uvp; 1021 struct ieee80211vap *vap; 1022 1023 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1024 return (NULL); 1025 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1026 vap = &uvp->vap; 1027 /* enable s/w bmiss handling for sta mode */ 1028 1029 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1030 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1031 /* out of memory */ 1032 free(uvp, M_80211_VAP); 1033 return (NULL); 1034 } 1035 1036 /* override state transition machine */ 1037 uvp->newstate = vap->iv_newstate; 1038 vap->iv_newstate = urtw_newstate; 1039 1040 /* complete setup */ 1041 ieee80211_vap_attach(vap, ieee80211_media_change, 1042 ieee80211_media_status, mac); 1043 ic->ic_opmode = opmode; 1044 return (vap); 1045 } 1046 1047 static void 1048 urtw_vap_delete(struct ieee80211vap *vap) 1049 { 1050 struct urtw_vap *uvp = URTW_VAP(vap); 1051 1052 ieee80211_vap_detach(vap); 1053 free(uvp, M_80211_VAP); 1054 } 1055 1056 static void 1057 urtw_init(struct urtw_softc *sc) 1058 { 1059 usb_error_t error; 1060 int ret; 1061 1062 URTW_ASSERT_LOCKED(sc); 1063 1064 if (sc->sc_flags & URTW_RUNNING) 1065 urtw_stop(sc); 1066 1067 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1068 urtw_adapter_start(sc); 1069 if (error != 0) 1070 goto fail; 1071 1072 /* reset softc variables */ 1073 sc->sc_txtimer = 0; 1074 1075 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1076 ret = urtw_alloc_rx_data_list(sc); 1077 if (ret != 0) 1078 goto fail; 1079 ret = urtw_alloc_tx_data_list(sc); 1080 if (ret != 0) 1081 goto fail; 1082 sc->sc_flags |= URTW_INIT_ONCE; 1083 } 1084 1085 error = urtw_rx_enable(sc); 1086 if (error != 0) 1087 goto fail; 1088 error = urtw_tx_enable(sc); 1089 if (error != 0) 1090 goto fail; 1091 1092 if (sc->sc_flags & URTW_RTL8187B) 1093 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1094 1095 sc->sc_flags |= URTW_RUNNING; 1096 1097 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1098 fail: 1099 return; 1100 } 1101 1102 static usb_error_t 1103 urtw_adapter_start_b(struct urtw_softc *sc) 1104 { 1105 uint8_t data8; 1106 usb_error_t error; 1107 1108 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1109 if (error) 1110 goto fail; 1111 1112 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1113 urtw_write8_m(sc, URTW_CONFIG3, 1114 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1115 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1116 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1117 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1118 1119 urtw_write8_m(sc, 0x61, 0x10); 1120 urtw_read8_m(sc, 0x62, &data8); 1121 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1122 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1123 1124 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1125 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1126 urtw_write8_m(sc, URTW_CONFIG3, data8); 1127 1128 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1129 if (error) 1130 goto fail; 1131 1132 error = urtw_8187b_cmd_reset(sc); 1133 if (error) 1134 goto fail; 1135 1136 error = sc->sc_rf_init(sc); 1137 if (error != 0) 1138 goto fail; 1139 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1140 1141 /* fix RTL8187B RX stall */ 1142 error = urtw_intr_enable(sc); 1143 if (error) 1144 goto fail; 1145 1146 error = urtw_write8e(sc, 0x41, 0xf4); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x40, 0x00); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x00); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x42, 0x01); 1156 if (error) 1157 goto fail; 1158 error = urtw_write8e(sc, 0x40, 0x0f); 1159 if (error) 1160 goto fail; 1161 error = urtw_write8e(sc, 0x42, 0x00); 1162 if (error) 1163 goto fail; 1164 error = urtw_write8e(sc, 0x42, 0x01); 1165 if (error) 1166 goto fail; 1167 1168 urtw_read8_m(sc, 0xdb, &data8); 1169 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1170 urtw_write16_m(sc, 0x372, 0x59fa); 1171 urtw_write16_m(sc, 0x374, 0x59d2); 1172 urtw_write16_m(sc, 0x376, 0x59d2); 1173 urtw_write16_m(sc, 0x378, 0x19fa); 1174 urtw_write16_m(sc, 0x37a, 0x19fa); 1175 urtw_write16_m(sc, 0x37c, 0x00d0); 1176 urtw_write8_m(sc, 0x61, 0); 1177 1178 urtw_write8_m(sc, 0x180, 0x0f); 1179 urtw_write8_m(sc, 0x183, 0x03); 1180 urtw_write8_m(sc, 0xda, 0x10); 1181 urtw_write8_m(sc, 0x24d, 0x08); 1182 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1183 1184 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1185 fail: 1186 return (error); 1187 } 1188 1189 static usb_error_t 1190 urtw_adapter_start(struct urtw_softc *sc) 1191 { 1192 struct ieee80211com *ic = &sc->sc_ic; 1193 usb_error_t error; 1194 1195 error = urtw_reset(sc); 1196 if (error) 1197 goto fail; 1198 1199 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1200 urtw_write8_m(sc, URTW_GPIO, 0); 1201 1202 /* for led */ 1203 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1204 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1205 if (error != 0) 1206 goto fail; 1207 1208 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1209 if (error) 1210 goto fail; 1211 /* applying MAC address again. */ 1212 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1213 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1214 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1215 if (error) 1216 goto fail; 1217 1218 error = urtw_update_msr(sc); 1219 if (error) 1220 goto fail; 1221 1222 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1223 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1224 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1225 error = urtw_set_rate(sc); 1226 if (error != 0) 1227 goto fail; 1228 1229 error = sc->sc_rf_init(sc); 1230 if (error != 0) 1231 goto fail; 1232 if (sc->sc_rf_set_sens != NULL) 1233 sc->sc_rf_set_sens(sc, sc->sc_sens); 1234 1235 /* XXX correct? to call write16 */ 1236 urtw_write16_m(sc, URTW_PSR, 1); 1237 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1238 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1239 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1240 /* XXX correct? to call write16 */ 1241 urtw_write16_m(sc, URTW_PSR, 0); 1242 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1243 1244 error = urtw_intr_enable(sc); 1245 if (error != 0) 1246 goto fail; 1247 1248 fail: 1249 return (error); 1250 } 1251 1252 static usb_error_t 1253 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1254 { 1255 uint8_t data; 1256 usb_error_t error; 1257 1258 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1259 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1260 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1261 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1262 fail: 1263 return (error); 1264 } 1265 1266 static usb_error_t 1267 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1268 { 1269 int i; 1270 uint8_t data8; 1271 usb_error_t error; 1272 1273 /* XXX the code can be duplicate with urtw_reset(). */ 1274 urtw_read8_m(sc, URTW_CMD, &data8); 1275 data8 = (data8 & 0x2) | URTW_CMD_RST; 1276 urtw_write8_m(sc, URTW_CMD, data8); 1277 1278 for (i = 0; i < 20; i++) { 1279 usb_pause_mtx(&sc->sc_mtx, 2); 1280 urtw_read8_m(sc, URTW_CMD, &data8); 1281 if (!(data8 & URTW_CMD_RST)) 1282 break; 1283 } 1284 if (i >= 20) { 1285 device_printf(sc->sc_dev, "reset timeout\n"); 1286 goto fail; 1287 } 1288 fail: 1289 return (error); 1290 } 1291 1292 static usb_error_t 1293 urtw_do_request(struct urtw_softc *sc, 1294 struct usb_device_request *req, void *data) 1295 { 1296 usb_error_t err; 1297 int ntries = 10; 1298 1299 URTW_ASSERT_LOCKED(sc); 1300 1301 while (ntries--) { 1302 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1303 req, data, 0, NULL, 250 /* ms */); 1304 if (err == 0) 1305 break; 1306 1307 DPRINTF(sc, URTW_DEBUG_INIT, 1308 "Control request failed, %s (retrying)\n", 1309 usbd_errstr(err)); 1310 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1311 } 1312 return (err); 1313 } 1314 1315 static void 1316 urtw_stop(struct urtw_softc *sc) 1317 { 1318 uint8_t data8; 1319 usb_error_t error; 1320 1321 URTW_ASSERT_LOCKED(sc); 1322 1323 sc->sc_flags &= ~URTW_RUNNING; 1324 1325 error = urtw_intr_disable(sc); 1326 if (error) 1327 goto fail; 1328 urtw_read8_m(sc, URTW_CMD, &data8); 1329 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1330 urtw_write8_m(sc, URTW_CMD, data8); 1331 1332 error = sc->sc_rf_stop(sc); 1333 if (error != 0) 1334 goto fail; 1335 1336 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1337 if (error) 1338 goto fail; 1339 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1340 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1341 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1342 if (error) 1343 goto fail; 1344 fail: 1345 if (error) 1346 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1347 usbd_errstr(error)); 1348 1349 usb_callout_stop(&sc->sc_led_ch); 1350 callout_stop(&sc->sc_watchdog_ch); 1351 1352 urtw_abort_xfers(sc); 1353 } 1354 1355 static void 1356 urtw_abort_xfers(struct urtw_softc *sc) 1357 { 1358 int i, max; 1359 1360 URTW_ASSERT_LOCKED(sc); 1361 1362 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1363 URTW_8187L_N_XFERS; 1364 1365 /* abort any pending transfers */ 1366 for (i = 0; i < max; i++) 1367 usbd_transfer_stop(sc->sc_xfer[i]); 1368 } 1369 1370 static void 1371 urtw_parent(struct ieee80211com *ic) 1372 { 1373 struct urtw_softc *sc = ic->ic_softc; 1374 int startall = 0; 1375 1376 URTW_LOCK(sc); 1377 if (sc->sc_flags & URTW_DETACHED) { 1378 URTW_UNLOCK(sc); 1379 return; 1380 } 1381 1382 if (ic->ic_nrunning > 0) { 1383 if (sc->sc_flags & URTW_RUNNING) { 1384 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1385 urtw_set_multi(sc); 1386 } else { 1387 urtw_init(sc); 1388 startall = 1; 1389 } 1390 } else if (sc->sc_flags & URTW_RUNNING) 1391 urtw_stop(sc); 1392 URTW_UNLOCK(sc); 1393 if (startall) 1394 ieee80211_start_all(ic); 1395 } 1396 1397 static int 1398 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1399 { 1400 struct urtw_softc *sc = ic->ic_softc; 1401 int error; 1402 1403 URTW_LOCK(sc); 1404 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1405 URTW_UNLOCK(sc); 1406 return (ENXIO); 1407 } 1408 error = mbufq_enqueue(&sc->sc_snd, m); 1409 if (error) { 1410 URTW_UNLOCK(sc); 1411 return (error); 1412 } 1413 urtw_start(sc); 1414 URTW_UNLOCK(sc); 1415 1416 return (0); 1417 } 1418 1419 static void 1420 urtw_start(struct urtw_softc *sc) 1421 { 1422 struct urtw_data *bf; 1423 struct ieee80211_node *ni; 1424 struct mbuf *m; 1425 1426 URTW_ASSERT_LOCKED(sc); 1427 1428 if ((sc->sc_flags & URTW_RUNNING) == 0) 1429 return; 1430 1431 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1432 bf = urtw_getbuf(sc); 1433 if (bf == NULL) { 1434 mbufq_prepend(&sc->sc_snd, m); 1435 break; 1436 } 1437 1438 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1439 m->m_pkthdr.rcvif = NULL; 1440 1441 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1442 if_inc_counter(ni->ni_vap->iv_ifp, 1443 IFCOUNTER_OERRORS, 1); 1444 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1445 ieee80211_free_node(ni); 1446 break; 1447 } 1448 1449 sc->sc_txtimer = 5; 1450 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1451 } 1452 } 1453 1454 static int 1455 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1456 int ndata, int maxsz, void *dma_buf) 1457 { 1458 int i, error; 1459 1460 for (i = 0; i < ndata; i++) { 1461 struct urtw_data *dp = &data[i]; 1462 1463 dp->sc = sc; 1464 if (dma_buf == NULL) { 1465 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1466 if (dp->m == NULL) { 1467 device_printf(sc->sc_dev, 1468 "could not allocate rx mbuf\n"); 1469 error = ENOMEM; 1470 goto fail; 1471 } 1472 dp->buf = mtod(dp->m, uint8_t *); 1473 } else { 1474 dp->m = NULL; 1475 dp->buf = ((uint8_t *)dma_buf) + 1476 (i * maxsz); 1477 } 1478 dp->ni = NULL; 1479 } 1480 return (0); 1481 1482 fail: urtw_free_data_list(sc, data, ndata, 1); 1483 return (error); 1484 } 1485 1486 static int 1487 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1488 { 1489 int error, i; 1490 1491 error = urtw_alloc_data_list(sc, 1492 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1493 MCLBYTES, NULL /* mbufs */); 1494 if (error != 0) 1495 return (error); 1496 1497 STAILQ_INIT(&sc->sc_rx_active); 1498 STAILQ_INIT(&sc->sc_rx_inactive); 1499 1500 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1501 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1502 1503 return (0); 1504 } 1505 1506 static int 1507 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1508 { 1509 int error, i; 1510 1511 error = urtw_alloc_data_list(sc, 1512 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1513 sc->sc_tx_dma_buf /* no mbufs */); 1514 if (error != 0) 1515 return (error); 1516 1517 STAILQ_INIT(&sc->sc_tx_active); 1518 STAILQ_INIT(&sc->sc_tx_inactive); 1519 STAILQ_INIT(&sc->sc_tx_pending); 1520 1521 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1522 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1523 next); 1524 1525 return (0); 1526 } 1527 1528 static int 1529 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1530 const struct ieee80211_bpf_params *params) 1531 { 1532 struct ieee80211com *ic = ni->ni_ic; 1533 struct urtw_softc *sc = ic->ic_softc; 1534 struct urtw_data *bf; 1535 1536 /* prevent management frames from being sent if we're not ready */ 1537 if (!(sc->sc_flags & URTW_RUNNING)) { 1538 m_freem(m); 1539 return ENETDOWN; 1540 } 1541 URTW_LOCK(sc); 1542 bf = urtw_getbuf(sc); 1543 if (bf == NULL) { 1544 m_freem(m); 1545 URTW_UNLOCK(sc); 1546 return (ENOBUFS); /* XXX */ 1547 } 1548 1549 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1550 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1551 URTW_UNLOCK(sc); 1552 return (EIO); 1553 } 1554 URTW_UNLOCK(sc); 1555 1556 sc->sc_txtimer = 5; 1557 return (0); 1558 } 1559 1560 static void 1561 urtw_scan_start(struct ieee80211com *ic) 1562 { 1563 1564 /* XXX do nothing? */ 1565 } 1566 1567 static void 1568 urtw_scan_end(struct ieee80211com *ic) 1569 { 1570 1571 /* XXX do nothing? */ 1572 } 1573 1574 static void 1575 urtw_getradiocaps(struct ieee80211com *ic, 1576 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1577 { 1578 uint8_t bands[IEEE80211_MODE_BYTES]; 1579 1580 memset(bands, 0, sizeof(bands)); 1581 setbit(bands, IEEE80211_MODE_11B); 1582 setbit(bands, IEEE80211_MODE_11G); 1583 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1584 } 1585 1586 static void 1587 urtw_set_channel(struct ieee80211com *ic) 1588 { 1589 struct urtw_softc *sc = ic->ic_softc; 1590 uint32_t data, orig; 1591 usb_error_t error; 1592 1593 /* 1594 * if the user set a channel explicitly using ifconfig(8) this function 1595 * can be called earlier than we're expected that in some cases the 1596 * initialization would be failed if setting a channel is called before 1597 * the init have done. 1598 */ 1599 if (!(sc->sc_flags & URTW_RUNNING)) 1600 return; 1601 1602 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1603 return; 1604 1605 URTW_LOCK(sc); 1606 1607 /* 1608 * during changing th channel we need to temporarily be disable 1609 * TX. 1610 */ 1611 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1612 data = orig & ~URTW_TX_LOOPBACK_MASK; 1613 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1614 1615 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1616 if (error != 0) 1617 goto fail; 1618 usb_pause_mtx(&sc->sc_mtx, 10); 1619 urtw_write32_m(sc, URTW_TX_CONF, orig); 1620 1621 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1622 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1623 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1624 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1625 1626 fail: 1627 URTW_UNLOCK(sc); 1628 1629 sc->sc_curchan = ic->ic_curchan; 1630 1631 if (error != 0) 1632 device_printf(sc->sc_dev, "could not change the channel\n"); 1633 } 1634 1635 static void 1636 urtw_update_promisc(struct ieee80211com *ic) 1637 { 1638 struct urtw_softc *sc = ic->ic_softc; 1639 1640 URTW_LOCK(sc); 1641 if (sc->sc_flags & URTW_RUNNING) 1642 urtw_rx_setconf(sc); 1643 URTW_UNLOCK(sc); 1644 } 1645 1646 static void 1647 urtw_update_mcast(struct ieee80211com *ic) 1648 { 1649 1650 /* XXX do nothing? */ 1651 } 1652 1653 static int 1654 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1655 struct urtw_data *data, int prior) 1656 { 1657 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1658 struct ieee80211_key *k; 1659 const struct ieee80211_txparam *tp = ni->ni_txparms; 1660 struct ieee80211com *ic = &sc->sc_ic; 1661 struct ieee80211vap *vap = ni->ni_vap; 1662 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1663 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1664 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1665 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1666 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1667 }; 1668 struct usb_xfer *xfer; 1669 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type, 1670 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast; 1671 uint16_t acktime, rtstime, ctstime; 1672 uint32_t flags; 1673 usb_error_t error; 1674 1675 URTW_ASSERT_LOCKED(sc); 1676 1677 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1678 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1679 1680 /* 1681 * Software crypto. 1682 */ 1683 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1684 k = ieee80211_crypto_encap(ni, m0); 1685 if (k == NULL) { 1686 device_printf(sc->sc_dev, 1687 "ieee80211_crypto_encap returns NULL.\n"); 1688 /* XXX we don't expect the fragmented frames */ 1689 m_freem(m0); 1690 return (ENOBUFS); 1691 } 1692 1693 /* in case packet header moved, reset pointer */ 1694 wh = mtod(m0, struct ieee80211_frame *); 1695 } 1696 1697 if (ieee80211_radiotap_active_vap(vap)) { 1698 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1699 1700 tap->wt_flags = 0; 1701 ieee80211_radiotap_tx(vap, m0); 1702 } 1703 1704 if (type == IEEE80211_FC0_TYPE_MGT || 1705 type == IEEE80211_FC0_TYPE_CTL || 1706 (m0->m_flags & M_EAPOL) != 0) { 1707 rate = tp->mgmtrate; 1708 } else { 1709 /* for data frames */ 1710 if (ismcast) 1711 rate = tp->mcastrate; 1712 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1713 rate = tp->ucastrate; 1714 else 1715 rate = urtw_rtl2rate(sc->sc_currate); 1716 } 1717 1718 sc->sc_stats.txrates[sc->sc_currate]++; 1719 1720 if (ismcast) 1721 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1722 IEEE80211_CRC_LEN, rate, 0, 0); 1723 else { 1724 acktime = urtw_compute_txtime(14, 2,0, 0); 1725 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1726 rtsenable = 1; 1727 ctsenable = 0; 1728 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1729 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1730 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1731 IEEE80211_CRC_LEN, rate, 0, isshort); 1732 rtsdur = ctstime + pkttime + acktime + 1733 3 * URTW_ASIFS_TIME; 1734 txdur = rtstime + rtsdur; 1735 } else { 1736 rtsenable = ctsenable = rtsdur = 0; 1737 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1738 IEEE80211_CRC_LEN, rate, 0, isshort); 1739 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1740 } 1741 1742 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1743 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1744 IEEE80211_CRC_LEN, rate, 0, isshort) + 1745 3 * URTW_ASIFS_TIME + 1746 2 * acktime; 1747 else 1748 dur = URTW_ASIFS_TIME + acktime; 1749 } 1750 USETW(wh->i_dur, dur); 1751 1752 xferlen = m0->m_pkthdr.len; 1753 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1754 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1755 xferlen += 1; 1756 1757 memset(data->buf, 0, URTW_TX_MAXSIZE); 1758 flags = m0->m_pkthdr.len & 0xfff; 1759 flags |= URTW_TX_FLAG_NO_ENC; 1760 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1761 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1762 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1763 (sc->sc_currate != 0)) 1764 flags |= URTW_TX_FLAG_SPLCP; 1765 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1766 flags |= URTW_TX_FLAG_MOREFRAG; 1767 1768 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1769 1770 if (sc->sc_flags & URTW_RTL8187B) { 1771 struct urtw_8187b_txhdr *tx; 1772 1773 tx = (struct urtw_8187b_txhdr *)data->buf; 1774 if (ctsenable) 1775 flags |= URTW_TX_FLAG_CTS; 1776 if (rtsenable) { 1777 flags |= URTW_TX_FLAG_RTS; 1778 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1779 tx->rtsdur = rtsdur; 1780 } 1781 tx->flag = htole32(flags); 1782 tx->txdur = txdur; 1783 if (type == IEEE80211_FC0_TYPE_MGT && 1784 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1785 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1786 tx->retry = 1; 1787 else 1788 tx->retry = URTW_TX_MAXRETRY; 1789 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1790 } else { 1791 struct urtw_8187l_txhdr *tx; 1792 1793 tx = (struct urtw_8187l_txhdr *)data->buf; 1794 if (rtsenable) { 1795 flags |= URTW_TX_FLAG_RTS; 1796 tx->rtsdur = rtsdur; 1797 } 1798 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1799 tx->flag = htole32(flags); 1800 tx->retry = 3; /* CW minimum */ 1801 tx->retry |= 7 << 4; /* CW maximum */ 1802 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1803 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1804 } 1805 1806 data->buflen = xferlen; 1807 data->ni = ni; 1808 data->m = m0; 1809 1810 if (sc->sc_flags & URTW_RTL8187B) { 1811 switch (type) { 1812 case IEEE80211_FC0_TYPE_CTL: 1813 case IEEE80211_FC0_TYPE_MGT: 1814 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1815 break; 1816 default: 1817 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1818 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1819 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1820 break; 1821 } 1822 } else 1823 xfer = (prior == URTW_PRIORITY_LOW) ? 1824 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1825 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1826 1827 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1828 usbd_transfer_start(xfer); 1829 1830 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1831 if (error != 0) 1832 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1833 error); 1834 return (0); 1835 } 1836 1837 static int 1838 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1839 { 1840 struct ieee80211com *ic = vap->iv_ic; 1841 struct urtw_softc *sc = ic->ic_softc; 1842 struct urtw_vap *uvp = URTW_VAP(vap); 1843 struct ieee80211_node *ni; 1844 usb_error_t error = 0; 1845 1846 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1847 ieee80211_state_name[vap->iv_state], 1848 ieee80211_state_name[nstate]); 1849 1850 sc->sc_state = nstate; 1851 1852 IEEE80211_UNLOCK(ic); 1853 URTW_LOCK(sc); 1854 usb_callout_stop(&sc->sc_led_ch); 1855 callout_stop(&sc->sc_watchdog_ch); 1856 1857 switch (nstate) { 1858 case IEEE80211_S_INIT: 1859 case IEEE80211_S_SCAN: 1860 case IEEE80211_S_AUTH: 1861 case IEEE80211_S_ASSOC: 1862 break; 1863 case IEEE80211_S_RUN: 1864 ni = ieee80211_ref_node(vap->iv_bss); 1865 /* setting bssid. */ 1866 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1867 urtw_write16_m(sc, URTW_BSSID + 4, 1868 ((uint16_t *)ni->ni_bssid)[2]); 1869 urtw_update_msr(sc); 1870 /* XXX maybe the below would be incorrect. */ 1871 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1872 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1873 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1874 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1875 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1876 if (error != 0) 1877 device_printf(sc->sc_dev, 1878 "could not control LED (%d)\n", error); 1879 ieee80211_free_node(ni); 1880 break; 1881 default: 1882 break; 1883 } 1884 fail: 1885 URTW_UNLOCK(sc); 1886 IEEE80211_LOCK(ic); 1887 return (uvp->newstate(vap, nstate, arg)); 1888 } 1889 1890 static void 1891 urtw_watchdog(void *arg) 1892 { 1893 struct urtw_softc *sc = arg; 1894 1895 if (sc->sc_txtimer > 0) { 1896 if (--sc->sc_txtimer == 0) { 1897 device_printf(sc->sc_dev, "device timeout\n"); 1898 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1899 return; 1900 } 1901 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1902 } 1903 } 1904 1905 static void 1906 urtw_set_multi(void *arg) 1907 { 1908 /* XXX don't know how to set a device. Lack of docs. */ 1909 } 1910 1911 static usb_error_t 1912 urtw_set_rate(struct urtw_softc *sc) 1913 { 1914 int i, basic_rate, min_rr_rate, max_rr_rate; 1915 uint16_t data; 1916 usb_error_t error; 1917 1918 basic_rate = URTW_RIDX_OFDM24; 1919 min_rr_rate = URTW_RIDX_OFDM6; 1920 max_rr_rate = URTW_RIDX_OFDM24; 1921 1922 urtw_write8_m(sc, URTW_RESP_RATE, 1923 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1924 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1925 1926 urtw_read16_m(sc, URTW_BRSR, &data); 1927 data &= ~URTW_BRSR_MBR_8185; 1928 1929 for (i = 0; i <= basic_rate; i++) 1930 data |= (1 << i); 1931 1932 urtw_write16_m(sc, URTW_BRSR, data); 1933 fail: 1934 return (error); 1935 } 1936 1937 static uint16_t 1938 urtw_rtl2rate(uint32_t rate) 1939 { 1940 unsigned int i; 1941 1942 for (i = 0; i < nitems(urtw_ratetable); i++) { 1943 if (rate == urtw_ratetable[i].val) 1944 return urtw_ratetable[i].reg; 1945 } 1946 1947 return (0); 1948 } 1949 1950 static usb_error_t 1951 urtw_update_msr(struct urtw_softc *sc) 1952 { 1953 struct ieee80211com *ic = &sc->sc_ic; 1954 uint8_t data; 1955 usb_error_t error; 1956 1957 urtw_read8_m(sc, URTW_MSR, &data); 1958 data &= ~URTW_MSR_LINK_MASK; 1959 1960 if (sc->sc_state == IEEE80211_S_RUN) { 1961 switch (ic->ic_opmode) { 1962 case IEEE80211_M_STA: 1963 case IEEE80211_M_MONITOR: 1964 data |= URTW_MSR_LINK_STA; 1965 if (sc->sc_flags & URTW_RTL8187B) 1966 data |= URTW_MSR_LINK_ENEDCA; 1967 break; 1968 case IEEE80211_M_IBSS: 1969 data |= URTW_MSR_LINK_ADHOC; 1970 break; 1971 case IEEE80211_M_HOSTAP: 1972 data |= URTW_MSR_LINK_HOSTAP; 1973 break; 1974 default: 1975 DPRINTF(sc, URTW_DEBUG_STATE, 1976 "unsupported operation mode 0x%x\n", 1977 ic->ic_opmode); 1978 error = USB_ERR_INVAL; 1979 goto fail; 1980 } 1981 } else 1982 data |= URTW_MSR_LINK_NONE; 1983 1984 urtw_write8_m(sc, URTW_MSR, data); 1985 fail: 1986 return (error); 1987 } 1988 1989 static usb_error_t 1990 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1991 { 1992 struct usb_device_request req; 1993 usb_error_t error; 1994 1995 URTW_ASSERT_LOCKED(sc); 1996 1997 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1998 req.bRequest = URTW_8187_GETREGS_REQ; 1999 USETW(req.wValue, (val & 0xff) | 0xff00); 2000 USETW(req.wIndex, (val >> 8) & 0x3); 2001 USETW(req.wLength, sizeof(uint8_t)); 2002 2003 error = urtw_do_request(sc, &req, data); 2004 return (error); 2005 } 2006 2007 static usb_error_t 2008 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2009 { 2010 struct usb_device_request req; 2011 usb_error_t error; 2012 2013 URTW_ASSERT_LOCKED(sc); 2014 2015 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2016 req.bRequest = URTW_8187_GETREGS_REQ; 2017 USETW(req.wValue, (val & 0xff) | 0xff00); 2018 USETW(req.wIndex, (val >> 8) & 0x3); 2019 USETW(req.wLength, sizeof(uint16_t)); 2020 2021 error = urtw_do_request(sc, &req, data); 2022 return (error); 2023 } 2024 2025 static usb_error_t 2026 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2027 { 2028 struct usb_device_request req; 2029 usb_error_t error; 2030 2031 URTW_ASSERT_LOCKED(sc); 2032 2033 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2034 req.bRequest = URTW_8187_GETREGS_REQ; 2035 USETW(req.wValue, (val & 0xff) | 0xff00); 2036 USETW(req.wIndex, (val >> 8) & 0x3); 2037 USETW(req.wLength, sizeof(uint32_t)); 2038 2039 error = urtw_do_request(sc, &req, data); 2040 return (error); 2041 } 2042 2043 static usb_error_t 2044 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2045 { 2046 struct usb_device_request req; 2047 2048 URTW_ASSERT_LOCKED(sc); 2049 2050 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2051 req.bRequest = URTW_8187_SETREGS_REQ; 2052 USETW(req.wValue, (val & 0xff) | 0xff00); 2053 USETW(req.wIndex, (val >> 8) & 0x3); 2054 USETW(req.wLength, sizeof(uint8_t)); 2055 2056 return (urtw_do_request(sc, &req, &data)); 2057 } 2058 2059 static usb_error_t 2060 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2061 { 2062 struct usb_device_request req; 2063 2064 URTW_ASSERT_LOCKED(sc); 2065 2066 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2067 req.bRequest = URTW_8187_SETREGS_REQ; 2068 USETW(req.wValue, (val & 0xff) | 0xff00); 2069 USETW(req.wIndex, (val >> 8) & 0x3); 2070 USETW(req.wLength, sizeof(uint16_t)); 2071 2072 return (urtw_do_request(sc, &req, &data)); 2073 } 2074 2075 static usb_error_t 2076 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2077 { 2078 struct usb_device_request req; 2079 2080 URTW_ASSERT_LOCKED(sc); 2081 2082 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2083 req.bRequest = URTW_8187_SETREGS_REQ; 2084 USETW(req.wValue, (val & 0xff) | 0xff00); 2085 USETW(req.wIndex, (val >> 8) & 0x3); 2086 USETW(req.wLength, sizeof(uint32_t)); 2087 2088 return (urtw_do_request(sc, &req, &data)); 2089 } 2090 2091 static usb_error_t 2092 urtw_get_macaddr(struct urtw_softc *sc) 2093 { 2094 struct ieee80211com *ic = &sc->sc_ic; 2095 uint32_t data; 2096 usb_error_t error; 2097 2098 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2099 if (error != 0) 2100 goto fail; 2101 ic->ic_macaddr[0] = data & 0xff; 2102 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2103 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2104 if (error != 0) 2105 goto fail; 2106 ic->ic_macaddr[2] = data & 0xff; 2107 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2108 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2109 if (error != 0) 2110 goto fail; 2111 ic->ic_macaddr[4] = data & 0xff; 2112 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2113 fail: 2114 return (error); 2115 } 2116 2117 static usb_error_t 2118 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2119 { 2120 #define URTW_READCMD_LEN 3 2121 int addrlen, i; 2122 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2123 usb_error_t error; 2124 2125 /* NB: make sure the buffer is initialized */ 2126 *data = 0; 2127 2128 /* enable EPROM programming */ 2129 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2130 DELAY(URTW_EPROM_DELAY); 2131 2132 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2133 if (error != 0) 2134 goto fail; 2135 error = urtw_eprom_ck(sc); 2136 if (error != 0) 2137 goto fail; 2138 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2139 if (error != 0) 2140 goto fail; 2141 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2142 addrlen = 8; 2143 addrstr[0] = addr & (1 << 7); 2144 addrstr[1] = addr & (1 << 6); 2145 addrstr[2] = addr & (1 << 5); 2146 addrstr[3] = addr & (1 << 4); 2147 addrstr[4] = addr & (1 << 3); 2148 addrstr[5] = addr & (1 << 2); 2149 addrstr[6] = addr & (1 << 1); 2150 addrstr[7] = addr & (1 << 0); 2151 } else { 2152 addrlen=6; 2153 addrstr[0] = addr & (1 << 5); 2154 addrstr[1] = addr & (1 << 4); 2155 addrstr[2] = addr & (1 << 3); 2156 addrstr[3] = addr & (1 << 2); 2157 addrstr[4] = addr & (1 << 1); 2158 addrstr[5] = addr & (1 << 0); 2159 } 2160 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2161 if (error != 0) 2162 goto fail; 2163 2164 error = urtw_eprom_writebit(sc, 0); 2165 if (error != 0) 2166 goto fail; 2167 2168 for (i = 0; i < 16; i++) { 2169 error = urtw_eprom_ck(sc); 2170 if (error != 0) 2171 goto fail; 2172 error = urtw_eprom_readbit(sc, &data16); 2173 if (error != 0) 2174 goto fail; 2175 2176 (*data) |= (data16 << (15 - i)); 2177 } 2178 2179 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2180 if (error != 0) 2181 goto fail; 2182 error = urtw_eprom_ck(sc); 2183 if (error != 0) 2184 goto fail; 2185 2186 /* now disable EPROM programming */ 2187 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2188 fail: 2189 return (error); 2190 #undef URTW_READCMD_LEN 2191 } 2192 2193 static usb_error_t 2194 urtw_eprom_cs(struct urtw_softc *sc, int able) 2195 { 2196 uint8_t data; 2197 usb_error_t error; 2198 2199 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2200 if (able == URTW_EPROM_ENABLE) 2201 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2202 else 2203 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2204 DELAY(URTW_EPROM_DELAY); 2205 fail: 2206 return (error); 2207 } 2208 2209 static usb_error_t 2210 urtw_eprom_ck(struct urtw_softc *sc) 2211 { 2212 uint8_t data; 2213 usb_error_t error; 2214 2215 /* masking */ 2216 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2217 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2218 DELAY(URTW_EPROM_DELAY); 2219 /* unmasking */ 2220 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2221 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2222 DELAY(URTW_EPROM_DELAY); 2223 fail: 2224 return (error); 2225 } 2226 2227 static usb_error_t 2228 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2229 { 2230 uint8_t data8; 2231 usb_error_t error; 2232 2233 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2234 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2235 DELAY(URTW_EPROM_DELAY); 2236 2237 fail: 2238 return (error); 2239 } 2240 2241 static usb_error_t 2242 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2243 { 2244 uint8_t data; 2245 usb_error_t error; 2246 2247 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2248 if (bit != 0) 2249 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2250 else 2251 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2252 DELAY(URTW_EPROM_DELAY); 2253 fail: 2254 return (error); 2255 } 2256 2257 static usb_error_t 2258 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2259 { 2260 int i = 0; 2261 usb_error_t error = 0; 2262 2263 for (i = 0; i < buflen; i++) { 2264 error = urtw_eprom_writebit(sc, buf[i]); 2265 if (error != 0) 2266 goto fail; 2267 error = urtw_eprom_ck(sc); 2268 if (error != 0) 2269 goto fail; 2270 } 2271 fail: 2272 return (error); 2273 } 2274 2275 2276 static usb_error_t 2277 urtw_get_txpwr(struct urtw_softc *sc) 2278 { 2279 int i, j; 2280 uint32_t data; 2281 usb_error_t error; 2282 2283 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2284 if (error != 0) 2285 goto fail; 2286 sc->sc_txpwr_cck_base = data & 0xf; 2287 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2288 2289 for (i = 1, j = 0; i < 6; i += 2, j++) { 2290 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2291 if (error != 0) 2292 goto fail; 2293 sc->sc_txpwr_cck[i] = data & 0xf; 2294 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2295 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2296 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2297 } 2298 for (i = 1, j = 0; i < 4; i += 2, j++) { 2299 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2300 if (error != 0) 2301 goto fail; 2302 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2303 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2304 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2305 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2306 } 2307 if (sc->sc_flags & URTW_RTL8187B) { 2308 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2309 if (error != 0) 2310 goto fail; 2311 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2312 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2313 error = urtw_eprom_read32(sc, 0x0a, &data); 2314 if (error != 0) 2315 goto fail; 2316 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2317 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2318 error = urtw_eprom_read32(sc, 0x1c, &data); 2319 if (error != 0) 2320 goto fail; 2321 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2322 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2323 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2324 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2325 } else { 2326 for (i = 1, j = 0; i < 4; i += 2, j++) { 2327 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2328 &data); 2329 if (error != 0) 2330 goto fail; 2331 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2332 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2333 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2334 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2335 } 2336 } 2337 fail: 2338 return (error); 2339 } 2340 2341 2342 static usb_error_t 2343 urtw_get_rfchip(struct urtw_softc *sc) 2344 { 2345 int ret; 2346 uint8_t data8; 2347 uint32_t data; 2348 usb_error_t error; 2349 2350 if (sc->sc_flags & URTW_RTL8187B) { 2351 urtw_read8_m(sc, 0xe1, &data8); 2352 switch (data8) { 2353 case 0: 2354 sc->sc_flags |= URTW_RTL8187B_REV_B; 2355 break; 2356 case 1: 2357 sc->sc_flags |= URTW_RTL8187B_REV_D; 2358 break; 2359 case 2: 2360 sc->sc_flags |= URTW_RTL8187B_REV_E; 2361 break; 2362 default: 2363 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2364 sc->sc_flags |= URTW_RTL8187B_REV_B; 2365 break; 2366 } 2367 } else { 2368 urtw_read32_m(sc, URTW_TX_CONF, &data); 2369 switch (data & URTW_TX_HWMASK) { 2370 case URTW_TX_R8187vD_B: 2371 sc->sc_flags |= URTW_RTL8187B; 2372 break; 2373 case URTW_TX_R8187vD: 2374 break; 2375 default: 2376 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2377 data & URTW_TX_HWMASK); 2378 break; 2379 } 2380 } 2381 2382 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2383 if (error != 0) 2384 goto fail; 2385 switch (data & 0xff) { 2386 case URTW_EPROM_RFCHIPID_RTL8225U: 2387 error = urtw_8225_isv2(sc, &ret); 2388 if (error != 0) 2389 goto fail; 2390 if (ret == 0) { 2391 sc->sc_rf_init = urtw_8225_rf_init; 2392 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2393 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2394 sc->sc_rf_stop = urtw_8225_rf_stop; 2395 } else { 2396 sc->sc_rf_init = urtw_8225v2_rf_init; 2397 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2398 sc->sc_rf_stop = urtw_8225_rf_stop; 2399 } 2400 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2401 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2402 break; 2403 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2404 sc->sc_rf_init = urtw_8225v2b_rf_init; 2405 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2406 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2407 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2408 sc->sc_rf_stop = urtw_8225_rf_stop; 2409 break; 2410 default: 2411 DPRINTF(sc, URTW_DEBUG_STATE, 2412 "unsupported RF chip %d\n", data & 0xff); 2413 error = USB_ERR_INVAL; 2414 goto fail; 2415 } 2416 2417 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2418 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2419 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2420 "rtl8225z2", 2421 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2422 (data8 == 1) ? "d" : "e") : "none"); 2423 2424 fail: 2425 return (error); 2426 } 2427 2428 2429 static usb_error_t 2430 urtw_led_init(struct urtw_softc *sc) 2431 { 2432 uint32_t rev; 2433 usb_error_t error; 2434 2435 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2436 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2437 if (error != 0) 2438 goto fail; 2439 2440 switch (rev & URTW_EPROM_CID_MASK) { 2441 case URTW_EPROM_CID_ALPHA0: 2442 sc->sc_strategy = URTW_SW_LED_MODE1; 2443 break; 2444 case URTW_EPROM_CID_SERCOMM_PS: 2445 sc->sc_strategy = URTW_SW_LED_MODE3; 2446 break; 2447 case URTW_EPROM_CID_HW_LED: 2448 sc->sc_strategy = URTW_HW_LED; 2449 break; 2450 case URTW_EPROM_CID_RSVD0: 2451 case URTW_EPROM_CID_RSVD1: 2452 default: 2453 sc->sc_strategy = URTW_SW_LED_MODE0; 2454 break; 2455 } 2456 2457 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2458 2459 fail: 2460 return (error); 2461 } 2462 2463 2464 static usb_error_t 2465 urtw_8225_rf_init(struct urtw_softc *sc) 2466 { 2467 unsigned int i; 2468 uint16_t data; 2469 usb_error_t error; 2470 2471 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2472 if (error) 2473 goto fail; 2474 2475 error = urtw_8225_usb_init(sc); 2476 if (error) 2477 goto fail; 2478 2479 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2480 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2481 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2482 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2483 2484 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2485 if (error) 2486 goto fail; 2487 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2488 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2489 if (error) 2490 goto fail; 2491 2492 error = urtw_8185_rf_pins_enable(sc); 2493 if (error) 2494 goto fail; 2495 usb_pause_mtx(&sc->sc_mtx, 1000); 2496 2497 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2498 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2499 urtw_8225_rf_part1[i].val); 2500 usb_pause_mtx(&sc->sc_mtx, 1); 2501 } 2502 usb_pause_mtx(&sc->sc_mtx, 100); 2503 urtw_8225_write(sc, 2504 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2505 usb_pause_mtx(&sc->sc_mtx, 200); 2506 urtw_8225_write(sc, 2507 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2508 usb_pause_mtx(&sc->sc_mtx, 200); 2509 urtw_8225_write(sc, 2510 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2511 2512 for (i = 0; i < 95; i++) { 2513 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2514 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2515 } 2516 2517 urtw_8225_write(sc, 2518 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2519 urtw_8225_write(sc, 2520 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2521 2522 for (i = 0; i < 128; i++) { 2523 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2524 usb_pause_mtx(&sc->sc_mtx, 1); 2525 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2526 usb_pause_mtx(&sc->sc_mtx, 1); 2527 } 2528 2529 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2530 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2531 urtw_8225_rf_part2[i].val); 2532 usb_pause_mtx(&sc->sc_mtx, 1); 2533 } 2534 2535 error = urtw_8225_setgain(sc, 4); 2536 if (error) 2537 goto fail; 2538 2539 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2540 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2541 urtw_8225_rf_part3[i].val); 2542 usb_pause_mtx(&sc->sc_mtx, 1); 2543 } 2544 2545 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2546 2547 error = urtw_8225_set_txpwrlvl(sc, 1); 2548 if (error) 2549 goto fail; 2550 2551 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2552 usb_pause_mtx(&sc->sc_mtx, 1); 2553 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2554 usb_pause_mtx(&sc->sc_mtx, 1); 2555 2556 /* TX ant A, 0x0 for B */ 2557 error = urtw_8185_tx_antenna(sc, 0x3); 2558 if (error) 2559 goto fail; 2560 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2561 2562 error = urtw_8225_rf_set_chan(sc, 1); 2563 fail: 2564 return (error); 2565 } 2566 2567 static usb_error_t 2568 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2569 { 2570 usb_error_t error = 0; 2571 2572 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2573 fail: 2574 return (error); 2575 } 2576 2577 static usb_error_t 2578 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2579 { 2580 usb_error_t error; 2581 2582 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2583 usb_pause_mtx(&sc->sc_mtx, 1); 2584 fail: 2585 return (error); 2586 } 2587 2588 static usb_error_t 2589 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2590 { 2591 2592 data = data & 0xff; 2593 return urtw_8187_write_phy(sc, addr, data); 2594 } 2595 2596 static usb_error_t 2597 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2598 { 2599 2600 data = data & 0xff; 2601 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2602 } 2603 2604 static usb_error_t 2605 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2606 { 2607 uint32_t phyw; 2608 usb_error_t error; 2609 2610 phyw = ((data << 8) | (addr | 0x80)); 2611 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2612 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2613 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2614 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2615 usb_pause_mtx(&sc->sc_mtx, 1); 2616 fail: 2617 return (error); 2618 } 2619 2620 static usb_error_t 2621 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2622 { 2623 usb_error_t error; 2624 2625 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2626 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2627 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2628 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2629 fail: 2630 return (error); 2631 } 2632 2633 static usb_error_t 2634 urtw_8225_usb_init(struct urtw_softc *sc) 2635 { 2636 uint8_t data; 2637 usb_error_t error; 2638 2639 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2640 urtw_write8_m(sc, URTW_GPIO, 0); 2641 error = urtw_read8e(sc, 0x53, &data); 2642 if (error) 2643 goto fail; 2644 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2645 if (error) 2646 goto fail; 2647 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2648 urtw_write8_m(sc, URTW_GPIO, 0x20); 2649 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2650 2651 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2652 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2653 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2654 2655 usb_pause_mtx(&sc->sc_mtx, 500); 2656 fail: 2657 return (error); 2658 } 2659 2660 static usb_error_t 2661 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2662 { 2663 uint16_t d80, d82, d84; 2664 usb_error_t error; 2665 2666 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2667 d80 &= URTW_RF_PINS_MAGIC1; 2668 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2669 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2670 d84 &= URTW_RF_PINS_MAGIC2; 2671 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2672 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2673 DELAY(10); 2674 2675 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2676 DELAY(2); 2677 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2678 DELAY(10); 2679 2680 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2681 if (error != 0) 2682 goto fail; 2683 2684 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2685 DELAY(10); 2686 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2687 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2688 usb_pause_mtx(&sc->sc_mtx, 2); 2689 fail: 2690 return (error); 2691 } 2692 2693 static usb_error_t 2694 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2695 uint16_t *data) 2696 { 2697 uint8_t buf[2]; 2698 uint16_t data16; 2699 struct usb_device_request req; 2700 usb_error_t error = 0; 2701 2702 data16 = *data; 2703 2704 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2705 req.bRequest = URTW_8187_SETREGS_REQ; 2706 USETW(req.wValue, addr); 2707 USETW(req.wIndex, index); 2708 USETW(req.wLength, sizeof(uint16_t)); 2709 buf[0] = (data16 & 0x00ff); 2710 buf[1] = (data16 & 0xff00) >> 8; 2711 2712 error = urtw_do_request(sc, &req, buf); 2713 2714 return (error); 2715 } 2716 2717 static usb_error_t 2718 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2719 { 2720 usb_error_t error; 2721 2722 error = urtw_8225_set_txpwrlvl(sc, chan); 2723 if (error) 2724 goto fail; 2725 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2726 usb_pause_mtx(&sc->sc_mtx, 10); 2727 fail: 2728 return (error); 2729 } 2730 2731 static usb_error_t 2732 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2733 { 2734 usb_error_t error; 2735 2736 if (sens < 0 || sens > 6) 2737 return -1; 2738 2739 if (sens > 4) 2740 urtw_8225_write(sc, 2741 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2742 else 2743 urtw_8225_write(sc, 2744 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2745 2746 sens = 6 - sens; 2747 error = urtw_8225_setgain(sc, sens); 2748 if (error) 2749 goto fail; 2750 2751 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2752 2753 fail: 2754 return (error); 2755 } 2756 2757 static usb_error_t 2758 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2759 { 2760 int i, idx, set; 2761 uint8_t *cck_pwltable; 2762 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2763 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2764 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2765 usb_error_t error; 2766 2767 cck_pwrlvl_max = 11; 2768 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2769 ofdm_pwrlvl_min = 10; 2770 2771 /* CCK power setting */ 2772 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2773 idx = cck_pwrlvl % 6; 2774 set = cck_pwrlvl / 6; 2775 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2776 urtw_8225_txpwr_cck; 2777 2778 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2779 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2780 for (i = 0; i < 8; i++) { 2781 urtw_8187_write_phy_cck(sc, 0x44 + i, 2782 cck_pwltable[idx * 8 + i]); 2783 } 2784 usb_pause_mtx(&sc->sc_mtx, 1); 2785 2786 /* OFDM power setting */ 2787 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2788 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2789 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2790 2791 idx = ofdm_pwrlvl % 6; 2792 set = ofdm_pwrlvl / 6; 2793 2794 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2795 if (error) 2796 goto fail; 2797 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2798 urtw_8187_write_phy_ofdm(sc, 6, 0); 2799 urtw_8187_write_phy_ofdm(sc, 8, 0); 2800 2801 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2802 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2803 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2804 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2805 usb_pause_mtx(&sc->sc_mtx, 1); 2806 fail: 2807 return (error); 2808 } 2809 2810 2811 static usb_error_t 2812 urtw_8225_rf_stop(struct urtw_softc *sc) 2813 { 2814 uint8_t data; 2815 usb_error_t error; 2816 2817 urtw_8225_write(sc, 0x4, 0x1f); 2818 2819 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2820 if (error) 2821 goto fail; 2822 2823 urtw_read8_m(sc, URTW_CONFIG3, &data); 2824 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2825 if (sc->sc_flags & URTW_RTL8187B) { 2826 urtw_write32_m(sc, URTW_ANAPARAM2, 2827 URTW_8187B_8225_ANAPARAM2_OFF); 2828 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2829 urtw_write32_m(sc, URTW_ANAPARAM3, 2830 URTW_8187B_8225_ANAPARAM3_OFF); 2831 } else { 2832 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2833 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2834 } 2835 2836 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2837 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2838 if (error) 2839 goto fail; 2840 2841 fail: 2842 return (error); 2843 } 2844 2845 static usb_error_t 2846 urtw_8225v2_rf_init(struct urtw_softc *sc) 2847 { 2848 unsigned int i; 2849 uint16_t data; 2850 uint32_t data32; 2851 usb_error_t error; 2852 2853 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2854 if (error) 2855 goto fail; 2856 2857 error = urtw_8225_usb_init(sc); 2858 if (error) 2859 goto fail; 2860 2861 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2862 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2863 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2864 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2865 2866 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2867 if (error) 2868 goto fail; 2869 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2870 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2871 if (error) 2872 goto fail; 2873 2874 error = urtw_8185_rf_pins_enable(sc); 2875 if (error) 2876 goto fail; 2877 2878 usb_pause_mtx(&sc->sc_mtx, 500); 2879 2880 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2881 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2882 urtw_8225v2_rf_part1[i].val); 2883 } 2884 usb_pause_mtx(&sc->sc_mtx, 50); 2885 2886 urtw_8225_write(sc, 2887 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2888 2889 for (i = 0; i < 95; i++) { 2890 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2891 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2892 urtw_8225v2_rxgain[i]); 2893 } 2894 2895 urtw_8225_write(sc, 2896 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2897 urtw_8225_write(sc, 2898 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2899 urtw_8225_write(sc, 2900 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2901 urtw_8225_write(sc, 2902 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2903 usb_pause_mtx(&sc->sc_mtx, 100); 2904 urtw_8225_write(sc, 2905 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2906 usb_pause_mtx(&sc->sc_mtx, 100); 2907 2908 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2909 if (error != 0) 2910 goto fail; 2911 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2912 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2913 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2914 urtw_8225_write(sc, 2915 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2916 usb_pause_mtx(&sc->sc_mtx, 100); 2917 urtw_8225_write(sc, 2918 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2919 usb_pause_mtx(&sc->sc_mtx, 50); 2920 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2921 if (error != 0) 2922 goto fail; 2923 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2924 device_printf(sc->sc_dev, "RF calibration failed\n"); 2925 } 2926 usb_pause_mtx(&sc->sc_mtx, 100); 2927 2928 urtw_8225_write(sc, 2929 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2930 for (i = 0; i < 128; i++) { 2931 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2932 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2933 } 2934 2935 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2936 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2937 urtw_8225v2_rf_part2[i].val); 2938 } 2939 2940 error = urtw_8225v2_setgain(sc, 4); 2941 if (error) 2942 goto fail; 2943 2944 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2945 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2946 urtw_8225v2_rf_part3[i].val); 2947 } 2948 2949 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2950 2951 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2952 if (error) 2953 goto fail; 2954 2955 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2956 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2957 2958 /* TX ant A, 0x0 for B */ 2959 error = urtw_8185_tx_antenna(sc, 0x3); 2960 if (error) 2961 goto fail; 2962 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2963 2964 error = urtw_8225_rf_set_chan(sc, 1); 2965 fail: 2966 return (error); 2967 } 2968 2969 static usb_error_t 2970 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2971 { 2972 usb_error_t error; 2973 2974 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2975 if (error) 2976 goto fail; 2977 2978 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2979 usb_pause_mtx(&sc->sc_mtx, 10); 2980 fail: 2981 return (error); 2982 } 2983 2984 static usb_error_t 2985 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2986 { 2987 int i; 2988 int16_t bit; 2989 uint8_t rlen = 12, wlen = 6; 2990 uint16_t o1, o2, o3, tmp; 2991 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2992 uint32_t mask = 0x80000000, value = 0; 2993 usb_error_t error; 2994 2995 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 2996 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 2997 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 2998 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 2999 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3000 o1 &= ~URTW_RF_PINS_MAGIC4; 3001 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3002 DELAY(5); 3003 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3004 DELAY(5); 3005 3006 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3007 bit = ((d2w & mask) != 0) ? 1 : 0; 3008 3009 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3010 DELAY(2); 3011 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3012 URTW_BB_HOST_BANG_CLK); 3013 DELAY(2); 3014 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3015 URTW_BB_HOST_BANG_CLK); 3016 DELAY(2); 3017 mask = mask >> 1; 3018 if (i == 2) 3019 break; 3020 bit = ((d2w & mask) != 0) ? 1 : 0; 3021 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3022 URTW_BB_HOST_BANG_CLK); 3023 DELAY(2); 3024 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3025 URTW_BB_HOST_BANG_CLK); 3026 DELAY(2); 3027 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3028 DELAY(1); 3029 } 3030 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3031 URTW_BB_HOST_BANG_CLK); 3032 DELAY(2); 3033 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3034 DELAY(2); 3035 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3036 DELAY(2); 3037 3038 mask = 0x800; 3039 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3040 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3041 o1 | URTW_BB_HOST_BANG_RW); 3042 DELAY(2); 3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3044 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3045 DELAY(2); 3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3047 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3048 DELAY(2); 3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3050 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3051 DELAY(2); 3052 3053 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3054 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3055 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3056 o1 | URTW_BB_HOST_BANG_RW); 3057 DELAY(2); 3058 } 3059 3060 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3061 URTW_BB_HOST_BANG_RW); 3062 DELAY(2); 3063 3064 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3065 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3066 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3067 3068 if (data != NULL) 3069 *data = value; 3070 fail: 3071 return (error); 3072 } 3073 3074 3075 static usb_error_t 3076 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3077 { 3078 int i; 3079 uint8_t *cck_pwrtable; 3080 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3081 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3082 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3083 usb_error_t error; 3084 3085 /* CCK power setting */ 3086 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3087 cck_pwrlvl += sc->sc_txpwr_cck_base; 3088 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3089 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3090 urtw_8225v2_txpwr_cck; 3091 3092 for (i = 0; i < 8; i++) 3093 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3094 3095 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3096 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3097 usb_pause_mtx(&sc->sc_mtx, 1); 3098 3099 /* OFDM power setting */ 3100 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3101 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3102 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3103 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3104 3105 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3106 if (error) 3107 goto fail; 3108 3109 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3110 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3111 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3112 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3113 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3114 3115 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3116 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3117 usb_pause_mtx(&sc->sc_mtx, 1); 3118 fail: 3119 return (error); 3120 } 3121 3122 static usb_error_t 3123 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3124 { 3125 uint8_t *gainp; 3126 usb_error_t error; 3127 3128 /* XXX for A? */ 3129 gainp = urtw_8225v2_gain_bg; 3130 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3131 usb_pause_mtx(&sc->sc_mtx, 1); 3132 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3133 usb_pause_mtx(&sc->sc_mtx, 1); 3134 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3135 usb_pause_mtx(&sc->sc_mtx, 1); 3136 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3137 usb_pause_mtx(&sc->sc_mtx, 1); 3138 fail: 3139 return (error); 3140 } 3141 3142 static usb_error_t 3143 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3144 { 3145 uint32_t data; 3146 usb_error_t error; 3147 3148 *ret = 1; 3149 3150 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3151 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3152 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3153 usb_pause_mtx(&sc->sc_mtx, 500); 3154 3155 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3156 URTW_8225_ADDR_0_DATA_MAGIC1); 3157 3158 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3159 if (error != 0) 3160 goto fail; 3161 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3162 *ret = 0; 3163 else { 3164 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3165 if (error != 0) 3166 goto fail; 3167 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3168 *ret = 0; 3169 } 3170 3171 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3172 URTW_8225_ADDR_0_DATA_MAGIC2); 3173 fail: 3174 return (error); 3175 } 3176 3177 static usb_error_t 3178 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3179 { 3180 struct ieee80211com *ic = &sc->sc_ic; 3181 unsigned int i; 3182 uint8_t data8; 3183 usb_error_t error; 3184 3185 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3186 if (error) 3187 goto fail; 3188 3189 /* 3190 * initialize extra registers on 8187 3191 */ 3192 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3193 3194 /* retry limit */ 3195 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3196 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3197 urtw_write8_m(sc, URTW_CW_CONF, data8); 3198 3199 /* TX AGC */ 3200 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3201 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3202 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3203 3204 /* Auto Rate Fallback Control */ 3205 #define URTW_ARFR 0x1e0 3206 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3207 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3208 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3209 data8 | URTW_RATE_FALLBACK_ENABLE); 3210 3211 urtw_read8_m(sc, URTW_MSR, &data8); 3212 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3213 urtw_read8_m(sc, URTW_MSR, &data8); 3214 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3215 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3216 3217 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3218 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3219 #define URTW_FEMR_FOR_8187B 0x1d4 3220 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3221 3222 /* led type */ 3223 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3224 data8 = (data8 & 0x3f) | 0x80; 3225 urtw_write8_m(sc, URTW_CONFIG1, data8); 3226 3227 /* applying MAC address again. */ 3228 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3229 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3230 3231 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3232 if (error) 3233 goto fail; 3234 3235 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3236 3237 /* 3238 * MAC configuration 3239 */ 3240 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3241 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3242 urtw_8225v2b_rf_part1[i].val); 3243 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3244 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3245 urtw_write32_m(sc, 0x1f0, 0); 3246 urtw_write32_m(sc, 0x1f4, 0); 3247 urtw_write8_m(sc, 0x1f8, 0); 3248 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3249 3250 #define URTW_RFSW_CTRL 0x272 3251 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3252 3253 /* 3254 * initialize PHY 3255 */ 3256 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3257 if (error) 3258 goto fail; 3259 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3260 urtw_write8_m(sc, URTW_CONFIG3, 3261 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3262 3263 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3264 if (error) 3265 goto fail; 3266 3267 /* setup RFE initial timing */ 3268 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3269 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3270 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3271 usb_pause_mtx(&sc->sc_mtx, 1100); 3272 3273 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3274 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3275 urtw_8225v2b_rf_part0[i].val); 3276 usb_pause_mtx(&sc->sc_mtx, 1); 3277 } 3278 urtw_8225_write(sc, 0x00, 0x01b7); 3279 3280 for (i = 0; i < 95; i++) { 3281 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3282 usb_pause_mtx(&sc->sc_mtx, 1); 3283 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3284 urtw_8225v2b_rxgain[i]); 3285 usb_pause_mtx(&sc->sc_mtx, 1); 3286 } 3287 3288 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3289 usb_pause_mtx(&sc->sc_mtx, 1); 3290 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3291 usb_pause_mtx(&sc->sc_mtx, 1); 3292 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3293 usb_pause_mtx(&sc->sc_mtx, 1); 3294 usb_pause_mtx(&sc->sc_mtx, 3000); 3295 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3296 usb_pause_mtx(&sc->sc_mtx, 2000); 3297 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3298 usb_pause_mtx(&sc->sc_mtx, 1); 3299 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3300 usb_pause_mtx(&sc->sc_mtx, 1); 3301 3302 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3303 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3304 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3305 3306 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3307 for (i = 0; i < 128; i++) { 3308 uint32_t addr, data; 3309 3310 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3311 addr = ((i + 0x80) << 8) | 0x0000008e; 3312 3313 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3314 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3315 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3316 } 3317 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3318 3319 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3320 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3321 3322 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3323 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3324 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3325 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3326 3327 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3328 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3329 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3330 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3331 3332 fail: 3333 return (error); 3334 } 3335 3336 static usb_error_t 3337 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3338 { 3339 usb_error_t error; 3340 3341 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3342 if (error) 3343 goto fail; 3344 3345 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3346 usb_pause_mtx(&sc->sc_mtx, 10); 3347 fail: 3348 return (error); 3349 } 3350 3351 static usb_error_t 3352 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3353 { 3354 int i; 3355 uint8_t *cck_pwrtable; 3356 uint8_t cck_pwrlvl_max = 15; 3357 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3358 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3359 usb_error_t error; 3360 3361 /* CCK power setting */ 3362 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3363 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3364 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3365 cck_pwrlvl += sc->sc_txpwr_cck_base; 3366 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3367 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3368 urtw_8225v2b_txpwr_cck; 3369 3370 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3371 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3372 ((cck_pwrlvl <= 11) ? 8 : 16); 3373 else 3374 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3375 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3376 3377 for (i = 0; i < 8; i++) 3378 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3379 3380 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3381 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3382 usb_pause_mtx(&sc->sc_mtx, 1); 3383 3384 /* OFDM power setting */ 3385 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3386 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3387 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3388 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3389 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3390 3391 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3392 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3393 3394 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3395 if (ofdm_pwrlvl <= 11) { 3396 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3397 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3398 } else { 3399 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3400 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3401 } 3402 } else { 3403 if (ofdm_pwrlvl <= 11) { 3404 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3405 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3406 } else if (ofdm_pwrlvl <= 17) { 3407 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3408 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3409 } else { 3410 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3411 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3412 } 3413 } 3414 usb_pause_mtx(&sc->sc_mtx, 1); 3415 fail: 3416 return (error); 3417 } 3418 3419 static usb_error_t 3420 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3421 { 3422 struct usb_device_request req; 3423 usb_error_t error; 3424 3425 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3426 req.bRequest = URTW_8187_GETREGS_REQ; 3427 USETW(req.wValue, val | 0xfe00); 3428 USETW(req.wIndex, 0); 3429 USETW(req.wLength, sizeof(uint8_t)); 3430 3431 error = urtw_do_request(sc, &req, data); 3432 return (error); 3433 } 3434 3435 static usb_error_t 3436 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3437 { 3438 struct usb_device_request req; 3439 3440 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3441 req.bRequest = URTW_8187_SETREGS_REQ; 3442 USETW(req.wValue, val | 0xfe00); 3443 USETW(req.wIndex, 0); 3444 USETW(req.wLength, sizeof(uint8_t)); 3445 3446 return (urtw_do_request(sc, &req, &data)); 3447 } 3448 3449 static usb_error_t 3450 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3451 { 3452 uint8_t data; 3453 usb_error_t error; 3454 3455 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3456 if (error) 3457 goto fail; 3458 3459 urtw_read8_m(sc, URTW_CONFIG3, &data); 3460 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3461 urtw_write32_m(sc, URTW_ANAPARAM, val); 3462 urtw_read8_m(sc, URTW_CONFIG3, &data); 3463 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3464 3465 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3466 if (error) 3467 goto fail; 3468 fail: 3469 return (error); 3470 } 3471 3472 static usb_error_t 3473 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3474 { 3475 uint8_t data; 3476 usb_error_t error; 3477 3478 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3479 if (error) 3480 goto fail; 3481 3482 urtw_read8_m(sc, URTW_CONFIG3, &data); 3483 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3484 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3485 urtw_read8_m(sc, URTW_CONFIG3, &data); 3486 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3487 3488 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3489 if (error) 3490 goto fail; 3491 fail: 3492 return (error); 3493 } 3494 3495 static usb_error_t 3496 urtw_intr_enable(struct urtw_softc *sc) 3497 { 3498 usb_error_t error; 3499 3500 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3501 fail: 3502 return (error); 3503 } 3504 3505 static usb_error_t 3506 urtw_intr_disable(struct urtw_softc *sc) 3507 { 3508 usb_error_t error; 3509 3510 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3511 fail: 3512 return (error); 3513 } 3514 3515 static usb_error_t 3516 urtw_reset(struct urtw_softc *sc) 3517 { 3518 uint8_t data; 3519 usb_error_t error; 3520 3521 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3522 if (error) 3523 goto fail; 3524 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3525 if (error) 3526 goto fail; 3527 3528 error = urtw_intr_disable(sc); 3529 if (error) 3530 goto fail; 3531 usb_pause_mtx(&sc->sc_mtx, 100); 3532 3533 error = urtw_write8e(sc, 0x18, 0x10); 3534 if (error != 0) 3535 goto fail; 3536 error = urtw_write8e(sc, 0x18, 0x11); 3537 if (error != 0) 3538 goto fail; 3539 error = urtw_write8e(sc, 0x18, 0x00); 3540 if (error != 0) 3541 goto fail; 3542 usb_pause_mtx(&sc->sc_mtx, 100); 3543 3544 urtw_read8_m(sc, URTW_CMD, &data); 3545 data = (data & 0x2) | URTW_CMD_RST; 3546 urtw_write8_m(sc, URTW_CMD, data); 3547 usb_pause_mtx(&sc->sc_mtx, 100); 3548 3549 urtw_read8_m(sc, URTW_CMD, &data); 3550 if (data & URTW_CMD_RST) { 3551 device_printf(sc->sc_dev, "reset timeout\n"); 3552 goto fail; 3553 } 3554 3555 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3556 if (error) 3557 goto fail; 3558 usb_pause_mtx(&sc->sc_mtx, 100); 3559 3560 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3561 if (error) 3562 goto fail; 3563 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3564 if (error) 3565 goto fail; 3566 fail: 3567 return (error); 3568 } 3569 3570 static usb_error_t 3571 urtw_led_ctl(struct urtw_softc *sc, int mode) 3572 { 3573 usb_error_t error = 0; 3574 3575 switch (sc->sc_strategy) { 3576 case URTW_SW_LED_MODE0: 3577 error = urtw_led_mode0(sc, mode); 3578 break; 3579 case URTW_SW_LED_MODE1: 3580 error = urtw_led_mode1(sc, mode); 3581 break; 3582 case URTW_SW_LED_MODE2: 3583 error = urtw_led_mode2(sc, mode); 3584 break; 3585 case URTW_SW_LED_MODE3: 3586 error = urtw_led_mode3(sc, mode); 3587 break; 3588 default: 3589 DPRINTF(sc, URTW_DEBUG_STATE, 3590 "unsupported LED mode %d\n", sc->sc_strategy); 3591 error = USB_ERR_INVAL; 3592 break; 3593 } 3594 3595 return (error); 3596 } 3597 3598 static usb_error_t 3599 urtw_led_mode0(struct urtw_softc *sc, int mode) 3600 { 3601 3602 switch (mode) { 3603 case URTW_LED_CTL_POWER_ON: 3604 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3605 break; 3606 case URTW_LED_CTL_TX: 3607 if (sc->sc_gpio_ledinprogress == 1) 3608 return (0); 3609 3610 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3611 sc->sc_gpio_blinktime = 2; 3612 break; 3613 case URTW_LED_CTL_LINK: 3614 sc->sc_gpio_ledstate = URTW_LED_ON; 3615 break; 3616 default: 3617 DPRINTF(sc, URTW_DEBUG_STATE, 3618 "unsupported LED mode 0x%x", mode); 3619 return (USB_ERR_INVAL); 3620 } 3621 3622 switch (sc->sc_gpio_ledstate) { 3623 case URTW_LED_ON: 3624 if (sc->sc_gpio_ledinprogress != 0) 3625 break; 3626 urtw_led_on(sc, URTW_LED_GPIO); 3627 break; 3628 case URTW_LED_BLINK_NORMAL: 3629 if (sc->sc_gpio_ledinprogress != 0) 3630 break; 3631 sc->sc_gpio_ledinprogress = 1; 3632 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3633 URTW_LED_OFF : URTW_LED_ON; 3634 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3635 break; 3636 case URTW_LED_POWER_ON_BLINK: 3637 urtw_led_on(sc, URTW_LED_GPIO); 3638 usb_pause_mtx(&sc->sc_mtx, 100); 3639 urtw_led_off(sc, URTW_LED_GPIO); 3640 break; 3641 default: 3642 DPRINTF(sc, URTW_DEBUG_STATE, 3643 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3644 return (USB_ERR_INVAL); 3645 } 3646 return (0); 3647 } 3648 3649 static usb_error_t 3650 urtw_led_mode1(struct urtw_softc *sc, int mode) 3651 { 3652 return (USB_ERR_INVAL); 3653 } 3654 3655 static usb_error_t 3656 urtw_led_mode2(struct urtw_softc *sc, int mode) 3657 { 3658 return (USB_ERR_INVAL); 3659 } 3660 3661 static usb_error_t 3662 urtw_led_mode3(struct urtw_softc *sc, int mode) 3663 { 3664 return (USB_ERR_INVAL); 3665 } 3666 3667 static usb_error_t 3668 urtw_led_on(struct urtw_softc *sc, int type) 3669 { 3670 usb_error_t error; 3671 3672 if (type == URTW_LED_GPIO) { 3673 switch (sc->sc_gpio_ledpin) { 3674 case URTW_LED_PIN_GPIO0: 3675 urtw_write8_m(sc, URTW_GPIO, 0x01); 3676 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3677 break; 3678 default: 3679 DPRINTF(sc, URTW_DEBUG_STATE, 3680 "unsupported LED PIN type 0x%x", 3681 sc->sc_gpio_ledpin); 3682 error = USB_ERR_INVAL; 3683 goto fail; 3684 } 3685 } else { 3686 DPRINTF(sc, URTW_DEBUG_STATE, 3687 "unsupported LED type 0x%x", type); 3688 error = USB_ERR_INVAL; 3689 goto fail; 3690 } 3691 3692 sc->sc_gpio_ledon = 1; 3693 fail: 3694 return (error); 3695 } 3696 3697 static usb_error_t 3698 urtw_led_off(struct urtw_softc *sc, int type) 3699 { 3700 usb_error_t error; 3701 3702 if (type == URTW_LED_GPIO) { 3703 switch (sc->sc_gpio_ledpin) { 3704 case URTW_LED_PIN_GPIO0: 3705 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3706 urtw_write8_m(sc, 3707 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3708 break; 3709 default: 3710 DPRINTF(sc, URTW_DEBUG_STATE, 3711 "unsupported LED PIN type 0x%x", 3712 sc->sc_gpio_ledpin); 3713 error = USB_ERR_INVAL; 3714 goto fail; 3715 } 3716 } else { 3717 DPRINTF(sc, URTW_DEBUG_STATE, 3718 "unsupported LED type 0x%x", type); 3719 error = USB_ERR_INVAL; 3720 goto fail; 3721 } 3722 3723 sc->sc_gpio_ledon = 0; 3724 3725 fail: 3726 return (error); 3727 } 3728 3729 static void 3730 urtw_led_ch(void *arg) 3731 { 3732 struct urtw_softc *sc = arg; 3733 struct ieee80211com *ic = &sc->sc_ic; 3734 3735 ieee80211_runtask(ic, &sc->sc_led_task); 3736 } 3737 3738 static void 3739 urtw_ledtask(void *arg, int pending) 3740 { 3741 struct urtw_softc *sc = arg; 3742 3743 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3744 DPRINTF(sc, URTW_DEBUG_STATE, 3745 "could not process a LED strategy 0x%x", 3746 sc->sc_strategy); 3747 return; 3748 } 3749 3750 URTW_LOCK(sc); 3751 urtw_led_blink(sc); 3752 URTW_UNLOCK(sc); 3753 } 3754 3755 static usb_error_t 3756 urtw_led_blink(struct urtw_softc *sc) 3757 { 3758 uint8_t ing = 0; 3759 usb_error_t error; 3760 3761 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3762 error = urtw_led_on(sc, URTW_LED_GPIO); 3763 else 3764 error = urtw_led_off(sc, URTW_LED_GPIO); 3765 sc->sc_gpio_blinktime--; 3766 if (sc->sc_gpio_blinktime == 0) 3767 ing = 1; 3768 else { 3769 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3770 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3771 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3772 ing = 1; 3773 } 3774 if (ing == 1) { 3775 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3776 sc->sc_gpio_ledon == 0) 3777 error = urtw_led_on(sc, URTW_LED_GPIO); 3778 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3779 sc->sc_gpio_ledon == 1) 3780 error = urtw_led_off(sc, URTW_LED_GPIO); 3781 3782 sc->sc_gpio_blinktime = 0; 3783 sc->sc_gpio_ledinprogress = 0; 3784 return (0); 3785 } 3786 3787 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3788 URTW_LED_ON : URTW_LED_OFF; 3789 3790 switch (sc->sc_gpio_ledstate) { 3791 case URTW_LED_BLINK_NORMAL: 3792 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3793 break; 3794 default: 3795 DPRINTF(sc, URTW_DEBUG_STATE, 3796 "unknown LED status 0x%x", 3797 sc->sc_gpio_ledstate); 3798 return (USB_ERR_INVAL); 3799 } 3800 return (0); 3801 } 3802 3803 static usb_error_t 3804 urtw_rx_enable(struct urtw_softc *sc) 3805 { 3806 uint8_t data; 3807 usb_error_t error; 3808 3809 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3810 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3811 3812 error = urtw_rx_setconf(sc); 3813 if (error != 0) 3814 goto fail; 3815 3816 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3817 urtw_read8_m(sc, URTW_CMD, &data); 3818 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3819 } 3820 fail: 3821 return (error); 3822 } 3823 3824 static usb_error_t 3825 urtw_tx_enable(struct urtw_softc *sc) 3826 { 3827 uint8_t data8; 3828 uint32_t data; 3829 usb_error_t error; 3830 3831 if (sc->sc_flags & URTW_RTL8187B) { 3832 urtw_read32_m(sc, URTW_TX_CONF, &data); 3833 data &= ~URTW_TX_LOOPBACK_MASK; 3834 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3835 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3836 data &= ~URTW_TX_SWPLCPLEN; 3837 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3838 (7 << 8) | /* short retry limit */ 3839 (7 << 0) | /* long retry limit */ 3840 (7 << 21); /* MAX TX DMA */ 3841 urtw_write32_m(sc, URTW_TX_CONF, data); 3842 3843 urtw_read8_m(sc, URTW_MSR, &data8); 3844 data8 |= URTW_MSR_LINK_ENEDCA; 3845 urtw_write8_m(sc, URTW_MSR, data8); 3846 return (error); 3847 } 3848 3849 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3850 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3851 urtw_write8_m(sc, URTW_CW_CONF, data8); 3852 3853 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3854 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3855 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3856 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3857 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3858 3859 urtw_read32_m(sc, URTW_TX_CONF, &data); 3860 data &= ~URTW_TX_LOOPBACK_MASK; 3861 data |= URTW_TX_LOOPBACK_NONE; 3862 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3863 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3864 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3865 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3866 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3867 data &= ~URTW_TX_SWPLCPLEN; 3868 data |= URTW_TX_NOICV; 3869 urtw_write32_m(sc, URTW_TX_CONF, data); 3870 3871 urtw_read8_m(sc, URTW_CMD, &data8); 3872 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3873 fail: 3874 return (error); 3875 } 3876 3877 static usb_error_t 3878 urtw_rx_setconf(struct urtw_softc *sc) 3879 { 3880 struct ieee80211com *ic = &sc->sc_ic; 3881 uint32_t data; 3882 usb_error_t error; 3883 3884 urtw_read32_m(sc, URTW_RX, &data); 3885 data = data &~ URTW_RX_FILTER_MASK; 3886 if (sc->sc_flags & URTW_RTL8187B) { 3887 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3888 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3889 URTW_RX_FIFO_THRESHOLD_NONE | 3890 URTW_MAX_RX_DMA_2048 | 3891 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3892 } else { 3893 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3894 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3895 3896 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3897 data = data | URTW_RX_FILTER_ICVERR; 3898 data = data | URTW_RX_FILTER_PWR; 3899 } 3900 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3901 data = data | URTW_RX_FILTER_CRCERR; 3902 3903 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3904 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3905 URTW_RX_AUTORESETPHY; 3906 data = data &~ URTW_MAX_RX_DMA_MASK; 3907 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3908 } 3909 3910 /* XXX allmulti should not be checked here... */ 3911 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3912 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3913 data = data | URTW_RX_FILTER_CTL; 3914 data = data | URTW_RX_FILTER_ALLMAC; 3915 } else { 3916 data = data | URTW_RX_FILTER_NICMAC; 3917 data = data | URTW_RX_CHECK_BSSID; 3918 } 3919 3920 urtw_write32_m(sc, URTW_RX, data); 3921 fail: 3922 return (error); 3923 } 3924 3925 static struct mbuf * 3926 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3927 int8_t *nf_p) 3928 { 3929 int actlen, flen, rssi; 3930 struct ieee80211_frame *wh; 3931 struct mbuf *m, *mnew; 3932 struct urtw_softc *sc = data->sc; 3933 struct ieee80211com *ic = &sc->sc_ic; 3934 uint8_t noise = 0, rate; 3935 3936 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3937 3938 if (sc->sc_flags & URTW_RTL8187B) { 3939 struct urtw_8187b_rxhdr *rx; 3940 3941 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3942 goto fail; 3943 3944 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3945 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3946 flen = le32toh(rx->flag) & 0xfff; 3947 if (flen > actlen - sizeof(*rx)) 3948 goto fail; 3949 3950 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3951 /* XXX correct? */ 3952 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3953 noise = rx->noise; 3954 } else { 3955 struct urtw_8187l_rxhdr *rx; 3956 3957 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3958 goto fail; 3959 3960 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3961 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3962 flen = le32toh(rx->flag) & 0xfff; 3963 if (flen > actlen - sizeof(*rx)) 3964 goto fail; 3965 3966 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3967 /* XXX correct? */ 3968 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3969 noise = rx->noise; 3970 } 3971 3972 if (flen < IEEE80211_ACK_LEN) 3973 goto fail; 3974 3975 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3976 if (mnew == NULL) 3977 goto fail; 3978 3979 m = data->m; 3980 data->m = mnew; 3981 data->buf = mtod(mnew, uint8_t *); 3982 3983 /* finalize mbuf */ 3984 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3985 3986 if (ieee80211_radiotap_active(ic)) { 3987 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3988 3989 tap->wr_flags = 0; 3990 tap->wr_dbm_antsignal = (int8_t)rssi; 3991 } 3992 3993 wh = mtod(m, struct ieee80211_frame *); 3994 if (IEEE80211_IS_DATA(wh)) 3995 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3996 3997 *rssi_p = rssi; 3998 *nf_p = noise; /* XXX correct? */ 3999 4000 return (m); 4001 4002 fail: 4003 counter_u64_add(ic->ic_ierrors, 1); 4004 return (NULL); 4005 } 4006 4007 static void 4008 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4009 { 4010 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4011 struct ieee80211com *ic = &sc->sc_ic; 4012 struct ieee80211_node *ni; 4013 struct mbuf *m = NULL; 4014 struct urtw_data *data; 4015 int8_t nf = -95; 4016 int rssi = 1; 4017 4018 URTW_ASSERT_LOCKED(sc); 4019 4020 switch (USB_GET_STATE(xfer)) { 4021 case USB_ST_TRANSFERRED: 4022 data = STAILQ_FIRST(&sc->sc_rx_active); 4023 if (data == NULL) 4024 goto setup; 4025 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4026 m = urtw_rxeof(xfer, data, &rssi, &nf); 4027 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4028 /* FALLTHROUGH */ 4029 case USB_ST_SETUP: 4030 setup: 4031 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4032 if (data == NULL) { 4033 KASSERT(m == NULL, ("mbuf isn't NULL")); 4034 return; 4035 } 4036 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4037 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4038 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4039 usbd_xfer_max_len(xfer)); 4040 usbd_transfer_submit(xfer); 4041 4042 /* 4043 * To avoid LOR we should unlock our private mutex here to call 4044 * ieee80211_input() because here is at the end of a USB 4045 * callback and safe to unlock. 4046 */ 4047 URTW_UNLOCK(sc); 4048 if (m != NULL) { 4049 if (m->m_pkthdr.len >= 4050 sizeof(struct ieee80211_frame_min)) { 4051 ni = ieee80211_find_rxnode(ic, 4052 mtod(m, struct ieee80211_frame_min *)); 4053 } else 4054 ni = NULL; 4055 4056 if (ni != NULL) { 4057 (void) ieee80211_input(ni, m, rssi, nf); 4058 /* node is no longer needed */ 4059 ieee80211_free_node(ni); 4060 } else 4061 (void) ieee80211_input_all(ic, m, rssi, nf); 4062 m = NULL; 4063 } 4064 URTW_LOCK(sc); 4065 break; 4066 default: 4067 /* needs it to the inactive queue due to a error. */ 4068 data = STAILQ_FIRST(&sc->sc_rx_active); 4069 if (data != NULL) { 4070 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4071 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4072 } 4073 if (error != USB_ERR_CANCELLED) { 4074 usbd_xfer_set_stall(xfer); 4075 counter_u64_add(ic->ic_ierrors, 1); 4076 goto setup; 4077 } 4078 break; 4079 } 4080 } 4081 4082 #define URTW_STATUS_TYPE_TXCLOSE 1 4083 #define URTW_STATUS_TYPE_BEACON_INTR 0 4084 4085 static void 4086 urtw_txstatus_eof(struct usb_xfer *xfer) 4087 { 4088 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4089 struct ieee80211com *ic = &sc->sc_ic; 4090 int actlen, type, pktretry, seq; 4091 uint64_t val; 4092 4093 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4094 4095 if (actlen != sizeof(uint64_t)) 4096 return; 4097 4098 val = le64toh(sc->sc_txstatus); 4099 type = (val >> 30) & 0x3; 4100 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4101 pktretry = val & 0xff; 4102 seq = (val >> 16) & 0xff; 4103 if (pktretry == URTW_TX_MAXRETRY) 4104 counter_u64_add(ic->ic_oerrors, 1); 4105 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4106 pktretry, seq); 4107 } 4108 } 4109 4110 static void 4111 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4112 { 4113 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4114 struct ieee80211com *ic = &sc->sc_ic; 4115 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4116 4117 URTW_ASSERT_LOCKED(sc); 4118 4119 switch (USB_GET_STATE(xfer)) { 4120 case USB_ST_TRANSFERRED: 4121 urtw_txstatus_eof(xfer); 4122 /* FALLTHROUGH */ 4123 case USB_ST_SETUP: 4124 setup: 4125 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4126 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4127 usbd_transfer_submit(xfer); 4128 break; 4129 default: 4130 if (error != USB_ERR_CANCELLED) { 4131 usbd_xfer_set_stall(xfer); 4132 counter_u64_add(ic->ic_ierrors, 1); 4133 goto setup; 4134 } 4135 break; 4136 } 4137 } 4138 4139 static void 4140 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4141 { 4142 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4143 4144 URTW_ASSERT_LOCKED(sc); 4145 4146 if (data->m) { 4147 /* XXX status? */ 4148 ieee80211_tx_complete(data->ni, data->m, 0); 4149 data->m = NULL; 4150 data->ni = NULL; 4151 } 4152 sc->sc_txtimer = 0; 4153 } 4154 4155 static void 4156 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4157 { 4158 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4159 struct urtw_data *data; 4160 4161 URTW_ASSERT_LOCKED(sc); 4162 4163 switch (USB_GET_STATE(xfer)) { 4164 case USB_ST_TRANSFERRED: 4165 data = STAILQ_FIRST(&sc->sc_tx_active); 4166 if (data == NULL) 4167 goto setup; 4168 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4169 urtw_txeof(xfer, data); 4170 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4171 /* FALLTHROUGH */ 4172 case USB_ST_SETUP: 4173 setup: 4174 data = STAILQ_FIRST(&sc->sc_tx_pending); 4175 if (data == NULL) { 4176 DPRINTF(sc, URTW_DEBUG_XMIT, 4177 "%s: empty pending queue\n", __func__); 4178 return; 4179 } 4180 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4181 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4182 4183 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4184 usbd_transfer_submit(xfer); 4185 4186 urtw_start(sc); 4187 break; 4188 default: 4189 data = STAILQ_FIRST(&sc->sc_tx_active); 4190 if (data == NULL) 4191 goto setup; 4192 if (data->ni != NULL) { 4193 if_inc_counter(data->ni->ni_vap->iv_ifp, 4194 IFCOUNTER_OERRORS, 1); 4195 ieee80211_free_node(data->ni); 4196 data->ni = NULL; 4197 } 4198 if (error != USB_ERR_CANCELLED) { 4199 usbd_xfer_set_stall(xfer); 4200 goto setup; 4201 } 4202 break; 4203 } 4204 } 4205 4206 static struct urtw_data * 4207 _urtw_getbuf(struct urtw_softc *sc) 4208 { 4209 struct urtw_data *bf; 4210 4211 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4212 if (bf != NULL) 4213 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4214 else 4215 bf = NULL; 4216 if (bf == NULL) 4217 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4218 "out of xmit buffers"); 4219 return (bf); 4220 } 4221 4222 static struct urtw_data * 4223 urtw_getbuf(struct urtw_softc *sc) 4224 { 4225 struct urtw_data *bf; 4226 4227 URTW_ASSERT_LOCKED(sc); 4228 4229 bf = _urtw_getbuf(sc); 4230 if (bf == NULL) 4231 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4232 return (bf); 4233 } 4234 4235 static int 4236 urtw_isbmode(uint16_t rate) 4237 { 4238 4239 return ((rate <= 22 && rate != 12 && rate != 18) || 4240 rate == 44) ? (1) : (0); 4241 } 4242 4243 static uint16_t 4244 urtw_rate2dbps(uint16_t rate) 4245 { 4246 4247 switch(rate) { 4248 case 12: 4249 case 18: 4250 case 24: 4251 case 36: 4252 case 48: 4253 case 72: 4254 case 96: 4255 case 108: 4256 return (rate * 2); 4257 default: 4258 break; 4259 } 4260 return (24); 4261 } 4262 4263 static int 4264 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4265 uint8_t ismgt, uint8_t isshort) 4266 { 4267 uint16_t ceiling, frametime, n_dbps; 4268 4269 if (urtw_isbmode(rate)) { 4270 if (ismgt || !isshort || rate == 2) 4271 frametime = (uint16_t)(144 + 48 + 4272 (framelen * 8 / (rate / 2))); 4273 else 4274 frametime = (uint16_t)(72 + 24 + 4275 (framelen * 8 / (rate / 2))); 4276 if ((framelen * 8 % (rate / 2)) != 0) 4277 frametime++; 4278 } else { 4279 n_dbps = urtw_rate2dbps(rate); 4280 ceiling = (16 + 8 * framelen + 6) / n_dbps 4281 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4282 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4283 } 4284 return (frametime); 4285 } 4286 4287 /* 4288 * Callback from the 802.11 layer to update the 4289 * slot time based on the current setting. 4290 */ 4291 static void 4292 urtw_updateslot(struct ieee80211com *ic) 4293 { 4294 struct urtw_softc *sc = ic->ic_softc; 4295 4296 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4297 } 4298 4299 static void 4300 urtw_updateslottask(void *arg, int pending) 4301 { 4302 struct urtw_softc *sc = arg; 4303 struct ieee80211com *ic = &sc->sc_ic; 4304 int error; 4305 4306 URTW_LOCK(sc); 4307 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4308 URTW_UNLOCK(sc); 4309 return; 4310 } 4311 if (sc->sc_flags & URTW_RTL8187B) { 4312 urtw_write8_m(sc, URTW_SIFS, 0x22); 4313 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4314 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4315 else 4316 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4317 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4318 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4319 } else { 4320 urtw_write8_m(sc, URTW_SIFS, 0x22); 4321 if (sc->sc_state == IEEE80211_S_ASSOC && 4322 ic->ic_flags & IEEE80211_F_SHSLOT) 4323 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4324 else 4325 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4326 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4327 urtw_write8_m(sc, URTW_DIFS, 0x14); 4328 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4329 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4330 } else { 4331 urtw_write8_m(sc, URTW_DIFS, 0x24); 4332 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4333 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4334 } 4335 } 4336 fail: 4337 URTW_UNLOCK(sc); 4338 } 4339 4340 static void 4341 urtw_sysctl_node(struct urtw_softc *sc) 4342 { 4343 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4344 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4345 struct sysctl_ctx_list *ctx; 4346 struct sysctl_oid_list *child, *parent; 4347 struct sysctl_oid *tree; 4348 struct urtw_stats *stats = &sc->sc_stats; 4349 4350 ctx = device_get_sysctl_ctx(sc->sc_dev); 4351 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4352 4353 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4354 NULL, "URTW statistics"); 4355 parent = SYSCTL_CHILDREN(tree); 4356 4357 /* Tx statistics. */ 4358 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4359 NULL, "Tx MAC statistics"); 4360 child = SYSCTL_CHILDREN(tree); 4361 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4362 "1 Mbit/s"); 4363 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4364 "2 Mbit/s"); 4365 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4366 "5.5 Mbit/s"); 4367 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4368 "6 Mbit/s"); 4369 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4370 "9 Mbit/s"); 4371 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4372 "11 Mbit/s"); 4373 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4374 "12 Mbit/s"); 4375 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4376 "18 Mbit/s"); 4377 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4378 "24 Mbit/s"); 4379 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4380 "36 Mbit/s"); 4381 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4382 "48 Mbit/s"); 4383 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4384 "54 Mbit/s"); 4385 #undef URTW_SYSCTL_STAT_ADD32 4386 } 4387 4388 static device_method_t urtw_methods[] = { 4389 DEVMETHOD(device_probe, urtw_match), 4390 DEVMETHOD(device_attach, urtw_attach), 4391 DEVMETHOD(device_detach, urtw_detach), 4392 DEVMETHOD_END 4393 }; 4394 static driver_t urtw_driver = { 4395 .name = "urtw", 4396 .methods = urtw_methods, 4397 .size = sizeof(struct urtw_softc) 4398 }; 4399 static devclass_t urtw_devclass; 4400 4401 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4402 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4403 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4404 MODULE_VERSION(urtw, 1); 4405 USB_PNP_HOST_INFO(urtw_devs); 4406