1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 #include <sys/param.h> 20 #include <sys/sockio.h> 21 #include <sys/sysctl.h> 22 #include <sys/lock.h> 23 #include <sys/mutex.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/malloc.h> 29 #include <sys/module.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kdb.h> 33 34 #include <machine/bus.h> 35 #include <machine/resource.h> 36 #include <sys/rman.h> 37 38 #include <net/if.h> 39 #include <net/if_var.h> 40 #include <net/if_arp.h> 41 #include <net/ethernet.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #ifdef INET 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_ether.h> 51 #include <netinet/ip.h> 52 #endif 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_regdomain.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include "usbdevs.h" 61 62 #include <dev/usb/wlan/if_urtwreg.h> 63 #include <dev/usb/wlan/if_urtwvar.h> 64 65 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 66 #ifdef URTW_DEBUG 67 int urtw_debug = 0; 68 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 69 "control debugging printfs"); 70 enum { 71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 77 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 80 URTW_DEBUG_ANY = 0xffffffff 81 }; 82 #define DPRINTF(sc, m, fmt, ...) do { \ 83 if (sc->sc_debug & (m)) \ 84 printf(fmt, __VA_ARGS__); \ 85 } while (0) 86 #else 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 (void) sc; \ 89 } while (0) 90 #endif 91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 93 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 94 95 /* recognized device vendors/products */ 96 #define urtw_lookup(v, p) \ 97 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 98 #define URTW_DEV_B(v,p) \ 99 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 100 #define URTW_DEV_L(v,p) \ 101 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 102 #define URTW_REV_RTL8187B 0 103 #define URTW_REV_RTL8187L 1 104 static const STRUCT_USB_HOST_ID urtw_devs[] = { 105 URTW_DEV_B(NETGEAR, WG111V3), 106 URTW_DEV_B(REALTEK, RTL8187B_0), 107 URTW_DEV_B(REALTEK, RTL8187B_1), 108 URTW_DEV_B(REALTEK, RTL8187B_2), 109 URTW_DEV_B(SITECOMEU, WL168V4), 110 URTW_DEV_L(ASUS, P5B_WIFI), 111 URTW_DEV_L(BELKIN, F5D7050E), 112 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 113 URTW_DEV_L(NETGEAR, WG111V2), 114 URTW_DEV_L(REALTEK, RTL8187), 115 URTW_DEV_L(SITECOMEU, WL168V1), 116 URTW_DEV_L(SURECOM, EP9001G2A), 117 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 118 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 119 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 120 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 121 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 122 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 124 #undef URTW_DEV_L 125 #undef URTW_DEV_B 126 }; 127 128 #define urtw_read8_m(sc, val, data) do { \ 129 error = urtw_read8_c(sc, val, data); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_write8_m(sc, val, data) do { \ 134 error = urtw_write8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_m(sc, val, data) do { \ 139 error = urtw_read16_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_read32_m(sc, val, data) do { \ 149 error = urtw_read32_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_write32_m(sc, val, data) do { \ 154 error = urtw_write32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 159 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 164 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8225_write(sc, val, data) do { \ 169 error = urtw_8225_write_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 174 struct urtw_pair { 175 uint32_t reg; 176 uint32_t val; 177 }; 178 179 static uint8_t urtw_8225_agc[] = { 180 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 181 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 182 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 183 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 184 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 185 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 186 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 187 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 188 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 189 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 192 }; 193 194 static uint8_t urtw_8225z2_agc[] = { 195 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 196 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 197 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 198 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 199 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 200 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 201 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 202 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 203 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 204 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 205 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 207 }; 208 209 static uint32_t urtw_8225_channel[] = { 210 0x0000, /* dummy channel 0 */ 211 0x085c, /* 1 */ 212 0x08dc, /* 2 */ 213 0x095c, /* 3 */ 214 0x09dc, /* 4 */ 215 0x0a5c, /* 5 */ 216 0x0adc, /* 6 */ 217 0x0b5c, /* 7 */ 218 0x0bdc, /* 8 */ 219 0x0c5c, /* 9 */ 220 0x0cdc, /* 10 */ 221 0x0d5c, /* 11 */ 222 0x0ddc, /* 12 */ 223 0x0e5c, /* 13 */ 224 0x0f72, /* 14 */ 225 }; 226 227 static uint8_t urtw_8225_gain[] = { 228 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 229 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 230 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 231 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 232 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 233 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 234 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 235 }; 236 237 static struct urtw_pair urtw_8225_rf_part1[] = { 238 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 239 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 240 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 241 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 242 }; 243 244 static struct urtw_pair urtw_8225_rf_part2[] = { 245 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 246 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 247 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 248 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 249 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 250 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 251 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 252 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 253 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 254 { 0x27, 0x88 } 255 }; 256 257 static struct urtw_pair urtw_8225_rf_part3[] = { 258 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 259 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 260 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 261 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 262 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 263 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 264 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 265 }; 266 267 static uint16_t urtw_8225_rxgain[] = { 268 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 269 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 270 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 271 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 272 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 273 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 274 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 275 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 276 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 277 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 278 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 279 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 280 }; 281 282 static uint8_t urtw_8225_threshold[] = { 283 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 284 }; 285 286 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 287 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 288 }; 289 290 static uint8_t urtw_8225_txpwr_cck[] = { 291 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 292 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 293 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 294 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 295 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 296 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 297 }; 298 299 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 300 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 301 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 302 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 303 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 304 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 305 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 306 }; 307 308 static uint8_t urtw_8225_txpwr_ofdm[]={ 309 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 310 }; 311 312 static uint8_t urtw_8225v2_gain_bg[]={ 313 0x23, 0x15, 0xa5, /* -82-1dbm */ 314 0x23, 0x15, 0xb5, /* -82-2dbm */ 315 0x23, 0x15, 0xc5, /* -82-3dbm */ 316 0x33, 0x15, 0xc5, /* -78dbm */ 317 0x43, 0x15, 0xc5, /* -74dbm */ 318 0x53, 0x15, 0xc5, /* -70dbm */ 319 0x63, 0x15, 0xc5, /* -66dbm */ 320 }; 321 322 static struct urtw_pair urtw_8225v2_rf_part1[] = { 323 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 324 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 325 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 326 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 327 }; 328 329 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 330 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 331 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 332 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 333 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 334 }; 335 336 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 337 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 338 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 339 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 340 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 341 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 342 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 343 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 344 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 345 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 346 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 347 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 348 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 349 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 350 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 351 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 352 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 353 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 354 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 355 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 356 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 357 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 358 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 359 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 360 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 361 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 362 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 363 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 364 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 365 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 366 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 367 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 368 }; 369 370 static struct urtw_pair urtw_8225v2_rf_part2[] = { 371 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 372 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 373 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 374 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 375 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 376 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 377 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 378 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 379 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 380 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 381 }; 382 383 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 384 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 385 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 386 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 387 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 388 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 389 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 390 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 391 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 392 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 393 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 394 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 395 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 396 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 397 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 398 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 399 }; 400 401 static struct urtw_pair urtw_8225v2_rf_part3[] = { 402 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 403 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 404 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 405 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 406 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 407 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 408 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 409 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 410 }; 411 412 static uint16_t urtw_8225v2_rxgain[] = { 413 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 414 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 415 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 416 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 417 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 418 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 419 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 420 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 421 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 422 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 423 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 424 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 425 }; 426 427 static uint16_t urtw_8225v2b_rxgain[] = { 428 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 429 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 430 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 431 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 432 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 433 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 434 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 435 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 436 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 437 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 438 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 439 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 440 }; 441 442 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 443 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 444 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 445 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 446 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 447 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 448 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 449 }; 450 451 static uint8_t urtw_8225v2_txpwr_cck[] = { 452 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 453 }; 454 455 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 456 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 457 }; 458 459 static uint8_t urtw_8225v2b_txpwr_cck[] = { 460 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 461 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 462 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 463 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 464 }; 465 466 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 467 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 468 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 471 }; 472 473 static struct urtw_pair urtw_ratetable[] = { 474 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 475 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 476 { 96, 10 }, { 108, 11 } 477 }; 478 479 #if 0 480 static const uint8_t urtw_8187b_reg_table[][3] = { 481 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 482 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 483 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 484 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 485 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 486 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 487 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 488 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 489 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 490 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 491 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 492 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 493 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 494 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 495 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 496 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 497 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 498 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 499 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 500 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 501 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 502 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 503 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 504 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 505 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 506 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 507 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 508 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 509 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 510 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 511 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 512 }; 513 #endif 514 515 static usb_callback_t urtw_bulk_rx_callback; 516 static usb_callback_t urtw_bulk_tx_callback; 517 static usb_callback_t urtw_bulk_tx_status_callback; 518 519 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 520 [URTW_8187B_BULK_RX] = { 521 .type = UE_BULK, 522 .endpoint = 0x83, 523 .direction = UE_DIR_IN, 524 .bufsize = MCLBYTES, 525 .flags = { 526 .ext_buffer = 1, 527 .pipe_bof = 1, 528 .short_xfer_ok = 1 529 }, 530 .callback = urtw_bulk_rx_callback 531 }, 532 [URTW_8187B_BULK_TX_STATUS] = { 533 .type = UE_BULK, 534 .endpoint = 0x89, 535 .direction = UE_DIR_IN, 536 .bufsize = sizeof(uint64_t), 537 .flags = { 538 .pipe_bof = 1, 539 .short_xfer_ok = 1 540 }, 541 .callback = urtw_bulk_tx_status_callback 542 }, 543 [URTW_8187B_BULK_TX_BE] = { 544 .type = UE_BULK, 545 .endpoint = URTW_8187B_TXPIPE_BE, 546 .direction = UE_DIR_OUT, 547 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 548 .flags = { 549 .force_short_xfer = 1, 550 .pipe_bof = 1, 551 }, 552 .callback = urtw_bulk_tx_callback, 553 .timeout = URTW_DATA_TIMEOUT 554 }, 555 [URTW_8187B_BULK_TX_BK] = { 556 .type = UE_BULK, 557 .endpoint = URTW_8187B_TXPIPE_BK, 558 .direction = UE_DIR_OUT, 559 .bufsize = URTW_TX_MAXSIZE, 560 .flags = { 561 .ext_buffer = 1, 562 .force_short_xfer = 1, 563 .pipe_bof = 1, 564 }, 565 .callback = urtw_bulk_tx_callback, 566 .timeout = URTW_DATA_TIMEOUT 567 }, 568 [URTW_8187B_BULK_TX_VI] = { 569 .type = UE_BULK, 570 .endpoint = URTW_8187B_TXPIPE_VI, 571 .direction = UE_DIR_OUT, 572 .bufsize = URTW_TX_MAXSIZE, 573 .flags = { 574 .ext_buffer = 1, 575 .force_short_xfer = 1, 576 .pipe_bof = 1, 577 }, 578 .callback = urtw_bulk_tx_callback, 579 .timeout = URTW_DATA_TIMEOUT 580 }, 581 [URTW_8187B_BULK_TX_VO] = { 582 .type = UE_BULK, 583 .endpoint = URTW_8187B_TXPIPE_VO, 584 .direction = UE_DIR_OUT, 585 .bufsize = URTW_TX_MAXSIZE, 586 .flags = { 587 .ext_buffer = 1, 588 .force_short_xfer = 1, 589 .pipe_bof = 1, 590 }, 591 .callback = urtw_bulk_tx_callback, 592 .timeout = URTW_DATA_TIMEOUT 593 }, 594 [URTW_8187B_BULK_TX_EP12] = { 595 .type = UE_BULK, 596 .endpoint = 0xc, 597 .direction = UE_DIR_OUT, 598 .bufsize = URTW_TX_MAXSIZE, 599 .flags = { 600 .ext_buffer = 1, 601 .force_short_xfer = 1, 602 .pipe_bof = 1, 603 }, 604 .callback = urtw_bulk_tx_callback, 605 .timeout = URTW_DATA_TIMEOUT 606 } 607 }; 608 609 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 610 [URTW_8187L_BULK_RX] = { 611 .type = UE_BULK, 612 .endpoint = 0x81, 613 .direction = UE_DIR_IN, 614 .bufsize = MCLBYTES, 615 .flags = { 616 .ext_buffer = 1, 617 .pipe_bof = 1, 618 .short_xfer_ok = 1 619 }, 620 .callback = urtw_bulk_rx_callback 621 }, 622 [URTW_8187L_BULK_TX_LOW] = { 623 .type = UE_BULK, 624 .endpoint = 0x2, 625 .direction = UE_DIR_OUT, 626 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 627 .flags = { 628 .force_short_xfer = 1, 629 .pipe_bof = 1, 630 }, 631 .callback = urtw_bulk_tx_callback, 632 .timeout = URTW_DATA_TIMEOUT 633 }, 634 [URTW_8187L_BULK_TX_NORMAL] = { 635 .type = UE_BULK, 636 .endpoint = 0x3, 637 .direction = UE_DIR_OUT, 638 .bufsize = URTW_TX_MAXSIZE, 639 .flags = { 640 .ext_buffer = 1, 641 .force_short_xfer = 1, 642 .pipe_bof = 1, 643 }, 644 .callback = urtw_bulk_tx_callback, 645 .timeout = URTW_DATA_TIMEOUT 646 }, 647 }; 648 649 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 650 const char [IFNAMSIZ], int, enum ieee80211_opmode, 651 int, const uint8_t [IEEE80211_ADDR_LEN], 652 const uint8_t [IEEE80211_ADDR_LEN]); 653 static void urtw_vap_delete(struct ieee80211vap *); 654 static void urtw_init(struct urtw_softc *); 655 static void urtw_stop(struct urtw_softc *); 656 static void urtw_parent(struct ieee80211com *); 657 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 658 static void urtw_start(struct urtw_softc *); 659 static int urtw_alloc_rx_data_list(struct urtw_softc *); 660 static int urtw_alloc_tx_data_list(struct urtw_softc *); 661 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 662 const struct ieee80211_bpf_params *); 663 static void urtw_scan_start(struct ieee80211com *); 664 static void urtw_scan_end(struct ieee80211com *); 665 static void urtw_set_channel(struct ieee80211com *); 666 static void urtw_update_mcast(struct ieee80211com *); 667 static int urtw_tx_start(struct urtw_softc *, 668 struct ieee80211_node *, struct mbuf *, 669 struct urtw_data *, int); 670 static int urtw_newstate(struct ieee80211vap *, 671 enum ieee80211_state, int); 672 static void urtw_led_ch(void *); 673 static void urtw_ledtask(void *, int); 674 static void urtw_watchdog(void *); 675 static void urtw_set_multi(void *); 676 static int urtw_isbmode(uint16_t); 677 static uint16_t urtw_rate2rtl(uint32_t); 678 static uint16_t urtw_rtl2rate(uint32_t); 679 static usb_error_t urtw_set_rate(struct urtw_softc *); 680 static usb_error_t urtw_update_msr(struct urtw_softc *); 681 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 682 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 683 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 684 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 685 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 686 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 687 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 688 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 689 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 690 int); 691 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 692 uint32_t *); 693 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 694 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 695 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 696 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 697 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 698 static usb_error_t urtw_led_init(struct urtw_softc *); 699 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 700 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 701 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 702 uint32_t); 703 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 704 uint8_t, uint32_t); 705 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 706 uint32_t); 707 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 708 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 709 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 710 uint16_t); 711 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 712 uint16_t *); 713 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 714 uint32_t *); 715 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 716 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 717 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 718 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 719 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 720 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 721 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 722 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 723 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 724 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 725 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 726 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 727 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 728 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 729 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 730 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 731 static usb_error_t urtw_intr_enable(struct urtw_softc *); 732 static usb_error_t urtw_intr_disable(struct urtw_softc *); 733 static usb_error_t urtw_reset(struct urtw_softc *); 734 static usb_error_t urtw_led_on(struct urtw_softc *, int); 735 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 736 static usb_error_t urtw_led_blink(struct urtw_softc *); 737 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 738 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 739 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 740 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 741 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 742 static usb_error_t urtw_rx_enable(struct urtw_softc *); 743 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 744 static void urtw_free_tx_data_list(struct urtw_softc *); 745 static void urtw_free_rx_data_list(struct urtw_softc *); 746 static void urtw_free_data_list(struct urtw_softc *, 747 struct urtw_data data[], int, int); 748 static usb_error_t urtw_adapter_start(struct urtw_softc *); 749 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 750 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 751 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 752 static usb_error_t urtw_do_request(struct urtw_softc *, 753 struct usb_device_request *, void *); 754 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 755 static usb_error_t urtw_led_off(struct urtw_softc *, int); 756 static void urtw_abort_xfers(struct urtw_softc *); 757 static struct urtw_data * 758 urtw_getbuf(struct urtw_softc *sc); 759 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 760 uint8_t); 761 static void urtw_updateslot(struct ieee80211com *); 762 static void urtw_updateslottask(void *, int); 763 static void urtw_sysctl_node(struct urtw_softc *); 764 765 static int 766 urtw_match(device_t dev) 767 { 768 struct usb_attach_arg *uaa = device_get_ivars(dev); 769 770 if (uaa->usb_mode != USB_MODE_HOST) 771 return (ENXIO); 772 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 773 return (ENXIO); 774 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 775 return (ENXIO); 776 777 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 778 } 779 780 static int 781 urtw_attach(device_t dev) 782 { 783 const struct usb_config *setup_start; 784 int ret = ENXIO; 785 struct urtw_softc *sc = device_get_softc(dev); 786 struct usb_attach_arg *uaa = device_get_ivars(dev); 787 struct ieee80211com *ic = &sc->sc_ic; 788 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */ 789 uint16_t n_setup; 790 uint32_t data; 791 usb_error_t error; 792 793 device_set_usb_desc(dev); 794 795 sc->sc_dev = dev; 796 sc->sc_udev = uaa->device; 797 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 798 sc->sc_flags |= URTW_RTL8187B; 799 #ifdef URTW_DEBUG 800 sc->sc_debug = urtw_debug; 801 #endif 802 803 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 804 MTX_DEF); 805 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 806 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 807 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 808 callout_init(&sc->sc_watchdog_ch, 0); 809 mbufq_init(&sc->sc_snd, ifqmaxlen); 810 811 if (sc->sc_flags & URTW_RTL8187B) { 812 setup_start = urtw_8187b_usbconfig; 813 n_setup = URTW_8187B_N_XFERS; 814 } else { 815 setup_start = urtw_8187l_usbconfig; 816 n_setup = URTW_8187L_N_XFERS; 817 } 818 819 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 820 setup_start, n_setup, sc, &sc->sc_mtx); 821 if (error) { 822 device_printf(dev, "could not allocate USB transfers, " 823 "err=%s\n", usbd_errstr(error)); 824 ret = ENXIO; 825 goto fail0; 826 } 827 828 if (sc->sc_flags & URTW_RTL8187B) { 829 sc->sc_tx_dma_buf = 830 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 831 URTW_8187B_BULK_TX_BE], 0); 832 } else { 833 sc->sc_tx_dma_buf = 834 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 835 URTW_8187L_BULK_TX_LOW], 0); 836 } 837 838 URTW_LOCK(sc); 839 840 urtw_read32_m(sc, URTW_RX, &data); 841 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 842 URTW_EEPROM_93C46; 843 844 error = urtw_get_rfchip(sc); 845 if (error != 0) 846 goto fail; 847 error = urtw_get_macaddr(sc); 848 if (error != 0) 849 goto fail; 850 error = urtw_get_txpwr(sc); 851 if (error != 0) 852 goto fail; 853 error = urtw_led_init(sc); 854 if (error != 0) 855 goto fail; 856 857 URTW_UNLOCK(sc); 858 859 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 860 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 861 sc->sc_currate = 3; 862 sc->sc_preamble_mode = urtw_preamble_mode; 863 864 ic->ic_softc = sc; 865 ic->ic_name = device_get_nameunit(dev); 866 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 867 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 868 869 /* set device capabilities */ 870 ic->ic_caps = 871 IEEE80211_C_STA | /* station mode */ 872 IEEE80211_C_MONITOR | /* monitor mode supported */ 873 IEEE80211_C_TXPMGT | /* tx power management */ 874 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 875 IEEE80211_C_SHSLOT | /* short slot time supported */ 876 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 877 IEEE80211_C_WPA; /* 802.11i */ 878 879 bands = 0; 880 setbit(&bands, IEEE80211_MODE_11B); 881 setbit(&bands, IEEE80211_MODE_11G); 882 ieee80211_init_channels(ic, NULL, &bands); 883 884 ieee80211_ifattach(ic); 885 ic->ic_raw_xmit = urtw_raw_xmit; 886 ic->ic_scan_start = urtw_scan_start; 887 ic->ic_scan_end = urtw_scan_end; 888 ic->ic_set_channel = urtw_set_channel; 889 ic->ic_updateslot = urtw_updateslot; 890 ic->ic_vap_create = urtw_vap_create; 891 ic->ic_vap_delete = urtw_vap_delete; 892 ic->ic_update_mcast = urtw_update_mcast; 893 ic->ic_parent = urtw_parent; 894 ic->ic_transmit = urtw_transmit; 895 896 ieee80211_radiotap_attach(ic, 897 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 898 URTW_TX_RADIOTAP_PRESENT, 899 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 900 URTW_RX_RADIOTAP_PRESENT); 901 902 urtw_sysctl_node(sc); 903 904 if (bootverbose) 905 ieee80211_announce(ic); 906 return (0); 907 908 fail: 909 URTW_UNLOCK(sc); 910 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 911 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 912 fail0: 913 return (ret); 914 } 915 916 static int 917 urtw_detach(device_t dev) 918 { 919 struct urtw_softc *sc = device_get_softc(dev); 920 struct ieee80211com *ic = &sc->sc_ic; 921 unsigned int x; 922 unsigned int n_xfers; 923 924 /* Prevent further ioctls */ 925 URTW_LOCK(sc); 926 sc->sc_flags |= URTW_DETACHED; 927 urtw_stop(sc); 928 URTW_UNLOCK(sc); 929 930 ieee80211_draintask(ic, &sc->sc_updateslot_task); 931 ieee80211_draintask(ic, &sc->sc_led_task); 932 933 usb_callout_drain(&sc->sc_led_ch); 934 callout_drain(&sc->sc_watchdog_ch); 935 936 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 937 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 938 939 /* prevent further allocations from RX/TX data lists */ 940 URTW_LOCK(sc); 941 STAILQ_INIT(&sc->sc_tx_active); 942 STAILQ_INIT(&sc->sc_tx_inactive); 943 STAILQ_INIT(&sc->sc_tx_pending); 944 945 STAILQ_INIT(&sc->sc_rx_active); 946 STAILQ_INIT(&sc->sc_rx_inactive); 947 URTW_UNLOCK(sc); 948 949 /* drain USB transfers */ 950 for (x = 0; x != n_xfers; x++) 951 usbd_transfer_drain(sc->sc_xfer[x]); 952 953 /* free data buffers */ 954 URTW_LOCK(sc); 955 urtw_free_tx_data_list(sc); 956 urtw_free_rx_data_list(sc); 957 URTW_UNLOCK(sc); 958 959 /* free USB transfers and some data buffers */ 960 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 961 962 ieee80211_ifdetach(ic); 963 mbufq_drain(&sc->sc_snd); 964 mtx_destroy(&sc->sc_mtx); 965 return (0); 966 } 967 968 static void 969 urtw_free_tx_data_list(struct urtw_softc *sc) 970 { 971 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 972 } 973 974 static void 975 urtw_free_rx_data_list(struct urtw_softc *sc) 976 { 977 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 978 } 979 980 static void 981 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 982 int fillmbuf) 983 { 984 int i; 985 986 for (i = 0; i < ndata; i++) { 987 struct urtw_data *dp = &data[i]; 988 989 if (fillmbuf == 1) { 990 if (dp->m != NULL) { 991 m_freem(dp->m); 992 dp->m = NULL; 993 dp->buf = NULL; 994 } 995 } else { 996 dp->buf = NULL; 997 } 998 if (dp->ni != NULL) { 999 ieee80211_free_node(dp->ni); 1000 dp->ni = NULL; 1001 } 1002 } 1003 } 1004 1005 static struct ieee80211vap * 1006 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1007 enum ieee80211_opmode opmode, int flags, 1008 const uint8_t bssid[IEEE80211_ADDR_LEN], 1009 const uint8_t mac[IEEE80211_ADDR_LEN]) 1010 { 1011 struct urtw_vap *uvp; 1012 struct ieee80211vap *vap; 1013 1014 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1015 return (NULL); 1016 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1017 vap = &uvp->vap; 1018 /* enable s/w bmiss handling for sta mode */ 1019 1020 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1021 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1022 /* out of memory */ 1023 free(uvp, M_80211_VAP); 1024 return (NULL); 1025 } 1026 1027 /* override state transition machine */ 1028 uvp->newstate = vap->iv_newstate; 1029 vap->iv_newstate = urtw_newstate; 1030 1031 /* complete setup */ 1032 ieee80211_vap_attach(vap, ieee80211_media_change, 1033 ieee80211_media_status, mac); 1034 ic->ic_opmode = opmode; 1035 return (vap); 1036 } 1037 1038 static void 1039 urtw_vap_delete(struct ieee80211vap *vap) 1040 { 1041 struct urtw_vap *uvp = URTW_VAP(vap); 1042 1043 ieee80211_vap_detach(vap); 1044 free(uvp, M_80211_VAP); 1045 } 1046 1047 static void 1048 urtw_init(struct urtw_softc *sc) 1049 { 1050 usb_error_t error; 1051 int ret; 1052 1053 URTW_ASSERT_LOCKED(sc); 1054 1055 if (sc->sc_flags & URTW_RUNNING) 1056 urtw_stop(sc); 1057 1058 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1059 urtw_adapter_start(sc); 1060 if (error != 0) 1061 goto fail; 1062 1063 /* reset softc variables */ 1064 sc->sc_txtimer = 0; 1065 1066 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1067 ret = urtw_alloc_rx_data_list(sc); 1068 if (ret != 0) 1069 goto fail; 1070 ret = urtw_alloc_tx_data_list(sc); 1071 if (ret != 0) 1072 goto fail; 1073 sc->sc_flags |= URTW_INIT_ONCE; 1074 } 1075 1076 error = urtw_rx_enable(sc); 1077 if (error != 0) 1078 goto fail; 1079 error = urtw_tx_enable(sc); 1080 if (error != 0) 1081 goto fail; 1082 1083 if (sc->sc_flags & URTW_RTL8187B) 1084 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1085 1086 sc->sc_flags |= URTW_RUNNING; 1087 1088 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1089 fail: 1090 return; 1091 } 1092 1093 static usb_error_t 1094 urtw_adapter_start_b(struct urtw_softc *sc) 1095 { 1096 uint8_t data8; 1097 usb_error_t error; 1098 1099 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1100 if (error) 1101 goto fail; 1102 1103 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1104 urtw_write8_m(sc, URTW_CONFIG3, 1105 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1106 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1107 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1108 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1109 1110 urtw_write8_m(sc, 0x61, 0x10); 1111 urtw_read8_m(sc, 0x62, &data8); 1112 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1113 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1114 1115 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1116 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1117 urtw_write8_m(sc, URTW_CONFIG3, data8); 1118 1119 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1120 if (error) 1121 goto fail; 1122 1123 error = urtw_8187b_cmd_reset(sc); 1124 if (error) 1125 goto fail; 1126 1127 error = sc->sc_rf_init(sc); 1128 if (error != 0) 1129 goto fail; 1130 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1131 1132 /* fix RTL8187B RX stall */ 1133 error = urtw_intr_enable(sc); 1134 if (error) 1135 goto fail; 1136 1137 error = urtw_write8e(sc, 0x41, 0xf4); 1138 if (error) 1139 goto fail; 1140 error = urtw_write8e(sc, 0x40, 0x00); 1141 if (error) 1142 goto fail; 1143 error = urtw_write8e(sc, 0x42, 0x00); 1144 if (error) 1145 goto fail; 1146 error = urtw_write8e(sc, 0x42, 0x01); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x40, 0x0f); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x00); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x42, 0x01); 1156 if (error) 1157 goto fail; 1158 1159 urtw_read8_m(sc, 0xdb, &data8); 1160 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1161 urtw_write16_m(sc, 0x372, 0x59fa); 1162 urtw_write16_m(sc, 0x374, 0x59d2); 1163 urtw_write16_m(sc, 0x376, 0x59d2); 1164 urtw_write16_m(sc, 0x378, 0x19fa); 1165 urtw_write16_m(sc, 0x37a, 0x19fa); 1166 urtw_write16_m(sc, 0x37c, 0x00d0); 1167 urtw_write8_m(sc, 0x61, 0); 1168 1169 urtw_write8_m(sc, 0x180, 0x0f); 1170 urtw_write8_m(sc, 0x183, 0x03); 1171 urtw_write8_m(sc, 0xda, 0x10); 1172 urtw_write8_m(sc, 0x24d, 0x08); 1173 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1174 1175 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1176 fail: 1177 return (error); 1178 } 1179 1180 static usb_error_t 1181 urtw_adapter_start(struct urtw_softc *sc) 1182 { 1183 struct ieee80211com *ic = &sc->sc_ic; 1184 usb_error_t error; 1185 1186 error = urtw_reset(sc); 1187 if (error) 1188 goto fail; 1189 1190 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1191 urtw_write8_m(sc, URTW_GPIO, 0); 1192 1193 /* for led */ 1194 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1195 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1196 if (error != 0) 1197 goto fail; 1198 1199 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1200 if (error) 1201 goto fail; 1202 /* applying MAC address again. */ 1203 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1204 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1205 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1206 if (error) 1207 goto fail; 1208 1209 error = urtw_update_msr(sc); 1210 if (error) 1211 goto fail; 1212 1213 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1214 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1215 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1216 error = urtw_set_rate(sc); 1217 if (error != 0) 1218 goto fail; 1219 1220 error = sc->sc_rf_init(sc); 1221 if (error != 0) 1222 goto fail; 1223 if (sc->sc_rf_set_sens != NULL) 1224 sc->sc_rf_set_sens(sc, sc->sc_sens); 1225 1226 /* XXX correct? to call write16 */ 1227 urtw_write16_m(sc, URTW_PSR, 1); 1228 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1229 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1230 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1231 /* XXX correct? to call write16 */ 1232 urtw_write16_m(sc, URTW_PSR, 0); 1233 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1234 1235 error = urtw_intr_enable(sc); 1236 if (error != 0) 1237 goto fail; 1238 1239 fail: 1240 return (error); 1241 } 1242 1243 static usb_error_t 1244 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1245 { 1246 uint8_t data; 1247 usb_error_t error; 1248 1249 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1250 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1251 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1252 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1253 fail: 1254 return (error); 1255 } 1256 1257 static usb_error_t 1258 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1259 { 1260 int i; 1261 uint8_t data8; 1262 usb_error_t error; 1263 1264 /* XXX the code can be duplicate with urtw_reset(). */ 1265 urtw_read8_m(sc, URTW_CMD, &data8); 1266 data8 = (data8 & 0x2) | URTW_CMD_RST; 1267 urtw_write8_m(sc, URTW_CMD, data8); 1268 1269 for (i = 0; i < 20; i++) { 1270 usb_pause_mtx(&sc->sc_mtx, 2); 1271 urtw_read8_m(sc, URTW_CMD, &data8); 1272 if (!(data8 & URTW_CMD_RST)) 1273 break; 1274 } 1275 if (i >= 20) { 1276 device_printf(sc->sc_dev, "reset timeout\n"); 1277 goto fail; 1278 } 1279 fail: 1280 return (error); 1281 } 1282 1283 static usb_error_t 1284 urtw_do_request(struct urtw_softc *sc, 1285 struct usb_device_request *req, void *data) 1286 { 1287 usb_error_t err; 1288 int ntries = 10; 1289 1290 URTW_ASSERT_LOCKED(sc); 1291 1292 while (ntries--) { 1293 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1294 req, data, 0, NULL, 250 /* ms */); 1295 if (err == 0) 1296 break; 1297 1298 DPRINTF(sc, URTW_DEBUG_INIT, 1299 "Control request failed, %s (retrying)\n", 1300 usbd_errstr(err)); 1301 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1302 } 1303 return (err); 1304 } 1305 1306 static void 1307 urtw_stop(struct urtw_softc *sc) 1308 { 1309 uint8_t data8; 1310 usb_error_t error; 1311 1312 URTW_ASSERT_LOCKED(sc); 1313 1314 sc->sc_flags &= ~URTW_RUNNING; 1315 1316 error = urtw_intr_disable(sc); 1317 if (error) 1318 goto fail; 1319 urtw_read8_m(sc, URTW_CMD, &data8); 1320 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1321 urtw_write8_m(sc, URTW_CMD, data8); 1322 1323 error = sc->sc_rf_stop(sc); 1324 if (error != 0) 1325 goto fail; 1326 1327 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1328 if (error) 1329 goto fail; 1330 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1331 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1332 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1333 if (error) 1334 goto fail; 1335 fail: 1336 if (error) 1337 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1338 usbd_errstr(error)); 1339 1340 usb_callout_stop(&sc->sc_led_ch); 1341 callout_stop(&sc->sc_watchdog_ch); 1342 1343 urtw_abort_xfers(sc); 1344 } 1345 1346 static void 1347 urtw_abort_xfers(struct urtw_softc *sc) 1348 { 1349 int i, max; 1350 1351 URTW_ASSERT_LOCKED(sc); 1352 1353 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1354 URTW_8187L_N_XFERS; 1355 1356 /* abort any pending transfers */ 1357 for (i = 0; i < max; i++) 1358 usbd_transfer_stop(sc->sc_xfer[i]); 1359 } 1360 1361 static void 1362 urtw_parent(struct ieee80211com *ic) 1363 { 1364 struct urtw_softc *sc = ic->ic_softc; 1365 int startall = 0; 1366 1367 URTW_LOCK(sc); 1368 if (sc->sc_flags & URTW_DETACHED) { 1369 URTW_UNLOCK(sc); 1370 return; 1371 } 1372 1373 if (ic->ic_nrunning > 0) { 1374 if (sc->sc_flags & URTW_RUNNING) { 1375 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1376 urtw_set_multi(sc); 1377 } else { 1378 urtw_init(sc); 1379 startall = 1; 1380 } 1381 } else if (sc->sc_flags & URTW_RUNNING) 1382 urtw_stop(sc); 1383 URTW_UNLOCK(sc); 1384 if (startall) 1385 ieee80211_start_all(ic); 1386 } 1387 1388 static int 1389 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1390 { 1391 struct urtw_softc *sc = ic->ic_softc; 1392 int error; 1393 1394 URTW_LOCK(sc); 1395 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1396 URTW_UNLOCK(sc); 1397 return (ENXIO); 1398 } 1399 error = mbufq_enqueue(&sc->sc_snd, m); 1400 if (error) { 1401 URTW_UNLOCK(sc); 1402 return (error); 1403 } 1404 urtw_start(sc); 1405 URTW_UNLOCK(sc); 1406 1407 return (0); 1408 } 1409 1410 static void 1411 urtw_start(struct urtw_softc *sc) 1412 { 1413 struct urtw_data *bf; 1414 struct ieee80211_node *ni; 1415 struct mbuf *m; 1416 1417 URTW_ASSERT_LOCKED(sc); 1418 1419 if ((sc->sc_flags & URTW_RUNNING) == 0) 1420 return; 1421 1422 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1423 bf = urtw_getbuf(sc); 1424 if (bf == NULL) { 1425 mbufq_prepend(&sc->sc_snd, m); 1426 break; 1427 } 1428 1429 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1430 m->m_pkthdr.rcvif = NULL; 1431 1432 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1433 if_inc_counter(ni->ni_vap->iv_ifp, 1434 IFCOUNTER_OERRORS, 1); 1435 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1436 ieee80211_free_node(ni); 1437 break; 1438 } 1439 1440 sc->sc_txtimer = 5; 1441 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1442 } 1443 } 1444 1445 static int 1446 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1447 int ndata, int maxsz, void *dma_buf) 1448 { 1449 int i, error; 1450 1451 for (i = 0; i < ndata; i++) { 1452 struct urtw_data *dp = &data[i]; 1453 1454 dp->sc = sc; 1455 if (dma_buf == NULL) { 1456 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1457 if (dp->m == NULL) { 1458 device_printf(sc->sc_dev, 1459 "could not allocate rx mbuf\n"); 1460 error = ENOMEM; 1461 goto fail; 1462 } 1463 dp->buf = mtod(dp->m, uint8_t *); 1464 } else { 1465 dp->m = NULL; 1466 dp->buf = ((uint8_t *)dma_buf) + 1467 (i * maxsz); 1468 } 1469 dp->ni = NULL; 1470 } 1471 return (0); 1472 1473 fail: urtw_free_data_list(sc, data, ndata, 1); 1474 return (error); 1475 } 1476 1477 static int 1478 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1479 { 1480 int error, i; 1481 1482 error = urtw_alloc_data_list(sc, 1483 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1484 MCLBYTES, NULL /* mbufs */); 1485 if (error != 0) 1486 return (error); 1487 1488 STAILQ_INIT(&sc->sc_rx_active); 1489 STAILQ_INIT(&sc->sc_rx_inactive); 1490 1491 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1492 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1493 1494 return (0); 1495 } 1496 1497 static int 1498 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1499 { 1500 int error, i; 1501 1502 error = urtw_alloc_data_list(sc, 1503 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1504 sc->sc_tx_dma_buf /* no mbufs */); 1505 if (error != 0) 1506 return (error); 1507 1508 STAILQ_INIT(&sc->sc_tx_active); 1509 STAILQ_INIT(&sc->sc_tx_inactive); 1510 STAILQ_INIT(&sc->sc_tx_pending); 1511 1512 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1513 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1514 next); 1515 1516 return (0); 1517 } 1518 1519 static int 1520 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1521 const struct ieee80211_bpf_params *params) 1522 { 1523 struct ieee80211com *ic = ni->ni_ic; 1524 struct urtw_softc *sc = ic->ic_softc; 1525 struct urtw_data *bf; 1526 1527 /* prevent management frames from being sent if we're not ready */ 1528 if (!(sc->sc_flags & URTW_RUNNING)) { 1529 m_freem(m); 1530 ieee80211_free_node(ni); 1531 return ENETDOWN; 1532 } 1533 URTW_LOCK(sc); 1534 bf = urtw_getbuf(sc); 1535 if (bf == NULL) { 1536 ieee80211_free_node(ni); 1537 m_freem(m); 1538 URTW_UNLOCK(sc); 1539 return (ENOBUFS); /* XXX */ 1540 } 1541 1542 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1543 ieee80211_free_node(ni); 1544 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1545 URTW_UNLOCK(sc); 1546 return (EIO); 1547 } 1548 URTW_UNLOCK(sc); 1549 1550 sc->sc_txtimer = 5; 1551 return (0); 1552 } 1553 1554 static void 1555 urtw_scan_start(struct ieee80211com *ic) 1556 { 1557 1558 /* XXX do nothing? */ 1559 } 1560 1561 static void 1562 urtw_scan_end(struct ieee80211com *ic) 1563 { 1564 1565 /* XXX do nothing? */ 1566 } 1567 1568 static void 1569 urtw_set_channel(struct ieee80211com *ic) 1570 { 1571 struct urtw_softc *sc = ic->ic_softc; 1572 uint32_t data, orig; 1573 usb_error_t error; 1574 1575 /* 1576 * if the user set a channel explicitly using ifconfig(8) this function 1577 * can be called earlier than we're expected that in some cases the 1578 * initialization would be failed if setting a channel is called before 1579 * the init have done. 1580 */ 1581 if (!(sc->sc_flags & URTW_RUNNING)) 1582 return; 1583 1584 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1585 return; 1586 1587 URTW_LOCK(sc); 1588 1589 /* 1590 * during changing th channel we need to temporarily be disable 1591 * TX. 1592 */ 1593 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1594 data = orig & ~URTW_TX_LOOPBACK_MASK; 1595 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1596 1597 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1598 if (error != 0) 1599 goto fail; 1600 usb_pause_mtx(&sc->sc_mtx, 10); 1601 urtw_write32_m(sc, URTW_TX_CONF, orig); 1602 1603 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1604 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1605 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1606 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1607 1608 fail: 1609 URTW_UNLOCK(sc); 1610 1611 sc->sc_curchan = ic->ic_curchan; 1612 1613 if (error != 0) 1614 device_printf(sc->sc_dev, "could not change the channel\n"); 1615 } 1616 1617 static void 1618 urtw_update_mcast(struct ieee80211com *ic) 1619 { 1620 1621 /* XXX do nothing? */ 1622 } 1623 1624 static int 1625 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1626 struct urtw_data *data, int prior) 1627 { 1628 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1629 struct ieee80211_key *k; 1630 const struct ieee80211_txparam *tp; 1631 struct ieee80211com *ic = &sc->sc_ic; 1632 struct ieee80211vap *vap = ni->ni_vap; 1633 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1634 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1635 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1636 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1637 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1638 }; 1639 struct usb_xfer *xfer; 1640 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, 1641 pkttime = 0, txdur = 0, isshort = 0, xferlen; 1642 uint16_t acktime, rtstime, ctstime; 1643 uint32_t flags; 1644 usb_error_t error; 1645 1646 URTW_ASSERT_LOCKED(sc); 1647 1648 /* 1649 * Software crypto. 1650 */ 1651 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1652 k = ieee80211_crypto_encap(ni, m0); 1653 if (k == NULL) { 1654 device_printf(sc->sc_dev, 1655 "ieee80211_crypto_encap returns NULL.\n"); 1656 /* XXX we don't expect the fragmented frames */ 1657 m_freem(m0); 1658 return (ENOBUFS); 1659 } 1660 1661 /* in case packet header moved, reset pointer */ 1662 wh = mtod(m0, struct ieee80211_frame *); 1663 } 1664 1665 if (ieee80211_radiotap_active_vap(vap)) { 1666 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1667 1668 /* XXX Are variables correct? */ 1669 tap->wt_flags = 0; 1670 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1671 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1672 1673 ieee80211_radiotap_tx(vap, m0); 1674 } 1675 1676 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT || 1677 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { 1678 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1679 rate = tp->mgmtrate; 1680 } else { 1681 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1682 /* for data frames */ 1683 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1684 rate = tp->mcastrate; 1685 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1686 rate = tp->ucastrate; 1687 else 1688 rate = urtw_rtl2rate(sc->sc_currate); 1689 } 1690 1691 sc->sc_stats.txrates[sc->sc_currate]++; 1692 1693 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1694 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1695 IEEE80211_CRC_LEN, rate, 0, 0); 1696 else { 1697 acktime = urtw_compute_txtime(14, 2,0, 0); 1698 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1699 rtsenable = 1; 1700 ctsenable = 0; 1701 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1702 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1703 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1704 IEEE80211_CRC_LEN, rate, 0, isshort); 1705 rtsdur = ctstime + pkttime + acktime + 1706 3 * URTW_ASIFS_TIME; 1707 txdur = rtstime + rtsdur; 1708 } else { 1709 rtsenable = ctsenable = rtsdur = 0; 1710 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1711 IEEE80211_CRC_LEN, rate, 0, isshort); 1712 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1713 } 1714 1715 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1716 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1717 IEEE80211_CRC_LEN, rate, 0, isshort) + 1718 3 * URTW_ASIFS_TIME + 1719 2 * acktime; 1720 else 1721 dur = URTW_ASIFS_TIME + acktime; 1722 } 1723 USETW(wh->i_dur, dur); 1724 1725 xferlen = m0->m_pkthdr.len; 1726 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1727 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1728 xferlen += 1; 1729 1730 memset(data->buf, 0, URTW_TX_MAXSIZE); 1731 flags = m0->m_pkthdr.len & 0xfff; 1732 flags |= URTW_TX_FLAG_NO_ENC; 1733 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1734 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1735 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1736 (sc->sc_currate != 0)) 1737 flags |= URTW_TX_FLAG_SPLCP; 1738 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1739 flags |= URTW_TX_FLAG_MOREFRAG; 1740 1741 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1742 1743 if (sc->sc_flags & URTW_RTL8187B) { 1744 struct urtw_8187b_txhdr *tx; 1745 1746 tx = (struct urtw_8187b_txhdr *)data->buf; 1747 if (ctsenable) 1748 flags |= URTW_TX_FLAG_CTS; 1749 if (rtsenable) { 1750 flags |= URTW_TX_FLAG_RTS; 1751 flags |= (urtw_rate2rtl(11) & 0xf) << 1752 URTW_TX_FLAG_RTSRATE_SHIFT; 1753 tx->rtsdur = rtsdur; 1754 } 1755 tx->flag = htole32(flags); 1756 tx->txdur = txdur; 1757 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1758 IEEE80211_FC0_TYPE_MGT && 1759 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1760 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1761 tx->retry = 1; 1762 else 1763 tx->retry = URTW_TX_MAXRETRY; 1764 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1765 } else { 1766 struct urtw_8187l_txhdr *tx; 1767 1768 tx = (struct urtw_8187l_txhdr *)data->buf; 1769 if (rtsenable) { 1770 flags |= URTW_TX_FLAG_RTS; 1771 tx->rtsdur = rtsdur; 1772 } 1773 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT; 1774 tx->flag = htole32(flags); 1775 tx->retry = 3; /* CW minimum */ 1776 tx->retry = 7 << 4; /* CW maximum */ 1777 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */ 1778 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1779 } 1780 1781 data->buflen = xferlen; 1782 data->ni = ni; 1783 data->m = m0; 1784 1785 if (sc->sc_flags & URTW_RTL8187B) { 1786 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1787 case IEEE80211_FC0_TYPE_CTL: 1788 case IEEE80211_FC0_TYPE_MGT: 1789 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1790 break; 1791 default: 1792 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1793 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1794 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1795 break; 1796 } 1797 } else 1798 xfer = (prior == URTW_PRIORITY_LOW) ? 1799 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1800 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1801 1802 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1803 usbd_transfer_start(xfer); 1804 1805 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1806 if (error != 0) 1807 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1808 error); 1809 return (0); 1810 } 1811 1812 static int 1813 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1814 { 1815 struct ieee80211com *ic = vap->iv_ic; 1816 struct urtw_softc *sc = ic->ic_softc; 1817 struct urtw_vap *uvp = URTW_VAP(vap); 1818 struct ieee80211_node *ni; 1819 usb_error_t error = 0; 1820 1821 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1822 ieee80211_state_name[vap->iv_state], 1823 ieee80211_state_name[nstate]); 1824 1825 sc->sc_state = nstate; 1826 1827 IEEE80211_UNLOCK(ic); 1828 URTW_LOCK(sc); 1829 usb_callout_stop(&sc->sc_led_ch); 1830 callout_stop(&sc->sc_watchdog_ch); 1831 1832 switch (nstate) { 1833 case IEEE80211_S_INIT: 1834 case IEEE80211_S_SCAN: 1835 case IEEE80211_S_AUTH: 1836 case IEEE80211_S_ASSOC: 1837 break; 1838 case IEEE80211_S_RUN: 1839 ni = ieee80211_ref_node(vap->iv_bss); 1840 /* setting bssid. */ 1841 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1842 urtw_write16_m(sc, URTW_BSSID + 4, 1843 ((uint16_t *)ni->ni_bssid)[2]); 1844 urtw_update_msr(sc); 1845 /* XXX maybe the below would be incorrect. */ 1846 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1847 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1848 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1849 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1850 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1851 if (error != 0) 1852 device_printf(sc->sc_dev, 1853 "could not control LED (%d)\n", error); 1854 ieee80211_free_node(ni); 1855 break; 1856 default: 1857 break; 1858 } 1859 fail: 1860 URTW_UNLOCK(sc); 1861 IEEE80211_LOCK(ic); 1862 return (uvp->newstate(vap, nstate, arg)); 1863 } 1864 1865 static void 1866 urtw_watchdog(void *arg) 1867 { 1868 struct urtw_softc *sc = arg; 1869 1870 if (sc->sc_txtimer > 0) { 1871 if (--sc->sc_txtimer == 0) { 1872 device_printf(sc->sc_dev, "device timeout\n"); 1873 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1874 return; 1875 } 1876 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1877 } 1878 } 1879 1880 static void 1881 urtw_set_multi(void *arg) 1882 { 1883 /* XXX don't know how to set a device. Lack of docs. */ 1884 } 1885 1886 static usb_error_t 1887 urtw_set_rate(struct urtw_softc *sc) 1888 { 1889 int i, basic_rate, min_rr_rate, max_rr_rate; 1890 uint16_t data; 1891 usb_error_t error; 1892 1893 basic_rate = urtw_rate2rtl(48); 1894 min_rr_rate = urtw_rate2rtl(12); 1895 max_rr_rate = urtw_rate2rtl(48); 1896 1897 urtw_write8_m(sc, URTW_RESP_RATE, 1898 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1899 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1900 1901 urtw_read16_m(sc, URTW_BRSR, &data); 1902 data &= ~URTW_BRSR_MBR_8185; 1903 1904 for (i = 0; i <= basic_rate; i++) 1905 data |= (1 << i); 1906 1907 urtw_write16_m(sc, URTW_BRSR, data); 1908 fail: 1909 return (error); 1910 } 1911 1912 static uint16_t 1913 urtw_rate2rtl(uint32_t rate) 1914 { 1915 int i; 1916 1917 for (i = 0; i < nitems(urtw_ratetable); i++) { 1918 if (rate == urtw_ratetable[i].reg) 1919 return urtw_ratetable[i].val; 1920 } 1921 1922 return (3); 1923 } 1924 1925 static uint16_t 1926 urtw_rtl2rate(uint32_t rate) 1927 { 1928 int i; 1929 1930 for (i = 0; i < nitems(urtw_ratetable); i++) { 1931 if (rate == urtw_ratetable[i].val) 1932 return urtw_ratetable[i].reg; 1933 } 1934 1935 return (0); 1936 } 1937 1938 static usb_error_t 1939 urtw_update_msr(struct urtw_softc *sc) 1940 { 1941 struct ieee80211com *ic = &sc->sc_ic; 1942 uint8_t data; 1943 usb_error_t error; 1944 1945 urtw_read8_m(sc, URTW_MSR, &data); 1946 data &= ~URTW_MSR_LINK_MASK; 1947 1948 if (sc->sc_state == IEEE80211_S_RUN) { 1949 switch (ic->ic_opmode) { 1950 case IEEE80211_M_STA: 1951 case IEEE80211_M_MONITOR: 1952 data |= URTW_MSR_LINK_STA; 1953 if (sc->sc_flags & URTW_RTL8187B) 1954 data |= URTW_MSR_LINK_ENEDCA; 1955 break; 1956 case IEEE80211_M_IBSS: 1957 data |= URTW_MSR_LINK_ADHOC; 1958 break; 1959 case IEEE80211_M_HOSTAP: 1960 data |= URTW_MSR_LINK_HOSTAP; 1961 break; 1962 default: 1963 DPRINTF(sc, URTW_DEBUG_STATE, 1964 "unsupported operation mode 0x%x\n", 1965 ic->ic_opmode); 1966 error = USB_ERR_INVAL; 1967 goto fail; 1968 } 1969 } else 1970 data |= URTW_MSR_LINK_NONE; 1971 1972 urtw_write8_m(sc, URTW_MSR, data); 1973 fail: 1974 return (error); 1975 } 1976 1977 static usb_error_t 1978 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1979 { 1980 struct usb_device_request req; 1981 usb_error_t error; 1982 1983 URTW_ASSERT_LOCKED(sc); 1984 1985 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1986 req.bRequest = URTW_8187_GETREGS_REQ; 1987 USETW(req.wValue, (val & 0xff) | 0xff00); 1988 USETW(req.wIndex, (val >> 8) & 0x3); 1989 USETW(req.wLength, sizeof(uint8_t)); 1990 1991 error = urtw_do_request(sc, &req, data); 1992 return (error); 1993 } 1994 1995 static usb_error_t 1996 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 1997 { 1998 struct usb_device_request req; 1999 usb_error_t error; 2000 2001 URTW_ASSERT_LOCKED(sc); 2002 2003 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2004 req.bRequest = URTW_8187_GETREGS_REQ; 2005 USETW(req.wValue, (val & 0xff) | 0xff00); 2006 USETW(req.wIndex, (val >> 8) & 0x3); 2007 USETW(req.wLength, sizeof(uint16_t)); 2008 2009 error = urtw_do_request(sc, &req, data); 2010 return (error); 2011 } 2012 2013 static usb_error_t 2014 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2015 { 2016 struct usb_device_request req; 2017 usb_error_t error; 2018 2019 URTW_ASSERT_LOCKED(sc); 2020 2021 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2022 req.bRequest = URTW_8187_GETREGS_REQ; 2023 USETW(req.wValue, (val & 0xff) | 0xff00); 2024 USETW(req.wIndex, (val >> 8) & 0x3); 2025 USETW(req.wLength, sizeof(uint32_t)); 2026 2027 error = urtw_do_request(sc, &req, data); 2028 return (error); 2029 } 2030 2031 static usb_error_t 2032 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2033 { 2034 struct usb_device_request req; 2035 2036 URTW_ASSERT_LOCKED(sc); 2037 2038 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2039 req.bRequest = URTW_8187_SETREGS_REQ; 2040 USETW(req.wValue, (val & 0xff) | 0xff00); 2041 USETW(req.wIndex, (val >> 8) & 0x3); 2042 USETW(req.wLength, sizeof(uint8_t)); 2043 2044 return (urtw_do_request(sc, &req, &data)); 2045 } 2046 2047 static usb_error_t 2048 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2049 { 2050 struct usb_device_request req; 2051 2052 URTW_ASSERT_LOCKED(sc); 2053 2054 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2055 req.bRequest = URTW_8187_SETREGS_REQ; 2056 USETW(req.wValue, (val & 0xff) | 0xff00); 2057 USETW(req.wIndex, (val >> 8) & 0x3); 2058 USETW(req.wLength, sizeof(uint16_t)); 2059 2060 return (urtw_do_request(sc, &req, &data)); 2061 } 2062 2063 static usb_error_t 2064 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2065 { 2066 struct usb_device_request req; 2067 2068 URTW_ASSERT_LOCKED(sc); 2069 2070 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2071 req.bRequest = URTW_8187_SETREGS_REQ; 2072 USETW(req.wValue, (val & 0xff) | 0xff00); 2073 USETW(req.wIndex, (val >> 8) & 0x3); 2074 USETW(req.wLength, sizeof(uint32_t)); 2075 2076 return (urtw_do_request(sc, &req, &data)); 2077 } 2078 2079 static usb_error_t 2080 urtw_get_macaddr(struct urtw_softc *sc) 2081 { 2082 struct ieee80211com *ic = &sc->sc_ic; 2083 uint32_t data; 2084 usb_error_t error; 2085 2086 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2087 if (error != 0) 2088 goto fail; 2089 ic->ic_macaddr[0] = data & 0xff; 2090 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2091 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2092 if (error != 0) 2093 goto fail; 2094 ic->ic_macaddr[2] = data & 0xff; 2095 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2096 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2097 if (error != 0) 2098 goto fail; 2099 ic->ic_macaddr[4] = data & 0xff; 2100 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2101 fail: 2102 return (error); 2103 } 2104 2105 static usb_error_t 2106 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2107 { 2108 #define URTW_READCMD_LEN 3 2109 int addrlen, i; 2110 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2111 usb_error_t error; 2112 2113 /* NB: make sure the buffer is initialized */ 2114 *data = 0; 2115 2116 /* enable EPROM programming */ 2117 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2118 DELAY(URTW_EPROM_DELAY); 2119 2120 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2121 if (error != 0) 2122 goto fail; 2123 error = urtw_eprom_ck(sc); 2124 if (error != 0) 2125 goto fail; 2126 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2127 if (error != 0) 2128 goto fail; 2129 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2130 addrlen = 8; 2131 addrstr[0] = addr & (1 << 7); 2132 addrstr[1] = addr & (1 << 6); 2133 addrstr[2] = addr & (1 << 5); 2134 addrstr[3] = addr & (1 << 4); 2135 addrstr[4] = addr & (1 << 3); 2136 addrstr[5] = addr & (1 << 2); 2137 addrstr[6] = addr & (1 << 1); 2138 addrstr[7] = addr & (1 << 0); 2139 } else { 2140 addrlen=6; 2141 addrstr[0] = addr & (1 << 5); 2142 addrstr[1] = addr & (1 << 4); 2143 addrstr[2] = addr & (1 << 3); 2144 addrstr[3] = addr & (1 << 2); 2145 addrstr[4] = addr & (1 << 1); 2146 addrstr[5] = addr & (1 << 0); 2147 } 2148 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2149 if (error != 0) 2150 goto fail; 2151 2152 error = urtw_eprom_writebit(sc, 0); 2153 if (error != 0) 2154 goto fail; 2155 2156 for (i = 0; i < 16; i++) { 2157 error = urtw_eprom_ck(sc); 2158 if (error != 0) 2159 goto fail; 2160 error = urtw_eprom_readbit(sc, &data16); 2161 if (error != 0) 2162 goto fail; 2163 2164 (*data) |= (data16 << (15 - i)); 2165 } 2166 2167 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2168 if (error != 0) 2169 goto fail; 2170 error = urtw_eprom_ck(sc); 2171 if (error != 0) 2172 goto fail; 2173 2174 /* now disable EPROM programming */ 2175 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2176 fail: 2177 return (error); 2178 #undef URTW_READCMD_LEN 2179 } 2180 2181 static usb_error_t 2182 urtw_eprom_cs(struct urtw_softc *sc, int able) 2183 { 2184 uint8_t data; 2185 usb_error_t error; 2186 2187 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2188 if (able == URTW_EPROM_ENABLE) 2189 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2190 else 2191 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2192 DELAY(URTW_EPROM_DELAY); 2193 fail: 2194 return (error); 2195 } 2196 2197 static usb_error_t 2198 urtw_eprom_ck(struct urtw_softc *sc) 2199 { 2200 uint8_t data; 2201 usb_error_t error; 2202 2203 /* masking */ 2204 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2205 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2206 DELAY(URTW_EPROM_DELAY); 2207 /* unmasking */ 2208 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2209 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2210 DELAY(URTW_EPROM_DELAY); 2211 fail: 2212 return (error); 2213 } 2214 2215 static usb_error_t 2216 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2217 { 2218 uint8_t data8; 2219 usb_error_t error; 2220 2221 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2222 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2223 DELAY(URTW_EPROM_DELAY); 2224 2225 fail: 2226 return (error); 2227 } 2228 2229 static usb_error_t 2230 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2231 { 2232 uint8_t data; 2233 usb_error_t error; 2234 2235 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2236 if (bit != 0) 2237 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2238 else 2239 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2240 DELAY(URTW_EPROM_DELAY); 2241 fail: 2242 return (error); 2243 } 2244 2245 static usb_error_t 2246 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2247 { 2248 int i = 0; 2249 usb_error_t error = 0; 2250 2251 for (i = 0; i < buflen; i++) { 2252 error = urtw_eprom_writebit(sc, buf[i]); 2253 if (error != 0) 2254 goto fail; 2255 error = urtw_eprom_ck(sc); 2256 if (error != 0) 2257 goto fail; 2258 } 2259 fail: 2260 return (error); 2261 } 2262 2263 2264 static usb_error_t 2265 urtw_get_txpwr(struct urtw_softc *sc) 2266 { 2267 int i, j; 2268 uint32_t data; 2269 usb_error_t error; 2270 2271 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2272 if (error != 0) 2273 goto fail; 2274 sc->sc_txpwr_cck_base = data & 0xf; 2275 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2276 2277 for (i = 1, j = 0; i < 6; i += 2, j++) { 2278 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2279 if (error != 0) 2280 goto fail; 2281 sc->sc_txpwr_cck[i] = data & 0xf; 2282 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2283 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2284 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2285 } 2286 for (i = 1, j = 0; i < 4; i += 2, j++) { 2287 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2288 if (error != 0) 2289 goto fail; 2290 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2291 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2292 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2293 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2294 } 2295 if (sc->sc_flags & URTW_RTL8187B) { 2296 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2297 if (error != 0) 2298 goto fail; 2299 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2300 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2301 error = urtw_eprom_read32(sc, 0x0a, &data); 2302 if (error != 0) 2303 goto fail; 2304 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2305 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2306 error = urtw_eprom_read32(sc, 0x1c, &data); 2307 if (error != 0) 2308 goto fail; 2309 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2310 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2311 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2312 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2313 } else { 2314 for (i = 1, j = 0; i < 4; i += 2, j++) { 2315 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2316 &data); 2317 if (error != 0) 2318 goto fail; 2319 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2320 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2321 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2322 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2323 } 2324 } 2325 fail: 2326 return (error); 2327 } 2328 2329 2330 static usb_error_t 2331 urtw_get_rfchip(struct urtw_softc *sc) 2332 { 2333 int ret; 2334 uint8_t data8; 2335 uint32_t data; 2336 usb_error_t error; 2337 2338 if (sc->sc_flags & URTW_RTL8187B) { 2339 urtw_read8_m(sc, 0xe1, &data8); 2340 switch (data8) { 2341 case 0: 2342 sc->sc_flags |= URTW_RTL8187B_REV_B; 2343 break; 2344 case 1: 2345 sc->sc_flags |= URTW_RTL8187B_REV_D; 2346 break; 2347 case 2: 2348 sc->sc_flags |= URTW_RTL8187B_REV_E; 2349 break; 2350 default: 2351 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2352 sc->sc_flags |= URTW_RTL8187B_REV_B; 2353 break; 2354 } 2355 } else { 2356 urtw_read32_m(sc, URTW_TX_CONF, &data); 2357 switch (data & URTW_TX_HWMASK) { 2358 case URTW_TX_R8187vD_B: 2359 sc->sc_flags |= URTW_RTL8187B; 2360 break; 2361 case URTW_TX_R8187vD: 2362 break; 2363 default: 2364 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2365 data & URTW_TX_HWMASK); 2366 break; 2367 } 2368 } 2369 2370 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2371 if (error != 0) 2372 goto fail; 2373 switch (data & 0xff) { 2374 case URTW_EPROM_RFCHIPID_RTL8225U: 2375 error = urtw_8225_isv2(sc, &ret); 2376 if (error != 0) 2377 goto fail; 2378 if (ret == 0) { 2379 sc->sc_rf_init = urtw_8225_rf_init; 2380 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2381 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2382 sc->sc_rf_stop = urtw_8225_rf_stop; 2383 } else { 2384 sc->sc_rf_init = urtw_8225v2_rf_init; 2385 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2386 sc->sc_rf_stop = urtw_8225_rf_stop; 2387 } 2388 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2389 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2390 break; 2391 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2392 sc->sc_rf_init = urtw_8225v2b_rf_init; 2393 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2394 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2395 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2396 sc->sc_rf_stop = urtw_8225_rf_stop; 2397 break; 2398 default: 2399 DPRINTF(sc, URTW_DEBUG_STATE, 2400 "unsupported RF chip %d\n", data & 0xff); 2401 error = USB_ERR_INVAL; 2402 goto fail; 2403 } 2404 2405 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2406 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2407 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2408 "rtl8225z2", 2409 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2410 (data8 == 1) ? "d" : "e") : "none"); 2411 2412 fail: 2413 return (error); 2414 } 2415 2416 2417 static usb_error_t 2418 urtw_led_init(struct urtw_softc *sc) 2419 { 2420 uint32_t rev; 2421 usb_error_t error; 2422 2423 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2424 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2425 if (error != 0) 2426 goto fail; 2427 2428 switch (rev & URTW_EPROM_CID_MASK) { 2429 case URTW_EPROM_CID_ALPHA0: 2430 sc->sc_strategy = URTW_SW_LED_MODE1; 2431 break; 2432 case URTW_EPROM_CID_SERCOMM_PS: 2433 sc->sc_strategy = URTW_SW_LED_MODE3; 2434 break; 2435 case URTW_EPROM_CID_HW_LED: 2436 sc->sc_strategy = URTW_HW_LED; 2437 break; 2438 case URTW_EPROM_CID_RSVD0: 2439 case URTW_EPROM_CID_RSVD1: 2440 default: 2441 sc->sc_strategy = URTW_SW_LED_MODE0; 2442 break; 2443 } 2444 2445 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2446 2447 fail: 2448 return (error); 2449 } 2450 2451 2452 static usb_error_t 2453 urtw_8225_rf_init(struct urtw_softc *sc) 2454 { 2455 int i; 2456 uint16_t data; 2457 usb_error_t error; 2458 2459 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2460 if (error) 2461 goto fail; 2462 2463 error = urtw_8225_usb_init(sc); 2464 if (error) 2465 goto fail; 2466 2467 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2468 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2469 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2470 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2471 2472 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2473 if (error) 2474 goto fail; 2475 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2476 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2477 if (error) 2478 goto fail; 2479 2480 error = urtw_8185_rf_pins_enable(sc); 2481 if (error) 2482 goto fail; 2483 usb_pause_mtx(&sc->sc_mtx, 1000); 2484 2485 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2486 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2487 urtw_8225_rf_part1[i].val); 2488 usb_pause_mtx(&sc->sc_mtx, 1); 2489 } 2490 usb_pause_mtx(&sc->sc_mtx, 100); 2491 urtw_8225_write(sc, 2492 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2493 usb_pause_mtx(&sc->sc_mtx, 200); 2494 urtw_8225_write(sc, 2495 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2496 usb_pause_mtx(&sc->sc_mtx, 200); 2497 urtw_8225_write(sc, 2498 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2499 2500 for (i = 0; i < 95; i++) { 2501 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2502 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2503 } 2504 2505 urtw_8225_write(sc, 2506 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2507 urtw_8225_write(sc, 2508 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2509 2510 for (i = 0; i < 128; i++) { 2511 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2512 usb_pause_mtx(&sc->sc_mtx, 1); 2513 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2514 usb_pause_mtx(&sc->sc_mtx, 1); 2515 } 2516 2517 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2518 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2519 urtw_8225_rf_part2[i].val); 2520 usb_pause_mtx(&sc->sc_mtx, 1); 2521 } 2522 2523 error = urtw_8225_setgain(sc, 4); 2524 if (error) 2525 goto fail; 2526 2527 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2528 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2529 urtw_8225_rf_part3[i].val); 2530 usb_pause_mtx(&sc->sc_mtx, 1); 2531 } 2532 2533 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2534 2535 error = urtw_8225_set_txpwrlvl(sc, 1); 2536 if (error) 2537 goto fail; 2538 2539 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2540 usb_pause_mtx(&sc->sc_mtx, 1); 2541 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2542 usb_pause_mtx(&sc->sc_mtx, 1); 2543 2544 /* TX ant A, 0x0 for B */ 2545 error = urtw_8185_tx_antenna(sc, 0x3); 2546 if (error) 2547 goto fail; 2548 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2549 2550 error = urtw_8225_rf_set_chan(sc, 1); 2551 fail: 2552 return (error); 2553 } 2554 2555 static usb_error_t 2556 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2557 { 2558 usb_error_t error = 0; 2559 2560 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2561 fail: 2562 return (error); 2563 } 2564 2565 static usb_error_t 2566 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2567 { 2568 usb_error_t error; 2569 2570 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2571 usb_pause_mtx(&sc->sc_mtx, 1); 2572 fail: 2573 return (error); 2574 } 2575 2576 static usb_error_t 2577 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2578 { 2579 2580 data = data & 0xff; 2581 return urtw_8187_write_phy(sc, addr, data); 2582 } 2583 2584 static usb_error_t 2585 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2586 { 2587 2588 data = data & 0xff; 2589 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2590 } 2591 2592 static usb_error_t 2593 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2594 { 2595 uint32_t phyw; 2596 usb_error_t error; 2597 2598 phyw = ((data << 8) | (addr | 0x80)); 2599 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2600 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2601 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2602 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2603 usb_pause_mtx(&sc->sc_mtx, 1); 2604 fail: 2605 return (error); 2606 } 2607 2608 static usb_error_t 2609 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2610 { 2611 usb_error_t error; 2612 2613 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2614 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2615 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2616 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2617 fail: 2618 return (error); 2619 } 2620 2621 static usb_error_t 2622 urtw_8225_usb_init(struct urtw_softc *sc) 2623 { 2624 uint8_t data; 2625 usb_error_t error; 2626 2627 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2628 urtw_write8_m(sc, URTW_GPIO, 0); 2629 error = urtw_read8e(sc, 0x53, &data); 2630 if (error) 2631 goto fail; 2632 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2633 if (error) 2634 goto fail; 2635 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2636 urtw_write8_m(sc, URTW_GPIO, 0x20); 2637 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2638 2639 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2640 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2641 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2642 2643 usb_pause_mtx(&sc->sc_mtx, 500); 2644 fail: 2645 return (error); 2646 } 2647 2648 static usb_error_t 2649 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2650 { 2651 uint16_t d80, d82, d84; 2652 usb_error_t error; 2653 2654 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2655 d80 &= URTW_RF_PINS_MAGIC1; 2656 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2657 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2658 d84 &= URTW_RF_PINS_MAGIC2; 2659 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2660 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2661 DELAY(10); 2662 2663 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2664 DELAY(2); 2665 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2666 DELAY(10); 2667 2668 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2669 if (error != 0) 2670 goto fail; 2671 2672 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2673 DELAY(10); 2674 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2675 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2676 usb_pause_mtx(&sc->sc_mtx, 2); 2677 fail: 2678 return (error); 2679 } 2680 2681 static usb_error_t 2682 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2683 uint16_t *data) 2684 { 2685 uint8_t buf[2]; 2686 uint16_t data16; 2687 struct usb_device_request req; 2688 usb_error_t error = 0; 2689 2690 data16 = *data; 2691 2692 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2693 req.bRequest = URTW_8187_SETREGS_REQ; 2694 USETW(req.wValue, addr); 2695 USETW(req.wIndex, index); 2696 USETW(req.wLength, sizeof(uint16_t)); 2697 buf[0] = (data16 & 0x00ff); 2698 buf[1] = (data16 & 0xff00) >> 8; 2699 2700 error = urtw_do_request(sc, &req, buf); 2701 2702 return (error); 2703 } 2704 2705 static usb_error_t 2706 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2707 { 2708 usb_error_t error; 2709 2710 error = urtw_8225_set_txpwrlvl(sc, chan); 2711 if (error) 2712 goto fail; 2713 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2714 usb_pause_mtx(&sc->sc_mtx, 10); 2715 fail: 2716 return (error); 2717 } 2718 2719 static usb_error_t 2720 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2721 { 2722 usb_error_t error; 2723 2724 if (sens < 0 || sens > 6) 2725 return -1; 2726 2727 if (sens > 4) 2728 urtw_8225_write(sc, 2729 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2730 else 2731 urtw_8225_write(sc, 2732 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2733 2734 sens = 6 - sens; 2735 error = urtw_8225_setgain(sc, sens); 2736 if (error) 2737 goto fail; 2738 2739 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2740 2741 fail: 2742 return (error); 2743 } 2744 2745 static usb_error_t 2746 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2747 { 2748 int i, idx, set; 2749 uint8_t *cck_pwltable; 2750 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2751 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2752 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2753 usb_error_t error; 2754 2755 cck_pwrlvl_max = 11; 2756 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2757 ofdm_pwrlvl_min = 10; 2758 2759 /* CCK power setting */ 2760 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2761 idx = cck_pwrlvl % 6; 2762 set = cck_pwrlvl / 6; 2763 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2764 urtw_8225_txpwr_cck; 2765 2766 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2767 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2768 for (i = 0; i < 8; i++) { 2769 urtw_8187_write_phy_cck(sc, 0x44 + i, 2770 cck_pwltable[idx * 8 + i]); 2771 } 2772 usb_pause_mtx(&sc->sc_mtx, 1); 2773 2774 /* OFDM power setting */ 2775 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2776 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2777 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2778 2779 idx = ofdm_pwrlvl % 6; 2780 set = ofdm_pwrlvl / 6; 2781 2782 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2783 if (error) 2784 goto fail; 2785 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2786 urtw_8187_write_phy_ofdm(sc, 6, 0); 2787 urtw_8187_write_phy_ofdm(sc, 8, 0); 2788 2789 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2790 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2791 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2792 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2793 usb_pause_mtx(&sc->sc_mtx, 1); 2794 fail: 2795 return (error); 2796 } 2797 2798 2799 static usb_error_t 2800 urtw_8225_rf_stop(struct urtw_softc *sc) 2801 { 2802 uint8_t data; 2803 usb_error_t error; 2804 2805 urtw_8225_write(sc, 0x4, 0x1f); 2806 2807 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2808 if (error) 2809 goto fail; 2810 2811 urtw_read8_m(sc, URTW_CONFIG3, &data); 2812 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2813 if (sc->sc_flags & URTW_RTL8187B) { 2814 urtw_write32_m(sc, URTW_ANAPARAM2, 2815 URTW_8187B_8225_ANAPARAM2_OFF); 2816 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2817 urtw_write32_m(sc, URTW_ANAPARAM3, 2818 URTW_8187B_8225_ANAPARAM3_OFF); 2819 } else { 2820 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2821 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2822 } 2823 2824 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2825 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2826 if (error) 2827 goto fail; 2828 2829 fail: 2830 return (error); 2831 } 2832 2833 static usb_error_t 2834 urtw_8225v2_rf_init(struct urtw_softc *sc) 2835 { 2836 int i; 2837 uint16_t data; 2838 uint32_t data32; 2839 usb_error_t error; 2840 2841 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2842 if (error) 2843 goto fail; 2844 2845 error = urtw_8225_usb_init(sc); 2846 if (error) 2847 goto fail; 2848 2849 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2850 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2851 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2852 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2853 2854 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2855 if (error) 2856 goto fail; 2857 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2858 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2859 if (error) 2860 goto fail; 2861 2862 error = urtw_8185_rf_pins_enable(sc); 2863 if (error) 2864 goto fail; 2865 2866 usb_pause_mtx(&sc->sc_mtx, 500); 2867 2868 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2869 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2870 urtw_8225v2_rf_part1[i].val); 2871 } 2872 usb_pause_mtx(&sc->sc_mtx, 50); 2873 2874 urtw_8225_write(sc, 2875 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2876 2877 for (i = 0; i < 95; i++) { 2878 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2879 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2880 urtw_8225v2_rxgain[i]); 2881 } 2882 2883 urtw_8225_write(sc, 2884 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2885 urtw_8225_write(sc, 2886 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2887 urtw_8225_write(sc, 2888 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2889 urtw_8225_write(sc, 2890 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2891 usb_pause_mtx(&sc->sc_mtx, 100); 2892 urtw_8225_write(sc, 2893 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2894 usb_pause_mtx(&sc->sc_mtx, 100); 2895 2896 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2897 if (error != 0) 2898 goto fail; 2899 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2900 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2901 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2902 urtw_8225_write(sc, 2903 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2904 usb_pause_mtx(&sc->sc_mtx, 100); 2905 urtw_8225_write(sc, 2906 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2907 usb_pause_mtx(&sc->sc_mtx, 50); 2908 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2909 if (error != 0) 2910 goto fail; 2911 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2912 device_printf(sc->sc_dev, "RF calibration failed\n"); 2913 } 2914 usb_pause_mtx(&sc->sc_mtx, 100); 2915 2916 urtw_8225_write(sc, 2917 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2918 for (i = 0; i < 128; i++) { 2919 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2920 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2921 } 2922 2923 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2924 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2925 urtw_8225v2_rf_part2[i].val); 2926 } 2927 2928 error = urtw_8225v2_setgain(sc, 4); 2929 if (error) 2930 goto fail; 2931 2932 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2933 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2934 urtw_8225v2_rf_part3[i].val); 2935 } 2936 2937 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2938 2939 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2940 if (error) 2941 goto fail; 2942 2943 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2944 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2945 2946 /* TX ant A, 0x0 for B */ 2947 error = urtw_8185_tx_antenna(sc, 0x3); 2948 if (error) 2949 goto fail; 2950 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2951 2952 error = urtw_8225_rf_set_chan(sc, 1); 2953 fail: 2954 return (error); 2955 } 2956 2957 static usb_error_t 2958 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2959 { 2960 usb_error_t error; 2961 2962 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2963 if (error) 2964 goto fail; 2965 2966 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2967 usb_pause_mtx(&sc->sc_mtx, 10); 2968 fail: 2969 return (error); 2970 } 2971 2972 static usb_error_t 2973 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2974 { 2975 int i; 2976 int16_t bit; 2977 uint8_t rlen = 12, wlen = 6; 2978 uint16_t o1, o2, o3, tmp; 2979 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2980 uint32_t mask = 0x80000000, value = 0; 2981 usb_error_t error; 2982 2983 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 2984 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 2985 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 2986 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 2987 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 2988 o1 &= ~URTW_RF_PINS_MAGIC4; 2989 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 2990 DELAY(5); 2991 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 2992 DELAY(5); 2993 2994 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 2995 bit = ((d2w & mask) != 0) ? 1 : 0; 2996 2997 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 2998 DELAY(2); 2999 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3000 URTW_BB_HOST_BANG_CLK); 3001 DELAY(2); 3002 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3003 URTW_BB_HOST_BANG_CLK); 3004 DELAY(2); 3005 mask = mask >> 1; 3006 if (i == 2) 3007 break; 3008 bit = ((d2w & mask) != 0) ? 1 : 0; 3009 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3010 URTW_BB_HOST_BANG_CLK); 3011 DELAY(2); 3012 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3013 URTW_BB_HOST_BANG_CLK); 3014 DELAY(2); 3015 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3016 DELAY(1); 3017 } 3018 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3019 URTW_BB_HOST_BANG_CLK); 3020 DELAY(2); 3021 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3022 DELAY(2); 3023 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3024 DELAY(2); 3025 3026 mask = 0x800; 3027 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3028 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3029 o1 | URTW_BB_HOST_BANG_RW); 3030 DELAY(2); 3031 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3032 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3033 DELAY(2); 3034 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3035 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3036 DELAY(2); 3037 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3038 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3039 DELAY(2); 3040 3041 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3042 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3044 o1 | URTW_BB_HOST_BANG_RW); 3045 DELAY(2); 3046 } 3047 3048 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3049 URTW_BB_HOST_BANG_RW); 3050 DELAY(2); 3051 3052 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3053 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3054 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3055 3056 if (data != NULL) 3057 *data = value; 3058 fail: 3059 return (error); 3060 } 3061 3062 3063 static usb_error_t 3064 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3065 { 3066 int i; 3067 uint8_t *cck_pwrtable; 3068 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3069 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3070 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3071 usb_error_t error; 3072 3073 /* CCK power setting */ 3074 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3075 cck_pwrlvl += sc->sc_txpwr_cck_base; 3076 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3077 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3078 urtw_8225v2_txpwr_cck; 3079 3080 for (i = 0; i < 8; i++) 3081 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3082 3083 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3084 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3085 usb_pause_mtx(&sc->sc_mtx, 1); 3086 3087 /* OFDM power setting */ 3088 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3089 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3090 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3091 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3092 3093 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3094 if (error) 3095 goto fail; 3096 3097 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3098 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3099 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3100 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3101 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3102 3103 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3104 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3105 usb_pause_mtx(&sc->sc_mtx, 1); 3106 fail: 3107 return (error); 3108 } 3109 3110 static usb_error_t 3111 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3112 { 3113 uint8_t *gainp; 3114 usb_error_t error; 3115 3116 /* XXX for A? */ 3117 gainp = urtw_8225v2_gain_bg; 3118 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3119 usb_pause_mtx(&sc->sc_mtx, 1); 3120 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3121 usb_pause_mtx(&sc->sc_mtx, 1); 3122 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3123 usb_pause_mtx(&sc->sc_mtx, 1); 3124 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3125 usb_pause_mtx(&sc->sc_mtx, 1); 3126 fail: 3127 return (error); 3128 } 3129 3130 static usb_error_t 3131 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3132 { 3133 uint32_t data; 3134 usb_error_t error; 3135 3136 *ret = 1; 3137 3138 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3139 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3140 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3141 usb_pause_mtx(&sc->sc_mtx, 500); 3142 3143 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3144 URTW_8225_ADDR_0_DATA_MAGIC1); 3145 3146 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3147 if (error != 0) 3148 goto fail; 3149 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3150 *ret = 0; 3151 else { 3152 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3153 if (error != 0) 3154 goto fail; 3155 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3156 *ret = 0; 3157 } 3158 3159 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3160 URTW_8225_ADDR_0_DATA_MAGIC2); 3161 fail: 3162 return (error); 3163 } 3164 3165 static usb_error_t 3166 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3167 { 3168 struct ieee80211com *ic = &sc->sc_ic; 3169 int i; 3170 uint8_t data8; 3171 usb_error_t error; 3172 3173 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3174 if (error) 3175 goto fail; 3176 3177 /* 3178 * initialize extra registers on 8187 3179 */ 3180 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3181 3182 /* retry limit */ 3183 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3184 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3185 urtw_write8_m(sc, URTW_CW_CONF, data8); 3186 3187 /* TX AGC */ 3188 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3189 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3190 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3191 3192 /* Auto Rate Fallback Control */ 3193 #define URTW_ARFR 0x1e0 3194 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3195 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3196 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3197 data8 | URTW_RATE_FALLBACK_ENABLE); 3198 3199 urtw_read8_m(sc, URTW_MSR, &data8); 3200 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3201 urtw_read8_m(sc, URTW_MSR, &data8); 3202 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3203 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3204 3205 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3206 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3207 #define URTW_FEMR_FOR_8187B 0x1d4 3208 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3209 3210 /* led type */ 3211 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3212 data8 = (data8 & 0x3f) | 0x80; 3213 urtw_write8_m(sc, URTW_CONFIG1, data8); 3214 3215 /* applying MAC address again. */ 3216 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3217 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3218 3219 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3220 if (error) 3221 goto fail; 3222 3223 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3224 3225 /* 3226 * MAC configuration 3227 */ 3228 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3229 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3230 urtw_8225v2b_rf_part1[i].val); 3231 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3232 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3233 urtw_write32_m(sc, 0x1f0, 0); 3234 urtw_write32_m(sc, 0x1f4, 0); 3235 urtw_write8_m(sc, 0x1f8, 0); 3236 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3237 3238 #define URTW_RFSW_CTRL 0x272 3239 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3240 3241 /* 3242 * initialize PHY 3243 */ 3244 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3245 if (error) 3246 goto fail; 3247 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3248 urtw_write8_m(sc, URTW_CONFIG3, 3249 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3250 3251 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3252 if (error) 3253 goto fail; 3254 3255 /* setup RFE initial timing */ 3256 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3257 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3258 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3259 usb_pause_mtx(&sc->sc_mtx, 1100); 3260 3261 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3262 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3263 urtw_8225v2b_rf_part0[i].val); 3264 usb_pause_mtx(&sc->sc_mtx, 1); 3265 } 3266 urtw_8225_write(sc, 0x00, 0x01b7); 3267 3268 for (i = 0; i < 95; i++) { 3269 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3270 usb_pause_mtx(&sc->sc_mtx, 1); 3271 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3272 urtw_8225v2b_rxgain[i]); 3273 usb_pause_mtx(&sc->sc_mtx, 1); 3274 } 3275 3276 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3277 usb_pause_mtx(&sc->sc_mtx, 1); 3278 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3279 usb_pause_mtx(&sc->sc_mtx, 1); 3280 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3281 usb_pause_mtx(&sc->sc_mtx, 1); 3282 usb_pause_mtx(&sc->sc_mtx, 3000); 3283 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3284 usb_pause_mtx(&sc->sc_mtx, 2000); 3285 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3286 usb_pause_mtx(&sc->sc_mtx, 1); 3287 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3288 usb_pause_mtx(&sc->sc_mtx, 1); 3289 3290 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3291 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3292 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3293 3294 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3295 for (i = 0; i < 128; i++) { 3296 uint32_t addr, data; 3297 3298 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3299 addr = ((i + 0x80) << 8) | 0x0000008e; 3300 3301 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3302 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3303 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3304 } 3305 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3306 3307 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3308 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3309 3310 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3311 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3312 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3313 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3314 3315 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3316 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3317 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3318 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3319 3320 fail: 3321 return (error); 3322 } 3323 3324 static usb_error_t 3325 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3326 { 3327 usb_error_t error; 3328 3329 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3330 if (error) 3331 goto fail; 3332 3333 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3334 usb_pause_mtx(&sc->sc_mtx, 10); 3335 fail: 3336 return (error); 3337 } 3338 3339 static usb_error_t 3340 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3341 { 3342 int i; 3343 uint8_t *cck_pwrtable; 3344 uint8_t cck_pwrlvl_max = 15; 3345 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3346 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3347 usb_error_t error; 3348 3349 /* CCK power setting */ 3350 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3351 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3352 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3353 cck_pwrlvl += sc->sc_txpwr_cck_base; 3354 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3355 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3356 urtw_8225v2b_txpwr_cck; 3357 3358 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3359 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3360 ((cck_pwrlvl <= 11) ? 8 : 16); 3361 else 3362 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3363 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3364 3365 for (i = 0; i < 8; i++) 3366 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3367 3368 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3369 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3370 usb_pause_mtx(&sc->sc_mtx, 1); 3371 3372 /* OFDM power setting */ 3373 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3374 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3375 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3376 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3377 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3378 3379 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3380 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3381 3382 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3383 if (ofdm_pwrlvl <= 11) { 3384 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3385 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3386 } else { 3387 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3388 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3389 } 3390 } else { 3391 if (ofdm_pwrlvl <= 11) { 3392 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3393 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3394 } else if (ofdm_pwrlvl <= 17) { 3395 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3396 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3397 } else { 3398 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3399 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3400 } 3401 } 3402 usb_pause_mtx(&sc->sc_mtx, 1); 3403 fail: 3404 return (error); 3405 } 3406 3407 static usb_error_t 3408 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3409 { 3410 struct usb_device_request req; 3411 usb_error_t error; 3412 3413 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3414 req.bRequest = URTW_8187_GETREGS_REQ; 3415 USETW(req.wValue, val | 0xfe00); 3416 USETW(req.wIndex, 0); 3417 USETW(req.wLength, sizeof(uint8_t)); 3418 3419 error = urtw_do_request(sc, &req, data); 3420 return (error); 3421 } 3422 3423 static usb_error_t 3424 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3425 { 3426 struct usb_device_request req; 3427 3428 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3429 req.bRequest = URTW_8187_SETREGS_REQ; 3430 USETW(req.wValue, val | 0xfe00); 3431 USETW(req.wIndex, 0); 3432 USETW(req.wLength, sizeof(uint8_t)); 3433 3434 return (urtw_do_request(sc, &req, &data)); 3435 } 3436 3437 static usb_error_t 3438 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3439 { 3440 uint8_t data; 3441 usb_error_t error; 3442 3443 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3444 if (error) 3445 goto fail; 3446 3447 urtw_read8_m(sc, URTW_CONFIG3, &data); 3448 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3449 urtw_write32_m(sc, URTW_ANAPARAM, val); 3450 urtw_read8_m(sc, URTW_CONFIG3, &data); 3451 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3452 3453 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3454 if (error) 3455 goto fail; 3456 fail: 3457 return (error); 3458 } 3459 3460 static usb_error_t 3461 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3462 { 3463 uint8_t data; 3464 usb_error_t error; 3465 3466 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3467 if (error) 3468 goto fail; 3469 3470 urtw_read8_m(sc, URTW_CONFIG3, &data); 3471 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3472 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3473 urtw_read8_m(sc, URTW_CONFIG3, &data); 3474 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3475 3476 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3477 if (error) 3478 goto fail; 3479 fail: 3480 return (error); 3481 } 3482 3483 static usb_error_t 3484 urtw_intr_enable(struct urtw_softc *sc) 3485 { 3486 usb_error_t error; 3487 3488 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3489 fail: 3490 return (error); 3491 } 3492 3493 static usb_error_t 3494 urtw_intr_disable(struct urtw_softc *sc) 3495 { 3496 usb_error_t error; 3497 3498 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3499 fail: 3500 return (error); 3501 } 3502 3503 static usb_error_t 3504 urtw_reset(struct urtw_softc *sc) 3505 { 3506 uint8_t data; 3507 usb_error_t error; 3508 3509 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3510 if (error) 3511 goto fail; 3512 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3513 if (error) 3514 goto fail; 3515 3516 error = urtw_intr_disable(sc); 3517 if (error) 3518 goto fail; 3519 usb_pause_mtx(&sc->sc_mtx, 100); 3520 3521 error = urtw_write8e(sc, 0x18, 0x10); 3522 if (error != 0) 3523 goto fail; 3524 error = urtw_write8e(sc, 0x18, 0x11); 3525 if (error != 0) 3526 goto fail; 3527 error = urtw_write8e(sc, 0x18, 0x00); 3528 if (error != 0) 3529 goto fail; 3530 usb_pause_mtx(&sc->sc_mtx, 100); 3531 3532 urtw_read8_m(sc, URTW_CMD, &data); 3533 data = (data & 0x2) | URTW_CMD_RST; 3534 urtw_write8_m(sc, URTW_CMD, data); 3535 usb_pause_mtx(&sc->sc_mtx, 100); 3536 3537 urtw_read8_m(sc, URTW_CMD, &data); 3538 if (data & URTW_CMD_RST) { 3539 device_printf(sc->sc_dev, "reset timeout\n"); 3540 goto fail; 3541 } 3542 3543 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3544 if (error) 3545 goto fail; 3546 usb_pause_mtx(&sc->sc_mtx, 100); 3547 3548 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3549 if (error) 3550 goto fail; 3551 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3552 if (error) 3553 goto fail; 3554 fail: 3555 return (error); 3556 } 3557 3558 static usb_error_t 3559 urtw_led_ctl(struct urtw_softc *sc, int mode) 3560 { 3561 usb_error_t error = 0; 3562 3563 switch (sc->sc_strategy) { 3564 case URTW_SW_LED_MODE0: 3565 error = urtw_led_mode0(sc, mode); 3566 break; 3567 case URTW_SW_LED_MODE1: 3568 error = urtw_led_mode1(sc, mode); 3569 break; 3570 case URTW_SW_LED_MODE2: 3571 error = urtw_led_mode2(sc, mode); 3572 break; 3573 case URTW_SW_LED_MODE3: 3574 error = urtw_led_mode3(sc, mode); 3575 break; 3576 default: 3577 DPRINTF(sc, URTW_DEBUG_STATE, 3578 "unsupported LED mode %d\n", sc->sc_strategy); 3579 error = USB_ERR_INVAL; 3580 break; 3581 } 3582 3583 return (error); 3584 } 3585 3586 static usb_error_t 3587 urtw_led_mode0(struct urtw_softc *sc, int mode) 3588 { 3589 3590 switch (mode) { 3591 case URTW_LED_CTL_POWER_ON: 3592 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3593 break; 3594 case URTW_LED_CTL_TX: 3595 if (sc->sc_gpio_ledinprogress == 1) 3596 return (0); 3597 3598 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3599 sc->sc_gpio_blinktime = 2; 3600 break; 3601 case URTW_LED_CTL_LINK: 3602 sc->sc_gpio_ledstate = URTW_LED_ON; 3603 break; 3604 default: 3605 DPRINTF(sc, URTW_DEBUG_STATE, 3606 "unsupported LED mode 0x%x", mode); 3607 return (USB_ERR_INVAL); 3608 } 3609 3610 switch (sc->sc_gpio_ledstate) { 3611 case URTW_LED_ON: 3612 if (sc->sc_gpio_ledinprogress != 0) 3613 break; 3614 urtw_led_on(sc, URTW_LED_GPIO); 3615 break; 3616 case URTW_LED_BLINK_NORMAL: 3617 if (sc->sc_gpio_ledinprogress != 0) 3618 break; 3619 sc->sc_gpio_ledinprogress = 1; 3620 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3621 URTW_LED_OFF : URTW_LED_ON; 3622 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3623 break; 3624 case URTW_LED_POWER_ON_BLINK: 3625 urtw_led_on(sc, URTW_LED_GPIO); 3626 usb_pause_mtx(&sc->sc_mtx, 100); 3627 urtw_led_off(sc, URTW_LED_GPIO); 3628 break; 3629 default: 3630 DPRINTF(sc, URTW_DEBUG_STATE, 3631 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3632 return (USB_ERR_INVAL); 3633 } 3634 return (0); 3635 } 3636 3637 static usb_error_t 3638 urtw_led_mode1(struct urtw_softc *sc, int mode) 3639 { 3640 return (USB_ERR_INVAL); 3641 } 3642 3643 static usb_error_t 3644 urtw_led_mode2(struct urtw_softc *sc, int mode) 3645 { 3646 return (USB_ERR_INVAL); 3647 } 3648 3649 static usb_error_t 3650 urtw_led_mode3(struct urtw_softc *sc, int mode) 3651 { 3652 return (USB_ERR_INVAL); 3653 } 3654 3655 static usb_error_t 3656 urtw_led_on(struct urtw_softc *sc, int type) 3657 { 3658 usb_error_t error; 3659 3660 if (type == URTW_LED_GPIO) { 3661 switch (sc->sc_gpio_ledpin) { 3662 case URTW_LED_PIN_GPIO0: 3663 urtw_write8_m(sc, URTW_GPIO, 0x01); 3664 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3665 break; 3666 default: 3667 DPRINTF(sc, URTW_DEBUG_STATE, 3668 "unsupported LED PIN type 0x%x", 3669 sc->sc_gpio_ledpin); 3670 error = USB_ERR_INVAL; 3671 goto fail; 3672 } 3673 } else { 3674 DPRINTF(sc, URTW_DEBUG_STATE, 3675 "unsupported LED type 0x%x", type); 3676 error = USB_ERR_INVAL; 3677 goto fail; 3678 } 3679 3680 sc->sc_gpio_ledon = 1; 3681 fail: 3682 return (error); 3683 } 3684 3685 static usb_error_t 3686 urtw_led_off(struct urtw_softc *sc, int type) 3687 { 3688 usb_error_t error; 3689 3690 if (type == URTW_LED_GPIO) { 3691 switch (sc->sc_gpio_ledpin) { 3692 case URTW_LED_PIN_GPIO0: 3693 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3694 urtw_write8_m(sc, 3695 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3696 break; 3697 default: 3698 DPRINTF(sc, URTW_DEBUG_STATE, 3699 "unsupported LED PIN type 0x%x", 3700 sc->sc_gpio_ledpin); 3701 error = USB_ERR_INVAL; 3702 goto fail; 3703 } 3704 } else { 3705 DPRINTF(sc, URTW_DEBUG_STATE, 3706 "unsupported LED type 0x%x", type); 3707 error = USB_ERR_INVAL; 3708 goto fail; 3709 } 3710 3711 sc->sc_gpio_ledon = 0; 3712 3713 fail: 3714 return (error); 3715 } 3716 3717 static void 3718 urtw_led_ch(void *arg) 3719 { 3720 struct urtw_softc *sc = arg; 3721 struct ieee80211com *ic = &sc->sc_ic; 3722 3723 ieee80211_runtask(ic, &sc->sc_led_task); 3724 } 3725 3726 static void 3727 urtw_ledtask(void *arg, int pending) 3728 { 3729 struct urtw_softc *sc = arg; 3730 3731 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3732 DPRINTF(sc, URTW_DEBUG_STATE, 3733 "could not process a LED strategy 0x%x", 3734 sc->sc_strategy); 3735 return; 3736 } 3737 3738 URTW_LOCK(sc); 3739 urtw_led_blink(sc); 3740 URTW_UNLOCK(sc); 3741 } 3742 3743 static usb_error_t 3744 urtw_led_blink(struct urtw_softc *sc) 3745 { 3746 uint8_t ing = 0; 3747 usb_error_t error; 3748 3749 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3750 error = urtw_led_on(sc, URTW_LED_GPIO); 3751 else 3752 error = urtw_led_off(sc, URTW_LED_GPIO); 3753 sc->sc_gpio_blinktime--; 3754 if (sc->sc_gpio_blinktime == 0) 3755 ing = 1; 3756 else { 3757 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3758 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3759 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3760 ing = 1; 3761 } 3762 if (ing == 1) { 3763 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3764 sc->sc_gpio_ledon == 0) 3765 error = urtw_led_on(sc, URTW_LED_GPIO); 3766 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3767 sc->sc_gpio_ledon == 1) 3768 error = urtw_led_off(sc, URTW_LED_GPIO); 3769 3770 sc->sc_gpio_blinktime = 0; 3771 sc->sc_gpio_ledinprogress = 0; 3772 return (0); 3773 } 3774 3775 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3776 URTW_LED_ON : URTW_LED_OFF; 3777 3778 switch (sc->sc_gpio_ledstate) { 3779 case URTW_LED_BLINK_NORMAL: 3780 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3781 break; 3782 default: 3783 DPRINTF(sc, URTW_DEBUG_STATE, 3784 "unknown LED status 0x%x", 3785 sc->sc_gpio_ledstate); 3786 return (USB_ERR_INVAL); 3787 } 3788 return (0); 3789 } 3790 3791 static usb_error_t 3792 urtw_rx_enable(struct urtw_softc *sc) 3793 { 3794 uint8_t data; 3795 usb_error_t error; 3796 3797 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3798 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3799 3800 error = urtw_rx_setconf(sc); 3801 if (error != 0) 3802 goto fail; 3803 3804 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3805 urtw_read8_m(sc, URTW_CMD, &data); 3806 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3807 } 3808 fail: 3809 return (error); 3810 } 3811 3812 static usb_error_t 3813 urtw_tx_enable(struct urtw_softc *sc) 3814 { 3815 uint8_t data8; 3816 uint32_t data; 3817 usb_error_t error; 3818 3819 if (sc->sc_flags & URTW_RTL8187B) { 3820 urtw_read32_m(sc, URTW_TX_CONF, &data); 3821 data &= ~URTW_TX_LOOPBACK_MASK; 3822 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3823 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3824 data &= ~URTW_TX_SWPLCPLEN; 3825 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3826 (7 << 8) | /* short retry limit */ 3827 (7 << 0) | /* long retry limit */ 3828 (7 << 21); /* MAX TX DMA */ 3829 urtw_write32_m(sc, URTW_TX_CONF, data); 3830 3831 urtw_read8_m(sc, URTW_MSR, &data8); 3832 data8 |= URTW_MSR_LINK_ENEDCA; 3833 urtw_write8_m(sc, URTW_MSR, data8); 3834 return (error); 3835 } 3836 3837 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3838 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3839 urtw_write8_m(sc, URTW_CW_CONF, data8); 3840 3841 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3842 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3843 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3844 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3845 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3846 3847 urtw_read32_m(sc, URTW_TX_CONF, &data); 3848 data &= ~URTW_TX_LOOPBACK_MASK; 3849 data |= URTW_TX_LOOPBACK_NONE; 3850 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3851 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3852 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3853 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3854 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3855 data &= ~URTW_TX_SWPLCPLEN; 3856 data |= URTW_TX_NOICV; 3857 urtw_write32_m(sc, URTW_TX_CONF, data); 3858 3859 urtw_read8_m(sc, URTW_CMD, &data8); 3860 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3861 fail: 3862 return (error); 3863 } 3864 3865 static usb_error_t 3866 urtw_rx_setconf(struct urtw_softc *sc) 3867 { 3868 struct ieee80211com *ic = &sc->sc_ic; 3869 uint32_t data; 3870 usb_error_t error; 3871 3872 urtw_read32_m(sc, URTW_RX, &data); 3873 data = data &~ URTW_RX_FILTER_MASK; 3874 if (sc->sc_flags & URTW_RTL8187B) { 3875 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3876 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3877 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID | 3878 URTW_RX_FIFO_THRESHOLD_NONE | 3879 URTW_MAX_RX_DMA_2048 | 3880 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3881 } else { 3882 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3883 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3884 3885 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3886 data = data | URTW_RX_FILTER_ICVERR; 3887 data = data | URTW_RX_FILTER_PWR; 3888 } 3889 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3890 data = data | URTW_RX_FILTER_CRCERR; 3891 3892 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3893 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3894 data = data | URTW_RX_FILTER_ALLMAC; 3895 } else { 3896 data = data | URTW_RX_FILTER_NICMAC; 3897 data = data | URTW_RX_CHECK_BSSID; 3898 } 3899 3900 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3901 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3902 URTW_RX_AUTORESETPHY; 3903 data = data &~ URTW_MAX_RX_DMA_MASK; 3904 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3905 } 3906 3907 urtw_write32_m(sc, URTW_RX, data); 3908 fail: 3909 return (error); 3910 } 3911 3912 static struct mbuf * 3913 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3914 int8_t *nf_p) 3915 { 3916 int actlen, flen, rssi; 3917 struct ieee80211_frame *wh; 3918 struct mbuf *m, *mnew; 3919 struct urtw_softc *sc = data->sc; 3920 struct ieee80211com *ic = &sc->sc_ic; 3921 uint8_t noise = 0, rate; 3922 3923 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3924 3925 if (actlen < (int)URTW_MIN_RXBUFSZ) { 3926 counter_u64_add(ic->ic_ierrors, 1); 3927 return (NULL); 3928 } 3929 3930 if (sc->sc_flags & URTW_RTL8187B) { 3931 struct urtw_8187b_rxhdr *rx; 3932 3933 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3934 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3935 flen = le32toh(rx->flag) & 0xfff; 3936 if (flen > actlen) { 3937 counter_u64_add(ic->ic_ierrors, 1); 3938 return (NULL); 3939 } 3940 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3941 /* XXX correct? */ 3942 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3943 noise = rx->noise; 3944 } else { 3945 struct urtw_8187l_rxhdr *rx; 3946 3947 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3948 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3949 flen = le32toh(rx->flag) & 0xfff; 3950 if (flen > actlen) { 3951 counter_u64_add(ic->ic_ierrors, 1); 3952 return (NULL); 3953 } 3954 3955 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3956 /* XXX correct? */ 3957 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3958 noise = rx->noise; 3959 } 3960 3961 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3962 if (mnew == NULL) { 3963 counter_u64_add(ic->ic_ierrors, 1); 3964 return (NULL); 3965 } 3966 3967 m = data->m; 3968 data->m = mnew; 3969 data->buf = mtod(mnew, uint8_t *); 3970 3971 /* finalize mbuf */ 3972 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3973 3974 if (ieee80211_radiotap_active(ic)) { 3975 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3976 3977 /* XXX Are variables correct? */ 3978 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 3979 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3980 tap->wr_dbm_antsignal = (int8_t)rssi; 3981 } 3982 3983 wh = mtod(m, struct ieee80211_frame *); 3984 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3985 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3986 3987 *rssi_p = rssi; 3988 *nf_p = noise; /* XXX correct? */ 3989 3990 return (m); 3991 } 3992 3993 static void 3994 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 3995 { 3996 struct urtw_softc *sc = usbd_xfer_softc(xfer); 3997 struct ieee80211com *ic = &sc->sc_ic; 3998 struct ieee80211_frame *wh; 3999 struct ieee80211_node *ni; 4000 struct mbuf *m = NULL; 4001 struct urtw_data *data; 4002 int8_t nf = -95; 4003 int rssi = 1; 4004 4005 URTW_ASSERT_LOCKED(sc); 4006 4007 switch (USB_GET_STATE(xfer)) { 4008 case USB_ST_TRANSFERRED: 4009 data = STAILQ_FIRST(&sc->sc_rx_active); 4010 if (data == NULL) 4011 goto setup; 4012 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4013 m = urtw_rxeof(xfer, data, &rssi, &nf); 4014 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4015 /* FALLTHROUGH */ 4016 case USB_ST_SETUP: 4017 setup: 4018 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4019 if (data == NULL) { 4020 KASSERT(m == NULL, ("mbuf isn't NULL")); 4021 return; 4022 } 4023 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4024 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4025 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4026 usbd_xfer_max_len(xfer)); 4027 usbd_transfer_submit(xfer); 4028 4029 /* 4030 * To avoid LOR we should unlock our private mutex here to call 4031 * ieee80211_input() because here is at the end of a USB 4032 * callback and safe to unlock. 4033 */ 4034 URTW_UNLOCK(sc); 4035 if (m != NULL) { 4036 wh = mtod(m, struct ieee80211_frame *); 4037 ni = ieee80211_find_rxnode(ic, 4038 (struct ieee80211_frame_min *)wh); 4039 if (ni != NULL) { 4040 (void) ieee80211_input(ni, m, rssi, nf); 4041 /* node is no longer needed */ 4042 ieee80211_free_node(ni); 4043 } else 4044 (void) ieee80211_input_all(ic, m, rssi, nf); 4045 m = NULL; 4046 } 4047 URTW_LOCK(sc); 4048 break; 4049 default: 4050 /* needs it to the inactive queue due to a error. */ 4051 data = STAILQ_FIRST(&sc->sc_rx_active); 4052 if (data != NULL) { 4053 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4054 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4055 } 4056 if (error != USB_ERR_CANCELLED) { 4057 usbd_xfer_set_stall(xfer); 4058 counter_u64_add(ic->ic_ierrors, 1); 4059 goto setup; 4060 } 4061 break; 4062 } 4063 } 4064 4065 #define URTW_STATUS_TYPE_TXCLOSE 1 4066 #define URTW_STATUS_TYPE_BEACON_INTR 0 4067 4068 static void 4069 urtw_txstatus_eof(struct usb_xfer *xfer) 4070 { 4071 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4072 struct ieee80211com *ic = &sc->sc_ic; 4073 int actlen, type, pktretry, seq; 4074 uint64_t val; 4075 4076 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4077 4078 if (actlen != sizeof(uint64_t)) 4079 return; 4080 4081 val = le64toh(sc->sc_txstatus); 4082 type = (val >> 30) & 0x3; 4083 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4084 pktretry = val & 0xff; 4085 seq = (val >> 16) & 0xff; 4086 if (pktretry == URTW_TX_MAXRETRY) 4087 counter_u64_add(ic->ic_oerrors, 1); 4088 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4089 pktretry, seq); 4090 } 4091 } 4092 4093 static void 4094 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4095 { 4096 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4097 struct ieee80211com *ic = &sc->sc_ic; 4098 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4099 4100 URTW_ASSERT_LOCKED(sc); 4101 4102 switch (USB_GET_STATE(xfer)) { 4103 case USB_ST_TRANSFERRED: 4104 urtw_txstatus_eof(xfer); 4105 /* FALLTHROUGH */ 4106 case USB_ST_SETUP: 4107 setup: 4108 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4109 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4110 usbd_transfer_submit(xfer); 4111 break; 4112 default: 4113 if (error != USB_ERR_CANCELLED) { 4114 usbd_xfer_set_stall(xfer); 4115 counter_u64_add(ic->ic_ierrors, 1); 4116 goto setup; 4117 } 4118 break; 4119 } 4120 } 4121 4122 static void 4123 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4124 { 4125 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4126 4127 URTW_ASSERT_LOCKED(sc); 4128 4129 if (data->m) { 4130 /* XXX status? */ 4131 ieee80211_tx_complete(data->ni, data->m, 0); 4132 data->m = NULL; 4133 data->ni = NULL; 4134 } 4135 sc->sc_txtimer = 0; 4136 } 4137 4138 static void 4139 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4140 { 4141 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4142 struct urtw_data *data; 4143 4144 URTW_ASSERT_LOCKED(sc); 4145 4146 switch (USB_GET_STATE(xfer)) { 4147 case USB_ST_TRANSFERRED: 4148 data = STAILQ_FIRST(&sc->sc_tx_active); 4149 if (data == NULL) 4150 goto setup; 4151 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4152 urtw_txeof(xfer, data); 4153 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4154 /* FALLTHROUGH */ 4155 case USB_ST_SETUP: 4156 setup: 4157 data = STAILQ_FIRST(&sc->sc_tx_pending); 4158 if (data == NULL) { 4159 DPRINTF(sc, URTW_DEBUG_XMIT, 4160 "%s: empty pending queue\n", __func__); 4161 return; 4162 } 4163 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4164 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4165 4166 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4167 usbd_transfer_submit(xfer); 4168 4169 urtw_start(sc); 4170 break; 4171 default: 4172 data = STAILQ_FIRST(&sc->sc_tx_active); 4173 if (data == NULL) 4174 goto setup; 4175 if (data->ni != NULL) { 4176 if_inc_counter(data->ni->ni_vap->iv_ifp, 4177 IFCOUNTER_OERRORS, 1); 4178 ieee80211_free_node(data->ni); 4179 data->ni = NULL; 4180 } 4181 if (error != USB_ERR_CANCELLED) { 4182 usbd_xfer_set_stall(xfer); 4183 goto setup; 4184 } 4185 break; 4186 } 4187 } 4188 4189 static struct urtw_data * 4190 _urtw_getbuf(struct urtw_softc *sc) 4191 { 4192 struct urtw_data *bf; 4193 4194 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4195 if (bf != NULL) 4196 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4197 else 4198 bf = NULL; 4199 if (bf == NULL) 4200 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4201 "out of xmit buffers"); 4202 return (bf); 4203 } 4204 4205 static struct urtw_data * 4206 urtw_getbuf(struct urtw_softc *sc) 4207 { 4208 struct urtw_data *bf; 4209 4210 URTW_ASSERT_LOCKED(sc); 4211 4212 bf = _urtw_getbuf(sc); 4213 if (bf == NULL) 4214 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4215 return (bf); 4216 } 4217 4218 static int 4219 urtw_isbmode(uint16_t rate) 4220 { 4221 4222 return ((rate <= 22 && rate != 12 && rate != 18) || 4223 rate == 44) ? (1) : (0); 4224 } 4225 4226 static uint16_t 4227 urtw_rate2dbps(uint16_t rate) 4228 { 4229 4230 switch(rate) { 4231 case 12: 4232 case 18: 4233 case 24: 4234 case 36: 4235 case 48: 4236 case 72: 4237 case 96: 4238 case 108: 4239 return (rate * 2); 4240 default: 4241 break; 4242 } 4243 return (24); 4244 } 4245 4246 static int 4247 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4248 uint8_t ismgt, uint8_t isshort) 4249 { 4250 uint16_t ceiling, frametime, n_dbps; 4251 4252 if (urtw_isbmode(rate)) { 4253 if (ismgt || !isshort || rate == 2) 4254 frametime = (uint16_t)(144 + 48 + 4255 (framelen * 8 / (rate / 2))); 4256 else 4257 frametime = (uint16_t)(72 + 24 + 4258 (framelen * 8 / (rate / 2))); 4259 if ((framelen * 8 % (rate / 2)) != 0) 4260 frametime++; 4261 } else { 4262 n_dbps = urtw_rate2dbps(rate); 4263 ceiling = (16 + 8 * framelen + 6) / n_dbps 4264 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4265 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4266 } 4267 return (frametime); 4268 } 4269 4270 /* 4271 * Callback from the 802.11 layer to update the 4272 * slot time based on the current setting. 4273 */ 4274 static void 4275 urtw_updateslot(struct ieee80211com *ic) 4276 { 4277 struct urtw_softc *sc = ic->ic_softc; 4278 4279 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4280 } 4281 4282 static void 4283 urtw_updateslottask(void *arg, int pending) 4284 { 4285 struct urtw_softc *sc = arg; 4286 struct ieee80211com *ic = &sc->sc_ic; 4287 int error; 4288 4289 URTW_LOCK(sc); 4290 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4291 URTW_UNLOCK(sc); 4292 return; 4293 } 4294 if (sc->sc_flags & URTW_RTL8187B) { 4295 urtw_write8_m(sc, URTW_SIFS, 0x22); 4296 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4297 urtw_write8_m(sc, URTW_SLOT, 0x9); 4298 else 4299 urtw_write8_m(sc, URTW_SLOT, 0x14); 4300 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4301 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4302 } else { 4303 urtw_write8_m(sc, URTW_SIFS, 0x22); 4304 if (sc->sc_state == IEEE80211_S_ASSOC && 4305 ic->ic_flags & IEEE80211_F_SHSLOT) 4306 urtw_write8_m(sc, URTW_SLOT, 0x9); 4307 else 4308 urtw_write8_m(sc, URTW_SLOT, 0x14); 4309 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4310 urtw_write8_m(sc, URTW_DIFS, 0x14); 4311 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4312 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4313 } else { 4314 urtw_write8_m(sc, URTW_DIFS, 0x24); 4315 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4316 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4317 } 4318 } 4319 fail: 4320 URTW_UNLOCK(sc); 4321 } 4322 4323 static void 4324 urtw_sysctl_node(struct urtw_softc *sc) 4325 { 4326 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4327 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4328 struct sysctl_ctx_list *ctx; 4329 struct sysctl_oid_list *child, *parent; 4330 struct sysctl_oid *tree; 4331 struct urtw_stats *stats = &sc->sc_stats; 4332 4333 ctx = device_get_sysctl_ctx(sc->sc_dev); 4334 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4335 4336 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4337 NULL, "URTW statistics"); 4338 parent = SYSCTL_CHILDREN(tree); 4339 4340 /* Tx statistics. */ 4341 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4342 NULL, "Tx MAC statistics"); 4343 child = SYSCTL_CHILDREN(tree); 4344 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4345 "1 Mbit/s"); 4346 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4347 "2 Mbit/s"); 4348 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4349 "5.5 Mbit/s"); 4350 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4351 "6 Mbit/s"); 4352 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4353 "9 Mbit/s"); 4354 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4355 "11 Mbit/s"); 4356 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4357 "12 Mbit/s"); 4358 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4359 "18 Mbit/s"); 4360 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4361 "24 Mbit/s"); 4362 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4363 "36 Mbit/s"); 4364 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4365 "48 Mbit/s"); 4366 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4367 "54 Mbit/s"); 4368 #undef URTW_SYSCTL_STAT_ADD32 4369 } 4370 4371 static device_method_t urtw_methods[] = { 4372 DEVMETHOD(device_probe, urtw_match), 4373 DEVMETHOD(device_attach, urtw_attach), 4374 DEVMETHOD(device_detach, urtw_detach), 4375 DEVMETHOD_END 4376 }; 4377 static driver_t urtw_driver = { 4378 .name = "urtw", 4379 .methods = urtw_methods, 4380 .size = sizeof(struct urtw_softc) 4381 }; 4382 static devclass_t urtw_devclass; 4383 4384 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4385 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4386 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4387 MODULE_VERSION(urtw, 1); 4388