1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 20 #include "opt_wlan.h" 21 22 #include <sys/param.h> 23 #include <sys/sockio.h> 24 #include <sys/sysctl.h> 25 #include <sys/lock.h> 26 #include <sys/mutex.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/module.h> 33 #include <sys/bus.h> 34 #include <sys/endian.h> 35 #include <sys/kdb.h> 36 37 #include <net/if.h> 38 #include <net/if_var.h> 39 #include <net/if_arp.h> 40 #include <net/ethernet.h> 41 #include <net/if_dl.h> 42 #include <net/if_media.h> 43 #include <net/if_types.h> 44 45 #ifdef INET 46 #include <netinet/in.h> 47 #include <netinet/in_systm.h> 48 #include <netinet/in_var.h> 49 #include <netinet/if_ether.h> 50 #include <netinet/ip.h> 51 #endif 52 53 #include <net80211/ieee80211_var.h> 54 #include <net80211/ieee80211_regdomain.h> 55 #include <net80211/ieee80211_radiotap.h> 56 57 #include <dev/usb/usb.h> 58 #include <dev/usb/usbdi.h> 59 #include "usbdevs.h" 60 61 #include <dev/usb/wlan/if_urtwreg.h> 62 #include <dev/usb/wlan/if_urtwvar.h> 63 64 /* copy some rate indices from if_rtwn_ridx.h */ 65 #define URTW_RIDX_CCK5 2 66 #define URTW_RIDX_CCK11 3 67 #define URTW_RIDX_OFDM6 4 68 #define URTW_RIDX_OFDM24 8 69 70 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 71 #ifdef URTW_DEBUG 72 int urtw_debug = 0; 73 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 74 "control debugging printfs"); 75 enum { 76 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 77 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 78 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 79 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 80 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 81 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 82 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 83 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 84 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 85 URTW_DEBUG_ANY = 0xffffffff 86 }; 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 if (sc->sc_debug & (m)) \ 89 printf(fmt, __VA_ARGS__); \ 90 } while (0) 91 #else 92 #define DPRINTF(sc, m, fmt, ...) do { \ 93 (void) sc; \ 94 } while (0) 95 #endif 96 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 97 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 98 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 99 100 /* recognized device vendors/products */ 101 #define urtw_lookup(v, p) \ 102 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 103 #define URTW_DEV_B(v,p) \ 104 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 105 #define URTW_DEV_L(v,p) \ 106 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 107 #define URTW_REV_RTL8187B 0 108 #define URTW_REV_RTL8187L 1 109 static const STRUCT_USB_HOST_ID urtw_devs[] = { 110 URTW_DEV_B(NETGEAR, WG111V3), 111 URTW_DEV_B(REALTEK, RTL8187B_0), 112 URTW_DEV_B(REALTEK, RTL8187B_1), 113 URTW_DEV_B(REALTEK, RTL8187B_2), 114 URTW_DEV_B(SITECOMEU, WL168V4), 115 URTW_DEV_L(ASUS, P5B_WIFI), 116 URTW_DEV_L(BELKIN, F5D7050E), 117 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 118 URTW_DEV_L(NETGEAR, WG111V2), 119 URTW_DEV_L(REALTEK, RTL8187), 120 URTW_DEV_L(SITECOMEU, WL168V1), 121 URTW_DEV_L(SURECOM, EP9001G2A), 122 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 124 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 125 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 126 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 127 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 128 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 129 #undef URTW_DEV_L 130 #undef URTW_DEV_B 131 }; 132 133 #define urtw_read8_m(sc, val, data) do { \ 134 error = urtw_read8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_write8_m(sc, val, data) do { \ 139 error = urtw_write8_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_read16_m(sc, val, data) do { \ 144 error = urtw_read16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_write16_m(sc, val, data) do { \ 149 error = urtw_write16_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_read32_m(sc, val, data) do { \ 154 error = urtw_read32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_write32_m(sc, val, data) do { \ 159 error = urtw_write32_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 164 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 169 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 #define urtw_8225_write(sc, val, data) do { \ 174 error = urtw_8225_write_c(sc, val, data); \ 175 if (error != 0) \ 176 goto fail; \ 177 } while (0) 178 179 struct urtw_pair { 180 uint32_t reg; 181 uint32_t val; 182 }; 183 184 static uint8_t urtw_8225_agc[] = { 185 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 186 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 187 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 188 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 189 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 190 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 191 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 192 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 193 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 194 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 195 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 196 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 197 }; 198 199 static uint8_t urtw_8225z2_agc[] = { 200 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 201 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 202 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 203 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 204 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 205 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 206 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 207 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 208 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 209 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 210 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 211 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 212 }; 213 214 static uint32_t urtw_8225_channel[] = { 215 0x0000, /* dummy channel 0 */ 216 0x085c, /* 1 */ 217 0x08dc, /* 2 */ 218 0x095c, /* 3 */ 219 0x09dc, /* 4 */ 220 0x0a5c, /* 5 */ 221 0x0adc, /* 6 */ 222 0x0b5c, /* 7 */ 223 0x0bdc, /* 8 */ 224 0x0c5c, /* 9 */ 225 0x0cdc, /* 10 */ 226 0x0d5c, /* 11 */ 227 0x0ddc, /* 12 */ 228 0x0e5c, /* 13 */ 229 0x0f72, /* 14 */ 230 }; 231 232 static uint8_t urtw_8225_gain[] = { 233 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 234 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 235 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 236 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 237 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 238 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 239 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 240 }; 241 242 static struct urtw_pair urtw_8225_rf_part1[] = { 243 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 244 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 245 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 246 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 247 }; 248 249 static struct urtw_pair urtw_8225_rf_part2[] = { 250 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 251 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 252 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 253 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 254 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 255 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 256 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 257 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 258 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 259 { 0x27, 0x88 } 260 }; 261 262 static struct urtw_pair urtw_8225_rf_part3[] = { 263 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 264 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 265 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 266 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 267 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 268 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 269 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 270 }; 271 272 static uint16_t urtw_8225_rxgain[] = { 273 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 274 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 275 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 276 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 277 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 278 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 279 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 280 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 281 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 282 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 283 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 284 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 285 }; 286 287 static uint8_t urtw_8225_threshold[] = { 288 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 289 }; 290 291 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 292 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 293 }; 294 295 static uint8_t urtw_8225_txpwr_cck[] = { 296 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 297 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 298 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 299 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 300 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 301 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 302 }; 303 304 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 305 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 306 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 307 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 308 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 309 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 310 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 311 }; 312 313 static uint8_t urtw_8225_txpwr_ofdm[]={ 314 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 315 }; 316 317 static uint8_t urtw_8225v2_gain_bg[]={ 318 0x23, 0x15, 0xa5, /* -82-1dbm */ 319 0x23, 0x15, 0xb5, /* -82-2dbm */ 320 0x23, 0x15, 0xc5, /* -82-3dbm */ 321 0x33, 0x15, 0xc5, /* -78dbm */ 322 0x43, 0x15, 0xc5, /* -74dbm */ 323 0x53, 0x15, 0xc5, /* -70dbm */ 324 0x63, 0x15, 0xc5, /* -66dbm */ 325 }; 326 327 static struct urtw_pair urtw_8225v2_rf_part1[] = { 328 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 329 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 330 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 331 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 332 }; 333 334 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 335 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 336 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 337 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 338 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 339 }; 340 341 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 342 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 343 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 344 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 345 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 346 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 347 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 348 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 349 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 350 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 351 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 352 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 353 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 354 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 355 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 356 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 357 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 358 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 359 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 360 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 361 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 362 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 363 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 364 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 365 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 366 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 367 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 368 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 369 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 370 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 371 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 372 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 373 }; 374 375 static struct urtw_pair urtw_8225v2_rf_part2[] = { 376 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 377 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 378 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 379 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 380 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 381 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 382 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 383 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 384 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 385 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 386 }; 387 388 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 389 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 390 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 391 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 392 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 393 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 394 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 395 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 396 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 397 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 398 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 399 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 400 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 401 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 402 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 403 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 404 }; 405 406 static struct urtw_pair urtw_8225v2_rf_part3[] = { 407 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 408 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 409 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 410 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 411 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 412 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 413 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 414 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 415 }; 416 417 static uint16_t urtw_8225v2_rxgain[] = { 418 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 419 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 420 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 421 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 422 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 423 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 424 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 425 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 426 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 427 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 428 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 429 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 430 }; 431 432 static uint16_t urtw_8225v2b_rxgain[] = { 433 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 434 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 435 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 436 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 437 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 438 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 439 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 440 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 441 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 442 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 443 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 444 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 445 }; 446 447 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 448 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 449 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 450 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 451 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 452 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 453 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 454 }; 455 456 static uint8_t urtw_8225v2_txpwr_cck[] = { 457 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 458 }; 459 460 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 461 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 462 }; 463 464 static uint8_t urtw_8225v2b_txpwr_cck[] = { 465 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 466 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 467 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 468 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 469 }; 470 471 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 472 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 474 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 475 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 476 }; 477 478 static struct urtw_pair urtw_ratetable[] = { 479 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 480 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 481 { 96, 10 }, { 108, 11 } 482 }; 483 484 #if 0 485 static const uint8_t urtw_8187b_reg_table[][3] = { 486 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 487 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 488 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 489 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 490 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 491 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 492 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 493 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 494 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 495 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 496 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 497 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 498 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 499 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 500 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 501 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 502 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 503 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 504 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 505 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 506 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 507 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 508 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 509 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 510 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 511 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 512 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 513 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 514 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 515 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 516 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 517 }; 518 #endif 519 520 static usb_callback_t urtw_bulk_rx_callback; 521 static usb_callback_t urtw_bulk_tx_callback; 522 static usb_callback_t urtw_bulk_tx_status_callback; 523 524 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 525 [URTW_8187B_BULK_RX] = { 526 .type = UE_BULK, 527 .endpoint = 0x83, 528 .direction = UE_DIR_IN, 529 .bufsize = MCLBYTES, 530 .flags = { 531 .ext_buffer = 1, 532 .pipe_bof = 1, 533 .short_xfer_ok = 1 534 }, 535 .callback = urtw_bulk_rx_callback 536 }, 537 [URTW_8187B_BULK_TX_STATUS] = { 538 .type = UE_BULK, 539 .endpoint = 0x89, 540 .direction = UE_DIR_IN, 541 .bufsize = sizeof(uint64_t), 542 .flags = { 543 .pipe_bof = 1, 544 .short_xfer_ok = 1 545 }, 546 .callback = urtw_bulk_tx_status_callback 547 }, 548 [URTW_8187B_BULK_TX_BE] = { 549 .type = UE_BULK, 550 .endpoint = URTW_8187B_TXPIPE_BE, 551 .direction = UE_DIR_OUT, 552 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 553 .flags = { 554 .force_short_xfer = 1, 555 .pipe_bof = 1, 556 }, 557 .callback = urtw_bulk_tx_callback, 558 .timeout = URTW_DATA_TIMEOUT 559 }, 560 [URTW_8187B_BULK_TX_BK] = { 561 .type = UE_BULK, 562 .endpoint = URTW_8187B_TXPIPE_BK, 563 .direction = UE_DIR_OUT, 564 .bufsize = URTW_TX_MAXSIZE, 565 .flags = { 566 .ext_buffer = 1, 567 .force_short_xfer = 1, 568 .pipe_bof = 1, 569 }, 570 .callback = urtw_bulk_tx_callback, 571 .timeout = URTW_DATA_TIMEOUT 572 }, 573 [URTW_8187B_BULK_TX_VI] = { 574 .type = UE_BULK, 575 .endpoint = URTW_8187B_TXPIPE_VI, 576 .direction = UE_DIR_OUT, 577 .bufsize = URTW_TX_MAXSIZE, 578 .flags = { 579 .ext_buffer = 1, 580 .force_short_xfer = 1, 581 .pipe_bof = 1, 582 }, 583 .callback = urtw_bulk_tx_callback, 584 .timeout = URTW_DATA_TIMEOUT 585 }, 586 [URTW_8187B_BULK_TX_VO] = { 587 .type = UE_BULK, 588 .endpoint = URTW_8187B_TXPIPE_VO, 589 .direction = UE_DIR_OUT, 590 .bufsize = URTW_TX_MAXSIZE, 591 .flags = { 592 .ext_buffer = 1, 593 .force_short_xfer = 1, 594 .pipe_bof = 1, 595 }, 596 .callback = urtw_bulk_tx_callback, 597 .timeout = URTW_DATA_TIMEOUT 598 }, 599 [URTW_8187B_BULK_TX_EP12] = { 600 .type = UE_BULK, 601 .endpoint = 0xc, 602 .direction = UE_DIR_OUT, 603 .bufsize = URTW_TX_MAXSIZE, 604 .flags = { 605 .ext_buffer = 1, 606 .force_short_xfer = 1, 607 .pipe_bof = 1, 608 }, 609 .callback = urtw_bulk_tx_callback, 610 .timeout = URTW_DATA_TIMEOUT 611 } 612 }; 613 614 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 615 [URTW_8187L_BULK_RX] = { 616 .type = UE_BULK, 617 .endpoint = 0x81, 618 .direction = UE_DIR_IN, 619 .bufsize = MCLBYTES, 620 .flags = { 621 .ext_buffer = 1, 622 .pipe_bof = 1, 623 .short_xfer_ok = 1 624 }, 625 .callback = urtw_bulk_rx_callback 626 }, 627 [URTW_8187L_BULK_TX_LOW] = { 628 .type = UE_BULK, 629 .endpoint = 0x2, 630 .direction = UE_DIR_OUT, 631 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 632 .flags = { 633 .force_short_xfer = 1, 634 .pipe_bof = 1, 635 }, 636 .callback = urtw_bulk_tx_callback, 637 .timeout = URTW_DATA_TIMEOUT 638 }, 639 [URTW_8187L_BULK_TX_NORMAL] = { 640 .type = UE_BULK, 641 .endpoint = 0x3, 642 .direction = UE_DIR_OUT, 643 .bufsize = URTW_TX_MAXSIZE, 644 .flags = { 645 .ext_buffer = 1, 646 .force_short_xfer = 1, 647 .pipe_bof = 1, 648 }, 649 .callback = urtw_bulk_tx_callback, 650 .timeout = URTW_DATA_TIMEOUT 651 }, 652 }; 653 654 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 655 const char [IFNAMSIZ], int, enum ieee80211_opmode, 656 int, const uint8_t [IEEE80211_ADDR_LEN], 657 const uint8_t [IEEE80211_ADDR_LEN]); 658 static void urtw_vap_delete(struct ieee80211vap *); 659 static void urtw_init(struct urtw_softc *); 660 static void urtw_stop(struct urtw_softc *); 661 static void urtw_parent(struct ieee80211com *); 662 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 663 static void urtw_start(struct urtw_softc *); 664 static int urtw_alloc_rx_data_list(struct urtw_softc *); 665 static int urtw_alloc_tx_data_list(struct urtw_softc *); 666 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 667 const struct ieee80211_bpf_params *); 668 static void urtw_scan_start(struct ieee80211com *); 669 static void urtw_scan_end(struct ieee80211com *); 670 static void urtw_getradiocaps(struct ieee80211com *, int, int *, 671 struct ieee80211_channel[]); 672 static void urtw_set_channel(struct ieee80211com *); 673 static void urtw_update_promisc(struct ieee80211com *); 674 static void urtw_update_mcast(struct ieee80211com *); 675 static int urtw_tx_start(struct urtw_softc *, 676 struct ieee80211_node *, struct mbuf *, 677 struct urtw_data *, int); 678 static int urtw_newstate(struct ieee80211vap *, 679 enum ieee80211_state, int); 680 static void urtw_led_ch(void *); 681 static void urtw_ledtask(void *, int); 682 static void urtw_watchdog(void *); 683 static void urtw_set_multi(void *); 684 static int urtw_isbmode(uint16_t); 685 static uint16_t urtw_rtl2rate(uint32_t); 686 static usb_error_t urtw_set_rate(struct urtw_softc *); 687 static usb_error_t urtw_update_msr(struct urtw_softc *); 688 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 689 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 690 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 691 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 692 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 693 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 694 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 695 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 696 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 697 int); 698 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 699 uint32_t *); 700 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 701 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 702 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 703 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 704 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 705 static usb_error_t urtw_led_init(struct urtw_softc *); 706 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 707 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 708 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 709 uint32_t); 710 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 711 uint8_t, uint32_t); 712 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 713 uint32_t); 714 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 715 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 716 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 717 uint16_t); 718 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 719 uint16_t *); 720 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 721 uint32_t *); 722 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 723 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 724 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 725 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 726 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 727 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 728 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 729 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 730 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 731 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 732 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 733 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 734 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 735 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 736 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 737 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 738 static usb_error_t urtw_intr_enable(struct urtw_softc *); 739 static usb_error_t urtw_intr_disable(struct urtw_softc *); 740 static usb_error_t urtw_reset(struct urtw_softc *); 741 static usb_error_t urtw_led_on(struct urtw_softc *, int); 742 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 743 static usb_error_t urtw_led_blink(struct urtw_softc *); 744 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 745 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 746 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 747 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 748 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 749 static usb_error_t urtw_rx_enable(struct urtw_softc *); 750 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 751 static void urtw_free_tx_data_list(struct urtw_softc *); 752 static void urtw_free_rx_data_list(struct urtw_softc *); 753 static void urtw_free_data_list(struct urtw_softc *, 754 struct urtw_data data[], int, int); 755 static usb_error_t urtw_adapter_start(struct urtw_softc *); 756 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 757 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 758 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 759 static usb_error_t urtw_do_request(struct urtw_softc *, 760 struct usb_device_request *, void *); 761 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 762 static usb_error_t urtw_led_off(struct urtw_softc *, int); 763 static void urtw_abort_xfers(struct urtw_softc *); 764 static struct urtw_data * 765 urtw_getbuf(struct urtw_softc *sc); 766 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 767 uint8_t); 768 static void urtw_updateslot(struct ieee80211com *); 769 static void urtw_updateslottask(void *, int); 770 static void urtw_sysctl_node(struct urtw_softc *); 771 772 static int 773 urtw_match(device_t dev) 774 { 775 struct usb_attach_arg *uaa = device_get_ivars(dev); 776 777 if (uaa->usb_mode != USB_MODE_HOST) 778 return (ENXIO); 779 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 780 return (ENXIO); 781 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 782 return (ENXIO); 783 784 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 785 } 786 787 static int 788 urtw_attach(device_t dev) 789 { 790 const struct usb_config *setup_start; 791 int ret = ENXIO; 792 struct urtw_softc *sc = device_get_softc(dev); 793 struct usb_attach_arg *uaa = device_get_ivars(dev); 794 struct ieee80211com *ic = &sc->sc_ic; 795 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 796 uint16_t n_setup; 797 uint32_t data; 798 usb_error_t error; 799 800 device_set_usb_desc(dev); 801 802 sc->sc_dev = dev; 803 sc->sc_udev = uaa->device; 804 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 805 sc->sc_flags |= URTW_RTL8187B; 806 #ifdef URTW_DEBUG 807 sc->sc_debug = urtw_debug; 808 #endif 809 810 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 811 MTX_DEF); 812 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 813 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 814 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 815 callout_init(&sc->sc_watchdog_ch, 0); 816 mbufq_init(&sc->sc_snd, ifqmaxlen); 817 818 if (sc->sc_flags & URTW_RTL8187B) { 819 setup_start = urtw_8187b_usbconfig; 820 n_setup = URTW_8187B_N_XFERS; 821 } else { 822 setup_start = urtw_8187l_usbconfig; 823 n_setup = URTW_8187L_N_XFERS; 824 } 825 826 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 827 setup_start, n_setup, sc, &sc->sc_mtx); 828 if (error) { 829 device_printf(dev, "could not allocate USB transfers, " 830 "err=%s\n", usbd_errstr(error)); 831 ret = ENXIO; 832 goto fail0; 833 } 834 835 if (sc->sc_flags & URTW_RTL8187B) { 836 sc->sc_tx_dma_buf = 837 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 838 URTW_8187B_BULK_TX_BE], 0); 839 } else { 840 sc->sc_tx_dma_buf = 841 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 842 URTW_8187L_BULK_TX_LOW], 0); 843 } 844 845 URTW_LOCK(sc); 846 847 urtw_read32_m(sc, URTW_RX, &data); 848 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 849 URTW_EEPROM_93C46; 850 851 error = urtw_get_rfchip(sc); 852 if (error != 0) 853 goto fail; 854 error = urtw_get_macaddr(sc); 855 if (error != 0) 856 goto fail; 857 error = urtw_get_txpwr(sc); 858 if (error != 0) 859 goto fail; 860 error = urtw_led_init(sc); 861 if (error != 0) 862 goto fail; 863 864 URTW_UNLOCK(sc); 865 866 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 867 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 868 sc->sc_currate = URTW_RIDX_CCK11; 869 sc->sc_preamble_mode = urtw_preamble_mode; 870 871 ic->ic_softc = sc; 872 ic->ic_name = device_get_nameunit(dev); 873 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 874 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 875 876 /* set device capabilities */ 877 ic->ic_caps = 878 IEEE80211_C_STA | /* station mode */ 879 IEEE80211_C_MONITOR | /* monitor mode supported */ 880 IEEE80211_C_TXPMGT | /* tx power management */ 881 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 882 IEEE80211_C_SHSLOT | /* short slot time supported */ 883 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 884 IEEE80211_C_WPA; /* 802.11i */ 885 886 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 887 888 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 889 ic->ic_channels); 890 891 ieee80211_ifattach(ic); 892 ic->ic_raw_xmit = urtw_raw_xmit; 893 ic->ic_scan_start = urtw_scan_start; 894 ic->ic_scan_end = urtw_scan_end; 895 ic->ic_getradiocaps = urtw_getradiocaps; 896 ic->ic_set_channel = urtw_set_channel; 897 ic->ic_updateslot = urtw_updateslot; 898 ic->ic_vap_create = urtw_vap_create; 899 ic->ic_vap_delete = urtw_vap_delete; 900 ic->ic_update_promisc = urtw_update_promisc; 901 ic->ic_update_mcast = urtw_update_mcast; 902 ic->ic_parent = urtw_parent; 903 ic->ic_transmit = urtw_transmit; 904 905 ieee80211_radiotap_attach(ic, 906 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 907 URTW_TX_RADIOTAP_PRESENT, 908 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 909 URTW_RX_RADIOTAP_PRESENT); 910 911 urtw_sysctl_node(sc); 912 913 if (bootverbose) 914 ieee80211_announce(ic); 915 return (0); 916 917 fail: 918 URTW_UNLOCK(sc); 919 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 920 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 921 fail0: 922 return (ret); 923 } 924 925 static int 926 urtw_detach(device_t dev) 927 { 928 struct urtw_softc *sc = device_get_softc(dev); 929 struct ieee80211com *ic = &sc->sc_ic; 930 unsigned int x; 931 unsigned int n_xfers; 932 933 /* Prevent further ioctls */ 934 URTW_LOCK(sc); 935 sc->sc_flags |= URTW_DETACHED; 936 urtw_stop(sc); 937 URTW_UNLOCK(sc); 938 939 ieee80211_draintask(ic, &sc->sc_updateslot_task); 940 ieee80211_draintask(ic, &sc->sc_led_task); 941 942 usb_callout_drain(&sc->sc_led_ch); 943 callout_drain(&sc->sc_watchdog_ch); 944 945 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 946 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 947 948 /* prevent further allocations from RX/TX data lists */ 949 URTW_LOCK(sc); 950 STAILQ_INIT(&sc->sc_tx_active); 951 STAILQ_INIT(&sc->sc_tx_inactive); 952 STAILQ_INIT(&sc->sc_tx_pending); 953 954 STAILQ_INIT(&sc->sc_rx_active); 955 STAILQ_INIT(&sc->sc_rx_inactive); 956 URTW_UNLOCK(sc); 957 958 /* drain USB transfers */ 959 for (x = 0; x != n_xfers; x++) 960 usbd_transfer_drain(sc->sc_xfer[x]); 961 962 /* free data buffers */ 963 URTW_LOCK(sc); 964 urtw_free_tx_data_list(sc); 965 urtw_free_rx_data_list(sc); 966 URTW_UNLOCK(sc); 967 968 /* free USB transfers and some data buffers */ 969 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 970 971 ieee80211_ifdetach(ic); 972 mbufq_drain(&sc->sc_snd); 973 mtx_destroy(&sc->sc_mtx); 974 return (0); 975 } 976 977 static void 978 urtw_free_tx_data_list(struct urtw_softc *sc) 979 { 980 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 981 } 982 983 static void 984 urtw_free_rx_data_list(struct urtw_softc *sc) 985 { 986 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 987 } 988 989 static void 990 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 991 int fillmbuf) 992 { 993 int i; 994 995 for (i = 0; i < ndata; i++) { 996 struct urtw_data *dp = &data[i]; 997 998 if (fillmbuf == 1) { 999 if (dp->m != NULL) { 1000 m_freem(dp->m); 1001 dp->m = NULL; 1002 dp->buf = NULL; 1003 } 1004 } else { 1005 dp->buf = NULL; 1006 } 1007 if (dp->ni != NULL) { 1008 ieee80211_free_node(dp->ni); 1009 dp->ni = NULL; 1010 } 1011 } 1012 } 1013 1014 static struct ieee80211vap * 1015 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1016 enum ieee80211_opmode opmode, int flags, 1017 const uint8_t bssid[IEEE80211_ADDR_LEN], 1018 const uint8_t mac[IEEE80211_ADDR_LEN]) 1019 { 1020 struct urtw_vap *uvp; 1021 struct ieee80211vap *vap; 1022 1023 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1024 return (NULL); 1025 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1026 vap = &uvp->vap; 1027 /* enable s/w bmiss handling for sta mode */ 1028 1029 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1030 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1031 /* out of memory */ 1032 free(uvp, M_80211_VAP); 1033 return (NULL); 1034 } 1035 1036 /* override state transition machine */ 1037 uvp->newstate = vap->iv_newstate; 1038 vap->iv_newstate = urtw_newstate; 1039 1040 /* complete setup */ 1041 ieee80211_vap_attach(vap, ieee80211_media_change, 1042 ieee80211_media_status, mac); 1043 ic->ic_opmode = opmode; 1044 return (vap); 1045 } 1046 1047 static void 1048 urtw_vap_delete(struct ieee80211vap *vap) 1049 { 1050 struct urtw_vap *uvp = URTW_VAP(vap); 1051 1052 ieee80211_vap_detach(vap); 1053 free(uvp, M_80211_VAP); 1054 } 1055 1056 static void 1057 urtw_init(struct urtw_softc *sc) 1058 { 1059 usb_error_t error; 1060 int ret; 1061 1062 URTW_ASSERT_LOCKED(sc); 1063 1064 if (sc->sc_flags & URTW_RUNNING) 1065 urtw_stop(sc); 1066 1067 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1068 urtw_adapter_start(sc); 1069 if (error != 0) 1070 goto fail; 1071 1072 /* reset softc variables */ 1073 sc->sc_txtimer = 0; 1074 1075 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1076 ret = urtw_alloc_rx_data_list(sc); 1077 if (ret != 0) 1078 goto fail; 1079 ret = urtw_alloc_tx_data_list(sc); 1080 if (ret != 0) 1081 goto fail; 1082 sc->sc_flags |= URTW_INIT_ONCE; 1083 } 1084 1085 error = urtw_rx_enable(sc); 1086 if (error != 0) 1087 goto fail; 1088 error = urtw_tx_enable(sc); 1089 if (error != 0) 1090 goto fail; 1091 1092 if (sc->sc_flags & URTW_RTL8187B) 1093 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1094 1095 sc->sc_flags |= URTW_RUNNING; 1096 1097 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1098 fail: 1099 return; 1100 } 1101 1102 static usb_error_t 1103 urtw_adapter_start_b(struct urtw_softc *sc) 1104 { 1105 uint8_t data8; 1106 usb_error_t error; 1107 1108 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1109 if (error) 1110 goto fail; 1111 1112 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1113 urtw_write8_m(sc, URTW_CONFIG3, 1114 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1115 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1116 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1117 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1118 1119 urtw_write8_m(sc, 0x61, 0x10); 1120 urtw_read8_m(sc, 0x62, &data8); 1121 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1122 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1123 1124 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1125 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1126 urtw_write8_m(sc, URTW_CONFIG3, data8); 1127 1128 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1129 if (error) 1130 goto fail; 1131 1132 error = urtw_8187b_cmd_reset(sc); 1133 if (error) 1134 goto fail; 1135 1136 error = sc->sc_rf_init(sc); 1137 if (error != 0) 1138 goto fail; 1139 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1140 1141 /* fix RTL8187B RX stall */ 1142 error = urtw_intr_enable(sc); 1143 if (error) 1144 goto fail; 1145 1146 error = urtw_write8e(sc, 0x41, 0xf4); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x40, 0x00); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x00); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x42, 0x01); 1156 if (error) 1157 goto fail; 1158 error = urtw_write8e(sc, 0x40, 0x0f); 1159 if (error) 1160 goto fail; 1161 error = urtw_write8e(sc, 0x42, 0x00); 1162 if (error) 1163 goto fail; 1164 error = urtw_write8e(sc, 0x42, 0x01); 1165 if (error) 1166 goto fail; 1167 1168 urtw_read8_m(sc, 0xdb, &data8); 1169 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1170 urtw_write16_m(sc, 0x372, 0x59fa); 1171 urtw_write16_m(sc, 0x374, 0x59d2); 1172 urtw_write16_m(sc, 0x376, 0x59d2); 1173 urtw_write16_m(sc, 0x378, 0x19fa); 1174 urtw_write16_m(sc, 0x37a, 0x19fa); 1175 urtw_write16_m(sc, 0x37c, 0x00d0); 1176 urtw_write8_m(sc, 0x61, 0); 1177 1178 urtw_write8_m(sc, 0x180, 0x0f); 1179 urtw_write8_m(sc, 0x183, 0x03); 1180 urtw_write8_m(sc, 0xda, 0x10); 1181 urtw_write8_m(sc, 0x24d, 0x08); 1182 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1183 1184 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1185 fail: 1186 return (error); 1187 } 1188 1189 static usb_error_t 1190 urtw_adapter_start(struct urtw_softc *sc) 1191 { 1192 struct ieee80211com *ic = &sc->sc_ic; 1193 usb_error_t error; 1194 1195 error = urtw_reset(sc); 1196 if (error) 1197 goto fail; 1198 1199 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1200 urtw_write8_m(sc, URTW_GPIO, 0); 1201 1202 /* for led */ 1203 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1204 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1205 if (error != 0) 1206 goto fail; 1207 1208 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1209 if (error) 1210 goto fail; 1211 /* applying MAC address again. */ 1212 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1213 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1214 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1215 if (error) 1216 goto fail; 1217 1218 error = urtw_update_msr(sc); 1219 if (error) 1220 goto fail; 1221 1222 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1223 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1224 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1225 error = urtw_set_rate(sc); 1226 if (error != 0) 1227 goto fail; 1228 1229 error = sc->sc_rf_init(sc); 1230 if (error != 0) 1231 goto fail; 1232 if (sc->sc_rf_set_sens != NULL) 1233 sc->sc_rf_set_sens(sc, sc->sc_sens); 1234 1235 /* XXX correct? to call write16 */ 1236 urtw_write16_m(sc, URTW_PSR, 1); 1237 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1238 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1239 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1240 /* XXX correct? to call write16 */ 1241 urtw_write16_m(sc, URTW_PSR, 0); 1242 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1243 1244 error = urtw_intr_enable(sc); 1245 if (error != 0) 1246 goto fail; 1247 1248 fail: 1249 return (error); 1250 } 1251 1252 static usb_error_t 1253 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1254 { 1255 uint8_t data; 1256 usb_error_t error; 1257 1258 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1259 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1260 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1261 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1262 fail: 1263 return (error); 1264 } 1265 1266 static usb_error_t 1267 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1268 { 1269 int i; 1270 uint8_t data8; 1271 usb_error_t error; 1272 1273 /* XXX the code can be duplicate with urtw_reset(). */ 1274 urtw_read8_m(sc, URTW_CMD, &data8); 1275 data8 = (data8 & 0x2) | URTW_CMD_RST; 1276 urtw_write8_m(sc, URTW_CMD, data8); 1277 1278 for (i = 0; i < 20; i++) { 1279 usb_pause_mtx(&sc->sc_mtx, 2); 1280 urtw_read8_m(sc, URTW_CMD, &data8); 1281 if (!(data8 & URTW_CMD_RST)) 1282 break; 1283 } 1284 if (i >= 20) { 1285 device_printf(sc->sc_dev, "reset timeout\n"); 1286 goto fail; 1287 } 1288 fail: 1289 return (error); 1290 } 1291 1292 static usb_error_t 1293 urtw_do_request(struct urtw_softc *sc, 1294 struct usb_device_request *req, void *data) 1295 { 1296 usb_error_t err; 1297 int ntries = 10; 1298 1299 URTW_ASSERT_LOCKED(sc); 1300 1301 while (ntries--) { 1302 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1303 req, data, 0, NULL, 250 /* ms */); 1304 if (err == 0) 1305 break; 1306 1307 DPRINTF(sc, URTW_DEBUG_INIT, 1308 "Control request failed, %s (retrying)\n", 1309 usbd_errstr(err)); 1310 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1311 } 1312 return (err); 1313 } 1314 1315 static void 1316 urtw_stop(struct urtw_softc *sc) 1317 { 1318 uint8_t data8; 1319 usb_error_t error; 1320 1321 URTW_ASSERT_LOCKED(sc); 1322 1323 sc->sc_flags &= ~URTW_RUNNING; 1324 1325 error = urtw_intr_disable(sc); 1326 if (error) 1327 goto fail; 1328 urtw_read8_m(sc, URTW_CMD, &data8); 1329 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1330 urtw_write8_m(sc, URTW_CMD, data8); 1331 1332 error = sc->sc_rf_stop(sc); 1333 if (error != 0) 1334 goto fail; 1335 1336 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1337 if (error) 1338 goto fail; 1339 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1340 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1341 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1342 if (error) 1343 goto fail; 1344 fail: 1345 if (error) 1346 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1347 usbd_errstr(error)); 1348 1349 usb_callout_stop(&sc->sc_led_ch); 1350 callout_stop(&sc->sc_watchdog_ch); 1351 1352 urtw_abort_xfers(sc); 1353 } 1354 1355 static void 1356 urtw_abort_xfers(struct urtw_softc *sc) 1357 { 1358 int i, max; 1359 1360 URTW_ASSERT_LOCKED(sc); 1361 1362 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1363 URTW_8187L_N_XFERS; 1364 1365 /* abort any pending transfers */ 1366 for (i = 0; i < max; i++) 1367 usbd_transfer_stop(sc->sc_xfer[i]); 1368 } 1369 1370 static void 1371 urtw_parent(struct ieee80211com *ic) 1372 { 1373 struct urtw_softc *sc = ic->ic_softc; 1374 int startall = 0; 1375 1376 URTW_LOCK(sc); 1377 if (sc->sc_flags & URTW_DETACHED) { 1378 URTW_UNLOCK(sc); 1379 return; 1380 } 1381 1382 if (ic->ic_nrunning > 0) { 1383 if (sc->sc_flags & URTW_RUNNING) { 1384 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1385 urtw_set_multi(sc); 1386 } else { 1387 urtw_init(sc); 1388 startall = 1; 1389 } 1390 } else if (sc->sc_flags & URTW_RUNNING) 1391 urtw_stop(sc); 1392 URTW_UNLOCK(sc); 1393 if (startall) 1394 ieee80211_start_all(ic); 1395 } 1396 1397 static int 1398 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1399 { 1400 struct urtw_softc *sc = ic->ic_softc; 1401 int error; 1402 1403 URTW_LOCK(sc); 1404 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1405 URTW_UNLOCK(sc); 1406 return (ENXIO); 1407 } 1408 error = mbufq_enqueue(&sc->sc_snd, m); 1409 if (error) { 1410 URTW_UNLOCK(sc); 1411 return (error); 1412 } 1413 urtw_start(sc); 1414 URTW_UNLOCK(sc); 1415 1416 return (0); 1417 } 1418 1419 static void 1420 urtw_start(struct urtw_softc *sc) 1421 { 1422 struct urtw_data *bf; 1423 struct ieee80211_node *ni; 1424 struct mbuf *m; 1425 1426 URTW_ASSERT_LOCKED(sc); 1427 1428 if ((sc->sc_flags & URTW_RUNNING) == 0) 1429 return; 1430 1431 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1432 bf = urtw_getbuf(sc); 1433 if (bf == NULL) { 1434 mbufq_prepend(&sc->sc_snd, m); 1435 break; 1436 } 1437 1438 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1439 m->m_pkthdr.rcvif = NULL; 1440 1441 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1442 if_inc_counter(ni->ni_vap->iv_ifp, 1443 IFCOUNTER_OERRORS, 1); 1444 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1445 ieee80211_free_node(ni); 1446 break; 1447 } 1448 1449 sc->sc_txtimer = 5; 1450 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1451 } 1452 } 1453 1454 static int 1455 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1456 int ndata, int maxsz, void *dma_buf) 1457 { 1458 int i, error; 1459 1460 for (i = 0; i < ndata; i++) { 1461 struct urtw_data *dp = &data[i]; 1462 1463 dp->sc = sc; 1464 if (dma_buf == NULL) { 1465 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1466 if (dp->m == NULL) { 1467 device_printf(sc->sc_dev, 1468 "could not allocate rx mbuf\n"); 1469 error = ENOMEM; 1470 goto fail; 1471 } 1472 dp->buf = mtod(dp->m, uint8_t *); 1473 } else { 1474 dp->m = NULL; 1475 dp->buf = ((uint8_t *)dma_buf) + 1476 (i * maxsz); 1477 } 1478 dp->ni = NULL; 1479 } 1480 return (0); 1481 1482 fail: urtw_free_data_list(sc, data, ndata, 1); 1483 return (error); 1484 } 1485 1486 static int 1487 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1488 { 1489 int error, i; 1490 1491 error = urtw_alloc_data_list(sc, 1492 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1493 MCLBYTES, NULL /* mbufs */); 1494 if (error != 0) 1495 return (error); 1496 1497 STAILQ_INIT(&sc->sc_rx_active); 1498 STAILQ_INIT(&sc->sc_rx_inactive); 1499 1500 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1501 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1502 1503 return (0); 1504 } 1505 1506 static int 1507 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1508 { 1509 int error, i; 1510 1511 error = urtw_alloc_data_list(sc, 1512 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1513 sc->sc_tx_dma_buf /* no mbufs */); 1514 if (error != 0) 1515 return (error); 1516 1517 STAILQ_INIT(&sc->sc_tx_active); 1518 STAILQ_INIT(&sc->sc_tx_inactive); 1519 STAILQ_INIT(&sc->sc_tx_pending); 1520 1521 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1522 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1523 next); 1524 1525 return (0); 1526 } 1527 1528 static int 1529 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1530 const struct ieee80211_bpf_params *params) 1531 { 1532 struct ieee80211com *ic = ni->ni_ic; 1533 struct urtw_softc *sc = ic->ic_softc; 1534 struct urtw_data *bf; 1535 1536 /* prevent management frames from being sent if we're not ready */ 1537 if (!(sc->sc_flags & URTW_RUNNING)) { 1538 m_freem(m); 1539 return ENETDOWN; 1540 } 1541 URTW_LOCK(sc); 1542 bf = urtw_getbuf(sc); 1543 if (bf == NULL) { 1544 m_freem(m); 1545 URTW_UNLOCK(sc); 1546 return (ENOBUFS); /* XXX */ 1547 } 1548 1549 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1550 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1551 URTW_UNLOCK(sc); 1552 return (EIO); 1553 } 1554 URTW_UNLOCK(sc); 1555 1556 sc->sc_txtimer = 5; 1557 return (0); 1558 } 1559 1560 static void 1561 urtw_scan_start(struct ieee80211com *ic) 1562 { 1563 1564 /* XXX do nothing? */ 1565 } 1566 1567 static void 1568 urtw_scan_end(struct ieee80211com *ic) 1569 { 1570 1571 /* XXX do nothing? */ 1572 } 1573 1574 static void 1575 urtw_getradiocaps(struct ieee80211com *ic, 1576 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1577 { 1578 uint8_t bands[IEEE80211_MODE_BYTES]; 1579 1580 memset(bands, 0, sizeof(bands)); 1581 setbit(bands, IEEE80211_MODE_11B); 1582 setbit(bands, IEEE80211_MODE_11G); 1583 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1584 } 1585 1586 static void 1587 urtw_set_channel(struct ieee80211com *ic) 1588 { 1589 struct urtw_softc *sc = ic->ic_softc; 1590 uint32_t data, orig; 1591 usb_error_t error; 1592 1593 /* 1594 * if the user set a channel explicitly using ifconfig(8) this function 1595 * can be called earlier than we're expected that in some cases the 1596 * initialization would be failed if setting a channel is called before 1597 * the init have done. 1598 */ 1599 if (!(sc->sc_flags & URTW_RUNNING)) 1600 return; 1601 1602 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1603 return; 1604 1605 URTW_LOCK(sc); 1606 1607 /* 1608 * during changing th channel we need to temporarily be disable 1609 * TX. 1610 */ 1611 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1612 data = orig & ~URTW_TX_LOOPBACK_MASK; 1613 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1614 1615 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1616 if (error != 0) 1617 goto fail; 1618 usb_pause_mtx(&sc->sc_mtx, 10); 1619 urtw_write32_m(sc, URTW_TX_CONF, orig); 1620 1621 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1622 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1623 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1624 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1625 1626 fail: 1627 URTW_UNLOCK(sc); 1628 1629 sc->sc_curchan = ic->ic_curchan; 1630 1631 if (error != 0) 1632 device_printf(sc->sc_dev, "could not change the channel\n"); 1633 } 1634 1635 static void 1636 urtw_update_promisc(struct ieee80211com *ic) 1637 { 1638 struct urtw_softc *sc = ic->ic_softc; 1639 1640 URTW_LOCK(sc); 1641 if (sc->sc_flags & URTW_RUNNING) 1642 urtw_rx_setconf(sc); 1643 URTW_UNLOCK(sc); 1644 } 1645 1646 static void 1647 urtw_update_mcast(struct ieee80211com *ic) 1648 { 1649 1650 /* XXX do nothing? */ 1651 } 1652 1653 static int 1654 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1655 struct urtw_data *data, int prior) 1656 { 1657 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1658 struct ieee80211_key *k; 1659 const struct ieee80211_txparam *tp = ni->ni_txparms; 1660 struct ieee80211com *ic = &sc->sc_ic; 1661 struct ieee80211vap *vap = ni->ni_vap; 1662 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1663 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1664 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1665 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1666 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1667 }; 1668 struct usb_xfer *xfer; 1669 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, type, 1670 pkttime = 0, txdur = 0, isshort = 0, xferlen, ismcast; 1671 uint16_t acktime, rtstime, ctstime; 1672 uint32_t flags; 1673 usb_error_t error; 1674 1675 URTW_ASSERT_LOCKED(sc); 1676 1677 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 1678 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 1679 1680 /* 1681 * Software crypto. 1682 */ 1683 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1684 k = ieee80211_crypto_encap(ni, m0); 1685 if (k == NULL) { 1686 device_printf(sc->sc_dev, 1687 "ieee80211_crypto_encap returns NULL.\n"); 1688 /* XXX we don't expect the fragmented frames */ 1689 m_freem(m0); 1690 return (ENOBUFS); 1691 } 1692 1693 /* in case packet header moved, reset pointer */ 1694 wh = mtod(m0, struct ieee80211_frame *); 1695 } 1696 1697 if (ieee80211_radiotap_active_vap(vap)) { 1698 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1699 1700 tap->wt_flags = 0; 1701 ieee80211_radiotap_tx(vap, m0); 1702 } 1703 1704 if (type == IEEE80211_FC0_TYPE_MGT || 1705 type == IEEE80211_FC0_TYPE_CTL || 1706 (m0->m_flags & M_EAPOL) != 0) { 1707 rate = tp->mgmtrate; 1708 } else { 1709 /* for data frames */ 1710 if (ismcast) 1711 rate = tp->mcastrate; 1712 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1713 rate = tp->ucastrate; 1714 else 1715 rate = urtw_rtl2rate(sc->sc_currate); 1716 } 1717 1718 sc->sc_stats.txrates[sc->sc_currate]++; 1719 1720 if (ismcast) 1721 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1722 IEEE80211_CRC_LEN, rate, 0, 0); 1723 else { 1724 acktime = urtw_compute_txtime(14, 2,0, 0); 1725 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1726 rtsenable = 1; 1727 ctsenable = 0; 1728 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1729 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1730 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1731 IEEE80211_CRC_LEN, rate, 0, isshort); 1732 rtsdur = ctstime + pkttime + acktime + 1733 3 * URTW_ASIFS_TIME; 1734 txdur = rtstime + rtsdur; 1735 } else { 1736 rtsenable = ctsenable = rtsdur = 0; 1737 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1738 IEEE80211_CRC_LEN, rate, 0, isshort); 1739 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1740 } 1741 1742 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1743 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1744 IEEE80211_CRC_LEN, rate, 0, isshort) + 1745 3 * URTW_ASIFS_TIME + 1746 2 * acktime; 1747 else 1748 dur = URTW_ASIFS_TIME + acktime; 1749 } 1750 USETW(wh->i_dur, dur); 1751 1752 xferlen = m0->m_pkthdr.len; 1753 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1754 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1755 xferlen += 1; 1756 1757 memset(data->buf, 0, URTW_TX_MAXSIZE); 1758 flags = m0->m_pkthdr.len & 0xfff; 1759 flags |= URTW_TX_FLAG_NO_ENC; 1760 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1761 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1762 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1763 (sc->sc_currate != 0)) 1764 flags |= URTW_TX_FLAG_SPLCP; 1765 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1766 flags |= URTW_TX_FLAG_MOREFRAG; 1767 1768 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1769 1770 if (sc->sc_flags & URTW_RTL8187B) { 1771 struct urtw_8187b_txhdr *tx; 1772 1773 tx = (struct urtw_8187b_txhdr *)data->buf; 1774 if (ctsenable) 1775 flags |= URTW_TX_FLAG_CTS; 1776 if (rtsenable) { 1777 flags |= URTW_TX_FLAG_RTS; 1778 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1779 tx->rtsdur = rtsdur; 1780 } 1781 tx->flag = htole32(flags); 1782 tx->txdur = txdur; 1783 if (type == IEEE80211_FC0_TYPE_MGT && 1784 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1785 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1786 tx->retry = 1; 1787 else 1788 tx->retry = URTW_TX_MAXRETRY; 1789 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1790 } else { 1791 struct urtw_8187l_txhdr *tx; 1792 1793 tx = (struct urtw_8187l_txhdr *)data->buf; 1794 if (rtsenable) { 1795 flags |= URTW_TX_FLAG_RTS; 1796 tx->rtsdur = rtsdur; 1797 } 1798 flags |= URTW_RIDX_CCK5 << URTW_TX_FLAG_RTSRATE_SHIFT; 1799 tx->flag = htole32(flags); 1800 tx->retry = 3; /* CW minimum */ 1801 tx->retry |= 7 << 4; /* CW maximum */ 1802 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1803 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1804 } 1805 1806 data->buflen = xferlen; 1807 data->ni = ni; 1808 data->m = m0; 1809 1810 if (sc->sc_flags & URTW_RTL8187B) { 1811 switch (type) { 1812 case IEEE80211_FC0_TYPE_CTL: 1813 case IEEE80211_FC0_TYPE_MGT: 1814 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1815 break; 1816 default: 1817 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1818 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1819 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1820 break; 1821 } 1822 } else 1823 xfer = (prior == URTW_PRIORITY_LOW) ? 1824 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1825 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1826 1827 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1828 usbd_transfer_start(xfer); 1829 1830 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1831 if (error != 0) 1832 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1833 error); 1834 return (0); 1835 } 1836 1837 static int 1838 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1839 { 1840 struct ieee80211com *ic = vap->iv_ic; 1841 struct urtw_softc *sc = ic->ic_softc; 1842 struct urtw_vap *uvp = URTW_VAP(vap); 1843 struct ieee80211_node *ni; 1844 usb_error_t error = 0; 1845 1846 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1847 ieee80211_state_name[vap->iv_state], 1848 ieee80211_state_name[nstate]); 1849 1850 sc->sc_state = nstate; 1851 1852 IEEE80211_UNLOCK(ic); 1853 URTW_LOCK(sc); 1854 usb_callout_stop(&sc->sc_led_ch); 1855 callout_stop(&sc->sc_watchdog_ch); 1856 1857 switch (nstate) { 1858 case IEEE80211_S_INIT: 1859 case IEEE80211_S_SCAN: 1860 case IEEE80211_S_AUTH: 1861 case IEEE80211_S_ASSOC: 1862 break; 1863 case IEEE80211_S_RUN: 1864 ni = ieee80211_ref_node(vap->iv_bss); 1865 /* setting bssid. */ 1866 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1867 urtw_write16_m(sc, URTW_BSSID + 4, 1868 ((uint16_t *)ni->ni_bssid)[2]); 1869 urtw_update_msr(sc); 1870 /* XXX maybe the below would be incorrect. */ 1871 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1872 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1873 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1874 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1875 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1876 if (error != 0) 1877 device_printf(sc->sc_dev, 1878 "could not control LED (%d)\n", error); 1879 ieee80211_free_node(ni); 1880 break; 1881 default: 1882 break; 1883 } 1884 fail: 1885 URTW_UNLOCK(sc); 1886 IEEE80211_LOCK(ic); 1887 return (uvp->newstate(vap, nstate, arg)); 1888 } 1889 1890 static void 1891 urtw_watchdog(void *arg) 1892 { 1893 struct urtw_softc *sc = arg; 1894 struct ieee80211com *ic = &sc->sc_ic; 1895 1896 if (sc->sc_txtimer > 0) { 1897 if (--sc->sc_txtimer == 0) { 1898 device_printf(sc->sc_dev, "device timeout\n"); 1899 counter_u64_add(ic->ic_oerrors, 1); 1900 ieee80211_restart_all(ic); 1901 return; 1902 } 1903 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1904 } 1905 } 1906 1907 static void 1908 urtw_set_multi(void *arg) 1909 { 1910 /* XXX don't know how to set a device. Lack of docs. */ 1911 } 1912 1913 static usb_error_t 1914 urtw_set_rate(struct urtw_softc *sc) 1915 { 1916 int i, basic_rate, min_rr_rate, max_rr_rate; 1917 uint16_t data; 1918 usb_error_t error; 1919 1920 basic_rate = URTW_RIDX_OFDM24; 1921 min_rr_rate = URTW_RIDX_OFDM6; 1922 max_rr_rate = URTW_RIDX_OFDM24; 1923 1924 urtw_write8_m(sc, URTW_RESP_RATE, 1925 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1926 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1927 1928 urtw_read16_m(sc, URTW_BRSR, &data); 1929 data &= ~URTW_BRSR_MBR_8185; 1930 1931 for (i = 0; i <= basic_rate; i++) 1932 data |= (1 << i); 1933 1934 urtw_write16_m(sc, URTW_BRSR, data); 1935 fail: 1936 return (error); 1937 } 1938 1939 static uint16_t 1940 urtw_rtl2rate(uint32_t rate) 1941 { 1942 unsigned int i; 1943 1944 for (i = 0; i < nitems(urtw_ratetable); i++) { 1945 if (rate == urtw_ratetable[i].val) 1946 return urtw_ratetable[i].reg; 1947 } 1948 1949 return (0); 1950 } 1951 1952 static usb_error_t 1953 urtw_update_msr(struct urtw_softc *sc) 1954 { 1955 struct ieee80211com *ic = &sc->sc_ic; 1956 uint8_t data; 1957 usb_error_t error; 1958 1959 urtw_read8_m(sc, URTW_MSR, &data); 1960 data &= ~URTW_MSR_LINK_MASK; 1961 1962 if (sc->sc_state == IEEE80211_S_RUN) { 1963 switch (ic->ic_opmode) { 1964 case IEEE80211_M_STA: 1965 case IEEE80211_M_MONITOR: 1966 data |= URTW_MSR_LINK_STA; 1967 if (sc->sc_flags & URTW_RTL8187B) 1968 data |= URTW_MSR_LINK_ENEDCA; 1969 break; 1970 case IEEE80211_M_IBSS: 1971 data |= URTW_MSR_LINK_ADHOC; 1972 break; 1973 case IEEE80211_M_HOSTAP: 1974 data |= URTW_MSR_LINK_HOSTAP; 1975 break; 1976 default: 1977 DPRINTF(sc, URTW_DEBUG_STATE, 1978 "unsupported operation mode 0x%x\n", 1979 ic->ic_opmode); 1980 error = USB_ERR_INVAL; 1981 goto fail; 1982 } 1983 } else 1984 data |= URTW_MSR_LINK_NONE; 1985 1986 urtw_write8_m(sc, URTW_MSR, data); 1987 fail: 1988 return (error); 1989 } 1990 1991 static usb_error_t 1992 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1993 { 1994 struct usb_device_request req; 1995 usb_error_t error; 1996 1997 URTW_ASSERT_LOCKED(sc); 1998 1999 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2000 req.bRequest = URTW_8187_GETREGS_REQ; 2001 USETW(req.wValue, (val & 0xff) | 0xff00); 2002 USETW(req.wIndex, (val >> 8) & 0x3); 2003 USETW(req.wLength, sizeof(uint8_t)); 2004 2005 error = urtw_do_request(sc, &req, data); 2006 return (error); 2007 } 2008 2009 static usb_error_t 2010 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2011 { 2012 struct usb_device_request req; 2013 usb_error_t error; 2014 2015 URTW_ASSERT_LOCKED(sc); 2016 2017 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2018 req.bRequest = URTW_8187_GETREGS_REQ; 2019 USETW(req.wValue, (val & 0xff) | 0xff00); 2020 USETW(req.wIndex, (val >> 8) & 0x3); 2021 USETW(req.wLength, sizeof(uint16_t)); 2022 2023 error = urtw_do_request(sc, &req, data); 2024 return (error); 2025 } 2026 2027 static usb_error_t 2028 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2029 { 2030 struct usb_device_request req; 2031 usb_error_t error; 2032 2033 URTW_ASSERT_LOCKED(sc); 2034 2035 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2036 req.bRequest = URTW_8187_GETREGS_REQ; 2037 USETW(req.wValue, (val & 0xff) | 0xff00); 2038 USETW(req.wIndex, (val >> 8) & 0x3); 2039 USETW(req.wLength, sizeof(uint32_t)); 2040 2041 error = urtw_do_request(sc, &req, data); 2042 return (error); 2043 } 2044 2045 static usb_error_t 2046 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2047 { 2048 struct usb_device_request req; 2049 2050 URTW_ASSERT_LOCKED(sc); 2051 2052 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2053 req.bRequest = URTW_8187_SETREGS_REQ; 2054 USETW(req.wValue, (val & 0xff) | 0xff00); 2055 USETW(req.wIndex, (val >> 8) & 0x3); 2056 USETW(req.wLength, sizeof(uint8_t)); 2057 2058 return (urtw_do_request(sc, &req, &data)); 2059 } 2060 2061 static usb_error_t 2062 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2063 { 2064 struct usb_device_request req; 2065 2066 URTW_ASSERT_LOCKED(sc); 2067 2068 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2069 req.bRequest = URTW_8187_SETREGS_REQ; 2070 USETW(req.wValue, (val & 0xff) | 0xff00); 2071 USETW(req.wIndex, (val >> 8) & 0x3); 2072 USETW(req.wLength, sizeof(uint16_t)); 2073 2074 return (urtw_do_request(sc, &req, &data)); 2075 } 2076 2077 static usb_error_t 2078 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2079 { 2080 struct usb_device_request req; 2081 2082 URTW_ASSERT_LOCKED(sc); 2083 2084 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2085 req.bRequest = URTW_8187_SETREGS_REQ; 2086 USETW(req.wValue, (val & 0xff) | 0xff00); 2087 USETW(req.wIndex, (val >> 8) & 0x3); 2088 USETW(req.wLength, sizeof(uint32_t)); 2089 2090 return (urtw_do_request(sc, &req, &data)); 2091 } 2092 2093 static usb_error_t 2094 urtw_get_macaddr(struct urtw_softc *sc) 2095 { 2096 struct ieee80211com *ic = &sc->sc_ic; 2097 uint32_t data; 2098 usb_error_t error; 2099 2100 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2101 if (error != 0) 2102 goto fail; 2103 ic->ic_macaddr[0] = data & 0xff; 2104 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2105 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2106 if (error != 0) 2107 goto fail; 2108 ic->ic_macaddr[2] = data & 0xff; 2109 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2110 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2111 if (error != 0) 2112 goto fail; 2113 ic->ic_macaddr[4] = data & 0xff; 2114 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2115 fail: 2116 return (error); 2117 } 2118 2119 static usb_error_t 2120 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2121 { 2122 #define URTW_READCMD_LEN 3 2123 int addrlen, i; 2124 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2125 usb_error_t error; 2126 2127 /* NB: make sure the buffer is initialized */ 2128 *data = 0; 2129 2130 /* enable EPROM programming */ 2131 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2132 DELAY(URTW_EPROM_DELAY); 2133 2134 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2135 if (error != 0) 2136 goto fail; 2137 error = urtw_eprom_ck(sc); 2138 if (error != 0) 2139 goto fail; 2140 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2141 if (error != 0) 2142 goto fail; 2143 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2144 addrlen = 8; 2145 addrstr[0] = addr & (1 << 7); 2146 addrstr[1] = addr & (1 << 6); 2147 addrstr[2] = addr & (1 << 5); 2148 addrstr[3] = addr & (1 << 4); 2149 addrstr[4] = addr & (1 << 3); 2150 addrstr[5] = addr & (1 << 2); 2151 addrstr[6] = addr & (1 << 1); 2152 addrstr[7] = addr & (1 << 0); 2153 } else { 2154 addrlen=6; 2155 addrstr[0] = addr & (1 << 5); 2156 addrstr[1] = addr & (1 << 4); 2157 addrstr[2] = addr & (1 << 3); 2158 addrstr[3] = addr & (1 << 2); 2159 addrstr[4] = addr & (1 << 1); 2160 addrstr[5] = addr & (1 << 0); 2161 } 2162 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2163 if (error != 0) 2164 goto fail; 2165 2166 error = urtw_eprom_writebit(sc, 0); 2167 if (error != 0) 2168 goto fail; 2169 2170 for (i = 0; i < 16; i++) { 2171 error = urtw_eprom_ck(sc); 2172 if (error != 0) 2173 goto fail; 2174 error = urtw_eprom_readbit(sc, &data16); 2175 if (error != 0) 2176 goto fail; 2177 2178 (*data) |= (data16 << (15 - i)); 2179 } 2180 2181 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2182 if (error != 0) 2183 goto fail; 2184 error = urtw_eprom_ck(sc); 2185 if (error != 0) 2186 goto fail; 2187 2188 /* now disable EPROM programming */ 2189 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2190 fail: 2191 return (error); 2192 #undef URTW_READCMD_LEN 2193 } 2194 2195 static usb_error_t 2196 urtw_eprom_cs(struct urtw_softc *sc, int able) 2197 { 2198 uint8_t data; 2199 usb_error_t error; 2200 2201 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2202 if (able == URTW_EPROM_ENABLE) 2203 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2204 else 2205 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2206 DELAY(URTW_EPROM_DELAY); 2207 fail: 2208 return (error); 2209 } 2210 2211 static usb_error_t 2212 urtw_eprom_ck(struct urtw_softc *sc) 2213 { 2214 uint8_t data; 2215 usb_error_t error; 2216 2217 /* masking */ 2218 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2219 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2220 DELAY(URTW_EPROM_DELAY); 2221 /* unmasking */ 2222 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2223 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2224 DELAY(URTW_EPROM_DELAY); 2225 fail: 2226 return (error); 2227 } 2228 2229 static usb_error_t 2230 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2231 { 2232 uint8_t data8; 2233 usb_error_t error; 2234 2235 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2236 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2237 DELAY(URTW_EPROM_DELAY); 2238 2239 fail: 2240 return (error); 2241 } 2242 2243 static usb_error_t 2244 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2245 { 2246 uint8_t data; 2247 usb_error_t error; 2248 2249 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2250 if (bit != 0) 2251 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2252 else 2253 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2254 DELAY(URTW_EPROM_DELAY); 2255 fail: 2256 return (error); 2257 } 2258 2259 static usb_error_t 2260 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2261 { 2262 int i = 0; 2263 usb_error_t error = 0; 2264 2265 for (i = 0; i < buflen; i++) { 2266 error = urtw_eprom_writebit(sc, buf[i]); 2267 if (error != 0) 2268 goto fail; 2269 error = urtw_eprom_ck(sc); 2270 if (error != 0) 2271 goto fail; 2272 } 2273 fail: 2274 return (error); 2275 } 2276 2277 2278 static usb_error_t 2279 urtw_get_txpwr(struct urtw_softc *sc) 2280 { 2281 int i, j; 2282 uint32_t data; 2283 usb_error_t error; 2284 2285 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2286 if (error != 0) 2287 goto fail; 2288 sc->sc_txpwr_cck_base = data & 0xf; 2289 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2290 2291 for (i = 1, j = 0; i < 6; i += 2, j++) { 2292 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2293 if (error != 0) 2294 goto fail; 2295 sc->sc_txpwr_cck[i] = data & 0xf; 2296 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2297 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2298 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2299 } 2300 for (i = 1, j = 0; i < 4; i += 2, j++) { 2301 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2302 if (error != 0) 2303 goto fail; 2304 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2305 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2306 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2307 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2308 } 2309 if (sc->sc_flags & URTW_RTL8187B) { 2310 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2311 if (error != 0) 2312 goto fail; 2313 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2314 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2315 error = urtw_eprom_read32(sc, 0x0a, &data); 2316 if (error != 0) 2317 goto fail; 2318 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2319 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2320 error = urtw_eprom_read32(sc, 0x1c, &data); 2321 if (error != 0) 2322 goto fail; 2323 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2324 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2325 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2326 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2327 } else { 2328 for (i = 1, j = 0; i < 4; i += 2, j++) { 2329 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2330 &data); 2331 if (error != 0) 2332 goto fail; 2333 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2334 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2335 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2336 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2337 } 2338 } 2339 fail: 2340 return (error); 2341 } 2342 2343 2344 static usb_error_t 2345 urtw_get_rfchip(struct urtw_softc *sc) 2346 { 2347 int ret; 2348 uint8_t data8; 2349 uint32_t data; 2350 usb_error_t error; 2351 2352 if (sc->sc_flags & URTW_RTL8187B) { 2353 urtw_read8_m(sc, 0xe1, &data8); 2354 switch (data8) { 2355 case 0: 2356 sc->sc_flags |= URTW_RTL8187B_REV_B; 2357 break; 2358 case 1: 2359 sc->sc_flags |= URTW_RTL8187B_REV_D; 2360 break; 2361 case 2: 2362 sc->sc_flags |= URTW_RTL8187B_REV_E; 2363 break; 2364 default: 2365 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2366 sc->sc_flags |= URTW_RTL8187B_REV_B; 2367 break; 2368 } 2369 } else { 2370 urtw_read32_m(sc, URTW_TX_CONF, &data); 2371 switch (data & URTW_TX_HWMASK) { 2372 case URTW_TX_R8187vD_B: 2373 sc->sc_flags |= URTW_RTL8187B; 2374 break; 2375 case URTW_TX_R8187vD: 2376 break; 2377 default: 2378 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2379 data & URTW_TX_HWMASK); 2380 break; 2381 } 2382 } 2383 2384 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2385 if (error != 0) 2386 goto fail; 2387 switch (data & 0xff) { 2388 case URTW_EPROM_RFCHIPID_RTL8225U: 2389 error = urtw_8225_isv2(sc, &ret); 2390 if (error != 0) 2391 goto fail; 2392 if (ret == 0) { 2393 sc->sc_rf_init = urtw_8225_rf_init; 2394 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2395 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2396 sc->sc_rf_stop = urtw_8225_rf_stop; 2397 } else { 2398 sc->sc_rf_init = urtw_8225v2_rf_init; 2399 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2400 sc->sc_rf_stop = urtw_8225_rf_stop; 2401 } 2402 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2403 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2404 break; 2405 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2406 sc->sc_rf_init = urtw_8225v2b_rf_init; 2407 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2408 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2409 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2410 sc->sc_rf_stop = urtw_8225_rf_stop; 2411 break; 2412 default: 2413 DPRINTF(sc, URTW_DEBUG_STATE, 2414 "unsupported RF chip %d\n", data & 0xff); 2415 error = USB_ERR_INVAL; 2416 goto fail; 2417 } 2418 2419 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2420 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2421 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2422 "rtl8225z2", 2423 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2424 (data8 == 1) ? "d" : "e") : "none"); 2425 2426 fail: 2427 return (error); 2428 } 2429 2430 2431 static usb_error_t 2432 urtw_led_init(struct urtw_softc *sc) 2433 { 2434 uint32_t rev; 2435 usb_error_t error; 2436 2437 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2438 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2439 if (error != 0) 2440 goto fail; 2441 2442 switch (rev & URTW_EPROM_CID_MASK) { 2443 case URTW_EPROM_CID_ALPHA0: 2444 sc->sc_strategy = URTW_SW_LED_MODE1; 2445 break; 2446 case URTW_EPROM_CID_SERCOMM_PS: 2447 sc->sc_strategy = URTW_SW_LED_MODE3; 2448 break; 2449 case URTW_EPROM_CID_HW_LED: 2450 sc->sc_strategy = URTW_HW_LED; 2451 break; 2452 case URTW_EPROM_CID_RSVD0: 2453 case URTW_EPROM_CID_RSVD1: 2454 default: 2455 sc->sc_strategy = URTW_SW_LED_MODE0; 2456 break; 2457 } 2458 2459 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2460 2461 fail: 2462 return (error); 2463 } 2464 2465 2466 static usb_error_t 2467 urtw_8225_rf_init(struct urtw_softc *sc) 2468 { 2469 unsigned int i; 2470 uint16_t data; 2471 usb_error_t error; 2472 2473 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2474 if (error) 2475 goto fail; 2476 2477 error = urtw_8225_usb_init(sc); 2478 if (error) 2479 goto fail; 2480 2481 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2482 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2483 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2484 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2485 2486 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2487 if (error) 2488 goto fail; 2489 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2490 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2491 if (error) 2492 goto fail; 2493 2494 error = urtw_8185_rf_pins_enable(sc); 2495 if (error) 2496 goto fail; 2497 usb_pause_mtx(&sc->sc_mtx, 1000); 2498 2499 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2500 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2501 urtw_8225_rf_part1[i].val); 2502 usb_pause_mtx(&sc->sc_mtx, 1); 2503 } 2504 usb_pause_mtx(&sc->sc_mtx, 100); 2505 urtw_8225_write(sc, 2506 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2507 usb_pause_mtx(&sc->sc_mtx, 200); 2508 urtw_8225_write(sc, 2509 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2510 usb_pause_mtx(&sc->sc_mtx, 200); 2511 urtw_8225_write(sc, 2512 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2513 2514 for (i = 0; i < 95; i++) { 2515 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2516 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2517 } 2518 2519 urtw_8225_write(sc, 2520 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2521 urtw_8225_write(sc, 2522 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2523 2524 for (i = 0; i < 128; i++) { 2525 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2526 usb_pause_mtx(&sc->sc_mtx, 1); 2527 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2528 usb_pause_mtx(&sc->sc_mtx, 1); 2529 } 2530 2531 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2532 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2533 urtw_8225_rf_part2[i].val); 2534 usb_pause_mtx(&sc->sc_mtx, 1); 2535 } 2536 2537 error = urtw_8225_setgain(sc, 4); 2538 if (error) 2539 goto fail; 2540 2541 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2542 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2543 urtw_8225_rf_part3[i].val); 2544 usb_pause_mtx(&sc->sc_mtx, 1); 2545 } 2546 2547 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2548 2549 error = urtw_8225_set_txpwrlvl(sc, 1); 2550 if (error) 2551 goto fail; 2552 2553 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2554 usb_pause_mtx(&sc->sc_mtx, 1); 2555 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2556 usb_pause_mtx(&sc->sc_mtx, 1); 2557 2558 /* TX ant A, 0x0 for B */ 2559 error = urtw_8185_tx_antenna(sc, 0x3); 2560 if (error) 2561 goto fail; 2562 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2563 2564 error = urtw_8225_rf_set_chan(sc, 1); 2565 fail: 2566 return (error); 2567 } 2568 2569 static usb_error_t 2570 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2571 { 2572 usb_error_t error = 0; 2573 2574 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2575 fail: 2576 return (error); 2577 } 2578 2579 static usb_error_t 2580 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2581 { 2582 usb_error_t error; 2583 2584 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2585 usb_pause_mtx(&sc->sc_mtx, 1); 2586 fail: 2587 return (error); 2588 } 2589 2590 static usb_error_t 2591 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2592 { 2593 2594 data = data & 0xff; 2595 return urtw_8187_write_phy(sc, addr, data); 2596 } 2597 2598 static usb_error_t 2599 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2600 { 2601 2602 data = data & 0xff; 2603 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2604 } 2605 2606 static usb_error_t 2607 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2608 { 2609 uint32_t phyw; 2610 usb_error_t error; 2611 2612 phyw = ((data << 8) | (addr | 0x80)); 2613 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2614 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2615 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2616 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2617 usb_pause_mtx(&sc->sc_mtx, 1); 2618 fail: 2619 return (error); 2620 } 2621 2622 static usb_error_t 2623 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2624 { 2625 usb_error_t error; 2626 2627 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2628 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2629 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2630 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2631 fail: 2632 return (error); 2633 } 2634 2635 static usb_error_t 2636 urtw_8225_usb_init(struct urtw_softc *sc) 2637 { 2638 uint8_t data; 2639 usb_error_t error; 2640 2641 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2642 urtw_write8_m(sc, URTW_GPIO, 0); 2643 error = urtw_read8e(sc, 0x53, &data); 2644 if (error) 2645 goto fail; 2646 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2647 if (error) 2648 goto fail; 2649 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2650 urtw_write8_m(sc, URTW_GPIO, 0x20); 2651 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2652 2653 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2654 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2655 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2656 2657 usb_pause_mtx(&sc->sc_mtx, 500); 2658 fail: 2659 return (error); 2660 } 2661 2662 static usb_error_t 2663 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2664 { 2665 uint16_t d80, d82, d84; 2666 usb_error_t error; 2667 2668 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2669 d80 &= URTW_RF_PINS_MAGIC1; 2670 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2671 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2672 d84 &= URTW_RF_PINS_MAGIC2; 2673 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2674 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2675 DELAY(10); 2676 2677 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2678 DELAY(2); 2679 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2680 DELAY(10); 2681 2682 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2683 if (error != 0) 2684 goto fail; 2685 2686 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2687 DELAY(10); 2688 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2689 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2690 usb_pause_mtx(&sc->sc_mtx, 2); 2691 fail: 2692 return (error); 2693 } 2694 2695 static usb_error_t 2696 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2697 uint16_t *data) 2698 { 2699 uint8_t buf[2]; 2700 uint16_t data16; 2701 struct usb_device_request req; 2702 usb_error_t error = 0; 2703 2704 data16 = *data; 2705 2706 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2707 req.bRequest = URTW_8187_SETREGS_REQ; 2708 USETW(req.wValue, addr); 2709 USETW(req.wIndex, index); 2710 USETW(req.wLength, sizeof(uint16_t)); 2711 buf[0] = (data16 & 0x00ff); 2712 buf[1] = (data16 & 0xff00) >> 8; 2713 2714 error = urtw_do_request(sc, &req, buf); 2715 2716 return (error); 2717 } 2718 2719 static usb_error_t 2720 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2721 { 2722 usb_error_t error; 2723 2724 error = urtw_8225_set_txpwrlvl(sc, chan); 2725 if (error) 2726 goto fail; 2727 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2728 usb_pause_mtx(&sc->sc_mtx, 10); 2729 fail: 2730 return (error); 2731 } 2732 2733 static usb_error_t 2734 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2735 { 2736 usb_error_t error; 2737 2738 if (sens < 0 || sens > 6) 2739 return -1; 2740 2741 if (sens > 4) 2742 urtw_8225_write(sc, 2743 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2744 else 2745 urtw_8225_write(sc, 2746 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2747 2748 sens = 6 - sens; 2749 error = urtw_8225_setgain(sc, sens); 2750 if (error) 2751 goto fail; 2752 2753 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2754 2755 fail: 2756 return (error); 2757 } 2758 2759 static usb_error_t 2760 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2761 { 2762 int i, idx, set; 2763 uint8_t *cck_pwltable; 2764 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2765 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2766 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2767 usb_error_t error; 2768 2769 cck_pwrlvl_max = 11; 2770 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2771 ofdm_pwrlvl_min = 10; 2772 2773 /* CCK power setting */ 2774 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2775 idx = cck_pwrlvl % 6; 2776 set = cck_pwrlvl / 6; 2777 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2778 urtw_8225_txpwr_cck; 2779 2780 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2781 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2782 for (i = 0; i < 8; i++) { 2783 urtw_8187_write_phy_cck(sc, 0x44 + i, 2784 cck_pwltable[idx * 8 + i]); 2785 } 2786 usb_pause_mtx(&sc->sc_mtx, 1); 2787 2788 /* OFDM power setting */ 2789 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2790 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2791 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2792 2793 idx = ofdm_pwrlvl % 6; 2794 set = ofdm_pwrlvl / 6; 2795 2796 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2797 if (error) 2798 goto fail; 2799 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2800 urtw_8187_write_phy_ofdm(sc, 6, 0); 2801 urtw_8187_write_phy_ofdm(sc, 8, 0); 2802 2803 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2804 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2805 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2806 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2807 usb_pause_mtx(&sc->sc_mtx, 1); 2808 fail: 2809 return (error); 2810 } 2811 2812 2813 static usb_error_t 2814 urtw_8225_rf_stop(struct urtw_softc *sc) 2815 { 2816 uint8_t data; 2817 usb_error_t error; 2818 2819 urtw_8225_write(sc, 0x4, 0x1f); 2820 2821 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2822 if (error) 2823 goto fail; 2824 2825 urtw_read8_m(sc, URTW_CONFIG3, &data); 2826 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2827 if (sc->sc_flags & URTW_RTL8187B) { 2828 urtw_write32_m(sc, URTW_ANAPARAM2, 2829 URTW_8187B_8225_ANAPARAM2_OFF); 2830 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2831 urtw_write32_m(sc, URTW_ANAPARAM3, 2832 URTW_8187B_8225_ANAPARAM3_OFF); 2833 } else { 2834 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2835 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2836 } 2837 2838 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2839 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2840 if (error) 2841 goto fail; 2842 2843 fail: 2844 return (error); 2845 } 2846 2847 static usb_error_t 2848 urtw_8225v2_rf_init(struct urtw_softc *sc) 2849 { 2850 unsigned int i; 2851 uint16_t data; 2852 uint32_t data32; 2853 usb_error_t error; 2854 2855 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2856 if (error) 2857 goto fail; 2858 2859 error = urtw_8225_usb_init(sc); 2860 if (error) 2861 goto fail; 2862 2863 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2864 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2865 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2866 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2867 2868 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2869 if (error) 2870 goto fail; 2871 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2872 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2873 if (error) 2874 goto fail; 2875 2876 error = urtw_8185_rf_pins_enable(sc); 2877 if (error) 2878 goto fail; 2879 2880 usb_pause_mtx(&sc->sc_mtx, 500); 2881 2882 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2883 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2884 urtw_8225v2_rf_part1[i].val); 2885 } 2886 usb_pause_mtx(&sc->sc_mtx, 50); 2887 2888 urtw_8225_write(sc, 2889 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2890 2891 for (i = 0; i < 95; i++) { 2892 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2893 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2894 urtw_8225v2_rxgain[i]); 2895 } 2896 2897 urtw_8225_write(sc, 2898 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2899 urtw_8225_write(sc, 2900 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2901 urtw_8225_write(sc, 2902 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2903 urtw_8225_write(sc, 2904 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2905 usb_pause_mtx(&sc->sc_mtx, 100); 2906 urtw_8225_write(sc, 2907 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2908 usb_pause_mtx(&sc->sc_mtx, 100); 2909 2910 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2911 if (error != 0) 2912 goto fail; 2913 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2914 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2915 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2916 urtw_8225_write(sc, 2917 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2918 usb_pause_mtx(&sc->sc_mtx, 100); 2919 urtw_8225_write(sc, 2920 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2921 usb_pause_mtx(&sc->sc_mtx, 50); 2922 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2923 if (error != 0) 2924 goto fail; 2925 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2926 device_printf(sc->sc_dev, "RF calibration failed\n"); 2927 } 2928 usb_pause_mtx(&sc->sc_mtx, 100); 2929 2930 urtw_8225_write(sc, 2931 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2932 for (i = 0; i < 128; i++) { 2933 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2934 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2935 } 2936 2937 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2938 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2939 urtw_8225v2_rf_part2[i].val); 2940 } 2941 2942 error = urtw_8225v2_setgain(sc, 4); 2943 if (error) 2944 goto fail; 2945 2946 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2947 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2948 urtw_8225v2_rf_part3[i].val); 2949 } 2950 2951 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2952 2953 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2954 if (error) 2955 goto fail; 2956 2957 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2958 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2959 2960 /* TX ant A, 0x0 for B */ 2961 error = urtw_8185_tx_antenna(sc, 0x3); 2962 if (error) 2963 goto fail; 2964 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2965 2966 error = urtw_8225_rf_set_chan(sc, 1); 2967 fail: 2968 return (error); 2969 } 2970 2971 static usb_error_t 2972 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2973 { 2974 usb_error_t error; 2975 2976 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2977 if (error) 2978 goto fail; 2979 2980 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2981 usb_pause_mtx(&sc->sc_mtx, 10); 2982 fail: 2983 return (error); 2984 } 2985 2986 static usb_error_t 2987 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2988 { 2989 int i; 2990 int16_t bit; 2991 uint8_t rlen = 12, wlen = 6; 2992 uint16_t o1, o2, o3, tmp; 2993 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2994 uint32_t mask = 0x80000000, value = 0; 2995 usb_error_t error; 2996 2997 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 2998 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 2999 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 3000 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 3001 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3002 o1 &= ~URTW_RF_PINS_MAGIC4; 3003 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3004 DELAY(5); 3005 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3006 DELAY(5); 3007 3008 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3009 bit = ((d2w & mask) != 0) ? 1 : 0; 3010 3011 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3012 DELAY(2); 3013 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3014 URTW_BB_HOST_BANG_CLK); 3015 DELAY(2); 3016 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3017 URTW_BB_HOST_BANG_CLK); 3018 DELAY(2); 3019 mask = mask >> 1; 3020 if (i == 2) 3021 break; 3022 bit = ((d2w & mask) != 0) ? 1 : 0; 3023 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3024 URTW_BB_HOST_BANG_CLK); 3025 DELAY(2); 3026 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3027 URTW_BB_HOST_BANG_CLK); 3028 DELAY(2); 3029 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3030 DELAY(1); 3031 } 3032 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3033 URTW_BB_HOST_BANG_CLK); 3034 DELAY(2); 3035 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3036 DELAY(2); 3037 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3038 DELAY(2); 3039 3040 mask = 0x800; 3041 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3042 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3043 o1 | URTW_BB_HOST_BANG_RW); 3044 DELAY(2); 3045 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3046 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3047 DELAY(2); 3048 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3049 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3050 DELAY(2); 3051 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3052 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3053 DELAY(2); 3054 3055 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3056 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3057 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3058 o1 | URTW_BB_HOST_BANG_RW); 3059 DELAY(2); 3060 } 3061 3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3063 URTW_BB_HOST_BANG_RW); 3064 DELAY(2); 3065 3066 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3067 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3068 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3069 3070 if (data != NULL) 3071 *data = value; 3072 fail: 3073 return (error); 3074 } 3075 3076 3077 static usb_error_t 3078 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3079 { 3080 int i; 3081 uint8_t *cck_pwrtable; 3082 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3083 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3084 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3085 usb_error_t error; 3086 3087 /* CCK power setting */ 3088 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3089 cck_pwrlvl += sc->sc_txpwr_cck_base; 3090 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3091 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3092 urtw_8225v2_txpwr_cck; 3093 3094 for (i = 0; i < 8; i++) 3095 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3096 3097 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3098 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3099 usb_pause_mtx(&sc->sc_mtx, 1); 3100 3101 /* OFDM power setting */ 3102 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3103 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3104 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3105 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3106 3107 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3108 if (error) 3109 goto fail; 3110 3111 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3112 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3113 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3114 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3115 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3116 3117 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3118 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3119 usb_pause_mtx(&sc->sc_mtx, 1); 3120 fail: 3121 return (error); 3122 } 3123 3124 static usb_error_t 3125 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3126 { 3127 uint8_t *gainp; 3128 usb_error_t error; 3129 3130 /* XXX for A? */ 3131 gainp = urtw_8225v2_gain_bg; 3132 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3133 usb_pause_mtx(&sc->sc_mtx, 1); 3134 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3135 usb_pause_mtx(&sc->sc_mtx, 1); 3136 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3137 usb_pause_mtx(&sc->sc_mtx, 1); 3138 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3139 usb_pause_mtx(&sc->sc_mtx, 1); 3140 fail: 3141 return (error); 3142 } 3143 3144 static usb_error_t 3145 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3146 { 3147 uint32_t data; 3148 usb_error_t error; 3149 3150 *ret = 1; 3151 3152 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3153 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3154 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3155 usb_pause_mtx(&sc->sc_mtx, 500); 3156 3157 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3158 URTW_8225_ADDR_0_DATA_MAGIC1); 3159 3160 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3161 if (error != 0) 3162 goto fail; 3163 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3164 *ret = 0; 3165 else { 3166 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3167 if (error != 0) 3168 goto fail; 3169 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3170 *ret = 0; 3171 } 3172 3173 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3174 URTW_8225_ADDR_0_DATA_MAGIC2); 3175 fail: 3176 return (error); 3177 } 3178 3179 static usb_error_t 3180 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3181 { 3182 struct ieee80211com *ic = &sc->sc_ic; 3183 unsigned int i; 3184 uint8_t data8; 3185 usb_error_t error; 3186 3187 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3188 if (error) 3189 goto fail; 3190 3191 /* 3192 * initialize extra registers on 8187 3193 */ 3194 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3195 3196 /* retry limit */ 3197 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3198 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3199 urtw_write8_m(sc, URTW_CW_CONF, data8); 3200 3201 /* TX AGC */ 3202 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3203 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3204 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3205 3206 /* Auto Rate Fallback Control */ 3207 #define URTW_ARFR 0x1e0 3208 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3209 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3210 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3211 data8 | URTW_RATE_FALLBACK_ENABLE); 3212 3213 urtw_read8_m(sc, URTW_MSR, &data8); 3214 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3215 urtw_read8_m(sc, URTW_MSR, &data8); 3216 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3217 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3218 3219 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3220 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3221 #define URTW_FEMR_FOR_8187B 0x1d4 3222 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3223 3224 /* led type */ 3225 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3226 data8 = (data8 & 0x3f) | 0x80; 3227 urtw_write8_m(sc, URTW_CONFIG1, data8); 3228 3229 /* applying MAC address again. */ 3230 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3231 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3232 3233 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3234 if (error) 3235 goto fail; 3236 3237 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3238 3239 /* 3240 * MAC configuration 3241 */ 3242 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3243 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3244 urtw_8225v2b_rf_part1[i].val); 3245 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3246 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3247 urtw_write32_m(sc, 0x1f0, 0); 3248 urtw_write32_m(sc, 0x1f4, 0); 3249 urtw_write8_m(sc, 0x1f8, 0); 3250 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3251 3252 #define URTW_RFSW_CTRL 0x272 3253 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3254 3255 /* 3256 * initialize PHY 3257 */ 3258 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3259 if (error) 3260 goto fail; 3261 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3262 urtw_write8_m(sc, URTW_CONFIG3, 3263 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3264 3265 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3266 if (error) 3267 goto fail; 3268 3269 /* setup RFE initial timing */ 3270 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3271 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3272 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3273 usb_pause_mtx(&sc->sc_mtx, 1100); 3274 3275 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3276 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3277 urtw_8225v2b_rf_part0[i].val); 3278 usb_pause_mtx(&sc->sc_mtx, 1); 3279 } 3280 urtw_8225_write(sc, 0x00, 0x01b7); 3281 3282 for (i = 0; i < 95; i++) { 3283 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3284 usb_pause_mtx(&sc->sc_mtx, 1); 3285 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3286 urtw_8225v2b_rxgain[i]); 3287 usb_pause_mtx(&sc->sc_mtx, 1); 3288 } 3289 3290 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3291 usb_pause_mtx(&sc->sc_mtx, 1); 3292 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3293 usb_pause_mtx(&sc->sc_mtx, 1); 3294 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3295 usb_pause_mtx(&sc->sc_mtx, 1); 3296 usb_pause_mtx(&sc->sc_mtx, 3000); 3297 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3298 usb_pause_mtx(&sc->sc_mtx, 2000); 3299 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3300 usb_pause_mtx(&sc->sc_mtx, 1); 3301 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3302 usb_pause_mtx(&sc->sc_mtx, 1); 3303 3304 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3305 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3306 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3307 3308 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3309 for (i = 0; i < 128; i++) { 3310 uint32_t addr, data; 3311 3312 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3313 addr = ((i + 0x80) << 8) | 0x0000008e; 3314 3315 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3316 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3317 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3318 } 3319 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3320 3321 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3322 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3323 3324 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3325 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3326 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3327 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3328 3329 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3330 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3331 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3332 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3333 3334 fail: 3335 return (error); 3336 } 3337 3338 static usb_error_t 3339 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3340 { 3341 usb_error_t error; 3342 3343 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3344 if (error) 3345 goto fail; 3346 3347 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3348 usb_pause_mtx(&sc->sc_mtx, 10); 3349 fail: 3350 return (error); 3351 } 3352 3353 static usb_error_t 3354 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3355 { 3356 int i; 3357 uint8_t *cck_pwrtable; 3358 uint8_t cck_pwrlvl_max = 15; 3359 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3360 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3361 usb_error_t error; 3362 3363 /* CCK power setting */ 3364 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3365 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3366 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3367 cck_pwrlvl += sc->sc_txpwr_cck_base; 3368 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3369 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3370 urtw_8225v2b_txpwr_cck; 3371 3372 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3373 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3374 ((cck_pwrlvl <= 11) ? 8 : 16); 3375 else 3376 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3377 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3378 3379 for (i = 0; i < 8; i++) 3380 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3381 3382 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3383 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3384 usb_pause_mtx(&sc->sc_mtx, 1); 3385 3386 /* OFDM power setting */ 3387 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3388 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3389 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3390 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3391 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3392 3393 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3394 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3395 3396 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3397 if (ofdm_pwrlvl <= 11) { 3398 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3399 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3400 } else { 3401 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3402 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3403 } 3404 } else { 3405 if (ofdm_pwrlvl <= 11) { 3406 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3407 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3408 } else if (ofdm_pwrlvl <= 17) { 3409 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3410 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3411 } else { 3412 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3413 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3414 } 3415 } 3416 usb_pause_mtx(&sc->sc_mtx, 1); 3417 fail: 3418 return (error); 3419 } 3420 3421 static usb_error_t 3422 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3423 { 3424 struct usb_device_request req; 3425 usb_error_t error; 3426 3427 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3428 req.bRequest = URTW_8187_GETREGS_REQ; 3429 USETW(req.wValue, val | 0xfe00); 3430 USETW(req.wIndex, 0); 3431 USETW(req.wLength, sizeof(uint8_t)); 3432 3433 error = urtw_do_request(sc, &req, data); 3434 return (error); 3435 } 3436 3437 static usb_error_t 3438 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3439 { 3440 struct usb_device_request req; 3441 3442 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3443 req.bRequest = URTW_8187_SETREGS_REQ; 3444 USETW(req.wValue, val | 0xfe00); 3445 USETW(req.wIndex, 0); 3446 USETW(req.wLength, sizeof(uint8_t)); 3447 3448 return (urtw_do_request(sc, &req, &data)); 3449 } 3450 3451 static usb_error_t 3452 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3453 { 3454 uint8_t data; 3455 usb_error_t error; 3456 3457 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3458 if (error) 3459 goto fail; 3460 3461 urtw_read8_m(sc, URTW_CONFIG3, &data); 3462 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3463 urtw_write32_m(sc, URTW_ANAPARAM, val); 3464 urtw_read8_m(sc, URTW_CONFIG3, &data); 3465 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3466 3467 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3468 if (error) 3469 goto fail; 3470 fail: 3471 return (error); 3472 } 3473 3474 static usb_error_t 3475 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3476 { 3477 uint8_t data; 3478 usb_error_t error; 3479 3480 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3481 if (error) 3482 goto fail; 3483 3484 urtw_read8_m(sc, URTW_CONFIG3, &data); 3485 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3486 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3487 urtw_read8_m(sc, URTW_CONFIG3, &data); 3488 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3489 3490 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3491 if (error) 3492 goto fail; 3493 fail: 3494 return (error); 3495 } 3496 3497 static usb_error_t 3498 urtw_intr_enable(struct urtw_softc *sc) 3499 { 3500 usb_error_t error; 3501 3502 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3503 fail: 3504 return (error); 3505 } 3506 3507 static usb_error_t 3508 urtw_intr_disable(struct urtw_softc *sc) 3509 { 3510 usb_error_t error; 3511 3512 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3513 fail: 3514 return (error); 3515 } 3516 3517 static usb_error_t 3518 urtw_reset(struct urtw_softc *sc) 3519 { 3520 uint8_t data; 3521 usb_error_t error; 3522 3523 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3524 if (error) 3525 goto fail; 3526 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3527 if (error) 3528 goto fail; 3529 3530 error = urtw_intr_disable(sc); 3531 if (error) 3532 goto fail; 3533 usb_pause_mtx(&sc->sc_mtx, 100); 3534 3535 error = urtw_write8e(sc, 0x18, 0x10); 3536 if (error != 0) 3537 goto fail; 3538 error = urtw_write8e(sc, 0x18, 0x11); 3539 if (error != 0) 3540 goto fail; 3541 error = urtw_write8e(sc, 0x18, 0x00); 3542 if (error != 0) 3543 goto fail; 3544 usb_pause_mtx(&sc->sc_mtx, 100); 3545 3546 urtw_read8_m(sc, URTW_CMD, &data); 3547 data = (data & 0x2) | URTW_CMD_RST; 3548 urtw_write8_m(sc, URTW_CMD, data); 3549 usb_pause_mtx(&sc->sc_mtx, 100); 3550 3551 urtw_read8_m(sc, URTW_CMD, &data); 3552 if (data & URTW_CMD_RST) { 3553 device_printf(sc->sc_dev, "reset timeout\n"); 3554 goto fail; 3555 } 3556 3557 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3558 if (error) 3559 goto fail; 3560 usb_pause_mtx(&sc->sc_mtx, 100); 3561 3562 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3563 if (error) 3564 goto fail; 3565 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3566 if (error) 3567 goto fail; 3568 fail: 3569 return (error); 3570 } 3571 3572 static usb_error_t 3573 urtw_led_ctl(struct urtw_softc *sc, int mode) 3574 { 3575 usb_error_t error = 0; 3576 3577 switch (sc->sc_strategy) { 3578 case URTW_SW_LED_MODE0: 3579 error = urtw_led_mode0(sc, mode); 3580 break; 3581 case URTW_SW_LED_MODE1: 3582 error = urtw_led_mode1(sc, mode); 3583 break; 3584 case URTW_SW_LED_MODE2: 3585 error = urtw_led_mode2(sc, mode); 3586 break; 3587 case URTW_SW_LED_MODE3: 3588 error = urtw_led_mode3(sc, mode); 3589 break; 3590 default: 3591 DPRINTF(sc, URTW_DEBUG_STATE, 3592 "unsupported LED mode %d\n", sc->sc_strategy); 3593 error = USB_ERR_INVAL; 3594 break; 3595 } 3596 3597 return (error); 3598 } 3599 3600 static usb_error_t 3601 urtw_led_mode0(struct urtw_softc *sc, int mode) 3602 { 3603 3604 switch (mode) { 3605 case URTW_LED_CTL_POWER_ON: 3606 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3607 break; 3608 case URTW_LED_CTL_TX: 3609 if (sc->sc_gpio_ledinprogress == 1) 3610 return (0); 3611 3612 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3613 sc->sc_gpio_blinktime = 2; 3614 break; 3615 case URTW_LED_CTL_LINK: 3616 sc->sc_gpio_ledstate = URTW_LED_ON; 3617 break; 3618 default: 3619 DPRINTF(sc, URTW_DEBUG_STATE, 3620 "unsupported LED mode 0x%x", mode); 3621 return (USB_ERR_INVAL); 3622 } 3623 3624 switch (sc->sc_gpio_ledstate) { 3625 case URTW_LED_ON: 3626 if (sc->sc_gpio_ledinprogress != 0) 3627 break; 3628 urtw_led_on(sc, URTW_LED_GPIO); 3629 break; 3630 case URTW_LED_BLINK_NORMAL: 3631 if (sc->sc_gpio_ledinprogress != 0) 3632 break; 3633 sc->sc_gpio_ledinprogress = 1; 3634 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3635 URTW_LED_OFF : URTW_LED_ON; 3636 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3637 break; 3638 case URTW_LED_POWER_ON_BLINK: 3639 urtw_led_on(sc, URTW_LED_GPIO); 3640 usb_pause_mtx(&sc->sc_mtx, 100); 3641 urtw_led_off(sc, URTW_LED_GPIO); 3642 break; 3643 default: 3644 DPRINTF(sc, URTW_DEBUG_STATE, 3645 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3646 return (USB_ERR_INVAL); 3647 } 3648 return (0); 3649 } 3650 3651 static usb_error_t 3652 urtw_led_mode1(struct urtw_softc *sc, int mode) 3653 { 3654 return (USB_ERR_INVAL); 3655 } 3656 3657 static usb_error_t 3658 urtw_led_mode2(struct urtw_softc *sc, int mode) 3659 { 3660 return (USB_ERR_INVAL); 3661 } 3662 3663 static usb_error_t 3664 urtw_led_mode3(struct urtw_softc *sc, int mode) 3665 { 3666 return (USB_ERR_INVAL); 3667 } 3668 3669 static usb_error_t 3670 urtw_led_on(struct urtw_softc *sc, int type) 3671 { 3672 usb_error_t error; 3673 3674 if (type == URTW_LED_GPIO) { 3675 switch (sc->sc_gpio_ledpin) { 3676 case URTW_LED_PIN_GPIO0: 3677 urtw_write8_m(sc, URTW_GPIO, 0x01); 3678 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3679 break; 3680 default: 3681 DPRINTF(sc, URTW_DEBUG_STATE, 3682 "unsupported LED PIN type 0x%x", 3683 sc->sc_gpio_ledpin); 3684 error = USB_ERR_INVAL; 3685 goto fail; 3686 } 3687 } else { 3688 DPRINTF(sc, URTW_DEBUG_STATE, 3689 "unsupported LED type 0x%x", type); 3690 error = USB_ERR_INVAL; 3691 goto fail; 3692 } 3693 3694 sc->sc_gpio_ledon = 1; 3695 fail: 3696 return (error); 3697 } 3698 3699 static usb_error_t 3700 urtw_led_off(struct urtw_softc *sc, int type) 3701 { 3702 usb_error_t error; 3703 3704 if (type == URTW_LED_GPIO) { 3705 switch (sc->sc_gpio_ledpin) { 3706 case URTW_LED_PIN_GPIO0: 3707 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3708 urtw_write8_m(sc, 3709 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3710 break; 3711 default: 3712 DPRINTF(sc, URTW_DEBUG_STATE, 3713 "unsupported LED PIN type 0x%x", 3714 sc->sc_gpio_ledpin); 3715 error = USB_ERR_INVAL; 3716 goto fail; 3717 } 3718 } else { 3719 DPRINTF(sc, URTW_DEBUG_STATE, 3720 "unsupported LED type 0x%x", type); 3721 error = USB_ERR_INVAL; 3722 goto fail; 3723 } 3724 3725 sc->sc_gpio_ledon = 0; 3726 3727 fail: 3728 return (error); 3729 } 3730 3731 static void 3732 urtw_led_ch(void *arg) 3733 { 3734 struct urtw_softc *sc = arg; 3735 struct ieee80211com *ic = &sc->sc_ic; 3736 3737 ieee80211_runtask(ic, &sc->sc_led_task); 3738 } 3739 3740 static void 3741 urtw_ledtask(void *arg, int pending) 3742 { 3743 struct urtw_softc *sc = arg; 3744 3745 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3746 DPRINTF(sc, URTW_DEBUG_STATE, 3747 "could not process a LED strategy 0x%x", 3748 sc->sc_strategy); 3749 return; 3750 } 3751 3752 URTW_LOCK(sc); 3753 urtw_led_blink(sc); 3754 URTW_UNLOCK(sc); 3755 } 3756 3757 static usb_error_t 3758 urtw_led_blink(struct urtw_softc *sc) 3759 { 3760 uint8_t ing = 0; 3761 usb_error_t error; 3762 3763 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3764 error = urtw_led_on(sc, URTW_LED_GPIO); 3765 else 3766 error = urtw_led_off(sc, URTW_LED_GPIO); 3767 sc->sc_gpio_blinktime--; 3768 if (sc->sc_gpio_blinktime == 0) 3769 ing = 1; 3770 else { 3771 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3772 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3773 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3774 ing = 1; 3775 } 3776 if (ing == 1) { 3777 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3778 sc->sc_gpio_ledon == 0) 3779 error = urtw_led_on(sc, URTW_LED_GPIO); 3780 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3781 sc->sc_gpio_ledon == 1) 3782 error = urtw_led_off(sc, URTW_LED_GPIO); 3783 3784 sc->sc_gpio_blinktime = 0; 3785 sc->sc_gpio_ledinprogress = 0; 3786 return (0); 3787 } 3788 3789 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3790 URTW_LED_ON : URTW_LED_OFF; 3791 3792 switch (sc->sc_gpio_ledstate) { 3793 case URTW_LED_BLINK_NORMAL: 3794 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3795 break; 3796 default: 3797 DPRINTF(sc, URTW_DEBUG_STATE, 3798 "unknown LED status 0x%x", 3799 sc->sc_gpio_ledstate); 3800 return (USB_ERR_INVAL); 3801 } 3802 return (0); 3803 } 3804 3805 static usb_error_t 3806 urtw_rx_enable(struct urtw_softc *sc) 3807 { 3808 uint8_t data; 3809 usb_error_t error; 3810 3811 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3812 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3813 3814 error = urtw_rx_setconf(sc); 3815 if (error != 0) 3816 goto fail; 3817 3818 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3819 urtw_read8_m(sc, URTW_CMD, &data); 3820 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3821 } 3822 fail: 3823 return (error); 3824 } 3825 3826 static usb_error_t 3827 urtw_tx_enable(struct urtw_softc *sc) 3828 { 3829 uint8_t data8; 3830 uint32_t data; 3831 usb_error_t error; 3832 3833 if (sc->sc_flags & URTW_RTL8187B) { 3834 urtw_read32_m(sc, URTW_TX_CONF, &data); 3835 data &= ~URTW_TX_LOOPBACK_MASK; 3836 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3837 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3838 data &= ~URTW_TX_SWPLCPLEN; 3839 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3840 (7 << 8) | /* short retry limit */ 3841 (7 << 0) | /* long retry limit */ 3842 (7 << 21); /* MAX TX DMA */ 3843 urtw_write32_m(sc, URTW_TX_CONF, data); 3844 3845 urtw_read8_m(sc, URTW_MSR, &data8); 3846 data8 |= URTW_MSR_LINK_ENEDCA; 3847 urtw_write8_m(sc, URTW_MSR, data8); 3848 return (error); 3849 } 3850 3851 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3852 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3853 urtw_write8_m(sc, URTW_CW_CONF, data8); 3854 3855 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3856 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3857 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3858 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3859 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3860 3861 urtw_read32_m(sc, URTW_TX_CONF, &data); 3862 data &= ~URTW_TX_LOOPBACK_MASK; 3863 data |= URTW_TX_LOOPBACK_NONE; 3864 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3865 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3866 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3867 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3868 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3869 data &= ~URTW_TX_SWPLCPLEN; 3870 data |= URTW_TX_NOICV; 3871 urtw_write32_m(sc, URTW_TX_CONF, data); 3872 3873 urtw_read8_m(sc, URTW_CMD, &data8); 3874 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3875 fail: 3876 return (error); 3877 } 3878 3879 static usb_error_t 3880 urtw_rx_setconf(struct urtw_softc *sc) 3881 { 3882 struct ieee80211com *ic = &sc->sc_ic; 3883 uint32_t data; 3884 usb_error_t error; 3885 3886 urtw_read32_m(sc, URTW_RX, &data); 3887 data = data &~ URTW_RX_FILTER_MASK; 3888 if (sc->sc_flags & URTW_RTL8187B) { 3889 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3890 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3891 URTW_RX_FIFO_THRESHOLD_NONE | 3892 URTW_MAX_RX_DMA_2048 | 3893 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3894 } else { 3895 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3896 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3897 3898 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3899 data = data | URTW_RX_FILTER_ICVERR; 3900 data = data | URTW_RX_FILTER_PWR; 3901 } 3902 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3903 data = data | URTW_RX_FILTER_CRCERR; 3904 3905 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3906 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3907 URTW_RX_AUTORESETPHY; 3908 data = data &~ URTW_MAX_RX_DMA_MASK; 3909 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3910 } 3911 3912 /* XXX allmulti should not be checked here... */ 3913 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3914 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3915 data = data | URTW_RX_FILTER_CTL; 3916 data = data | URTW_RX_FILTER_ALLMAC; 3917 } else { 3918 data = data | URTW_RX_FILTER_NICMAC; 3919 data = data | URTW_RX_CHECK_BSSID; 3920 } 3921 3922 urtw_write32_m(sc, URTW_RX, data); 3923 fail: 3924 return (error); 3925 } 3926 3927 static struct mbuf * 3928 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3929 int8_t *nf_p) 3930 { 3931 int actlen, flen, rssi; 3932 struct ieee80211_frame *wh; 3933 struct mbuf *m, *mnew; 3934 struct urtw_softc *sc = data->sc; 3935 struct ieee80211com *ic = &sc->sc_ic; 3936 uint8_t noise = 0, rate; 3937 uint64_t mactime; 3938 3939 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3940 3941 if (sc->sc_flags & URTW_RTL8187B) { 3942 struct urtw_8187b_rxhdr *rx; 3943 3944 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3945 goto fail; 3946 3947 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3948 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3949 flen = le32toh(rx->flag) & 0xfff; 3950 if (flen > actlen - sizeof(*rx)) 3951 goto fail; 3952 3953 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3954 /* XXX correct? */ 3955 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3956 noise = rx->noise; 3957 3958 if (ieee80211_radiotap_active(ic)) 3959 mactime = rx->mactime; 3960 } else { 3961 struct urtw_8187l_rxhdr *rx; 3962 3963 if (actlen < sizeof(*rx) + IEEE80211_ACK_LEN) 3964 goto fail; 3965 3966 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3967 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3968 flen = le32toh(rx->flag) & 0xfff; 3969 if (flen > actlen - sizeof(*rx)) 3970 goto fail; 3971 3972 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3973 /* XXX correct? */ 3974 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3975 noise = rx->noise; 3976 3977 if (ieee80211_radiotap_active(ic)) 3978 mactime = rx->mactime; 3979 } 3980 3981 if (flen < IEEE80211_ACK_LEN) 3982 goto fail; 3983 3984 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3985 if (mnew == NULL) 3986 goto fail; 3987 3988 m = data->m; 3989 data->m = mnew; 3990 data->buf = mtod(mnew, uint8_t *); 3991 3992 /* finalize mbuf */ 3993 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3994 3995 if (ieee80211_radiotap_active(ic)) { 3996 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3997 3998 tap->wr_tsf = mactime; 3999 tap->wr_flags = 0; 4000 tap->wr_dbm_antsignal = (int8_t)rssi; 4001 } 4002 4003 wh = mtod(m, struct ieee80211_frame *); 4004 if (IEEE80211_IS_DATA(wh)) 4005 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 4006 4007 *rssi_p = rssi; 4008 *nf_p = noise; /* XXX correct? */ 4009 4010 return (m); 4011 4012 fail: 4013 counter_u64_add(ic->ic_ierrors, 1); 4014 return (NULL); 4015 } 4016 4017 static void 4018 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4019 { 4020 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4021 struct ieee80211com *ic = &sc->sc_ic; 4022 struct ieee80211_node *ni; 4023 struct mbuf *m = NULL; 4024 struct urtw_data *data; 4025 int8_t nf = -95; 4026 int rssi = 1; 4027 4028 URTW_ASSERT_LOCKED(sc); 4029 4030 switch (USB_GET_STATE(xfer)) { 4031 case USB_ST_TRANSFERRED: 4032 data = STAILQ_FIRST(&sc->sc_rx_active); 4033 if (data == NULL) 4034 goto setup; 4035 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4036 m = urtw_rxeof(xfer, data, &rssi, &nf); 4037 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4038 /* FALLTHROUGH */ 4039 case USB_ST_SETUP: 4040 setup: 4041 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4042 if (data == NULL) { 4043 KASSERT(m == NULL, ("mbuf isn't NULL")); 4044 return; 4045 } 4046 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4047 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4048 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4049 usbd_xfer_max_len(xfer)); 4050 usbd_transfer_submit(xfer); 4051 4052 /* 4053 * To avoid LOR we should unlock our private mutex here to call 4054 * ieee80211_input() because here is at the end of a USB 4055 * callback and safe to unlock. 4056 */ 4057 URTW_UNLOCK(sc); 4058 if (m != NULL) { 4059 if (m->m_pkthdr.len >= 4060 sizeof(struct ieee80211_frame_min)) { 4061 ni = ieee80211_find_rxnode(ic, 4062 mtod(m, struct ieee80211_frame_min *)); 4063 } else 4064 ni = NULL; 4065 4066 if (ni != NULL) { 4067 (void) ieee80211_input(ni, m, rssi, nf); 4068 /* node is no longer needed */ 4069 ieee80211_free_node(ni); 4070 } else 4071 (void) ieee80211_input_all(ic, m, rssi, nf); 4072 m = NULL; 4073 } 4074 URTW_LOCK(sc); 4075 break; 4076 default: 4077 /* needs it to the inactive queue due to a error. */ 4078 data = STAILQ_FIRST(&sc->sc_rx_active); 4079 if (data != NULL) { 4080 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4081 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4082 } 4083 if (error != USB_ERR_CANCELLED) { 4084 usbd_xfer_set_stall(xfer); 4085 counter_u64_add(ic->ic_ierrors, 1); 4086 goto setup; 4087 } 4088 break; 4089 } 4090 } 4091 4092 #define URTW_STATUS_TYPE_TXCLOSE 1 4093 #define URTW_STATUS_TYPE_BEACON_INTR 0 4094 4095 static void 4096 urtw_txstatus_eof(struct usb_xfer *xfer) 4097 { 4098 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4099 struct ieee80211com *ic = &sc->sc_ic; 4100 int actlen, type, pktretry, seq; 4101 uint64_t val; 4102 4103 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4104 4105 if (actlen != sizeof(uint64_t)) 4106 return; 4107 4108 val = le64toh(sc->sc_txstatus); 4109 type = (val >> 30) & 0x3; 4110 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4111 pktretry = val & 0xff; 4112 seq = (val >> 16) & 0xff; 4113 if (pktretry == URTW_TX_MAXRETRY) 4114 counter_u64_add(ic->ic_oerrors, 1); 4115 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4116 pktretry, seq); 4117 } 4118 } 4119 4120 static void 4121 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4122 { 4123 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4124 struct ieee80211com *ic = &sc->sc_ic; 4125 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4126 4127 URTW_ASSERT_LOCKED(sc); 4128 4129 switch (USB_GET_STATE(xfer)) { 4130 case USB_ST_TRANSFERRED: 4131 urtw_txstatus_eof(xfer); 4132 /* FALLTHROUGH */ 4133 case USB_ST_SETUP: 4134 setup: 4135 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4136 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4137 usbd_transfer_submit(xfer); 4138 break; 4139 default: 4140 if (error != USB_ERR_CANCELLED) { 4141 usbd_xfer_set_stall(xfer); 4142 counter_u64_add(ic->ic_ierrors, 1); 4143 goto setup; 4144 } 4145 break; 4146 } 4147 } 4148 4149 static void 4150 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4151 { 4152 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4153 4154 URTW_ASSERT_LOCKED(sc); 4155 4156 if (data->m) { 4157 /* XXX status? */ 4158 ieee80211_tx_complete(data->ni, data->m, 0); 4159 data->m = NULL; 4160 data->ni = NULL; 4161 } 4162 sc->sc_txtimer = 0; 4163 } 4164 4165 static void 4166 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4167 { 4168 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4169 struct urtw_data *data; 4170 4171 URTW_ASSERT_LOCKED(sc); 4172 4173 switch (USB_GET_STATE(xfer)) { 4174 case USB_ST_TRANSFERRED: 4175 data = STAILQ_FIRST(&sc->sc_tx_active); 4176 if (data == NULL) 4177 goto setup; 4178 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4179 urtw_txeof(xfer, data); 4180 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4181 /* FALLTHROUGH */ 4182 case USB_ST_SETUP: 4183 setup: 4184 data = STAILQ_FIRST(&sc->sc_tx_pending); 4185 if (data == NULL) { 4186 DPRINTF(sc, URTW_DEBUG_XMIT, 4187 "%s: empty pending queue\n", __func__); 4188 return; 4189 } 4190 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4191 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4192 4193 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4194 usbd_transfer_submit(xfer); 4195 4196 urtw_start(sc); 4197 break; 4198 default: 4199 data = STAILQ_FIRST(&sc->sc_tx_active); 4200 if (data == NULL) 4201 goto setup; 4202 if (data->ni != NULL) { 4203 if_inc_counter(data->ni->ni_vap->iv_ifp, 4204 IFCOUNTER_OERRORS, 1); 4205 ieee80211_free_node(data->ni); 4206 data->ni = NULL; 4207 } 4208 if (error != USB_ERR_CANCELLED) { 4209 usbd_xfer_set_stall(xfer); 4210 goto setup; 4211 } 4212 break; 4213 } 4214 } 4215 4216 static struct urtw_data * 4217 _urtw_getbuf(struct urtw_softc *sc) 4218 { 4219 struct urtw_data *bf; 4220 4221 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4222 if (bf != NULL) 4223 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4224 else 4225 bf = NULL; 4226 if (bf == NULL) 4227 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4228 "out of xmit buffers"); 4229 return (bf); 4230 } 4231 4232 static struct urtw_data * 4233 urtw_getbuf(struct urtw_softc *sc) 4234 { 4235 struct urtw_data *bf; 4236 4237 URTW_ASSERT_LOCKED(sc); 4238 4239 bf = _urtw_getbuf(sc); 4240 if (bf == NULL) 4241 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4242 return (bf); 4243 } 4244 4245 static int 4246 urtw_isbmode(uint16_t rate) 4247 { 4248 4249 return ((rate <= 22 && rate != 12 && rate != 18) || 4250 rate == 44) ? (1) : (0); 4251 } 4252 4253 static uint16_t 4254 urtw_rate2dbps(uint16_t rate) 4255 { 4256 4257 switch(rate) { 4258 case 12: 4259 case 18: 4260 case 24: 4261 case 36: 4262 case 48: 4263 case 72: 4264 case 96: 4265 case 108: 4266 return (rate * 2); 4267 default: 4268 break; 4269 } 4270 return (24); 4271 } 4272 4273 static int 4274 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4275 uint8_t ismgt, uint8_t isshort) 4276 { 4277 uint16_t ceiling, frametime, n_dbps; 4278 4279 if (urtw_isbmode(rate)) { 4280 if (ismgt || !isshort || rate == 2) 4281 frametime = (uint16_t)(144 + 48 + 4282 (framelen * 8 / (rate / 2))); 4283 else 4284 frametime = (uint16_t)(72 + 24 + 4285 (framelen * 8 / (rate / 2))); 4286 if ((framelen * 8 % (rate / 2)) != 0) 4287 frametime++; 4288 } else { 4289 n_dbps = urtw_rate2dbps(rate); 4290 ceiling = (16 + 8 * framelen + 6) / n_dbps 4291 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4292 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4293 } 4294 return (frametime); 4295 } 4296 4297 /* 4298 * Callback from the 802.11 layer to update the 4299 * slot time based on the current setting. 4300 */ 4301 static void 4302 urtw_updateslot(struct ieee80211com *ic) 4303 { 4304 struct urtw_softc *sc = ic->ic_softc; 4305 4306 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4307 } 4308 4309 static void 4310 urtw_updateslottask(void *arg, int pending) 4311 { 4312 struct urtw_softc *sc = arg; 4313 struct ieee80211com *ic = &sc->sc_ic; 4314 int error; 4315 4316 URTW_LOCK(sc); 4317 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4318 URTW_UNLOCK(sc); 4319 return; 4320 } 4321 if (sc->sc_flags & URTW_RTL8187B) { 4322 urtw_write8_m(sc, URTW_SIFS, 0x22); 4323 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4324 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4325 else 4326 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4327 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4328 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4329 } else { 4330 urtw_write8_m(sc, URTW_SIFS, 0x22); 4331 if (sc->sc_state == IEEE80211_S_ASSOC && 4332 ic->ic_flags & IEEE80211_F_SHSLOT) 4333 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4334 else 4335 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4336 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4337 urtw_write8_m(sc, URTW_DIFS, 0x14); 4338 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4339 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4340 } else { 4341 urtw_write8_m(sc, URTW_DIFS, 0x24); 4342 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4343 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4344 } 4345 } 4346 fail: 4347 URTW_UNLOCK(sc); 4348 } 4349 4350 static void 4351 urtw_sysctl_node(struct urtw_softc *sc) 4352 { 4353 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4354 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4355 struct sysctl_ctx_list *ctx; 4356 struct sysctl_oid_list *child, *parent; 4357 struct sysctl_oid *tree; 4358 struct urtw_stats *stats = &sc->sc_stats; 4359 4360 ctx = device_get_sysctl_ctx(sc->sc_dev); 4361 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4362 4363 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4364 NULL, "URTW statistics"); 4365 parent = SYSCTL_CHILDREN(tree); 4366 4367 /* Tx statistics. */ 4368 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4369 NULL, "Tx MAC statistics"); 4370 child = SYSCTL_CHILDREN(tree); 4371 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4372 "1 Mbit/s"); 4373 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4374 "2 Mbit/s"); 4375 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4376 "5.5 Mbit/s"); 4377 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4378 "6 Mbit/s"); 4379 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4380 "9 Mbit/s"); 4381 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4382 "11 Mbit/s"); 4383 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4384 "12 Mbit/s"); 4385 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4386 "18 Mbit/s"); 4387 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4388 "24 Mbit/s"); 4389 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4390 "36 Mbit/s"); 4391 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4392 "48 Mbit/s"); 4393 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4394 "54 Mbit/s"); 4395 #undef URTW_SYSCTL_STAT_ADD32 4396 } 4397 4398 static device_method_t urtw_methods[] = { 4399 DEVMETHOD(device_probe, urtw_match), 4400 DEVMETHOD(device_attach, urtw_attach), 4401 DEVMETHOD(device_detach, urtw_detach), 4402 DEVMETHOD_END 4403 }; 4404 static driver_t urtw_driver = { 4405 .name = "urtw", 4406 .methods = urtw_methods, 4407 .size = sizeof(struct urtw_softc) 4408 }; 4409 static devclass_t urtw_devclass; 4410 4411 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4412 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4413 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4414 MODULE_VERSION(urtw, 1); 4415 USB_PNP_HOST_INFO(urtw_devs); 4416