1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 #include <sys/param.h> 20 #include <sys/sockio.h> 21 #include <sys/sysctl.h> 22 #include <sys/lock.h> 23 #include <sys/mutex.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/malloc.h> 29 #include <sys/module.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kdb.h> 33 34 #include <machine/bus.h> 35 #include <machine/resource.h> 36 #include <sys/rman.h> 37 38 #include <net/if.h> 39 #include <net/if_var.h> 40 #include <net/if_arp.h> 41 #include <net/ethernet.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #ifdef INET 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_ether.h> 51 #include <netinet/ip.h> 52 #endif 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_regdomain.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include "usbdevs.h" 61 62 #include <dev/usb/wlan/if_urtwreg.h> 63 #include <dev/usb/wlan/if_urtwvar.h> 64 65 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 66 #ifdef URTW_DEBUG 67 int urtw_debug = 0; 68 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 69 "control debugging printfs"); 70 enum { 71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 77 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 80 URTW_DEBUG_ANY = 0xffffffff 81 }; 82 #define DPRINTF(sc, m, fmt, ...) do { \ 83 if (sc->sc_debug & (m)) \ 84 printf(fmt, __VA_ARGS__); \ 85 } while (0) 86 #else 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 (void) sc; \ 89 } while (0) 90 #endif 91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 93 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 94 95 /* recognized device vendors/products */ 96 #define urtw_lookup(v, p) \ 97 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 98 #define URTW_DEV_B(v,p) \ 99 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 100 #define URTW_DEV_L(v,p) \ 101 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 102 #define URTW_REV_RTL8187B 0 103 #define URTW_REV_RTL8187L 1 104 static const STRUCT_USB_HOST_ID urtw_devs[] = { 105 URTW_DEV_B(NETGEAR, WG111V3), 106 URTW_DEV_B(REALTEK, RTL8187B_0), 107 URTW_DEV_B(REALTEK, RTL8187B_1), 108 URTW_DEV_B(REALTEK, RTL8187B_2), 109 URTW_DEV_B(SITECOMEU, WL168V4), 110 URTW_DEV_L(ASUS, P5B_WIFI), 111 URTW_DEV_L(BELKIN, F5D7050E), 112 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 113 URTW_DEV_L(NETGEAR, WG111V2), 114 URTW_DEV_L(REALTEK, RTL8187), 115 URTW_DEV_L(SITECOMEU, WL168V1), 116 URTW_DEV_L(SURECOM, EP9001G2A), 117 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 118 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 119 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 120 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 121 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 122 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 124 #undef URTW_DEV_L 125 #undef URTW_DEV_B 126 }; 127 128 #define urtw_read8_m(sc, val, data) do { \ 129 error = urtw_read8_c(sc, val, data); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_write8_m(sc, val, data) do { \ 134 error = urtw_write8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_m(sc, val, data) do { \ 139 error = urtw_read16_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_read32_m(sc, val, data) do { \ 149 error = urtw_read32_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_write32_m(sc, val, data) do { \ 154 error = urtw_write32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 159 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 164 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8225_write(sc, val, data) do { \ 169 error = urtw_8225_write_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 174 struct urtw_pair { 175 uint32_t reg; 176 uint32_t val; 177 }; 178 179 static uint8_t urtw_8225_agc[] = { 180 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 181 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 182 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 183 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 184 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 185 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 186 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 187 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 188 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 189 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 192 }; 193 194 static uint8_t urtw_8225z2_agc[] = { 195 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 196 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 197 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 198 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 199 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 200 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 201 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 202 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 203 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 204 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 205 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 207 }; 208 209 static const uint8_t urtw_chan_2ghz[] = 210 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 211 212 static uint32_t urtw_8225_channel[] = { 213 0x0000, /* dummy channel 0 */ 214 0x085c, /* 1 */ 215 0x08dc, /* 2 */ 216 0x095c, /* 3 */ 217 0x09dc, /* 4 */ 218 0x0a5c, /* 5 */ 219 0x0adc, /* 6 */ 220 0x0b5c, /* 7 */ 221 0x0bdc, /* 8 */ 222 0x0c5c, /* 9 */ 223 0x0cdc, /* 10 */ 224 0x0d5c, /* 11 */ 225 0x0ddc, /* 12 */ 226 0x0e5c, /* 13 */ 227 0x0f72, /* 14 */ 228 }; 229 230 static uint8_t urtw_8225_gain[] = { 231 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 232 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 233 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 234 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 235 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 236 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 237 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 238 }; 239 240 static struct urtw_pair urtw_8225_rf_part1[] = { 241 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 242 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 243 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 244 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 245 }; 246 247 static struct urtw_pair urtw_8225_rf_part2[] = { 248 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 249 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 250 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 251 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 252 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 253 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 254 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 255 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 256 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 257 { 0x27, 0x88 } 258 }; 259 260 static struct urtw_pair urtw_8225_rf_part3[] = { 261 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 262 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 263 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 264 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 265 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 266 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 267 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 268 }; 269 270 static uint16_t urtw_8225_rxgain[] = { 271 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 272 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 273 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 274 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 275 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 276 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 277 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 278 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 279 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 280 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 281 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 282 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 283 }; 284 285 static uint8_t urtw_8225_threshold[] = { 286 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 287 }; 288 289 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 290 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 291 }; 292 293 static uint8_t urtw_8225_txpwr_cck[] = { 294 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 295 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 296 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 297 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 298 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 299 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 300 }; 301 302 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 303 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 304 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 305 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 306 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 307 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 308 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 309 }; 310 311 static uint8_t urtw_8225_txpwr_ofdm[]={ 312 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 313 }; 314 315 static uint8_t urtw_8225v2_gain_bg[]={ 316 0x23, 0x15, 0xa5, /* -82-1dbm */ 317 0x23, 0x15, 0xb5, /* -82-2dbm */ 318 0x23, 0x15, 0xc5, /* -82-3dbm */ 319 0x33, 0x15, 0xc5, /* -78dbm */ 320 0x43, 0x15, 0xc5, /* -74dbm */ 321 0x53, 0x15, 0xc5, /* -70dbm */ 322 0x63, 0x15, 0xc5, /* -66dbm */ 323 }; 324 325 static struct urtw_pair urtw_8225v2_rf_part1[] = { 326 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 327 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 328 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 329 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 330 }; 331 332 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 333 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 334 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 335 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 336 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 337 }; 338 339 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 340 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 341 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 342 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 343 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 344 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 345 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 346 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 347 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 348 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 349 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 350 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 351 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 352 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 353 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 354 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 355 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 356 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 357 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 358 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 359 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 360 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 361 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 362 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 363 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 364 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 365 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 366 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 367 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 368 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 369 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 370 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 371 }; 372 373 static struct urtw_pair urtw_8225v2_rf_part2[] = { 374 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 375 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 376 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 377 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 378 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 379 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 380 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 381 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 382 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 383 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 384 }; 385 386 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 387 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 388 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 389 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 390 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 391 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 392 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 393 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 394 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 395 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 396 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 397 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 398 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 399 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 400 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 401 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 402 }; 403 404 static struct urtw_pair urtw_8225v2_rf_part3[] = { 405 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 406 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 407 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 408 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 409 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 410 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 411 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 412 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 413 }; 414 415 static uint16_t urtw_8225v2_rxgain[] = { 416 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 417 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 418 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 419 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 420 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 421 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 422 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 423 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 424 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 425 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 426 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 427 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 428 }; 429 430 static uint16_t urtw_8225v2b_rxgain[] = { 431 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 432 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 433 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 434 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 435 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 436 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 437 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 438 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 439 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 440 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 441 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 442 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 443 }; 444 445 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 446 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 447 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 448 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 449 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 450 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 451 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 452 }; 453 454 static uint8_t urtw_8225v2_txpwr_cck[] = { 455 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 456 }; 457 458 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 459 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 460 }; 461 462 static uint8_t urtw_8225v2b_txpwr_cck[] = { 463 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 464 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 465 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 466 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 467 }; 468 469 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 470 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 474 }; 475 476 static struct urtw_pair urtw_ratetable[] = { 477 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 478 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 479 { 96, 10 }, { 108, 11 } 480 }; 481 482 #if 0 483 static const uint8_t urtw_8187b_reg_table[][3] = { 484 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 485 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 486 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 487 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 488 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 489 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 490 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 491 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 492 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 493 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 494 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 495 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 496 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 497 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 498 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 499 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 500 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 501 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 502 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 503 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 504 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 505 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 506 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 507 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 508 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 509 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 510 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 511 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 512 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 513 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 514 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 515 }; 516 #endif 517 518 static usb_callback_t urtw_bulk_rx_callback; 519 static usb_callback_t urtw_bulk_tx_callback; 520 static usb_callback_t urtw_bulk_tx_status_callback; 521 522 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 523 [URTW_8187B_BULK_RX] = { 524 .type = UE_BULK, 525 .endpoint = 0x83, 526 .direction = UE_DIR_IN, 527 .bufsize = MCLBYTES, 528 .flags = { 529 .ext_buffer = 1, 530 .pipe_bof = 1, 531 .short_xfer_ok = 1 532 }, 533 .callback = urtw_bulk_rx_callback 534 }, 535 [URTW_8187B_BULK_TX_STATUS] = { 536 .type = UE_BULK, 537 .endpoint = 0x89, 538 .direction = UE_DIR_IN, 539 .bufsize = sizeof(uint64_t), 540 .flags = { 541 .pipe_bof = 1, 542 .short_xfer_ok = 1 543 }, 544 .callback = urtw_bulk_tx_status_callback 545 }, 546 [URTW_8187B_BULK_TX_BE] = { 547 .type = UE_BULK, 548 .endpoint = URTW_8187B_TXPIPE_BE, 549 .direction = UE_DIR_OUT, 550 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 551 .flags = { 552 .force_short_xfer = 1, 553 .pipe_bof = 1, 554 }, 555 .callback = urtw_bulk_tx_callback, 556 .timeout = URTW_DATA_TIMEOUT 557 }, 558 [URTW_8187B_BULK_TX_BK] = { 559 .type = UE_BULK, 560 .endpoint = URTW_8187B_TXPIPE_BK, 561 .direction = UE_DIR_OUT, 562 .bufsize = URTW_TX_MAXSIZE, 563 .flags = { 564 .ext_buffer = 1, 565 .force_short_xfer = 1, 566 .pipe_bof = 1, 567 }, 568 .callback = urtw_bulk_tx_callback, 569 .timeout = URTW_DATA_TIMEOUT 570 }, 571 [URTW_8187B_BULK_TX_VI] = { 572 .type = UE_BULK, 573 .endpoint = URTW_8187B_TXPIPE_VI, 574 .direction = UE_DIR_OUT, 575 .bufsize = URTW_TX_MAXSIZE, 576 .flags = { 577 .ext_buffer = 1, 578 .force_short_xfer = 1, 579 .pipe_bof = 1, 580 }, 581 .callback = urtw_bulk_tx_callback, 582 .timeout = URTW_DATA_TIMEOUT 583 }, 584 [URTW_8187B_BULK_TX_VO] = { 585 .type = UE_BULK, 586 .endpoint = URTW_8187B_TXPIPE_VO, 587 .direction = UE_DIR_OUT, 588 .bufsize = URTW_TX_MAXSIZE, 589 .flags = { 590 .ext_buffer = 1, 591 .force_short_xfer = 1, 592 .pipe_bof = 1, 593 }, 594 .callback = urtw_bulk_tx_callback, 595 .timeout = URTW_DATA_TIMEOUT 596 }, 597 [URTW_8187B_BULK_TX_EP12] = { 598 .type = UE_BULK, 599 .endpoint = 0xc, 600 .direction = UE_DIR_OUT, 601 .bufsize = URTW_TX_MAXSIZE, 602 .flags = { 603 .ext_buffer = 1, 604 .force_short_xfer = 1, 605 .pipe_bof = 1, 606 }, 607 .callback = urtw_bulk_tx_callback, 608 .timeout = URTW_DATA_TIMEOUT 609 } 610 }; 611 612 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 613 [URTW_8187L_BULK_RX] = { 614 .type = UE_BULK, 615 .endpoint = 0x81, 616 .direction = UE_DIR_IN, 617 .bufsize = MCLBYTES, 618 .flags = { 619 .ext_buffer = 1, 620 .pipe_bof = 1, 621 .short_xfer_ok = 1 622 }, 623 .callback = urtw_bulk_rx_callback 624 }, 625 [URTW_8187L_BULK_TX_LOW] = { 626 .type = UE_BULK, 627 .endpoint = 0x2, 628 .direction = UE_DIR_OUT, 629 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 630 .flags = { 631 .force_short_xfer = 1, 632 .pipe_bof = 1, 633 }, 634 .callback = urtw_bulk_tx_callback, 635 .timeout = URTW_DATA_TIMEOUT 636 }, 637 [URTW_8187L_BULK_TX_NORMAL] = { 638 .type = UE_BULK, 639 .endpoint = 0x3, 640 .direction = UE_DIR_OUT, 641 .bufsize = URTW_TX_MAXSIZE, 642 .flags = { 643 .ext_buffer = 1, 644 .force_short_xfer = 1, 645 .pipe_bof = 1, 646 }, 647 .callback = urtw_bulk_tx_callback, 648 .timeout = URTW_DATA_TIMEOUT 649 }, 650 }; 651 652 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 653 const char [IFNAMSIZ], int, enum ieee80211_opmode, 654 int, const uint8_t [IEEE80211_ADDR_LEN], 655 const uint8_t [IEEE80211_ADDR_LEN]); 656 static void urtw_vap_delete(struct ieee80211vap *); 657 static void urtw_init(struct urtw_softc *); 658 static void urtw_stop(struct urtw_softc *); 659 static void urtw_parent(struct ieee80211com *); 660 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 661 static void urtw_start(struct urtw_softc *); 662 static int urtw_alloc_rx_data_list(struct urtw_softc *); 663 static int urtw_alloc_tx_data_list(struct urtw_softc *); 664 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 665 const struct ieee80211_bpf_params *); 666 static void urtw_scan_start(struct ieee80211com *); 667 static void urtw_scan_end(struct ieee80211com *); 668 static void urtw_getradiocaps(struct ieee80211com *, int, int *, 669 struct ieee80211_channel[]); 670 static void urtw_set_channel(struct ieee80211com *); 671 static void urtw_update_mcast(struct ieee80211com *); 672 static int urtw_tx_start(struct urtw_softc *, 673 struct ieee80211_node *, struct mbuf *, 674 struct urtw_data *, int); 675 static int urtw_newstate(struct ieee80211vap *, 676 enum ieee80211_state, int); 677 static void urtw_led_ch(void *); 678 static void urtw_ledtask(void *, int); 679 static void urtw_watchdog(void *); 680 static void urtw_set_multi(void *); 681 static int urtw_isbmode(uint16_t); 682 static uint16_t urtw_rate2rtl(uint32_t); 683 static uint16_t urtw_rtl2rate(uint32_t); 684 static usb_error_t urtw_set_rate(struct urtw_softc *); 685 static usb_error_t urtw_update_msr(struct urtw_softc *); 686 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 687 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 688 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 689 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 690 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 691 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 692 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 693 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 694 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 695 int); 696 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 697 uint32_t *); 698 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 699 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 700 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 701 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 702 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 703 static usb_error_t urtw_led_init(struct urtw_softc *); 704 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 705 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 706 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 707 uint32_t); 708 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 709 uint8_t, uint32_t); 710 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 711 uint32_t); 712 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 713 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 714 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 715 uint16_t); 716 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 717 uint16_t *); 718 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 719 uint32_t *); 720 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 721 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 722 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 723 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 724 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 725 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 726 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 727 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 728 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 729 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 730 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 731 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 732 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 733 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 734 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 735 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 736 static usb_error_t urtw_intr_enable(struct urtw_softc *); 737 static usb_error_t urtw_intr_disable(struct urtw_softc *); 738 static usb_error_t urtw_reset(struct urtw_softc *); 739 static usb_error_t urtw_led_on(struct urtw_softc *, int); 740 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 741 static usb_error_t urtw_led_blink(struct urtw_softc *); 742 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 743 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 744 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 745 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 746 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 747 static usb_error_t urtw_rx_enable(struct urtw_softc *); 748 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 749 static void urtw_free_tx_data_list(struct urtw_softc *); 750 static void urtw_free_rx_data_list(struct urtw_softc *); 751 static void urtw_free_data_list(struct urtw_softc *, 752 struct urtw_data data[], int, int); 753 static usb_error_t urtw_adapter_start(struct urtw_softc *); 754 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 755 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 756 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 757 static usb_error_t urtw_do_request(struct urtw_softc *, 758 struct usb_device_request *, void *); 759 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 760 static usb_error_t urtw_led_off(struct urtw_softc *, int); 761 static void urtw_abort_xfers(struct urtw_softc *); 762 static struct urtw_data * 763 urtw_getbuf(struct urtw_softc *sc); 764 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 765 uint8_t); 766 static void urtw_updateslot(struct ieee80211com *); 767 static void urtw_updateslottask(void *, int); 768 static void urtw_sysctl_node(struct urtw_softc *); 769 770 static int 771 urtw_match(device_t dev) 772 { 773 struct usb_attach_arg *uaa = device_get_ivars(dev); 774 775 if (uaa->usb_mode != USB_MODE_HOST) 776 return (ENXIO); 777 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 778 return (ENXIO); 779 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 780 return (ENXIO); 781 782 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 783 } 784 785 static int 786 urtw_attach(device_t dev) 787 { 788 const struct usb_config *setup_start; 789 int ret = ENXIO; 790 struct urtw_softc *sc = device_get_softc(dev); 791 struct usb_attach_arg *uaa = device_get_ivars(dev); 792 struct ieee80211com *ic = &sc->sc_ic; 793 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 794 uint16_t n_setup; 795 uint32_t data; 796 usb_error_t error; 797 798 device_set_usb_desc(dev); 799 800 sc->sc_dev = dev; 801 sc->sc_udev = uaa->device; 802 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 803 sc->sc_flags |= URTW_RTL8187B; 804 #ifdef URTW_DEBUG 805 sc->sc_debug = urtw_debug; 806 #endif 807 808 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 809 MTX_DEF); 810 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 811 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 812 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 813 callout_init(&sc->sc_watchdog_ch, 0); 814 mbufq_init(&sc->sc_snd, ifqmaxlen); 815 816 if (sc->sc_flags & URTW_RTL8187B) { 817 setup_start = urtw_8187b_usbconfig; 818 n_setup = URTW_8187B_N_XFERS; 819 } else { 820 setup_start = urtw_8187l_usbconfig; 821 n_setup = URTW_8187L_N_XFERS; 822 } 823 824 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 825 setup_start, n_setup, sc, &sc->sc_mtx); 826 if (error) { 827 device_printf(dev, "could not allocate USB transfers, " 828 "err=%s\n", usbd_errstr(error)); 829 ret = ENXIO; 830 goto fail0; 831 } 832 833 if (sc->sc_flags & URTW_RTL8187B) { 834 sc->sc_tx_dma_buf = 835 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 836 URTW_8187B_BULK_TX_BE], 0); 837 } else { 838 sc->sc_tx_dma_buf = 839 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 840 URTW_8187L_BULK_TX_LOW], 0); 841 } 842 843 URTW_LOCK(sc); 844 845 urtw_read32_m(sc, URTW_RX, &data); 846 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 847 URTW_EEPROM_93C46; 848 849 error = urtw_get_rfchip(sc); 850 if (error != 0) 851 goto fail; 852 error = urtw_get_macaddr(sc); 853 if (error != 0) 854 goto fail; 855 error = urtw_get_txpwr(sc); 856 if (error != 0) 857 goto fail; 858 error = urtw_led_init(sc); 859 if (error != 0) 860 goto fail; 861 862 URTW_UNLOCK(sc); 863 864 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 865 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 866 sc->sc_currate = 3; 867 sc->sc_preamble_mode = urtw_preamble_mode; 868 869 ic->ic_softc = sc; 870 ic->ic_name = device_get_nameunit(dev); 871 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 872 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 873 874 /* set device capabilities */ 875 ic->ic_caps = 876 IEEE80211_C_STA | /* station mode */ 877 IEEE80211_C_MONITOR | /* monitor mode supported */ 878 IEEE80211_C_TXPMGT | /* tx power management */ 879 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 880 IEEE80211_C_SHSLOT | /* short slot time supported */ 881 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 882 IEEE80211_C_WPA; /* 802.11i */ 883 884 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 885 886 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 887 ic->ic_channels); 888 889 ieee80211_ifattach(ic); 890 ic->ic_raw_xmit = urtw_raw_xmit; 891 ic->ic_scan_start = urtw_scan_start; 892 ic->ic_scan_end = urtw_scan_end; 893 ic->ic_getradiocaps = urtw_getradiocaps; 894 ic->ic_set_channel = urtw_set_channel; 895 ic->ic_updateslot = urtw_updateslot; 896 ic->ic_vap_create = urtw_vap_create; 897 ic->ic_vap_delete = urtw_vap_delete; 898 ic->ic_update_mcast = urtw_update_mcast; 899 ic->ic_parent = urtw_parent; 900 ic->ic_transmit = urtw_transmit; 901 902 ieee80211_radiotap_attach(ic, 903 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 904 URTW_TX_RADIOTAP_PRESENT, 905 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 906 URTW_RX_RADIOTAP_PRESENT); 907 908 urtw_sysctl_node(sc); 909 910 if (bootverbose) 911 ieee80211_announce(ic); 912 return (0); 913 914 fail: 915 URTW_UNLOCK(sc); 916 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 917 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 918 fail0: 919 return (ret); 920 } 921 922 static int 923 urtw_detach(device_t dev) 924 { 925 struct urtw_softc *sc = device_get_softc(dev); 926 struct ieee80211com *ic = &sc->sc_ic; 927 unsigned int x; 928 unsigned int n_xfers; 929 930 /* Prevent further ioctls */ 931 URTW_LOCK(sc); 932 sc->sc_flags |= URTW_DETACHED; 933 urtw_stop(sc); 934 URTW_UNLOCK(sc); 935 936 ieee80211_draintask(ic, &sc->sc_updateslot_task); 937 ieee80211_draintask(ic, &sc->sc_led_task); 938 939 usb_callout_drain(&sc->sc_led_ch); 940 callout_drain(&sc->sc_watchdog_ch); 941 942 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 943 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 944 945 /* prevent further allocations from RX/TX data lists */ 946 URTW_LOCK(sc); 947 STAILQ_INIT(&sc->sc_tx_active); 948 STAILQ_INIT(&sc->sc_tx_inactive); 949 STAILQ_INIT(&sc->sc_tx_pending); 950 951 STAILQ_INIT(&sc->sc_rx_active); 952 STAILQ_INIT(&sc->sc_rx_inactive); 953 URTW_UNLOCK(sc); 954 955 /* drain USB transfers */ 956 for (x = 0; x != n_xfers; x++) 957 usbd_transfer_drain(sc->sc_xfer[x]); 958 959 /* free data buffers */ 960 URTW_LOCK(sc); 961 urtw_free_tx_data_list(sc); 962 urtw_free_rx_data_list(sc); 963 URTW_UNLOCK(sc); 964 965 /* free USB transfers and some data buffers */ 966 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 967 968 ieee80211_ifdetach(ic); 969 mbufq_drain(&sc->sc_snd); 970 mtx_destroy(&sc->sc_mtx); 971 return (0); 972 } 973 974 static void 975 urtw_free_tx_data_list(struct urtw_softc *sc) 976 { 977 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 978 } 979 980 static void 981 urtw_free_rx_data_list(struct urtw_softc *sc) 982 { 983 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 984 } 985 986 static void 987 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 988 int fillmbuf) 989 { 990 int i; 991 992 for (i = 0; i < ndata; i++) { 993 struct urtw_data *dp = &data[i]; 994 995 if (fillmbuf == 1) { 996 if (dp->m != NULL) { 997 m_freem(dp->m); 998 dp->m = NULL; 999 dp->buf = NULL; 1000 } 1001 } else { 1002 dp->buf = NULL; 1003 } 1004 if (dp->ni != NULL) { 1005 ieee80211_free_node(dp->ni); 1006 dp->ni = NULL; 1007 } 1008 } 1009 } 1010 1011 static struct ieee80211vap * 1012 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1013 enum ieee80211_opmode opmode, int flags, 1014 const uint8_t bssid[IEEE80211_ADDR_LEN], 1015 const uint8_t mac[IEEE80211_ADDR_LEN]) 1016 { 1017 struct urtw_vap *uvp; 1018 struct ieee80211vap *vap; 1019 1020 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1021 return (NULL); 1022 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1023 vap = &uvp->vap; 1024 /* enable s/w bmiss handling for sta mode */ 1025 1026 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1027 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1028 /* out of memory */ 1029 free(uvp, M_80211_VAP); 1030 return (NULL); 1031 } 1032 1033 /* override state transition machine */ 1034 uvp->newstate = vap->iv_newstate; 1035 vap->iv_newstate = urtw_newstate; 1036 1037 /* complete setup */ 1038 ieee80211_vap_attach(vap, ieee80211_media_change, 1039 ieee80211_media_status, mac); 1040 ic->ic_opmode = opmode; 1041 return (vap); 1042 } 1043 1044 static void 1045 urtw_vap_delete(struct ieee80211vap *vap) 1046 { 1047 struct urtw_vap *uvp = URTW_VAP(vap); 1048 1049 ieee80211_vap_detach(vap); 1050 free(uvp, M_80211_VAP); 1051 } 1052 1053 static void 1054 urtw_init(struct urtw_softc *sc) 1055 { 1056 usb_error_t error; 1057 int ret; 1058 1059 URTW_ASSERT_LOCKED(sc); 1060 1061 if (sc->sc_flags & URTW_RUNNING) 1062 urtw_stop(sc); 1063 1064 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1065 urtw_adapter_start(sc); 1066 if (error != 0) 1067 goto fail; 1068 1069 /* reset softc variables */ 1070 sc->sc_txtimer = 0; 1071 1072 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1073 ret = urtw_alloc_rx_data_list(sc); 1074 if (ret != 0) 1075 goto fail; 1076 ret = urtw_alloc_tx_data_list(sc); 1077 if (ret != 0) 1078 goto fail; 1079 sc->sc_flags |= URTW_INIT_ONCE; 1080 } 1081 1082 error = urtw_rx_enable(sc); 1083 if (error != 0) 1084 goto fail; 1085 error = urtw_tx_enable(sc); 1086 if (error != 0) 1087 goto fail; 1088 1089 if (sc->sc_flags & URTW_RTL8187B) 1090 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1091 1092 sc->sc_flags |= URTW_RUNNING; 1093 1094 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1095 fail: 1096 return; 1097 } 1098 1099 static usb_error_t 1100 urtw_adapter_start_b(struct urtw_softc *sc) 1101 { 1102 uint8_t data8; 1103 usb_error_t error; 1104 1105 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1106 if (error) 1107 goto fail; 1108 1109 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1110 urtw_write8_m(sc, URTW_CONFIG3, 1111 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1112 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1113 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1114 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1115 1116 urtw_write8_m(sc, 0x61, 0x10); 1117 urtw_read8_m(sc, 0x62, &data8); 1118 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1119 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1120 1121 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1122 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1123 urtw_write8_m(sc, URTW_CONFIG3, data8); 1124 1125 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1126 if (error) 1127 goto fail; 1128 1129 error = urtw_8187b_cmd_reset(sc); 1130 if (error) 1131 goto fail; 1132 1133 error = sc->sc_rf_init(sc); 1134 if (error != 0) 1135 goto fail; 1136 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1137 1138 /* fix RTL8187B RX stall */ 1139 error = urtw_intr_enable(sc); 1140 if (error) 1141 goto fail; 1142 1143 error = urtw_write8e(sc, 0x41, 0xf4); 1144 if (error) 1145 goto fail; 1146 error = urtw_write8e(sc, 0x40, 0x00); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x42, 0x00); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x01); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x40, 0x0f); 1156 if (error) 1157 goto fail; 1158 error = urtw_write8e(sc, 0x42, 0x00); 1159 if (error) 1160 goto fail; 1161 error = urtw_write8e(sc, 0x42, 0x01); 1162 if (error) 1163 goto fail; 1164 1165 urtw_read8_m(sc, 0xdb, &data8); 1166 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1167 urtw_write16_m(sc, 0x372, 0x59fa); 1168 urtw_write16_m(sc, 0x374, 0x59d2); 1169 urtw_write16_m(sc, 0x376, 0x59d2); 1170 urtw_write16_m(sc, 0x378, 0x19fa); 1171 urtw_write16_m(sc, 0x37a, 0x19fa); 1172 urtw_write16_m(sc, 0x37c, 0x00d0); 1173 urtw_write8_m(sc, 0x61, 0); 1174 1175 urtw_write8_m(sc, 0x180, 0x0f); 1176 urtw_write8_m(sc, 0x183, 0x03); 1177 urtw_write8_m(sc, 0xda, 0x10); 1178 urtw_write8_m(sc, 0x24d, 0x08); 1179 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1180 1181 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1182 fail: 1183 return (error); 1184 } 1185 1186 static usb_error_t 1187 urtw_adapter_start(struct urtw_softc *sc) 1188 { 1189 struct ieee80211com *ic = &sc->sc_ic; 1190 usb_error_t error; 1191 1192 error = urtw_reset(sc); 1193 if (error) 1194 goto fail; 1195 1196 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1197 urtw_write8_m(sc, URTW_GPIO, 0); 1198 1199 /* for led */ 1200 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1201 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1202 if (error != 0) 1203 goto fail; 1204 1205 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1206 if (error) 1207 goto fail; 1208 /* applying MAC address again. */ 1209 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1210 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1211 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1212 if (error) 1213 goto fail; 1214 1215 error = urtw_update_msr(sc); 1216 if (error) 1217 goto fail; 1218 1219 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1220 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1221 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1222 error = urtw_set_rate(sc); 1223 if (error != 0) 1224 goto fail; 1225 1226 error = sc->sc_rf_init(sc); 1227 if (error != 0) 1228 goto fail; 1229 if (sc->sc_rf_set_sens != NULL) 1230 sc->sc_rf_set_sens(sc, sc->sc_sens); 1231 1232 /* XXX correct? to call write16 */ 1233 urtw_write16_m(sc, URTW_PSR, 1); 1234 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1235 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1236 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1237 /* XXX correct? to call write16 */ 1238 urtw_write16_m(sc, URTW_PSR, 0); 1239 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1240 1241 error = urtw_intr_enable(sc); 1242 if (error != 0) 1243 goto fail; 1244 1245 fail: 1246 return (error); 1247 } 1248 1249 static usb_error_t 1250 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1251 { 1252 uint8_t data; 1253 usb_error_t error; 1254 1255 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1256 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1257 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1258 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1259 fail: 1260 return (error); 1261 } 1262 1263 static usb_error_t 1264 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1265 { 1266 int i; 1267 uint8_t data8; 1268 usb_error_t error; 1269 1270 /* XXX the code can be duplicate with urtw_reset(). */ 1271 urtw_read8_m(sc, URTW_CMD, &data8); 1272 data8 = (data8 & 0x2) | URTW_CMD_RST; 1273 urtw_write8_m(sc, URTW_CMD, data8); 1274 1275 for (i = 0; i < 20; i++) { 1276 usb_pause_mtx(&sc->sc_mtx, 2); 1277 urtw_read8_m(sc, URTW_CMD, &data8); 1278 if (!(data8 & URTW_CMD_RST)) 1279 break; 1280 } 1281 if (i >= 20) { 1282 device_printf(sc->sc_dev, "reset timeout\n"); 1283 goto fail; 1284 } 1285 fail: 1286 return (error); 1287 } 1288 1289 static usb_error_t 1290 urtw_do_request(struct urtw_softc *sc, 1291 struct usb_device_request *req, void *data) 1292 { 1293 usb_error_t err; 1294 int ntries = 10; 1295 1296 URTW_ASSERT_LOCKED(sc); 1297 1298 while (ntries--) { 1299 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1300 req, data, 0, NULL, 250 /* ms */); 1301 if (err == 0) 1302 break; 1303 1304 DPRINTF(sc, URTW_DEBUG_INIT, 1305 "Control request failed, %s (retrying)\n", 1306 usbd_errstr(err)); 1307 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1308 } 1309 return (err); 1310 } 1311 1312 static void 1313 urtw_stop(struct urtw_softc *sc) 1314 { 1315 uint8_t data8; 1316 usb_error_t error; 1317 1318 URTW_ASSERT_LOCKED(sc); 1319 1320 sc->sc_flags &= ~URTW_RUNNING; 1321 1322 error = urtw_intr_disable(sc); 1323 if (error) 1324 goto fail; 1325 urtw_read8_m(sc, URTW_CMD, &data8); 1326 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1327 urtw_write8_m(sc, URTW_CMD, data8); 1328 1329 error = sc->sc_rf_stop(sc); 1330 if (error != 0) 1331 goto fail; 1332 1333 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1334 if (error) 1335 goto fail; 1336 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1337 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1338 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1339 if (error) 1340 goto fail; 1341 fail: 1342 if (error) 1343 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1344 usbd_errstr(error)); 1345 1346 usb_callout_stop(&sc->sc_led_ch); 1347 callout_stop(&sc->sc_watchdog_ch); 1348 1349 urtw_abort_xfers(sc); 1350 } 1351 1352 static void 1353 urtw_abort_xfers(struct urtw_softc *sc) 1354 { 1355 int i, max; 1356 1357 URTW_ASSERT_LOCKED(sc); 1358 1359 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1360 URTW_8187L_N_XFERS; 1361 1362 /* abort any pending transfers */ 1363 for (i = 0; i < max; i++) 1364 usbd_transfer_stop(sc->sc_xfer[i]); 1365 } 1366 1367 static void 1368 urtw_parent(struct ieee80211com *ic) 1369 { 1370 struct urtw_softc *sc = ic->ic_softc; 1371 int startall = 0; 1372 1373 URTW_LOCK(sc); 1374 if (sc->sc_flags & URTW_DETACHED) { 1375 URTW_UNLOCK(sc); 1376 return; 1377 } 1378 1379 if (ic->ic_nrunning > 0) { 1380 if (sc->sc_flags & URTW_RUNNING) { 1381 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1382 urtw_set_multi(sc); 1383 } else { 1384 urtw_init(sc); 1385 startall = 1; 1386 } 1387 } else if (sc->sc_flags & URTW_RUNNING) 1388 urtw_stop(sc); 1389 URTW_UNLOCK(sc); 1390 if (startall) 1391 ieee80211_start_all(ic); 1392 } 1393 1394 static int 1395 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1396 { 1397 struct urtw_softc *sc = ic->ic_softc; 1398 int error; 1399 1400 URTW_LOCK(sc); 1401 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1402 URTW_UNLOCK(sc); 1403 return (ENXIO); 1404 } 1405 error = mbufq_enqueue(&sc->sc_snd, m); 1406 if (error) { 1407 URTW_UNLOCK(sc); 1408 return (error); 1409 } 1410 urtw_start(sc); 1411 URTW_UNLOCK(sc); 1412 1413 return (0); 1414 } 1415 1416 static void 1417 urtw_start(struct urtw_softc *sc) 1418 { 1419 struct urtw_data *bf; 1420 struct ieee80211_node *ni; 1421 struct mbuf *m; 1422 1423 URTW_ASSERT_LOCKED(sc); 1424 1425 if ((sc->sc_flags & URTW_RUNNING) == 0) 1426 return; 1427 1428 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1429 bf = urtw_getbuf(sc); 1430 if (bf == NULL) { 1431 mbufq_prepend(&sc->sc_snd, m); 1432 break; 1433 } 1434 1435 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1436 m->m_pkthdr.rcvif = NULL; 1437 1438 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1439 if_inc_counter(ni->ni_vap->iv_ifp, 1440 IFCOUNTER_OERRORS, 1); 1441 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1442 ieee80211_free_node(ni); 1443 break; 1444 } 1445 1446 sc->sc_txtimer = 5; 1447 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1448 } 1449 } 1450 1451 static int 1452 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1453 int ndata, int maxsz, void *dma_buf) 1454 { 1455 int i, error; 1456 1457 for (i = 0; i < ndata; i++) { 1458 struct urtw_data *dp = &data[i]; 1459 1460 dp->sc = sc; 1461 if (dma_buf == NULL) { 1462 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1463 if (dp->m == NULL) { 1464 device_printf(sc->sc_dev, 1465 "could not allocate rx mbuf\n"); 1466 error = ENOMEM; 1467 goto fail; 1468 } 1469 dp->buf = mtod(dp->m, uint8_t *); 1470 } else { 1471 dp->m = NULL; 1472 dp->buf = ((uint8_t *)dma_buf) + 1473 (i * maxsz); 1474 } 1475 dp->ni = NULL; 1476 } 1477 return (0); 1478 1479 fail: urtw_free_data_list(sc, data, ndata, 1); 1480 return (error); 1481 } 1482 1483 static int 1484 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1485 { 1486 int error, i; 1487 1488 error = urtw_alloc_data_list(sc, 1489 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1490 MCLBYTES, NULL /* mbufs */); 1491 if (error != 0) 1492 return (error); 1493 1494 STAILQ_INIT(&sc->sc_rx_active); 1495 STAILQ_INIT(&sc->sc_rx_inactive); 1496 1497 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1498 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1499 1500 return (0); 1501 } 1502 1503 static int 1504 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1505 { 1506 int error, i; 1507 1508 error = urtw_alloc_data_list(sc, 1509 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1510 sc->sc_tx_dma_buf /* no mbufs */); 1511 if (error != 0) 1512 return (error); 1513 1514 STAILQ_INIT(&sc->sc_tx_active); 1515 STAILQ_INIT(&sc->sc_tx_inactive); 1516 STAILQ_INIT(&sc->sc_tx_pending); 1517 1518 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1519 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1520 next); 1521 1522 return (0); 1523 } 1524 1525 static int 1526 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1527 const struct ieee80211_bpf_params *params) 1528 { 1529 struct ieee80211com *ic = ni->ni_ic; 1530 struct urtw_softc *sc = ic->ic_softc; 1531 struct urtw_data *bf; 1532 1533 /* prevent management frames from being sent if we're not ready */ 1534 if (!(sc->sc_flags & URTW_RUNNING)) { 1535 m_freem(m); 1536 return ENETDOWN; 1537 } 1538 URTW_LOCK(sc); 1539 bf = urtw_getbuf(sc); 1540 if (bf == NULL) { 1541 m_freem(m); 1542 URTW_UNLOCK(sc); 1543 return (ENOBUFS); /* XXX */ 1544 } 1545 1546 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1547 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1548 URTW_UNLOCK(sc); 1549 return (EIO); 1550 } 1551 URTW_UNLOCK(sc); 1552 1553 sc->sc_txtimer = 5; 1554 return (0); 1555 } 1556 1557 static void 1558 urtw_scan_start(struct ieee80211com *ic) 1559 { 1560 1561 /* XXX do nothing? */ 1562 } 1563 1564 static void 1565 urtw_scan_end(struct ieee80211com *ic) 1566 { 1567 1568 /* XXX do nothing? */ 1569 } 1570 1571 static void 1572 urtw_getradiocaps(struct ieee80211com *ic, 1573 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1574 { 1575 uint8_t bands[IEEE80211_MODE_BYTES]; 1576 1577 memset(bands, 0, sizeof(bands)); 1578 setbit(bands, IEEE80211_MODE_11B); 1579 setbit(bands, IEEE80211_MODE_11G); 1580 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 1581 urtw_chan_2ghz, nitems(urtw_chan_2ghz), bands, 0); 1582 } 1583 1584 static void 1585 urtw_set_channel(struct ieee80211com *ic) 1586 { 1587 struct urtw_softc *sc = ic->ic_softc; 1588 uint32_t data, orig; 1589 usb_error_t error; 1590 1591 /* 1592 * if the user set a channel explicitly using ifconfig(8) this function 1593 * can be called earlier than we're expected that in some cases the 1594 * initialization would be failed if setting a channel is called before 1595 * the init have done. 1596 */ 1597 if (!(sc->sc_flags & URTW_RUNNING)) 1598 return; 1599 1600 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1601 return; 1602 1603 URTW_LOCK(sc); 1604 1605 /* 1606 * during changing th channel we need to temporarily be disable 1607 * TX. 1608 */ 1609 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1610 data = orig & ~URTW_TX_LOOPBACK_MASK; 1611 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1612 1613 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1614 if (error != 0) 1615 goto fail; 1616 usb_pause_mtx(&sc->sc_mtx, 10); 1617 urtw_write32_m(sc, URTW_TX_CONF, orig); 1618 1619 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1620 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1621 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1622 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1623 1624 fail: 1625 URTW_UNLOCK(sc); 1626 1627 sc->sc_curchan = ic->ic_curchan; 1628 1629 if (error != 0) 1630 device_printf(sc->sc_dev, "could not change the channel\n"); 1631 } 1632 1633 static void 1634 urtw_update_mcast(struct ieee80211com *ic) 1635 { 1636 1637 /* XXX do nothing? */ 1638 } 1639 1640 static int 1641 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1642 struct urtw_data *data, int prior) 1643 { 1644 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1645 struct ieee80211_key *k; 1646 const struct ieee80211_txparam *tp = ni->ni_txparms; 1647 struct ieee80211com *ic = &sc->sc_ic; 1648 struct ieee80211vap *vap = ni->ni_vap; 1649 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1650 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1651 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1652 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1653 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1654 }; 1655 struct usb_xfer *xfer; 1656 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, 1657 pkttime = 0, txdur = 0, isshort = 0, xferlen; 1658 uint16_t acktime, rtstime, ctstime; 1659 uint32_t flags; 1660 usb_error_t error; 1661 1662 URTW_ASSERT_LOCKED(sc); 1663 1664 /* 1665 * Software crypto. 1666 */ 1667 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1668 k = ieee80211_crypto_encap(ni, m0); 1669 if (k == NULL) { 1670 device_printf(sc->sc_dev, 1671 "ieee80211_crypto_encap returns NULL.\n"); 1672 /* XXX we don't expect the fragmented frames */ 1673 m_freem(m0); 1674 return (ENOBUFS); 1675 } 1676 1677 /* in case packet header moved, reset pointer */ 1678 wh = mtod(m0, struct ieee80211_frame *); 1679 } 1680 1681 if (ieee80211_radiotap_active_vap(vap)) { 1682 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1683 1684 /* XXX Are variables correct? */ 1685 tap->wt_flags = 0; 1686 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1687 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1688 1689 ieee80211_radiotap_tx(vap, m0); 1690 } 1691 1692 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT || 1693 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL || 1694 (m0->m_flags & M_EAPOL) != 0) { 1695 rate = tp->mgmtrate; 1696 } else { 1697 /* for data frames */ 1698 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1699 rate = tp->mcastrate; 1700 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1701 rate = tp->ucastrate; 1702 else 1703 rate = urtw_rtl2rate(sc->sc_currate); 1704 } 1705 1706 sc->sc_stats.txrates[sc->sc_currate]++; 1707 1708 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1709 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1710 IEEE80211_CRC_LEN, rate, 0, 0); 1711 else { 1712 acktime = urtw_compute_txtime(14, 2,0, 0); 1713 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1714 rtsenable = 1; 1715 ctsenable = 0; 1716 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1717 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1718 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1719 IEEE80211_CRC_LEN, rate, 0, isshort); 1720 rtsdur = ctstime + pkttime + acktime + 1721 3 * URTW_ASIFS_TIME; 1722 txdur = rtstime + rtsdur; 1723 } else { 1724 rtsenable = ctsenable = rtsdur = 0; 1725 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1726 IEEE80211_CRC_LEN, rate, 0, isshort); 1727 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1728 } 1729 1730 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1731 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1732 IEEE80211_CRC_LEN, rate, 0, isshort) + 1733 3 * URTW_ASIFS_TIME + 1734 2 * acktime; 1735 else 1736 dur = URTW_ASIFS_TIME + acktime; 1737 } 1738 USETW(wh->i_dur, dur); 1739 1740 xferlen = m0->m_pkthdr.len; 1741 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1742 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1743 xferlen += 1; 1744 1745 memset(data->buf, 0, URTW_TX_MAXSIZE); 1746 flags = m0->m_pkthdr.len & 0xfff; 1747 flags |= URTW_TX_FLAG_NO_ENC; 1748 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1749 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1750 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1751 (sc->sc_currate != 0)) 1752 flags |= URTW_TX_FLAG_SPLCP; 1753 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1754 flags |= URTW_TX_FLAG_MOREFRAG; 1755 1756 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1757 1758 if (sc->sc_flags & URTW_RTL8187B) { 1759 struct urtw_8187b_txhdr *tx; 1760 1761 tx = (struct urtw_8187b_txhdr *)data->buf; 1762 if (ctsenable) 1763 flags |= URTW_TX_FLAG_CTS; 1764 if (rtsenable) { 1765 flags |= URTW_TX_FLAG_RTS; 1766 flags |= (urtw_rate2rtl(11) & 0xf) << 1767 URTW_TX_FLAG_RTSRATE_SHIFT; 1768 tx->rtsdur = rtsdur; 1769 } 1770 tx->flag = htole32(flags); 1771 tx->txdur = txdur; 1772 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1773 IEEE80211_FC0_TYPE_MGT && 1774 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1775 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1776 tx->retry = 1; 1777 else 1778 tx->retry = URTW_TX_MAXRETRY; 1779 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1780 } else { 1781 struct urtw_8187l_txhdr *tx; 1782 1783 tx = (struct urtw_8187l_txhdr *)data->buf; 1784 if (rtsenable) { 1785 flags |= URTW_TX_FLAG_RTS; 1786 tx->rtsdur = rtsdur; 1787 } 1788 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT; 1789 tx->flag = htole32(flags); 1790 tx->retry = 3; /* CW minimum */ 1791 tx->retry |= 7 << 4; /* CW maximum */ 1792 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1793 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1794 } 1795 1796 data->buflen = xferlen; 1797 data->ni = ni; 1798 data->m = m0; 1799 1800 if (sc->sc_flags & URTW_RTL8187B) { 1801 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1802 case IEEE80211_FC0_TYPE_CTL: 1803 case IEEE80211_FC0_TYPE_MGT: 1804 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1805 break; 1806 default: 1807 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1808 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1809 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1810 break; 1811 } 1812 } else 1813 xfer = (prior == URTW_PRIORITY_LOW) ? 1814 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1815 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1816 1817 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1818 usbd_transfer_start(xfer); 1819 1820 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1821 if (error != 0) 1822 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1823 error); 1824 return (0); 1825 } 1826 1827 static int 1828 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1829 { 1830 struct ieee80211com *ic = vap->iv_ic; 1831 struct urtw_softc *sc = ic->ic_softc; 1832 struct urtw_vap *uvp = URTW_VAP(vap); 1833 struct ieee80211_node *ni; 1834 usb_error_t error = 0; 1835 1836 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1837 ieee80211_state_name[vap->iv_state], 1838 ieee80211_state_name[nstate]); 1839 1840 sc->sc_state = nstate; 1841 1842 IEEE80211_UNLOCK(ic); 1843 URTW_LOCK(sc); 1844 usb_callout_stop(&sc->sc_led_ch); 1845 callout_stop(&sc->sc_watchdog_ch); 1846 1847 switch (nstate) { 1848 case IEEE80211_S_INIT: 1849 case IEEE80211_S_SCAN: 1850 case IEEE80211_S_AUTH: 1851 case IEEE80211_S_ASSOC: 1852 break; 1853 case IEEE80211_S_RUN: 1854 ni = ieee80211_ref_node(vap->iv_bss); 1855 /* setting bssid. */ 1856 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1857 urtw_write16_m(sc, URTW_BSSID + 4, 1858 ((uint16_t *)ni->ni_bssid)[2]); 1859 urtw_update_msr(sc); 1860 /* XXX maybe the below would be incorrect. */ 1861 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1862 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1863 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1864 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1865 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1866 if (error != 0) 1867 device_printf(sc->sc_dev, 1868 "could not control LED (%d)\n", error); 1869 ieee80211_free_node(ni); 1870 break; 1871 default: 1872 break; 1873 } 1874 fail: 1875 URTW_UNLOCK(sc); 1876 IEEE80211_LOCK(ic); 1877 return (uvp->newstate(vap, nstate, arg)); 1878 } 1879 1880 static void 1881 urtw_watchdog(void *arg) 1882 { 1883 struct urtw_softc *sc = arg; 1884 1885 if (sc->sc_txtimer > 0) { 1886 if (--sc->sc_txtimer == 0) { 1887 device_printf(sc->sc_dev, "device timeout\n"); 1888 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1889 return; 1890 } 1891 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1892 } 1893 } 1894 1895 static void 1896 urtw_set_multi(void *arg) 1897 { 1898 /* XXX don't know how to set a device. Lack of docs. */ 1899 } 1900 1901 static usb_error_t 1902 urtw_set_rate(struct urtw_softc *sc) 1903 { 1904 int i, basic_rate, min_rr_rate, max_rr_rate; 1905 uint16_t data; 1906 usb_error_t error; 1907 1908 basic_rate = urtw_rate2rtl(48); 1909 min_rr_rate = urtw_rate2rtl(12); 1910 max_rr_rate = urtw_rate2rtl(48); 1911 1912 urtw_write8_m(sc, URTW_RESP_RATE, 1913 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1914 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1915 1916 urtw_read16_m(sc, URTW_BRSR, &data); 1917 data &= ~URTW_BRSR_MBR_8185; 1918 1919 for (i = 0; i <= basic_rate; i++) 1920 data |= (1 << i); 1921 1922 urtw_write16_m(sc, URTW_BRSR, data); 1923 fail: 1924 return (error); 1925 } 1926 1927 static uint16_t 1928 urtw_rate2rtl(uint32_t rate) 1929 { 1930 unsigned int i; 1931 1932 for (i = 0; i < nitems(urtw_ratetable); i++) { 1933 if (rate == urtw_ratetable[i].reg) 1934 return urtw_ratetable[i].val; 1935 } 1936 1937 return (3); 1938 } 1939 1940 static uint16_t 1941 urtw_rtl2rate(uint32_t rate) 1942 { 1943 unsigned int i; 1944 1945 for (i = 0; i < nitems(urtw_ratetable); i++) { 1946 if (rate == urtw_ratetable[i].val) 1947 return urtw_ratetable[i].reg; 1948 } 1949 1950 return (0); 1951 } 1952 1953 static usb_error_t 1954 urtw_update_msr(struct urtw_softc *sc) 1955 { 1956 struct ieee80211com *ic = &sc->sc_ic; 1957 uint8_t data; 1958 usb_error_t error; 1959 1960 urtw_read8_m(sc, URTW_MSR, &data); 1961 data &= ~URTW_MSR_LINK_MASK; 1962 1963 if (sc->sc_state == IEEE80211_S_RUN) { 1964 switch (ic->ic_opmode) { 1965 case IEEE80211_M_STA: 1966 case IEEE80211_M_MONITOR: 1967 data |= URTW_MSR_LINK_STA; 1968 if (sc->sc_flags & URTW_RTL8187B) 1969 data |= URTW_MSR_LINK_ENEDCA; 1970 break; 1971 case IEEE80211_M_IBSS: 1972 data |= URTW_MSR_LINK_ADHOC; 1973 break; 1974 case IEEE80211_M_HOSTAP: 1975 data |= URTW_MSR_LINK_HOSTAP; 1976 break; 1977 default: 1978 DPRINTF(sc, URTW_DEBUG_STATE, 1979 "unsupported operation mode 0x%x\n", 1980 ic->ic_opmode); 1981 error = USB_ERR_INVAL; 1982 goto fail; 1983 } 1984 } else 1985 data |= URTW_MSR_LINK_NONE; 1986 1987 urtw_write8_m(sc, URTW_MSR, data); 1988 fail: 1989 return (error); 1990 } 1991 1992 static usb_error_t 1993 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1994 { 1995 struct usb_device_request req; 1996 usb_error_t error; 1997 1998 URTW_ASSERT_LOCKED(sc); 1999 2000 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2001 req.bRequest = URTW_8187_GETREGS_REQ; 2002 USETW(req.wValue, (val & 0xff) | 0xff00); 2003 USETW(req.wIndex, (val >> 8) & 0x3); 2004 USETW(req.wLength, sizeof(uint8_t)); 2005 2006 error = urtw_do_request(sc, &req, data); 2007 return (error); 2008 } 2009 2010 static usb_error_t 2011 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2012 { 2013 struct usb_device_request req; 2014 usb_error_t error; 2015 2016 URTW_ASSERT_LOCKED(sc); 2017 2018 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2019 req.bRequest = URTW_8187_GETREGS_REQ; 2020 USETW(req.wValue, (val & 0xff) | 0xff00); 2021 USETW(req.wIndex, (val >> 8) & 0x3); 2022 USETW(req.wLength, sizeof(uint16_t)); 2023 2024 error = urtw_do_request(sc, &req, data); 2025 return (error); 2026 } 2027 2028 static usb_error_t 2029 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2030 { 2031 struct usb_device_request req; 2032 usb_error_t error; 2033 2034 URTW_ASSERT_LOCKED(sc); 2035 2036 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2037 req.bRequest = URTW_8187_GETREGS_REQ; 2038 USETW(req.wValue, (val & 0xff) | 0xff00); 2039 USETW(req.wIndex, (val >> 8) & 0x3); 2040 USETW(req.wLength, sizeof(uint32_t)); 2041 2042 error = urtw_do_request(sc, &req, data); 2043 return (error); 2044 } 2045 2046 static usb_error_t 2047 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2048 { 2049 struct usb_device_request req; 2050 2051 URTW_ASSERT_LOCKED(sc); 2052 2053 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2054 req.bRequest = URTW_8187_SETREGS_REQ; 2055 USETW(req.wValue, (val & 0xff) | 0xff00); 2056 USETW(req.wIndex, (val >> 8) & 0x3); 2057 USETW(req.wLength, sizeof(uint8_t)); 2058 2059 return (urtw_do_request(sc, &req, &data)); 2060 } 2061 2062 static usb_error_t 2063 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2064 { 2065 struct usb_device_request req; 2066 2067 URTW_ASSERT_LOCKED(sc); 2068 2069 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2070 req.bRequest = URTW_8187_SETREGS_REQ; 2071 USETW(req.wValue, (val & 0xff) | 0xff00); 2072 USETW(req.wIndex, (val >> 8) & 0x3); 2073 USETW(req.wLength, sizeof(uint16_t)); 2074 2075 return (urtw_do_request(sc, &req, &data)); 2076 } 2077 2078 static usb_error_t 2079 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2080 { 2081 struct usb_device_request req; 2082 2083 URTW_ASSERT_LOCKED(sc); 2084 2085 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2086 req.bRequest = URTW_8187_SETREGS_REQ; 2087 USETW(req.wValue, (val & 0xff) | 0xff00); 2088 USETW(req.wIndex, (val >> 8) & 0x3); 2089 USETW(req.wLength, sizeof(uint32_t)); 2090 2091 return (urtw_do_request(sc, &req, &data)); 2092 } 2093 2094 static usb_error_t 2095 urtw_get_macaddr(struct urtw_softc *sc) 2096 { 2097 struct ieee80211com *ic = &sc->sc_ic; 2098 uint32_t data; 2099 usb_error_t error; 2100 2101 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2102 if (error != 0) 2103 goto fail; 2104 ic->ic_macaddr[0] = data & 0xff; 2105 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2106 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2107 if (error != 0) 2108 goto fail; 2109 ic->ic_macaddr[2] = data & 0xff; 2110 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2111 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2112 if (error != 0) 2113 goto fail; 2114 ic->ic_macaddr[4] = data & 0xff; 2115 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2116 fail: 2117 return (error); 2118 } 2119 2120 static usb_error_t 2121 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2122 { 2123 #define URTW_READCMD_LEN 3 2124 int addrlen, i; 2125 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2126 usb_error_t error; 2127 2128 /* NB: make sure the buffer is initialized */ 2129 *data = 0; 2130 2131 /* enable EPROM programming */ 2132 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2133 DELAY(URTW_EPROM_DELAY); 2134 2135 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2136 if (error != 0) 2137 goto fail; 2138 error = urtw_eprom_ck(sc); 2139 if (error != 0) 2140 goto fail; 2141 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2142 if (error != 0) 2143 goto fail; 2144 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2145 addrlen = 8; 2146 addrstr[0] = addr & (1 << 7); 2147 addrstr[1] = addr & (1 << 6); 2148 addrstr[2] = addr & (1 << 5); 2149 addrstr[3] = addr & (1 << 4); 2150 addrstr[4] = addr & (1 << 3); 2151 addrstr[5] = addr & (1 << 2); 2152 addrstr[6] = addr & (1 << 1); 2153 addrstr[7] = addr & (1 << 0); 2154 } else { 2155 addrlen=6; 2156 addrstr[0] = addr & (1 << 5); 2157 addrstr[1] = addr & (1 << 4); 2158 addrstr[2] = addr & (1 << 3); 2159 addrstr[3] = addr & (1 << 2); 2160 addrstr[4] = addr & (1 << 1); 2161 addrstr[5] = addr & (1 << 0); 2162 } 2163 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2164 if (error != 0) 2165 goto fail; 2166 2167 error = urtw_eprom_writebit(sc, 0); 2168 if (error != 0) 2169 goto fail; 2170 2171 for (i = 0; i < 16; i++) { 2172 error = urtw_eprom_ck(sc); 2173 if (error != 0) 2174 goto fail; 2175 error = urtw_eprom_readbit(sc, &data16); 2176 if (error != 0) 2177 goto fail; 2178 2179 (*data) |= (data16 << (15 - i)); 2180 } 2181 2182 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2183 if (error != 0) 2184 goto fail; 2185 error = urtw_eprom_ck(sc); 2186 if (error != 0) 2187 goto fail; 2188 2189 /* now disable EPROM programming */ 2190 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2191 fail: 2192 return (error); 2193 #undef URTW_READCMD_LEN 2194 } 2195 2196 static usb_error_t 2197 urtw_eprom_cs(struct urtw_softc *sc, int able) 2198 { 2199 uint8_t data; 2200 usb_error_t error; 2201 2202 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2203 if (able == URTW_EPROM_ENABLE) 2204 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2205 else 2206 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2207 DELAY(URTW_EPROM_DELAY); 2208 fail: 2209 return (error); 2210 } 2211 2212 static usb_error_t 2213 urtw_eprom_ck(struct urtw_softc *sc) 2214 { 2215 uint8_t data; 2216 usb_error_t error; 2217 2218 /* masking */ 2219 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2220 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2221 DELAY(URTW_EPROM_DELAY); 2222 /* unmasking */ 2223 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2224 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2225 DELAY(URTW_EPROM_DELAY); 2226 fail: 2227 return (error); 2228 } 2229 2230 static usb_error_t 2231 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2232 { 2233 uint8_t data8; 2234 usb_error_t error; 2235 2236 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2237 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2238 DELAY(URTW_EPROM_DELAY); 2239 2240 fail: 2241 return (error); 2242 } 2243 2244 static usb_error_t 2245 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2246 { 2247 uint8_t data; 2248 usb_error_t error; 2249 2250 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2251 if (bit != 0) 2252 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2253 else 2254 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2255 DELAY(URTW_EPROM_DELAY); 2256 fail: 2257 return (error); 2258 } 2259 2260 static usb_error_t 2261 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2262 { 2263 int i = 0; 2264 usb_error_t error = 0; 2265 2266 for (i = 0; i < buflen; i++) { 2267 error = urtw_eprom_writebit(sc, buf[i]); 2268 if (error != 0) 2269 goto fail; 2270 error = urtw_eprom_ck(sc); 2271 if (error != 0) 2272 goto fail; 2273 } 2274 fail: 2275 return (error); 2276 } 2277 2278 2279 static usb_error_t 2280 urtw_get_txpwr(struct urtw_softc *sc) 2281 { 2282 int i, j; 2283 uint32_t data; 2284 usb_error_t error; 2285 2286 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2287 if (error != 0) 2288 goto fail; 2289 sc->sc_txpwr_cck_base = data & 0xf; 2290 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2291 2292 for (i = 1, j = 0; i < 6; i += 2, j++) { 2293 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2294 if (error != 0) 2295 goto fail; 2296 sc->sc_txpwr_cck[i] = data & 0xf; 2297 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2298 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2299 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2300 } 2301 for (i = 1, j = 0; i < 4; i += 2, j++) { 2302 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2303 if (error != 0) 2304 goto fail; 2305 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2306 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2307 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2308 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2309 } 2310 if (sc->sc_flags & URTW_RTL8187B) { 2311 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2312 if (error != 0) 2313 goto fail; 2314 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2315 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2316 error = urtw_eprom_read32(sc, 0x0a, &data); 2317 if (error != 0) 2318 goto fail; 2319 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2320 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2321 error = urtw_eprom_read32(sc, 0x1c, &data); 2322 if (error != 0) 2323 goto fail; 2324 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2325 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2326 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2327 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2328 } else { 2329 for (i = 1, j = 0; i < 4; i += 2, j++) { 2330 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2331 &data); 2332 if (error != 0) 2333 goto fail; 2334 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2335 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2336 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2337 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2338 } 2339 } 2340 fail: 2341 return (error); 2342 } 2343 2344 2345 static usb_error_t 2346 urtw_get_rfchip(struct urtw_softc *sc) 2347 { 2348 int ret; 2349 uint8_t data8; 2350 uint32_t data; 2351 usb_error_t error; 2352 2353 if (sc->sc_flags & URTW_RTL8187B) { 2354 urtw_read8_m(sc, 0xe1, &data8); 2355 switch (data8) { 2356 case 0: 2357 sc->sc_flags |= URTW_RTL8187B_REV_B; 2358 break; 2359 case 1: 2360 sc->sc_flags |= URTW_RTL8187B_REV_D; 2361 break; 2362 case 2: 2363 sc->sc_flags |= URTW_RTL8187B_REV_E; 2364 break; 2365 default: 2366 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2367 sc->sc_flags |= URTW_RTL8187B_REV_B; 2368 break; 2369 } 2370 } else { 2371 urtw_read32_m(sc, URTW_TX_CONF, &data); 2372 switch (data & URTW_TX_HWMASK) { 2373 case URTW_TX_R8187vD_B: 2374 sc->sc_flags |= URTW_RTL8187B; 2375 break; 2376 case URTW_TX_R8187vD: 2377 break; 2378 default: 2379 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2380 data & URTW_TX_HWMASK); 2381 break; 2382 } 2383 } 2384 2385 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2386 if (error != 0) 2387 goto fail; 2388 switch (data & 0xff) { 2389 case URTW_EPROM_RFCHIPID_RTL8225U: 2390 error = urtw_8225_isv2(sc, &ret); 2391 if (error != 0) 2392 goto fail; 2393 if (ret == 0) { 2394 sc->sc_rf_init = urtw_8225_rf_init; 2395 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2396 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2397 sc->sc_rf_stop = urtw_8225_rf_stop; 2398 } else { 2399 sc->sc_rf_init = urtw_8225v2_rf_init; 2400 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2401 sc->sc_rf_stop = urtw_8225_rf_stop; 2402 } 2403 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2404 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2405 break; 2406 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2407 sc->sc_rf_init = urtw_8225v2b_rf_init; 2408 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2409 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2410 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2411 sc->sc_rf_stop = urtw_8225_rf_stop; 2412 break; 2413 default: 2414 DPRINTF(sc, URTW_DEBUG_STATE, 2415 "unsupported RF chip %d\n", data & 0xff); 2416 error = USB_ERR_INVAL; 2417 goto fail; 2418 } 2419 2420 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2421 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2422 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2423 "rtl8225z2", 2424 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2425 (data8 == 1) ? "d" : "e") : "none"); 2426 2427 fail: 2428 return (error); 2429 } 2430 2431 2432 static usb_error_t 2433 urtw_led_init(struct urtw_softc *sc) 2434 { 2435 uint32_t rev; 2436 usb_error_t error; 2437 2438 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2439 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2440 if (error != 0) 2441 goto fail; 2442 2443 switch (rev & URTW_EPROM_CID_MASK) { 2444 case URTW_EPROM_CID_ALPHA0: 2445 sc->sc_strategy = URTW_SW_LED_MODE1; 2446 break; 2447 case URTW_EPROM_CID_SERCOMM_PS: 2448 sc->sc_strategy = URTW_SW_LED_MODE3; 2449 break; 2450 case URTW_EPROM_CID_HW_LED: 2451 sc->sc_strategy = URTW_HW_LED; 2452 break; 2453 case URTW_EPROM_CID_RSVD0: 2454 case URTW_EPROM_CID_RSVD1: 2455 default: 2456 sc->sc_strategy = URTW_SW_LED_MODE0; 2457 break; 2458 } 2459 2460 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2461 2462 fail: 2463 return (error); 2464 } 2465 2466 2467 static usb_error_t 2468 urtw_8225_rf_init(struct urtw_softc *sc) 2469 { 2470 unsigned int i; 2471 uint16_t data; 2472 usb_error_t error; 2473 2474 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2475 if (error) 2476 goto fail; 2477 2478 error = urtw_8225_usb_init(sc); 2479 if (error) 2480 goto fail; 2481 2482 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2483 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2484 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2485 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2486 2487 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2488 if (error) 2489 goto fail; 2490 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2491 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2492 if (error) 2493 goto fail; 2494 2495 error = urtw_8185_rf_pins_enable(sc); 2496 if (error) 2497 goto fail; 2498 usb_pause_mtx(&sc->sc_mtx, 1000); 2499 2500 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2501 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2502 urtw_8225_rf_part1[i].val); 2503 usb_pause_mtx(&sc->sc_mtx, 1); 2504 } 2505 usb_pause_mtx(&sc->sc_mtx, 100); 2506 urtw_8225_write(sc, 2507 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2508 usb_pause_mtx(&sc->sc_mtx, 200); 2509 urtw_8225_write(sc, 2510 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2511 usb_pause_mtx(&sc->sc_mtx, 200); 2512 urtw_8225_write(sc, 2513 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2514 2515 for (i = 0; i < 95; i++) { 2516 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2517 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2518 } 2519 2520 urtw_8225_write(sc, 2521 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2522 urtw_8225_write(sc, 2523 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2524 2525 for (i = 0; i < 128; i++) { 2526 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2527 usb_pause_mtx(&sc->sc_mtx, 1); 2528 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2529 usb_pause_mtx(&sc->sc_mtx, 1); 2530 } 2531 2532 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2533 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2534 urtw_8225_rf_part2[i].val); 2535 usb_pause_mtx(&sc->sc_mtx, 1); 2536 } 2537 2538 error = urtw_8225_setgain(sc, 4); 2539 if (error) 2540 goto fail; 2541 2542 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2543 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2544 urtw_8225_rf_part3[i].val); 2545 usb_pause_mtx(&sc->sc_mtx, 1); 2546 } 2547 2548 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2549 2550 error = urtw_8225_set_txpwrlvl(sc, 1); 2551 if (error) 2552 goto fail; 2553 2554 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2555 usb_pause_mtx(&sc->sc_mtx, 1); 2556 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2557 usb_pause_mtx(&sc->sc_mtx, 1); 2558 2559 /* TX ant A, 0x0 for B */ 2560 error = urtw_8185_tx_antenna(sc, 0x3); 2561 if (error) 2562 goto fail; 2563 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2564 2565 error = urtw_8225_rf_set_chan(sc, 1); 2566 fail: 2567 return (error); 2568 } 2569 2570 static usb_error_t 2571 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2572 { 2573 usb_error_t error = 0; 2574 2575 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2576 fail: 2577 return (error); 2578 } 2579 2580 static usb_error_t 2581 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2582 { 2583 usb_error_t error; 2584 2585 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2586 usb_pause_mtx(&sc->sc_mtx, 1); 2587 fail: 2588 return (error); 2589 } 2590 2591 static usb_error_t 2592 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2593 { 2594 2595 data = data & 0xff; 2596 return urtw_8187_write_phy(sc, addr, data); 2597 } 2598 2599 static usb_error_t 2600 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2601 { 2602 2603 data = data & 0xff; 2604 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2605 } 2606 2607 static usb_error_t 2608 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2609 { 2610 uint32_t phyw; 2611 usb_error_t error; 2612 2613 phyw = ((data << 8) | (addr | 0x80)); 2614 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2615 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2616 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2617 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2618 usb_pause_mtx(&sc->sc_mtx, 1); 2619 fail: 2620 return (error); 2621 } 2622 2623 static usb_error_t 2624 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2625 { 2626 usb_error_t error; 2627 2628 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2629 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2630 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2631 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2632 fail: 2633 return (error); 2634 } 2635 2636 static usb_error_t 2637 urtw_8225_usb_init(struct urtw_softc *sc) 2638 { 2639 uint8_t data; 2640 usb_error_t error; 2641 2642 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2643 urtw_write8_m(sc, URTW_GPIO, 0); 2644 error = urtw_read8e(sc, 0x53, &data); 2645 if (error) 2646 goto fail; 2647 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2648 if (error) 2649 goto fail; 2650 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2651 urtw_write8_m(sc, URTW_GPIO, 0x20); 2652 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2653 2654 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2655 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2656 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2657 2658 usb_pause_mtx(&sc->sc_mtx, 500); 2659 fail: 2660 return (error); 2661 } 2662 2663 static usb_error_t 2664 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2665 { 2666 uint16_t d80, d82, d84; 2667 usb_error_t error; 2668 2669 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2670 d80 &= URTW_RF_PINS_MAGIC1; 2671 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2672 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2673 d84 &= URTW_RF_PINS_MAGIC2; 2674 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2675 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2676 DELAY(10); 2677 2678 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2679 DELAY(2); 2680 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2681 DELAY(10); 2682 2683 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2684 if (error != 0) 2685 goto fail; 2686 2687 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2688 DELAY(10); 2689 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2690 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2691 usb_pause_mtx(&sc->sc_mtx, 2); 2692 fail: 2693 return (error); 2694 } 2695 2696 static usb_error_t 2697 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2698 uint16_t *data) 2699 { 2700 uint8_t buf[2]; 2701 uint16_t data16; 2702 struct usb_device_request req; 2703 usb_error_t error = 0; 2704 2705 data16 = *data; 2706 2707 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2708 req.bRequest = URTW_8187_SETREGS_REQ; 2709 USETW(req.wValue, addr); 2710 USETW(req.wIndex, index); 2711 USETW(req.wLength, sizeof(uint16_t)); 2712 buf[0] = (data16 & 0x00ff); 2713 buf[1] = (data16 & 0xff00) >> 8; 2714 2715 error = urtw_do_request(sc, &req, buf); 2716 2717 return (error); 2718 } 2719 2720 static usb_error_t 2721 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2722 { 2723 usb_error_t error; 2724 2725 error = urtw_8225_set_txpwrlvl(sc, chan); 2726 if (error) 2727 goto fail; 2728 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2729 usb_pause_mtx(&sc->sc_mtx, 10); 2730 fail: 2731 return (error); 2732 } 2733 2734 static usb_error_t 2735 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2736 { 2737 usb_error_t error; 2738 2739 if (sens < 0 || sens > 6) 2740 return -1; 2741 2742 if (sens > 4) 2743 urtw_8225_write(sc, 2744 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2745 else 2746 urtw_8225_write(sc, 2747 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2748 2749 sens = 6 - sens; 2750 error = urtw_8225_setgain(sc, sens); 2751 if (error) 2752 goto fail; 2753 2754 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2755 2756 fail: 2757 return (error); 2758 } 2759 2760 static usb_error_t 2761 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2762 { 2763 int i, idx, set; 2764 uint8_t *cck_pwltable; 2765 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2766 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2767 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2768 usb_error_t error; 2769 2770 cck_pwrlvl_max = 11; 2771 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2772 ofdm_pwrlvl_min = 10; 2773 2774 /* CCK power setting */ 2775 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2776 idx = cck_pwrlvl % 6; 2777 set = cck_pwrlvl / 6; 2778 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2779 urtw_8225_txpwr_cck; 2780 2781 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2782 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2783 for (i = 0; i < 8; i++) { 2784 urtw_8187_write_phy_cck(sc, 0x44 + i, 2785 cck_pwltable[idx * 8 + i]); 2786 } 2787 usb_pause_mtx(&sc->sc_mtx, 1); 2788 2789 /* OFDM power setting */ 2790 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2791 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2792 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2793 2794 idx = ofdm_pwrlvl % 6; 2795 set = ofdm_pwrlvl / 6; 2796 2797 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2798 if (error) 2799 goto fail; 2800 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2801 urtw_8187_write_phy_ofdm(sc, 6, 0); 2802 urtw_8187_write_phy_ofdm(sc, 8, 0); 2803 2804 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2805 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2806 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2807 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2808 usb_pause_mtx(&sc->sc_mtx, 1); 2809 fail: 2810 return (error); 2811 } 2812 2813 2814 static usb_error_t 2815 urtw_8225_rf_stop(struct urtw_softc *sc) 2816 { 2817 uint8_t data; 2818 usb_error_t error; 2819 2820 urtw_8225_write(sc, 0x4, 0x1f); 2821 2822 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2823 if (error) 2824 goto fail; 2825 2826 urtw_read8_m(sc, URTW_CONFIG3, &data); 2827 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2828 if (sc->sc_flags & URTW_RTL8187B) { 2829 urtw_write32_m(sc, URTW_ANAPARAM2, 2830 URTW_8187B_8225_ANAPARAM2_OFF); 2831 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2832 urtw_write32_m(sc, URTW_ANAPARAM3, 2833 URTW_8187B_8225_ANAPARAM3_OFF); 2834 } else { 2835 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2836 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2837 } 2838 2839 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2840 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2841 if (error) 2842 goto fail; 2843 2844 fail: 2845 return (error); 2846 } 2847 2848 static usb_error_t 2849 urtw_8225v2_rf_init(struct urtw_softc *sc) 2850 { 2851 unsigned int i; 2852 uint16_t data; 2853 uint32_t data32; 2854 usb_error_t error; 2855 2856 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2857 if (error) 2858 goto fail; 2859 2860 error = urtw_8225_usb_init(sc); 2861 if (error) 2862 goto fail; 2863 2864 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2865 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2866 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2867 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2868 2869 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2870 if (error) 2871 goto fail; 2872 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2873 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2874 if (error) 2875 goto fail; 2876 2877 error = urtw_8185_rf_pins_enable(sc); 2878 if (error) 2879 goto fail; 2880 2881 usb_pause_mtx(&sc->sc_mtx, 500); 2882 2883 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2884 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2885 urtw_8225v2_rf_part1[i].val); 2886 } 2887 usb_pause_mtx(&sc->sc_mtx, 50); 2888 2889 urtw_8225_write(sc, 2890 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2891 2892 for (i = 0; i < 95; i++) { 2893 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2894 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2895 urtw_8225v2_rxgain[i]); 2896 } 2897 2898 urtw_8225_write(sc, 2899 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2900 urtw_8225_write(sc, 2901 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2902 urtw_8225_write(sc, 2903 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2904 urtw_8225_write(sc, 2905 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2906 usb_pause_mtx(&sc->sc_mtx, 100); 2907 urtw_8225_write(sc, 2908 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2909 usb_pause_mtx(&sc->sc_mtx, 100); 2910 2911 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2912 if (error != 0) 2913 goto fail; 2914 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2915 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2916 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2917 urtw_8225_write(sc, 2918 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2919 usb_pause_mtx(&sc->sc_mtx, 100); 2920 urtw_8225_write(sc, 2921 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2922 usb_pause_mtx(&sc->sc_mtx, 50); 2923 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2924 if (error != 0) 2925 goto fail; 2926 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2927 device_printf(sc->sc_dev, "RF calibration failed\n"); 2928 } 2929 usb_pause_mtx(&sc->sc_mtx, 100); 2930 2931 urtw_8225_write(sc, 2932 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2933 for (i = 0; i < 128; i++) { 2934 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2935 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2936 } 2937 2938 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2939 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2940 urtw_8225v2_rf_part2[i].val); 2941 } 2942 2943 error = urtw_8225v2_setgain(sc, 4); 2944 if (error) 2945 goto fail; 2946 2947 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2948 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2949 urtw_8225v2_rf_part3[i].val); 2950 } 2951 2952 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2953 2954 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2955 if (error) 2956 goto fail; 2957 2958 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2959 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2960 2961 /* TX ant A, 0x0 for B */ 2962 error = urtw_8185_tx_antenna(sc, 0x3); 2963 if (error) 2964 goto fail; 2965 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2966 2967 error = urtw_8225_rf_set_chan(sc, 1); 2968 fail: 2969 return (error); 2970 } 2971 2972 static usb_error_t 2973 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2974 { 2975 usb_error_t error; 2976 2977 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2978 if (error) 2979 goto fail; 2980 2981 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2982 usb_pause_mtx(&sc->sc_mtx, 10); 2983 fail: 2984 return (error); 2985 } 2986 2987 static usb_error_t 2988 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2989 { 2990 int i; 2991 int16_t bit; 2992 uint8_t rlen = 12, wlen = 6; 2993 uint16_t o1, o2, o3, tmp; 2994 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2995 uint32_t mask = 0x80000000, value = 0; 2996 usb_error_t error; 2997 2998 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 2999 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 3000 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 3001 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 3002 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3003 o1 &= ~URTW_RF_PINS_MAGIC4; 3004 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3005 DELAY(5); 3006 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3007 DELAY(5); 3008 3009 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3010 bit = ((d2w & mask) != 0) ? 1 : 0; 3011 3012 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3013 DELAY(2); 3014 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3015 URTW_BB_HOST_BANG_CLK); 3016 DELAY(2); 3017 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3018 URTW_BB_HOST_BANG_CLK); 3019 DELAY(2); 3020 mask = mask >> 1; 3021 if (i == 2) 3022 break; 3023 bit = ((d2w & mask) != 0) ? 1 : 0; 3024 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3025 URTW_BB_HOST_BANG_CLK); 3026 DELAY(2); 3027 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3028 URTW_BB_HOST_BANG_CLK); 3029 DELAY(2); 3030 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3031 DELAY(1); 3032 } 3033 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3034 URTW_BB_HOST_BANG_CLK); 3035 DELAY(2); 3036 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3037 DELAY(2); 3038 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3039 DELAY(2); 3040 3041 mask = 0x800; 3042 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3043 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3044 o1 | URTW_BB_HOST_BANG_RW); 3045 DELAY(2); 3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3047 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3048 DELAY(2); 3049 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3050 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3051 DELAY(2); 3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3053 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3054 DELAY(2); 3055 3056 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3057 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3058 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3059 o1 | URTW_BB_HOST_BANG_RW); 3060 DELAY(2); 3061 } 3062 3063 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3064 URTW_BB_HOST_BANG_RW); 3065 DELAY(2); 3066 3067 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3068 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3069 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3070 3071 if (data != NULL) 3072 *data = value; 3073 fail: 3074 return (error); 3075 } 3076 3077 3078 static usb_error_t 3079 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3080 { 3081 int i; 3082 uint8_t *cck_pwrtable; 3083 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3084 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3085 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3086 usb_error_t error; 3087 3088 /* CCK power setting */ 3089 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3090 cck_pwrlvl += sc->sc_txpwr_cck_base; 3091 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3092 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3093 urtw_8225v2_txpwr_cck; 3094 3095 for (i = 0; i < 8; i++) 3096 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3097 3098 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3099 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3100 usb_pause_mtx(&sc->sc_mtx, 1); 3101 3102 /* OFDM power setting */ 3103 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3104 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3105 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3106 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3107 3108 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3109 if (error) 3110 goto fail; 3111 3112 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3113 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3114 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3115 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3116 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3117 3118 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3119 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3120 usb_pause_mtx(&sc->sc_mtx, 1); 3121 fail: 3122 return (error); 3123 } 3124 3125 static usb_error_t 3126 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3127 { 3128 uint8_t *gainp; 3129 usb_error_t error; 3130 3131 /* XXX for A? */ 3132 gainp = urtw_8225v2_gain_bg; 3133 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3134 usb_pause_mtx(&sc->sc_mtx, 1); 3135 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3136 usb_pause_mtx(&sc->sc_mtx, 1); 3137 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3138 usb_pause_mtx(&sc->sc_mtx, 1); 3139 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3140 usb_pause_mtx(&sc->sc_mtx, 1); 3141 fail: 3142 return (error); 3143 } 3144 3145 static usb_error_t 3146 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3147 { 3148 uint32_t data; 3149 usb_error_t error; 3150 3151 *ret = 1; 3152 3153 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3154 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3155 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3156 usb_pause_mtx(&sc->sc_mtx, 500); 3157 3158 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3159 URTW_8225_ADDR_0_DATA_MAGIC1); 3160 3161 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3162 if (error != 0) 3163 goto fail; 3164 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3165 *ret = 0; 3166 else { 3167 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3168 if (error != 0) 3169 goto fail; 3170 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3171 *ret = 0; 3172 } 3173 3174 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3175 URTW_8225_ADDR_0_DATA_MAGIC2); 3176 fail: 3177 return (error); 3178 } 3179 3180 static usb_error_t 3181 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3182 { 3183 struct ieee80211com *ic = &sc->sc_ic; 3184 unsigned int i; 3185 uint8_t data8; 3186 usb_error_t error; 3187 3188 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3189 if (error) 3190 goto fail; 3191 3192 /* 3193 * initialize extra registers on 8187 3194 */ 3195 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3196 3197 /* retry limit */ 3198 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3199 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3200 urtw_write8_m(sc, URTW_CW_CONF, data8); 3201 3202 /* TX AGC */ 3203 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3204 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3205 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3206 3207 /* Auto Rate Fallback Control */ 3208 #define URTW_ARFR 0x1e0 3209 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3210 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3211 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3212 data8 | URTW_RATE_FALLBACK_ENABLE); 3213 3214 urtw_read8_m(sc, URTW_MSR, &data8); 3215 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3216 urtw_read8_m(sc, URTW_MSR, &data8); 3217 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3218 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3219 3220 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3221 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3222 #define URTW_FEMR_FOR_8187B 0x1d4 3223 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3224 3225 /* led type */ 3226 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3227 data8 = (data8 & 0x3f) | 0x80; 3228 urtw_write8_m(sc, URTW_CONFIG1, data8); 3229 3230 /* applying MAC address again. */ 3231 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3232 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3233 3234 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3235 if (error) 3236 goto fail; 3237 3238 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3239 3240 /* 3241 * MAC configuration 3242 */ 3243 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3244 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3245 urtw_8225v2b_rf_part1[i].val); 3246 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3247 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3248 urtw_write32_m(sc, 0x1f0, 0); 3249 urtw_write32_m(sc, 0x1f4, 0); 3250 urtw_write8_m(sc, 0x1f8, 0); 3251 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3252 3253 #define URTW_RFSW_CTRL 0x272 3254 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3255 3256 /* 3257 * initialize PHY 3258 */ 3259 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3260 if (error) 3261 goto fail; 3262 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3263 urtw_write8_m(sc, URTW_CONFIG3, 3264 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3265 3266 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3267 if (error) 3268 goto fail; 3269 3270 /* setup RFE initial timing */ 3271 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3272 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3273 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3274 usb_pause_mtx(&sc->sc_mtx, 1100); 3275 3276 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3277 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3278 urtw_8225v2b_rf_part0[i].val); 3279 usb_pause_mtx(&sc->sc_mtx, 1); 3280 } 3281 urtw_8225_write(sc, 0x00, 0x01b7); 3282 3283 for (i = 0; i < 95; i++) { 3284 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3285 usb_pause_mtx(&sc->sc_mtx, 1); 3286 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3287 urtw_8225v2b_rxgain[i]); 3288 usb_pause_mtx(&sc->sc_mtx, 1); 3289 } 3290 3291 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3292 usb_pause_mtx(&sc->sc_mtx, 1); 3293 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3294 usb_pause_mtx(&sc->sc_mtx, 1); 3295 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3296 usb_pause_mtx(&sc->sc_mtx, 1); 3297 usb_pause_mtx(&sc->sc_mtx, 3000); 3298 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3299 usb_pause_mtx(&sc->sc_mtx, 2000); 3300 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3301 usb_pause_mtx(&sc->sc_mtx, 1); 3302 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3303 usb_pause_mtx(&sc->sc_mtx, 1); 3304 3305 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3306 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3307 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3308 3309 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3310 for (i = 0; i < 128; i++) { 3311 uint32_t addr, data; 3312 3313 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3314 addr = ((i + 0x80) << 8) | 0x0000008e; 3315 3316 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3317 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3318 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3319 } 3320 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3321 3322 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3323 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3324 3325 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3326 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3327 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3328 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3329 3330 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3331 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3332 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3333 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3334 3335 fail: 3336 return (error); 3337 } 3338 3339 static usb_error_t 3340 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3341 { 3342 usb_error_t error; 3343 3344 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3345 if (error) 3346 goto fail; 3347 3348 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3349 usb_pause_mtx(&sc->sc_mtx, 10); 3350 fail: 3351 return (error); 3352 } 3353 3354 static usb_error_t 3355 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3356 { 3357 int i; 3358 uint8_t *cck_pwrtable; 3359 uint8_t cck_pwrlvl_max = 15; 3360 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3361 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3362 usb_error_t error; 3363 3364 /* CCK power setting */ 3365 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3366 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3367 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3368 cck_pwrlvl += sc->sc_txpwr_cck_base; 3369 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3370 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3371 urtw_8225v2b_txpwr_cck; 3372 3373 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3374 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3375 ((cck_pwrlvl <= 11) ? 8 : 16); 3376 else 3377 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3378 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3379 3380 for (i = 0; i < 8; i++) 3381 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3382 3383 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3384 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3385 usb_pause_mtx(&sc->sc_mtx, 1); 3386 3387 /* OFDM power setting */ 3388 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3389 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3390 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3391 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3392 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3393 3394 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3395 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3396 3397 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3398 if (ofdm_pwrlvl <= 11) { 3399 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3400 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3401 } else { 3402 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3403 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3404 } 3405 } else { 3406 if (ofdm_pwrlvl <= 11) { 3407 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3408 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3409 } else if (ofdm_pwrlvl <= 17) { 3410 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3411 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3412 } else { 3413 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3414 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3415 } 3416 } 3417 usb_pause_mtx(&sc->sc_mtx, 1); 3418 fail: 3419 return (error); 3420 } 3421 3422 static usb_error_t 3423 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3424 { 3425 struct usb_device_request req; 3426 usb_error_t error; 3427 3428 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3429 req.bRequest = URTW_8187_GETREGS_REQ; 3430 USETW(req.wValue, val | 0xfe00); 3431 USETW(req.wIndex, 0); 3432 USETW(req.wLength, sizeof(uint8_t)); 3433 3434 error = urtw_do_request(sc, &req, data); 3435 return (error); 3436 } 3437 3438 static usb_error_t 3439 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3440 { 3441 struct usb_device_request req; 3442 3443 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3444 req.bRequest = URTW_8187_SETREGS_REQ; 3445 USETW(req.wValue, val | 0xfe00); 3446 USETW(req.wIndex, 0); 3447 USETW(req.wLength, sizeof(uint8_t)); 3448 3449 return (urtw_do_request(sc, &req, &data)); 3450 } 3451 3452 static usb_error_t 3453 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3454 { 3455 uint8_t data; 3456 usb_error_t error; 3457 3458 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3459 if (error) 3460 goto fail; 3461 3462 urtw_read8_m(sc, URTW_CONFIG3, &data); 3463 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3464 urtw_write32_m(sc, URTW_ANAPARAM, val); 3465 urtw_read8_m(sc, URTW_CONFIG3, &data); 3466 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3467 3468 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3469 if (error) 3470 goto fail; 3471 fail: 3472 return (error); 3473 } 3474 3475 static usb_error_t 3476 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3477 { 3478 uint8_t data; 3479 usb_error_t error; 3480 3481 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3482 if (error) 3483 goto fail; 3484 3485 urtw_read8_m(sc, URTW_CONFIG3, &data); 3486 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3487 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3488 urtw_read8_m(sc, URTW_CONFIG3, &data); 3489 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3490 3491 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3492 if (error) 3493 goto fail; 3494 fail: 3495 return (error); 3496 } 3497 3498 static usb_error_t 3499 urtw_intr_enable(struct urtw_softc *sc) 3500 { 3501 usb_error_t error; 3502 3503 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3504 fail: 3505 return (error); 3506 } 3507 3508 static usb_error_t 3509 urtw_intr_disable(struct urtw_softc *sc) 3510 { 3511 usb_error_t error; 3512 3513 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3514 fail: 3515 return (error); 3516 } 3517 3518 static usb_error_t 3519 urtw_reset(struct urtw_softc *sc) 3520 { 3521 uint8_t data; 3522 usb_error_t error; 3523 3524 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3525 if (error) 3526 goto fail; 3527 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3528 if (error) 3529 goto fail; 3530 3531 error = urtw_intr_disable(sc); 3532 if (error) 3533 goto fail; 3534 usb_pause_mtx(&sc->sc_mtx, 100); 3535 3536 error = urtw_write8e(sc, 0x18, 0x10); 3537 if (error != 0) 3538 goto fail; 3539 error = urtw_write8e(sc, 0x18, 0x11); 3540 if (error != 0) 3541 goto fail; 3542 error = urtw_write8e(sc, 0x18, 0x00); 3543 if (error != 0) 3544 goto fail; 3545 usb_pause_mtx(&sc->sc_mtx, 100); 3546 3547 urtw_read8_m(sc, URTW_CMD, &data); 3548 data = (data & 0x2) | URTW_CMD_RST; 3549 urtw_write8_m(sc, URTW_CMD, data); 3550 usb_pause_mtx(&sc->sc_mtx, 100); 3551 3552 urtw_read8_m(sc, URTW_CMD, &data); 3553 if (data & URTW_CMD_RST) { 3554 device_printf(sc->sc_dev, "reset timeout\n"); 3555 goto fail; 3556 } 3557 3558 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3559 if (error) 3560 goto fail; 3561 usb_pause_mtx(&sc->sc_mtx, 100); 3562 3563 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3564 if (error) 3565 goto fail; 3566 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3567 if (error) 3568 goto fail; 3569 fail: 3570 return (error); 3571 } 3572 3573 static usb_error_t 3574 urtw_led_ctl(struct urtw_softc *sc, int mode) 3575 { 3576 usb_error_t error = 0; 3577 3578 switch (sc->sc_strategy) { 3579 case URTW_SW_LED_MODE0: 3580 error = urtw_led_mode0(sc, mode); 3581 break; 3582 case URTW_SW_LED_MODE1: 3583 error = urtw_led_mode1(sc, mode); 3584 break; 3585 case URTW_SW_LED_MODE2: 3586 error = urtw_led_mode2(sc, mode); 3587 break; 3588 case URTW_SW_LED_MODE3: 3589 error = urtw_led_mode3(sc, mode); 3590 break; 3591 default: 3592 DPRINTF(sc, URTW_DEBUG_STATE, 3593 "unsupported LED mode %d\n", sc->sc_strategy); 3594 error = USB_ERR_INVAL; 3595 break; 3596 } 3597 3598 return (error); 3599 } 3600 3601 static usb_error_t 3602 urtw_led_mode0(struct urtw_softc *sc, int mode) 3603 { 3604 3605 switch (mode) { 3606 case URTW_LED_CTL_POWER_ON: 3607 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3608 break; 3609 case URTW_LED_CTL_TX: 3610 if (sc->sc_gpio_ledinprogress == 1) 3611 return (0); 3612 3613 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3614 sc->sc_gpio_blinktime = 2; 3615 break; 3616 case URTW_LED_CTL_LINK: 3617 sc->sc_gpio_ledstate = URTW_LED_ON; 3618 break; 3619 default: 3620 DPRINTF(sc, URTW_DEBUG_STATE, 3621 "unsupported LED mode 0x%x", mode); 3622 return (USB_ERR_INVAL); 3623 } 3624 3625 switch (sc->sc_gpio_ledstate) { 3626 case URTW_LED_ON: 3627 if (sc->sc_gpio_ledinprogress != 0) 3628 break; 3629 urtw_led_on(sc, URTW_LED_GPIO); 3630 break; 3631 case URTW_LED_BLINK_NORMAL: 3632 if (sc->sc_gpio_ledinprogress != 0) 3633 break; 3634 sc->sc_gpio_ledinprogress = 1; 3635 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3636 URTW_LED_OFF : URTW_LED_ON; 3637 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3638 break; 3639 case URTW_LED_POWER_ON_BLINK: 3640 urtw_led_on(sc, URTW_LED_GPIO); 3641 usb_pause_mtx(&sc->sc_mtx, 100); 3642 urtw_led_off(sc, URTW_LED_GPIO); 3643 break; 3644 default: 3645 DPRINTF(sc, URTW_DEBUG_STATE, 3646 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3647 return (USB_ERR_INVAL); 3648 } 3649 return (0); 3650 } 3651 3652 static usb_error_t 3653 urtw_led_mode1(struct urtw_softc *sc, int mode) 3654 { 3655 return (USB_ERR_INVAL); 3656 } 3657 3658 static usb_error_t 3659 urtw_led_mode2(struct urtw_softc *sc, int mode) 3660 { 3661 return (USB_ERR_INVAL); 3662 } 3663 3664 static usb_error_t 3665 urtw_led_mode3(struct urtw_softc *sc, int mode) 3666 { 3667 return (USB_ERR_INVAL); 3668 } 3669 3670 static usb_error_t 3671 urtw_led_on(struct urtw_softc *sc, int type) 3672 { 3673 usb_error_t error; 3674 3675 if (type == URTW_LED_GPIO) { 3676 switch (sc->sc_gpio_ledpin) { 3677 case URTW_LED_PIN_GPIO0: 3678 urtw_write8_m(sc, URTW_GPIO, 0x01); 3679 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3680 break; 3681 default: 3682 DPRINTF(sc, URTW_DEBUG_STATE, 3683 "unsupported LED PIN type 0x%x", 3684 sc->sc_gpio_ledpin); 3685 error = USB_ERR_INVAL; 3686 goto fail; 3687 } 3688 } else { 3689 DPRINTF(sc, URTW_DEBUG_STATE, 3690 "unsupported LED type 0x%x", type); 3691 error = USB_ERR_INVAL; 3692 goto fail; 3693 } 3694 3695 sc->sc_gpio_ledon = 1; 3696 fail: 3697 return (error); 3698 } 3699 3700 static usb_error_t 3701 urtw_led_off(struct urtw_softc *sc, int type) 3702 { 3703 usb_error_t error; 3704 3705 if (type == URTW_LED_GPIO) { 3706 switch (sc->sc_gpio_ledpin) { 3707 case URTW_LED_PIN_GPIO0: 3708 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3709 urtw_write8_m(sc, 3710 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3711 break; 3712 default: 3713 DPRINTF(sc, URTW_DEBUG_STATE, 3714 "unsupported LED PIN type 0x%x", 3715 sc->sc_gpio_ledpin); 3716 error = USB_ERR_INVAL; 3717 goto fail; 3718 } 3719 } else { 3720 DPRINTF(sc, URTW_DEBUG_STATE, 3721 "unsupported LED type 0x%x", type); 3722 error = USB_ERR_INVAL; 3723 goto fail; 3724 } 3725 3726 sc->sc_gpio_ledon = 0; 3727 3728 fail: 3729 return (error); 3730 } 3731 3732 static void 3733 urtw_led_ch(void *arg) 3734 { 3735 struct urtw_softc *sc = arg; 3736 struct ieee80211com *ic = &sc->sc_ic; 3737 3738 ieee80211_runtask(ic, &sc->sc_led_task); 3739 } 3740 3741 static void 3742 urtw_ledtask(void *arg, int pending) 3743 { 3744 struct urtw_softc *sc = arg; 3745 3746 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3747 DPRINTF(sc, URTW_DEBUG_STATE, 3748 "could not process a LED strategy 0x%x", 3749 sc->sc_strategy); 3750 return; 3751 } 3752 3753 URTW_LOCK(sc); 3754 urtw_led_blink(sc); 3755 URTW_UNLOCK(sc); 3756 } 3757 3758 static usb_error_t 3759 urtw_led_blink(struct urtw_softc *sc) 3760 { 3761 uint8_t ing = 0; 3762 usb_error_t error; 3763 3764 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3765 error = urtw_led_on(sc, URTW_LED_GPIO); 3766 else 3767 error = urtw_led_off(sc, URTW_LED_GPIO); 3768 sc->sc_gpio_blinktime--; 3769 if (sc->sc_gpio_blinktime == 0) 3770 ing = 1; 3771 else { 3772 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3773 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3774 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3775 ing = 1; 3776 } 3777 if (ing == 1) { 3778 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3779 sc->sc_gpio_ledon == 0) 3780 error = urtw_led_on(sc, URTW_LED_GPIO); 3781 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3782 sc->sc_gpio_ledon == 1) 3783 error = urtw_led_off(sc, URTW_LED_GPIO); 3784 3785 sc->sc_gpio_blinktime = 0; 3786 sc->sc_gpio_ledinprogress = 0; 3787 return (0); 3788 } 3789 3790 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3791 URTW_LED_ON : URTW_LED_OFF; 3792 3793 switch (sc->sc_gpio_ledstate) { 3794 case URTW_LED_BLINK_NORMAL: 3795 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3796 break; 3797 default: 3798 DPRINTF(sc, URTW_DEBUG_STATE, 3799 "unknown LED status 0x%x", 3800 sc->sc_gpio_ledstate); 3801 return (USB_ERR_INVAL); 3802 } 3803 return (0); 3804 } 3805 3806 static usb_error_t 3807 urtw_rx_enable(struct urtw_softc *sc) 3808 { 3809 uint8_t data; 3810 usb_error_t error; 3811 3812 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3813 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3814 3815 error = urtw_rx_setconf(sc); 3816 if (error != 0) 3817 goto fail; 3818 3819 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3820 urtw_read8_m(sc, URTW_CMD, &data); 3821 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3822 } 3823 fail: 3824 return (error); 3825 } 3826 3827 static usb_error_t 3828 urtw_tx_enable(struct urtw_softc *sc) 3829 { 3830 uint8_t data8; 3831 uint32_t data; 3832 usb_error_t error; 3833 3834 if (sc->sc_flags & URTW_RTL8187B) { 3835 urtw_read32_m(sc, URTW_TX_CONF, &data); 3836 data &= ~URTW_TX_LOOPBACK_MASK; 3837 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3838 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3839 data &= ~URTW_TX_SWPLCPLEN; 3840 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3841 (7 << 8) | /* short retry limit */ 3842 (7 << 0) | /* long retry limit */ 3843 (7 << 21); /* MAX TX DMA */ 3844 urtw_write32_m(sc, URTW_TX_CONF, data); 3845 3846 urtw_read8_m(sc, URTW_MSR, &data8); 3847 data8 |= URTW_MSR_LINK_ENEDCA; 3848 urtw_write8_m(sc, URTW_MSR, data8); 3849 return (error); 3850 } 3851 3852 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3853 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3854 urtw_write8_m(sc, URTW_CW_CONF, data8); 3855 3856 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3857 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3858 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3859 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3860 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3861 3862 urtw_read32_m(sc, URTW_TX_CONF, &data); 3863 data &= ~URTW_TX_LOOPBACK_MASK; 3864 data |= URTW_TX_LOOPBACK_NONE; 3865 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3866 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3867 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3868 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3869 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3870 data &= ~URTW_TX_SWPLCPLEN; 3871 data |= URTW_TX_NOICV; 3872 urtw_write32_m(sc, URTW_TX_CONF, data); 3873 3874 urtw_read8_m(sc, URTW_CMD, &data8); 3875 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3876 fail: 3877 return (error); 3878 } 3879 3880 static usb_error_t 3881 urtw_rx_setconf(struct urtw_softc *sc) 3882 { 3883 struct ieee80211com *ic = &sc->sc_ic; 3884 uint32_t data; 3885 usb_error_t error; 3886 3887 urtw_read32_m(sc, URTW_RX, &data); 3888 data = data &~ URTW_RX_FILTER_MASK; 3889 if (sc->sc_flags & URTW_RTL8187B) { 3890 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3891 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3892 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID | 3893 URTW_RX_FIFO_THRESHOLD_NONE | 3894 URTW_MAX_RX_DMA_2048 | 3895 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3896 } else { 3897 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3898 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3899 3900 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3901 data = data | URTW_RX_FILTER_ICVERR; 3902 data = data | URTW_RX_FILTER_PWR; 3903 } 3904 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3905 data = data | URTW_RX_FILTER_CRCERR; 3906 3907 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3908 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3909 data = data | URTW_RX_FILTER_ALLMAC; 3910 } else { 3911 data = data | URTW_RX_FILTER_NICMAC; 3912 data = data | URTW_RX_CHECK_BSSID; 3913 } 3914 3915 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3916 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3917 URTW_RX_AUTORESETPHY; 3918 data = data &~ URTW_MAX_RX_DMA_MASK; 3919 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3920 } 3921 3922 urtw_write32_m(sc, URTW_RX, data); 3923 fail: 3924 return (error); 3925 } 3926 3927 static struct mbuf * 3928 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3929 int8_t *nf_p) 3930 { 3931 int actlen, flen, rssi; 3932 struct ieee80211_frame *wh; 3933 struct mbuf *m, *mnew; 3934 struct urtw_softc *sc = data->sc; 3935 struct ieee80211com *ic = &sc->sc_ic; 3936 uint8_t noise = 0, rate; 3937 3938 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3939 3940 if (actlen < (int)URTW_MIN_RXBUFSZ) { 3941 counter_u64_add(ic->ic_ierrors, 1); 3942 return (NULL); 3943 } 3944 3945 if (sc->sc_flags & URTW_RTL8187B) { 3946 struct urtw_8187b_rxhdr *rx; 3947 3948 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3949 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3950 flen = le32toh(rx->flag) & 0xfff; 3951 if (flen > actlen) { 3952 counter_u64_add(ic->ic_ierrors, 1); 3953 return (NULL); 3954 } 3955 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3956 /* XXX correct? */ 3957 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3958 noise = rx->noise; 3959 } else { 3960 struct urtw_8187l_rxhdr *rx; 3961 3962 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3963 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3964 flen = le32toh(rx->flag) & 0xfff; 3965 if (flen > actlen) { 3966 counter_u64_add(ic->ic_ierrors, 1); 3967 return (NULL); 3968 } 3969 3970 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3971 /* XXX correct? */ 3972 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3973 noise = rx->noise; 3974 } 3975 3976 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3977 if (mnew == NULL) { 3978 counter_u64_add(ic->ic_ierrors, 1); 3979 return (NULL); 3980 } 3981 3982 m = data->m; 3983 data->m = mnew; 3984 data->buf = mtod(mnew, uint8_t *); 3985 3986 /* finalize mbuf */ 3987 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3988 3989 if (ieee80211_radiotap_active(ic)) { 3990 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3991 3992 /* XXX Are variables correct? */ 3993 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 3994 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3995 tap->wr_dbm_antsignal = (int8_t)rssi; 3996 } 3997 3998 wh = mtod(m, struct ieee80211_frame *); 3999 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 4000 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 4001 4002 *rssi_p = rssi; 4003 *nf_p = noise; /* XXX correct? */ 4004 4005 return (m); 4006 } 4007 4008 static void 4009 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4010 { 4011 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4012 struct ieee80211com *ic = &sc->sc_ic; 4013 struct ieee80211_frame *wh; 4014 struct ieee80211_node *ni; 4015 struct mbuf *m = NULL; 4016 struct urtw_data *data; 4017 int8_t nf = -95; 4018 int rssi = 1; 4019 4020 URTW_ASSERT_LOCKED(sc); 4021 4022 switch (USB_GET_STATE(xfer)) { 4023 case USB_ST_TRANSFERRED: 4024 data = STAILQ_FIRST(&sc->sc_rx_active); 4025 if (data == NULL) 4026 goto setup; 4027 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4028 m = urtw_rxeof(xfer, data, &rssi, &nf); 4029 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4030 /* FALLTHROUGH */ 4031 case USB_ST_SETUP: 4032 setup: 4033 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4034 if (data == NULL) { 4035 KASSERT(m == NULL, ("mbuf isn't NULL")); 4036 return; 4037 } 4038 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4039 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4040 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4041 usbd_xfer_max_len(xfer)); 4042 usbd_transfer_submit(xfer); 4043 4044 /* 4045 * To avoid LOR we should unlock our private mutex here to call 4046 * ieee80211_input() because here is at the end of a USB 4047 * callback and safe to unlock. 4048 */ 4049 URTW_UNLOCK(sc); 4050 if (m != NULL) { 4051 wh = mtod(m, struct ieee80211_frame *); 4052 ni = ieee80211_find_rxnode(ic, 4053 (struct ieee80211_frame_min *)wh); 4054 if (ni != NULL) { 4055 (void) ieee80211_input(ni, m, rssi, nf); 4056 /* node is no longer needed */ 4057 ieee80211_free_node(ni); 4058 } else 4059 (void) ieee80211_input_all(ic, m, rssi, nf); 4060 m = NULL; 4061 } 4062 URTW_LOCK(sc); 4063 break; 4064 default: 4065 /* needs it to the inactive queue due to a error. */ 4066 data = STAILQ_FIRST(&sc->sc_rx_active); 4067 if (data != NULL) { 4068 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4069 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4070 } 4071 if (error != USB_ERR_CANCELLED) { 4072 usbd_xfer_set_stall(xfer); 4073 counter_u64_add(ic->ic_ierrors, 1); 4074 goto setup; 4075 } 4076 break; 4077 } 4078 } 4079 4080 #define URTW_STATUS_TYPE_TXCLOSE 1 4081 #define URTW_STATUS_TYPE_BEACON_INTR 0 4082 4083 static void 4084 urtw_txstatus_eof(struct usb_xfer *xfer) 4085 { 4086 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4087 struct ieee80211com *ic = &sc->sc_ic; 4088 int actlen, type, pktretry, seq; 4089 uint64_t val; 4090 4091 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4092 4093 if (actlen != sizeof(uint64_t)) 4094 return; 4095 4096 val = le64toh(sc->sc_txstatus); 4097 type = (val >> 30) & 0x3; 4098 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4099 pktretry = val & 0xff; 4100 seq = (val >> 16) & 0xff; 4101 if (pktretry == URTW_TX_MAXRETRY) 4102 counter_u64_add(ic->ic_oerrors, 1); 4103 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4104 pktretry, seq); 4105 } 4106 } 4107 4108 static void 4109 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4110 { 4111 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4112 struct ieee80211com *ic = &sc->sc_ic; 4113 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4114 4115 URTW_ASSERT_LOCKED(sc); 4116 4117 switch (USB_GET_STATE(xfer)) { 4118 case USB_ST_TRANSFERRED: 4119 urtw_txstatus_eof(xfer); 4120 /* FALLTHROUGH */ 4121 case USB_ST_SETUP: 4122 setup: 4123 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4124 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4125 usbd_transfer_submit(xfer); 4126 break; 4127 default: 4128 if (error != USB_ERR_CANCELLED) { 4129 usbd_xfer_set_stall(xfer); 4130 counter_u64_add(ic->ic_ierrors, 1); 4131 goto setup; 4132 } 4133 break; 4134 } 4135 } 4136 4137 static void 4138 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4139 { 4140 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4141 4142 URTW_ASSERT_LOCKED(sc); 4143 4144 if (data->m) { 4145 /* XXX status? */ 4146 ieee80211_tx_complete(data->ni, data->m, 0); 4147 data->m = NULL; 4148 data->ni = NULL; 4149 } 4150 sc->sc_txtimer = 0; 4151 } 4152 4153 static void 4154 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4155 { 4156 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4157 struct urtw_data *data; 4158 4159 URTW_ASSERT_LOCKED(sc); 4160 4161 switch (USB_GET_STATE(xfer)) { 4162 case USB_ST_TRANSFERRED: 4163 data = STAILQ_FIRST(&sc->sc_tx_active); 4164 if (data == NULL) 4165 goto setup; 4166 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4167 urtw_txeof(xfer, data); 4168 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4169 /* FALLTHROUGH */ 4170 case USB_ST_SETUP: 4171 setup: 4172 data = STAILQ_FIRST(&sc->sc_tx_pending); 4173 if (data == NULL) { 4174 DPRINTF(sc, URTW_DEBUG_XMIT, 4175 "%s: empty pending queue\n", __func__); 4176 return; 4177 } 4178 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4179 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4180 4181 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4182 usbd_transfer_submit(xfer); 4183 4184 urtw_start(sc); 4185 break; 4186 default: 4187 data = STAILQ_FIRST(&sc->sc_tx_active); 4188 if (data == NULL) 4189 goto setup; 4190 if (data->ni != NULL) { 4191 if_inc_counter(data->ni->ni_vap->iv_ifp, 4192 IFCOUNTER_OERRORS, 1); 4193 ieee80211_free_node(data->ni); 4194 data->ni = NULL; 4195 } 4196 if (error != USB_ERR_CANCELLED) { 4197 usbd_xfer_set_stall(xfer); 4198 goto setup; 4199 } 4200 break; 4201 } 4202 } 4203 4204 static struct urtw_data * 4205 _urtw_getbuf(struct urtw_softc *sc) 4206 { 4207 struct urtw_data *bf; 4208 4209 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4210 if (bf != NULL) 4211 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4212 else 4213 bf = NULL; 4214 if (bf == NULL) 4215 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4216 "out of xmit buffers"); 4217 return (bf); 4218 } 4219 4220 static struct urtw_data * 4221 urtw_getbuf(struct urtw_softc *sc) 4222 { 4223 struct urtw_data *bf; 4224 4225 URTW_ASSERT_LOCKED(sc); 4226 4227 bf = _urtw_getbuf(sc); 4228 if (bf == NULL) 4229 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4230 return (bf); 4231 } 4232 4233 static int 4234 urtw_isbmode(uint16_t rate) 4235 { 4236 4237 return ((rate <= 22 && rate != 12 && rate != 18) || 4238 rate == 44) ? (1) : (0); 4239 } 4240 4241 static uint16_t 4242 urtw_rate2dbps(uint16_t rate) 4243 { 4244 4245 switch(rate) { 4246 case 12: 4247 case 18: 4248 case 24: 4249 case 36: 4250 case 48: 4251 case 72: 4252 case 96: 4253 case 108: 4254 return (rate * 2); 4255 default: 4256 break; 4257 } 4258 return (24); 4259 } 4260 4261 static int 4262 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4263 uint8_t ismgt, uint8_t isshort) 4264 { 4265 uint16_t ceiling, frametime, n_dbps; 4266 4267 if (urtw_isbmode(rate)) { 4268 if (ismgt || !isshort || rate == 2) 4269 frametime = (uint16_t)(144 + 48 + 4270 (framelen * 8 / (rate / 2))); 4271 else 4272 frametime = (uint16_t)(72 + 24 + 4273 (framelen * 8 / (rate / 2))); 4274 if ((framelen * 8 % (rate / 2)) != 0) 4275 frametime++; 4276 } else { 4277 n_dbps = urtw_rate2dbps(rate); 4278 ceiling = (16 + 8 * framelen + 6) / n_dbps 4279 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4280 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4281 } 4282 return (frametime); 4283 } 4284 4285 /* 4286 * Callback from the 802.11 layer to update the 4287 * slot time based on the current setting. 4288 */ 4289 static void 4290 urtw_updateslot(struct ieee80211com *ic) 4291 { 4292 struct urtw_softc *sc = ic->ic_softc; 4293 4294 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4295 } 4296 4297 static void 4298 urtw_updateslottask(void *arg, int pending) 4299 { 4300 struct urtw_softc *sc = arg; 4301 struct ieee80211com *ic = &sc->sc_ic; 4302 int error; 4303 4304 URTW_LOCK(sc); 4305 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4306 URTW_UNLOCK(sc); 4307 return; 4308 } 4309 if (sc->sc_flags & URTW_RTL8187B) { 4310 urtw_write8_m(sc, URTW_SIFS, 0x22); 4311 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4312 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4313 else 4314 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4315 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4316 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4317 } else { 4318 urtw_write8_m(sc, URTW_SIFS, 0x22); 4319 if (sc->sc_state == IEEE80211_S_ASSOC && 4320 ic->ic_flags & IEEE80211_F_SHSLOT) 4321 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4322 else 4323 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4324 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4325 urtw_write8_m(sc, URTW_DIFS, 0x14); 4326 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4327 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4328 } else { 4329 urtw_write8_m(sc, URTW_DIFS, 0x24); 4330 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4331 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4332 } 4333 } 4334 fail: 4335 URTW_UNLOCK(sc); 4336 } 4337 4338 static void 4339 urtw_sysctl_node(struct urtw_softc *sc) 4340 { 4341 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4342 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4343 struct sysctl_ctx_list *ctx; 4344 struct sysctl_oid_list *child, *parent; 4345 struct sysctl_oid *tree; 4346 struct urtw_stats *stats = &sc->sc_stats; 4347 4348 ctx = device_get_sysctl_ctx(sc->sc_dev); 4349 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4350 4351 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4352 NULL, "URTW statistics"); 4353 parent = SYSCTL_CHILDREN(tree); 4354 4355 /* Tx statistics. */ 4356 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4357 NULL, "Tx MAC statistics"); 4358 child = SYSCTL_CHILDREN(tree); 4359 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4360 "1 Mbit/s"); 4361 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4362 "2 Mbit/s"); 4363 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4364 "5.5 Mbit/s"); 4365 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4366 "6 Mbit/s"); 4367 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4368 "9 Mbit/s"); 4369 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4370 "11 Mbit/s"); 4371 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4372 "12 Mbit/s"); 4373 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4374 "18 Mbit/s"); 4375 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4376 "24 Mbit/s"); 4377 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4378 "36 Mbit/s"); 4379 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4380 "48 Mbit/s"); 4381 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4382 "54 Mbit/s"); 4383 #undef URTW_SYSCTL_STAT_ADD32 4384 } 4385 4386 static device_method_t urtw_methods[] = { 4387 DEVMETHOD(device_probe, urtw_match), 4388 DEVMETHOD(device_attach, urtw_attach), 4389 DEVMETHOD(device_detach, urtw_detach), 4390 DEVMETHOD_END 4391 }; 4392 static driver_t urtw_driver = { 4393 .name = "urtw", 4394 .methods = urtw_methods, 4395 .size = sizeof(struct urtw_softc) 4396 }; 4397 static devclass_t urtw_devclass; 4398 4399 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4400 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4401 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4402 MODULE_VERSION(urtw, 1); 4403 USB_PNP_HOST_INFO(urtw_devs); 4404