1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 #include <sys/param.h> 20 #include <sys/sockio.h> 21 #include <sys/sysctl.h> 22 #include <sys/lock.h> 23 #include <sys/mutex.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/malloc.h> 29 #include <sys/module.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kdb.h> 33 34 #include <machine/bus.h> 35 #include <machine/resource.h> 36 #include <sys/rman.h> 37 38 #include <net/if.h> 39 #include <net/if_var.h> 40 #include <net/if_arp.h> 41 #include <net/ethernet.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #ifdef INET 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_ether.h> 51 #include <netinet/ip.h> 52 #endif 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_regdomain.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include "usbdevs.h" 61 62 #include <dev/usb/wlan/if_urtwreg.h> 63 #include <dev/usb/wlan/if_urtwvar.h> 64 65 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 66 #ifdef URTW_DEBUG 67 int urtw_debug = 0; 68 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 69 "control debugging printfs"); 70 enum { 71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 77 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 80 URTW_DEBUG_ANY = 0xffffffff 81 }; 82 #define DPRINTF(sc, m, fmt, ...) do { \ 83 if (sc->sc_debug & (m)) \ 84 printf(fmt, __VA_ARGS__); \ 85 } while (0) 86 #else 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 (void) sc; \ 89 } while (0) 90 #endif 91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 93 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 94 95 /* recognized device vendors/products */ 96 #define urtw_lookup(v, p) \ 97 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 98 #define URTW_DEV_B(v,p) \ 99 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 100 #define URTW_DEV_L(v,p) \ 101 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 102 #define URTW_REV_RTL8187B 0 103 #define URTW_REV_RTL8187L 1 104 static const STRUCT_USB_HOST_ID urtw_devs[] = { 105 URTW_DEV_B(NETGEAR, WG111V3), 106 URTW_DEV_B(REALTEK, RTL8187B_0), 107 URTW_DEV_B(REALTEK, RTL8187B_1), 108 URTW_DEV_B(REALTEK, RTL8187B_2), 109 URTW_DEV_B(SITECOMEU, WL168V4), 110 URTW_DEV_L(ASUS, P5B_WIFI), 111 URTW_DEV_L(BELKIN, F5D7050E), 112 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 113 URTW_DEV_L(NETGEAR, WG111V2), 114 URTW_DEV_L(REALTEK, RTL8187), 115 URTW_DEV_L(SITECOMEU, WL168V1), 116 URTW_DEV_L(SURECOM, EP9001G2A), 117 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 118 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 119 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 120 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 121 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 122 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 124 #undef URTW_DEV_L 125 #undef URTW_DEV_B 126 }; 127 128 #define urtw_read8_m(sc, val, data) do { \ 129 error = urtw_read8_c(sc, val, data); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_write8_m(sc, val, data) do { \ 134 error = urtw_write8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_m(sc, val, data) do { \ 139 error = urtw_read16_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_read32_m(sc, val, data) do { \ 149 error = urtw_read32_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_write32_m(sc, val, data) do { \ 154 error = urtw_write32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 159 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 164 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8225_write(sc, val, data) do { \ 169 error = urtw_8225_write_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 174 struct urtw_pair { 175 uint32_t reg; 176 uint32_t val; 177 }; 178 179 static uint8_t urtw_8225_agc[] = { 180 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 181 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 182 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 183 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 184 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 185 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 186 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 187 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 188 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 189 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 192 }; 193 194 static uint8_t urtw_8225z2_agc[] = { 195 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 196 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 197 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 198 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 199 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 200 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 201 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 202 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 203 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 204 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 205 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 207 }; 208 209 static const uint8_t urtw_chan_2ghz[] = 210 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 211 212 static uint32_t urtw_8225_channel[] = { 213 0x0000, /* dummy channel 0 */ 214 0x085c, /* 1 */ 215 0x08dc, /* 2 */ 216 0x095c, /* 3 */ 217 0x09dc, /* 4 */ 218 0x0a5c, /* 5 */ 219 0x0adc, /* 6 */ 220 0x0b5c, /* 7 */ 221 0x0bdc, /* 8 */ 222 0x0c5c, /* 9 */ 223 0x0cdc, /* 10 */ 224 0x0d5c, /* 11 */ 225 0x0ddc, /* 12 */ 226 0x0e5c, /* 13 */ 227 0x0f72, /* 14 */ 228 }; 229 230 static uint8_t urtw_8225_gain[] = { 231 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 232 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 233 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 234 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 235 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 236 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 237 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 238 }; 239 240 static struct urtw_pair urtw_8225_rf_part1[] = { 241 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 242 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 243 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 244 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 245 }; 246 247 static struct urtw_pair urtw_8225_rf_part2[] = { 248 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 249 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 250 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 251 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 252 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 253 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 254 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 255 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 256 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 257 { 0x27, 0x88 } 258 }; 259 260 static struct urtw_pair urtw_8225_rf_part3[] = { 261 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 262 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 263 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 264 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 265 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 266 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 267 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 268 }; 269 270 static uint16_t urtw_8225_rxgain[] = { 271 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 272 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 273 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 274 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 275 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 276 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 277 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 278 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 279 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 280 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 281 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 282 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 283 }; 284 285 static uint8_t urtw_8225_threshold[] = { 286 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 287 }; 288 289 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 290 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 291 }; 292 293 static uint8_t urtw_8225_txpwr_cck[] = { 294 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 295 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 296 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 297 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 298 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 299 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 300 }; 301 302 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 303 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 304 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 305 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 306 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 307 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 308 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 309 }; 310 311 static uint8_t urtw_8225_txpwr_ofdm[]={ 312 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 313 }; 314 315 static uint8_t urtw_8225v2_gain_bg[]={ 316 0x23, 0x15, 0xa5, /* -82-1dbm */ 317 0x23, 0x15, 0xb5, /* -82-2dbm */ 318 0x23, 0x15, 0xc5, /* -82-3dbm */ 319 0x33, 0x15, 0xc5, /* -78dbm */ 320 0x43, 0x15, 0xc5, /* -74dbm */ 321 0x53, 0x15, 0xc5, /* -70dbm */ 322 0x63, 0x15, 0xc5, /* -66dbm */ 323 }; 324 325 static struct urtw_pair urtw_8225v2_rf_part1[] = { 326 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 327 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 328 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 329 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 330 }; 331 332 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 333 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 334 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 335 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 336 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 337 }; 338 339 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 340 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 341 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 342 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 343 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 344 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 345 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 346 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 347 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 348 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 349 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 350 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 351 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 352 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 353 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 354 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 355 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 356 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 357 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 358 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 359 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 360 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 361 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 362 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 363 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 364 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 365 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 366 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 367 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 368 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 369 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 370 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 371 }; 372 373 static struct urtw_pair urtw_8225v2_rf_part2[] = { 374 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 375 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 376 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 377 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 378 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 379 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 380 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 381 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 382 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 383 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 384 }; 385 386 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 387 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 388 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 389 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 390 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 391 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 392 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 393 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 394 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 395 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 396 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 397 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 398 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 399 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 400 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 401 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 402 }; 403 404 static struct urtw_pair urtw_8225v2_rf_part3[] = { 405 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 406 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 407 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 408 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 409 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 410 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 411 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 412 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 413 }; 414 415 static uint16_t urtw_8225v2_rxgain[] = { 416 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 417 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 418 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 419 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 420 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 421 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 422 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 423 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 424 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 425 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 426 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 427 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 428 }; 429 430 static uint16_t urtw_8225v2b_rxgain[] = { 431 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 432 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 433 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 434 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 435 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 436 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 437 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 438 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 439 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 440 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 441 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 442 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 443 }; 444 445 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 446 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 447 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 448 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 449 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 450 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 451 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 452 }; 453 454 static uint8_t urtw_8225v2_txpwr_cck[] = { 455 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 456 }; 457 458 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 459 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 460 }; 461 462 static uint8_t urtw_8225v2b_txpwr_cck[] = { 463 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 464 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 465 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 466 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 467 }; 468 469 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 470 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 471 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 472 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 473 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 474 }; 475 476 static struct urtw_pair urtw_ratetable[] = { 477 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 478 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 479 { 96, 10 }, { 108, 11 } 480 }; 481 482 #if 0 483 static const uint8_t urtw_8187b_reg_table[][3] = { 484 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 485 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 486 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 487 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 488 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 489 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 490 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 491 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 492 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 493 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 494 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 495 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 496 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 497 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 498 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 499 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 500 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 501 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 502 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 503 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 504 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 505 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 506 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 507 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 508 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 509 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 510 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 511 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 512 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 513 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 514 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 515 }; 516 #endif 517 518 static usb_callback_t urtw_bulk_rx_callback; 519 static usb_callback_t urtw_bulk_tx_callback; 520 static usb_callback_t urtw_bulk_tx_status_callback; 521 522 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 523 [URTW_8187B_BULK_RX] = { 524 .type = UE_BULK, 525 .endpoint = 0x83, 526 .direction = UE_DIR_IN, 527 .bufsize = MCLBYTES, 528 .flags = { 529 .ext_buffer = 1, 530 .pipe_bof = 1, 531 .short_xfer_ok = 1 532 }, 533 .callback = urtw_bulk_rx_callback 534 }, 535 [URTW_8187B_BULK_TX_STATUS] = { 536 .type = UE_BULK, 537 .endpoint = 0x89, 538 .direction = UE_DIR_IN, 539 .bufsize = sizeof(uint64_t), 540 .flags = { 541 .pipe_bof = 1, 542 .short_xfer_ok = 1 543 }, 544 .callback = urtw_bulk_tx_status_callback 545 }, 546 [URTW_8187B_BULK_TX_BE] = { 547 .type = UE_BULK, 548 .endpoint = URTW_8187B_TXPIPE_BE, 549 .direction = UE_DIR_OUT, 550 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 551 .flags = { 552 .force_short_xfer = 1, 553 .pipe_bof = 1, 554 }, 555 .callback = urtw_bulk_tx_callback, 556 .timeout = URTW_DATA_TIMEOUT 557 }, 558 [URTW_8187B_BULK_TX_BK] = { 559 .type = UE_BULK, 560 .endpoint = URTW_8187B_TXPIPE_BK, 561 .direction = UE_DIR_OUT, 562 .bufsize = URTW_TX_MAXSIZE, 563 .flags = { 564 .ext_buffer = 1, 565 .force_short_xfer = 1, 566 .pipe_bof = 1, 567 }, 568 .callback = urtw_bulk_tx_callback, 569 .timeout = URTW_DATA_TIMEOUT 570 }, 571 [URTW_8187B_BULK_TX_VI] = { 572 .type = UE_BULK, 573 .endpoint = URTW_8187B_TXPIPE_VI, 574 .direction = UE_DIR_OUT, 575 .bufsize = URTW_TX_MAXSIZE, 576 .flags = { 577 .ext_buffer = 1, 578 .force_short_xfer = 1, 579 .pipe_bof = 1, 580 }, 581 .callback = urtw_bulk_tx_callback, 582 .timeout = URTW_DATA_TIMEOUT 583 }, 584 [URTW_8187B_BULK_TX_VO] = { 585 .type = UE_BULK, 586 .endpoint = URTW_8187B_TXPIPE_VO, 587 .direction = UE_DIR_OUT, 588 .bufsize = URTW_TX_MAXSIZE, 589 .flags = { 590 .ext_buffer = 1, 591 .force_short_xfer = 1, 592 .pipe_bof = 1, 593 }, 594 .callback = urtw_bulk_tx_callback, 595 .timeout = URTW_DATA_TIMEOUT 596 }, 597 [URTW_8187B_BULK_TX_EP12] = { 598 .type = UE_BULK, 599 .endpoint = 0xc, 600 .direction = UE_DIR_OUT, 601 .bufsize = URTW_TX_MAXSIZE, 602 .flags = { 603 .ext_buffer = 1, 604 .force_short_xfer = 1, 605 .pipe_bof = 1, 606 }, 607 .callback = urtw_bulk_tx_callback, 608 .timeout = URTW_DATA_TIMEOUT 609 } 610 }; 611 612 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 613 [URTW_8187L_BULK_RX] = { 614 .type = UE_BULK, 615 .endpoint = 0x81, 616 .direction = UE_DIR_IN, 617 .bufsize = MCLBYTES, 618 .flags = { 619 .ext_buffer = 1, 620 .pipe_bof = 1, 621 .short_xfer_ok = 1 622 }, 623 .callback = urtw_bulk_rx_callback 624 }, 625 [URTW_8187L_BULK_TX_LOW] = { 626 .type = UE_BULK, 627 .endpoint = 0x2, 628 .direction = UE_DIR_OUT, 629 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 630 .flags = { 631 .force_short_xfer = 1, 632 .pipe_bof = 1, 633 }, 634 .callback = urtw_bulk_tx_callback, 635 .timeout = URTW_DATA_TIMEOUT 636 }, 637 [URTW_8187L_BULK_TX_NORMAL] = { 638 .type = UE_BULK, 639 .endpoint = 0x3, 640 .direction = UE_DIR_OUT, 641 .bufsize = URTW_TX_MAXSIZE, 642 .flags = { 643 .ext_buffer = 1, 644 .force_short_xfer = 1, 645 .pipe_bof = 1, 646 }, 647 .callback = urtw_bulk_tx_callback, 648 .timeout = URTW_DATA_TIMEOUT 649 }, 650 }; 651 652 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 653 const char [IFNAMSIZ], int, enum ieee80211_opmode, 654 int, const uint8_t [IEEE80211_ADDR_LEN], 655 const uint8_t [IEEE80211_ADDR_LEN]); 656 static void urtw_vap_delete(struct ieee80211vap *); 657 static void urtw_init(struct urtw_softc *); 658 static void urtw_stop(struct urtw_softc *); 659 static void urtw_parent(struct ieee80211com *); 660 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 661 static void urtw_start(struct urtw_softc *); 662 static int urtw_alloc_rx_data_list(struct urtw_softc *); 663 static int urtw_alloc_tx_data_list(struct urtw_softc *); 664 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 665 const struct ieee80211_bpf_params *); 666 static void urtw_scan_start(struct ieee80211com *); 667 static void urtw_scan_end(struct ieee80211com *); 668 static void urtw_getradiocaps(struct ieee80211com *, int, int *, 669 struct ieee80211_channel[]); 670 static void urtw_set_channel(struct ieee80211com *); 671 static void urtw_update_mcast(struct ieee80211com *); 672 static int urtw_tx_start(struct urtw_softc *, 673 struct ieee80211_node *, struct mbuf *, 674 struct urtw_data *, int); 675 static int urtw_newstate(struct ieee80211vap *, 676 enum ieee80211_state, int); 677 static void urtw_led_ch(void *); 678 static void urtw_ledtask(void *, int); 679 static void urtw_watchdog(void *); 680 static void urtw_set_multi(void *); 681 static int urtw_isbmode(uint16_t); 682 static uint16_t urtw_rate2rtl(uint32_t); 683 static uint16_t urtw_rtl2rate(uint32_t); 684 static usb_error_t urtw_set_rate(struct urtw_softc *); 685 static usb_error_t urtw_update_msr(struct urtw_softc *); 686 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 687 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 688 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 689 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 690 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 691 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 692 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 693 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 694 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 695 int); 696 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 697 uint32_t *); 698 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 699 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 700 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 701 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 702 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 703 static usb_error_t urtw_led_init(struct urtw_softc *); 704 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 705 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 706 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 707 uint32_t); 708 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 709 uint8_t, uint32_t); 710 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 711 uint32_t); 712 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 713 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 714 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 715 uint16_t); 716 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 717 uint16_t *); 718 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 719 uint32_t *); 720 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 721 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 722 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 723 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 724 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 725 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 726 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 727 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 728 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 729 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 730 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 731 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 732 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 733 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 734 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 735 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 736 static usb_error_t urtw_intr_enable(struct urtw_softc *); 737 static usb_error_t urtw_intr_disable(struct urtw_softc *); 738 static usb_error_t urtw_reset(struct urtw_softc *); 739 static usb_error_t urtw_led_on(struct urtw_softc *, int); 740 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 741 static usb_error_t urtw_led_blink(struct urtw_softc *); 742 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 743 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 744 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 745 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 746 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 747 static usb_error_t urtw_rx_enable(struct urtw_softc *); 748 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 749 static void urtw_free_tx_data_list(struct urtw_softc *); 750 static void urtw_free_rx_data_list(struct urtw_softc *); 751 static void urtw_free_data_list(struct urtw_softc *, 752 struct urtw_data data[], int, int); 753 static usb_error_t urtw_adapter_start(struct urtw_softc *); 754 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 755 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 756 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 757 static usb_error_t urtw_do_request(struct urtw_softc *, 758 struct usb_device_request *, void *); 759 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 760 static usb_error_t urtw_led_off(struct urtw_softc *, int); 761 static void urtw_abort_xfers(struct urtw_softc *); 762 static struct urtw_data * 763 urtw_getbuf(struct urtw_softc *sc); 764 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 765 uint8_t); 766 static void urtw_updateslot(struct ieee80211com *); 767 static void urtw_updateslottask(void *, int); 768 static void urtw_sysctl_node(struct urtw_softc *); 769 770 static int 771 urtw_match(device_t dev) 772 { 773 struct usb_attach_arg *uaa = device_get_ivars(dev); 774 775 if (uaa->usb_mode != USB_MODE_HOST) 776 return (ENXIO); 777 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 778 return (ENXIO); 779 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 780 return (ENXIO); 781 782 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 783 } 784 785 static int 786 urtw_attach(device_t dev) 787 { 788 const struct usb_config *setup_start; 789 int ret = ENXIO; 790 struct urtw_softc *sc = device_get_softc(dev); 791 struct usb_attach_arg *uaa = device_get_ivars(dev); 792 struct ieee80211com *ic = &sc->sc_ic; 793 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 794 uint16_t n_setup; 795 uint32_t data; 796 usb_error_t error; 797 798 device_set_usb_desc(dev); 799 800 sc->sc_dev = dev; 801 sc->sc_udev = uaa->device; 802 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 803 sc->sc_flags |= URTW_RTL8187B; 804 #ifdef URTW_DEBUG 805 sc->sc_debug = urtw_debug; 806 #endif 807 808 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 809 MTX_DEF); 810 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 811 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 812 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 813 callout_init(&sc->sc_watchdog_ch, 0); 814 mbufq_init(&sc->sc_snd, ifqmaxlen); 815 816 if (sc->sc_flags & URTW_RTL8187B) { 817 setup_start = urtw_8187b_usbconfig; 818 n_setup = URTW_8187B_N_XFERS; 819 } else { 820 setup_start = urtw_8187l_usbconfig; 821 n_setup = URTW_8187L_N_XFERS; 822 } 823 824 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 825 setup_start, n_setup, sc, &sc->sc_mtx); 826 if (error) { 827 device_printf(dev, "could not allocate USB transfers, " 828 "err=%s\n", usbd_errstr(error)); 829 ret = ENXIO; 830 goto fail0; 831 } 832 833 if (sc->sc_flags & URTW_RTL8187B) { 834 sc->sc_tx_dma_buf = 835 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 836 URTW_8187B_BULK_TX_BE], 0); 837 } else { 838 sc->sc_tx_dma_buf = 839 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 840 URTW_8187L_BULK_TX_LOW], 0); 841 } 842 843 URTW_LOCK(sc); 844 845 urtw_read32_m(sc, URTW_RX, &data); 846 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 847 URTW_EEPROM_93C46; 848 849 error = urtw_get_rfchip(sc); 850 if (error != 0) 851 goto fail; 852 error = urtw_get_macaddr(sc); 853 if (error != 0) 854 goto fail; 855 error = urtw_get_txpwr(sc); 856 if (error != 0) 857 goto fail; 858 error = urtw_led_init(sc); 859 if (error != 0) 860 goto fail; 861 862 URTW_UNLOCK(sc); 863 864 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 865 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 866 sc->sc_currate = 3; 867 sc->sc_preamble_mode = urtw_preamble_mode; 868 869 ic->ic_softc = sc; 870 ic->ic_name = device_get_nameunit(dev); 871 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 872 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 873 874 /* set device capabilities */ 875 ic->ic_caps = 876 IEEE80211_C_STA | /* station mode */ 877 IEEE80211_C_MONITOR | /* monitor mode supported */ 878 IEEE80211_C_TXPMGT | /* tx power management */ 879 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 880 IEEE80211_C_SHSLOT | /* short slot time supported */ 881 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 882 IEEE80211_C_WPA; /* 802.11i */ 883 884 /* XXX TODO: setup regdomain if URTW_EPROM_CHANPLAN_BY_HW bit is set.*/ 885 886 urtw_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 887 ic->ic_channels); 888 889 ieee80211_ifattach(ic); 890 ic->ic_raw_xmit = urtw_raw_xmit; 891 ic->ic_scan_start = urtw_scan_start; 892 ic->ic_scan_end = urtw_scan_end; 893 ic->ic_getradiocaps = urtw_getradiocaps; 894 ic->ic_set_channel = urtw_set_channel; 895 ic->ic_updateslot = urtw_updateslot; 896 ic->ic_vap_create = urtw_vap_create; 897 ic->ic_vap_delete = urtw_vap_delete; 898 ic->ic_update_mcast = urtw_update_mcast; 899 ic->ic_parent = urtw_parent; 900 ic->ic_transmit = urtw_transmit; 901 902 ieee80211_radiotap_attach(ic, 903 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 904 URTW_TX_RADIOTAP_PRESENT, 905 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 906 URTW_RX_RADIOTAP_PRESENT); 907 908 urtw_sysctl_node(sc); 909 910 if (bootverbose) 911 ieee80211_announce(ic); 912 return (0); 913 914 fail: 915 URTW_UNLOCK(sc); 916 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 917 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 918 fail0: 919 return (ret); 920 } 921 922 static int 923 urtw_detach(device_t dev) 924 { 925 struct urtw_softc *sc = device_get_softc(dev); 926 struct ieee80211com *ic = &sc->sc_ic; 927 unsigned int x; 928 unsigned int n_xfers; 929 930 /* Prevent further ioctls */ 931 URTW_LOCK(sc); 932 sc->sc_flags |= URTW_DETACHED; 933 urtw_stop(sc); 934 URTW_UNLOCK(sc); 935 936 ieee80211_draintask(ic, &sc->sc_updateslot_task); 937 ieee80211_draintask(ic, &sc->sc_led_task); 938 939 usb_callout_drain(&sc->sc_led_ch); 940 callout_drain(&sc->sc_watchdog_ch); 941 942 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 943 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 944 945 /* prevent further allocations from RX/TX data lists */ 946 URTW_LOCK(sc); 947 STAILQ_INIT(&sc->sc_tx_active); 948 STAILQ_INIT(&sc->sc_tx_inactive); 949 STAILQ_INIT(&sc->sc_tx_pending); 950 951 STAILQ_INIT(&sc->sc_rx_active); 952 STAILQ_INIT(&sc->sc_rx_inactive); 953 URTW_UNLOCK(sc); 954 955 /* drain USB transfers */ 956 for (x = 0; x != n_xfers; x++) 957 usbd_transfer_drain(sc->sc_xfer[x]); 958 959 /* free data buffers */ 960 URTW_LOCK(sc); 961 urtw_free_tx_data_list(sc); 962 urtw_free_rx_data_list(sc); 963 URTW_UNLOCK(sc); 964 965 /* free USB transfers and some data buffers */ 966 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 967 968 ieee80211_ifdetach(ic); 969 mbufq_drain(&sc->sc_snd); 970 mtx_destroy(&sc->sc_mtx); 971 return (0); 972 } 973 974 static void 975 urtw_free_tx_data_list(struct urtw_softc *sc) 976 { 977 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 978 } 979 980 static void 981 urtw_free_rx_data_list(struct urtw_softc *sc) 982 { 983 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 984 } 985 986 static void 987 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 988 int fillmbuf) 989 { 990 int i; 991 992 for (i = 0; i < ndata; i++) { 993 struct urtw_data *dp = &data[i]; 994 995 if (fillmbuf == 1) { 996 if (dp->m != NULL) { 997 m_freem(dp->m); 998 dp->m = NULL; 999 dp->buf = NULL; 1000 } 1001 } else { 1002 dp->buf = NULL; 1003 } 1004 if (dp->ni != NULL) { 1005 ieee80211_free_node(dp->ni); 1006 dp->ni = NULL; 1007 } 1008 } 1009 } 1010 1011 static struct ieee80211vap * 1012 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1013 enum ieee80211_opmode opmode, int flags, 1014 const uint8_t bssid[IEEE80211_ADDR_LEN], 1015 const uint8_t mac[IEEE80211_ADDR_LEN]) 1016 { 1017 struct urtw_vap *uvp; 1018 struct ieee80211vap *vap; 1019 1020 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1021 return (NULL); 1022 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1023 vap = &uvp->vap; 1024 /* enable s/w bmiss handling for sta mode */ 1025 1026 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1027 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1028 /* out of memory */ 1029 free(uvp, M_80211_VAP); 1030 return (NULL); 1031 } 1032 1033 /* override state transition machine */ 1034 uvp->newstate = vap->iv_newstate; 1035 vap->iv_newstate = urtw_newstate; 1036 1037 /* complete setup */ 1038 ieee80211_vap_attach(vap, ieee80211_media_change, 1039 ieee80211_media_status, mac); 1040 ic->ic_opmode = opmode; 1041 return (vap); 1042 } 1043 1044 static void 1045 urtw_vap_delete(struct ieee80211vap *vap) 1046 { 1047 struct urtw_vap *uvp = URTW_VAP(vap); 1048 1049 ieee80211_vap_detach(vap); 1050 free(uvp, M_80211_VAP); 1051 } 1052 1053 static void 1054 urtw_init(struct urtw_softc *sc) 1055 { 1056 usb_error_t error; 1057 int ret; 1058 1059 URTW_ASSERT_LOCKED(sc); 1060 1061 if (sc->sc_flags & URTW_RUNNING) 1062 urtw_stop(sc); 1063 1064 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1065 urtw_adapter_start(sc); 1066 if (error != 0) 1067 goto fail; 1068 1069 /* reset softc variables */ 1070 sc->sc_txtimer = 0; 1071 1072 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1073 ret = urtw_alloc_rx_data_list(sc); 1074 if (ret != 0) 1075 goto fail; 1076 ret = urtw_alloc_tx_data_list(sc); 1077 if (ret != 0) 1078 goto fail; 1079 sc->sc_flags |= URTW_INIT_ONCE; 1080 } 1081 1082 error = urtw_rx_enable(sc); 1083 if (error != 0) 1084 goto fail; 1085 error = urtw_tx_enable(sc); 1086 if (error != 0) 1087 goto fail; 1088 1089 if (sc->sc_flags & URTW_RTL8187B) 1090 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1091 1092 sc->sc_flags |= URTW_RUNNING; 1093 1094 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1095 fail: 1096 return; 1097 } 1098 1099 static usb_error_t 1100 urtw_adapter_start_b(struct urtw_softc *sc) 1101 { 1102 uint8_t data8; 1103 usb_error_t error; 1104 1105 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1106 if (error) 1107 goto fail; 1108 1109 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1110 urtw_write8_m(sc, URTW_CONFIG3, 1111 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1112 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1113 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1114 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1115 1116 urtw_write8_m(sc, 0x61, 0x10); 1117 urtw_read8_m(sc, 0x62, &data8); 1118 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1119 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1120 1121 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1122 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1123 urtw_write8_m(sc, URTW_CONFIG3, data8); 1124 1125 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1126 if (error) 1127 goto fail; 1128 1129 error = urtw_8187b_cmd_reset(sc); 1130 if (error) 1131 goto fail; 1132 1133 error = sc->sc_rf_init(sc); 1134 if (error != 0) 1135 goto fail; 1136 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1137 1138 /* fix RTL8187B RX stall */ 1139 error = urtw_intr_enable(sc); 1140 if (error) 1141 goto fail; 1142 1143 error = urtw_write8e(sc, 0x41, 0xf4); 1144 if (error) 1145 goto fail; 1146 error = urtw_write8e(sc, 0x40, 0x00); 1147 if (error) 1148 goto fail; 1149 error = urtw_write8e(sc, 0x42, 0x00); 1150 if (error) 1151 goto fail; 1152 error = urtw_write8e(sc, 0x42, 0x01); 1153 if (error) 1154 goto fail; 1155 error = urtw_write8e(sc, 0x40, 0x0f); 1156 if (error) 1157 goto fail; 1158 error = urtw_write8e(sc, 0x42, 0x00); 1159 if (error) 1160 goto fail; 1161 error = urtw_write8e(sc, 0x42, 0x01); 1162 if (error) 1163 goto fail; 1164 1165 urtw_read8_m(sc, 0xdb, &data8); 1166 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1167 urtw_write16_m(sc, 0x372, 0x59fa); 1168 urtw_write16_m(sc, 0x374, 0x59d2); 1169 urtw_write16_m(sc, 0x376, 0x59d2); 1170 urtw_write16_m(sc, 0x378, 0x19fa); 1171 urtw_write16_m(sc, 0x37a, 0x19fa); 1172 urtw_write16_m(sc, 0x37c, 0x00d0); 1173 urtw_write8_m(sc, 0x61, 0); 1174 1175 urtw_write8_m(sc, 0x180, 0x0f); 1176 urtw_write8_m(sc, 0x183, 0x03); 1177 urtw_write8_m(sc, 0xda, 0x10); 1178 urtw_write8_m(sc, 0x24d, 0x08); 1179 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1180 1181 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1182 fail: 1183 return (error); 1184 } 1185 1186 static usb_error_t 1187 urtw_adapter_start(struct urtw_softc *sc) 1188 { 1189 struct ieee80211com *ic = &sc->sc_ic; 1190 usb_error_t error; 1191 1192 error = urtw_reset(sc); 1193 if (error) 1194 goto fail; 1195 1196 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1197 urtw_write8_m(sc, URTW_GPIO, 0); 1198 1199 /* for led */ 1200 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1201 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1202 if (error != 0) 1203 goto fail; 1204 1205 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1206 if (error) 1207 goto fail; 1208 /* applying MAC address again. */ 1209 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1210 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1211 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1212 if (error) 1213 goto fail; 1214 1215 error = urtw_update_msr(sc); 1216 if (error) 1217 goto fail; 1218 1219 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1220 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1221 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1222 error = urtw_set_rate(sc); 1223 if (error != 0) 1224 goto fail; 1225 1226 error = sc->sc_rf_init(sc); 1227 if (error != 0) 1228 goto fail; 1229 if (sc->sc_rf_set_sens != NULL) 1230 sc->sc_rf_set_sens(sc, sc->sc_sens); 1231 1232 /* XXX correct? to call write16 */ 1233 urtw_write16_m(sc, URTW_PSR, 1); 1234 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1235 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1236 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1237 /* XXX correct? to call write16 */ 1238 urtw_write16_m(sc, URTW_PSR, 0); 1239 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1240 1241 error = urtw_intr_enable(sc); 1242 if (error != 0) 1243 goto fail; 1244 1245 fail: 1246 return (error); 1247 } 1248 1249 static usb_error_t 1250 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1251 { 1252 uint8_t data; 1253 usb_error_t error; 1254 1255 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1256 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1257 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1258 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1259 fail: 1260 return (error); 1261 } 1262 1263 static usb_error_t 1264 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1265 { 1266 int i; 1267 uint8_t data8; 1268 usb_error_t error; 1269 1270 /* XXX the code can be duplicate with urtw_reset(). */ 1271 urtw_read8_m(sc, URTW_CMD, &data8); 1272 data8 = (data8 & 0x2) | URTW_CMD_RST; 1273 urtw_write8_m(sc, URTW_CMD, data8); 1274 1275 for (i = 0; i < 20; i++) { 1276 usb_pause_mtx(&sc->sc_mtx, 2); 1277 urtw_read8_m(sc, URTW_CMD, &data8); 1278 if (!(data8 & URTW_CMD_RST)) 1279 break; 1280 } 1281 if (i >= 20) { 1282 device_printf(sc->sc_dev, "reset timeout\n"); 1283 goto fail; 1284 } 1285 fail: 1286 return (error); 1287 } 1288 1289 static usb_error_t 1290 urtw_do_request(struct urtw_softc *sc, 1291 struct usb_device_request *req, void *data) 1292 { 1293 usb_error_t err; 1294 int ntries = 10; 1295 1296 URTW_ASSERT_LOCKED(sc); 1297 1298 while (ntries--) { 1299 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1300 req, data, 0, NULL, 250 /* ms */); 1301 if (err == 0) 1302 break; 1303 1304 DPRINTF(sc, URTW_DEBUG_INIT, 1305 "Control request failed, %s (retrying)\n", 1306 usbd_errstr(err)); 1307 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1308 } 1309 return (err); 1310 } 1311 1312 static void 1313 urtw_stop(struct urtw_softc *sc) 1314 { 1315 uint8_t data8; 1316 usb_error_t error; 1317 1318 URTW_ASSERT_LOCKED(sc); 1319 1320 sc->sc_flags &= ~URTW_RUNNING; 1321 1322 error = urtw_intr_disable(sc); 1323 if (error) 1324 goto fail; 1325 urtw_read8_m(sc, URTW_CMD, &data8); 1326 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1327 urtw_write8_m(sc, URTW_CMD, data8); 1328 1329 error = sc->sc_rf_stop(sc); 1330 if (error != 0) 1331 goto fail; 1332 1333 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1334 if (error) 1335 goto fail; 1336 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1337 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1338 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1339 if (error) 1340 goto fail; 1341 fail: 1342 if (error) 1343 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1344 usbd_errstr(error)); 1345 1346 usb_callout_stop(&sc->sc_led_ch); 1347 callout_stop(&sc->sc_watchdog_ch); 1348 1349 urtw_abort_xfers(sc); 1350 } 1351 1352 static void 1353 urtw_abort_xfers(struct urtw_softc *sc) 1354 { 1355 int i, max; 1356 1357 URTW_ASSERT_LOCKED(sc); 1358 1359 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1360 URTW_8187L_N_XFERS; 1361 1362 /* abort any pending transfers */ 1363 for (i = 0; i < max; i++) 1364 usbd_transfer_stop(sc->sc_xfer[i]); 1365 } 1366 1367 static void 1368 urtw_parent(struct ieee80211com *ic) 1369 { 1370 struct urtw_softc *sc = ic->ic_softc; 1371 int startall = 0; 1372 1373 URTW_LOCK(sc); 1374 if (sc->sc_flags & URTW_DETACHED) { 1375 URTW_UNLOCK(sc); 1376 return; 1377 } 1378 1379 if (ic->ic_nrunning > 0) { 1380 if (sc->sc_flags & URTW_RUNNING) { 1381 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1382 urtw_set_multi(sc); 1383 } else { 1384 urtw_init(sc); 1385 startall = 1; 1386 } 1387 } else if (sc->sc_flags & URTW_RUNNING) 1388 urtw_stop(sc); 1389 URTW_UNLOCK(sc); 1390 if (startall) 1391 ieee80211_start_all(ic); 1392 } 1393 1394 static int 1395 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1396 { 1397 struct urtw_softc *sc = ic->ic_softc; 1398 int error; 1399 1400 URTW_LOCK(sc); 1401 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1402 URTW_UNLOCK(sc); 1403 return (ENXIO); 1404 } 1405 error = mbufq_enqueue(&sc->sc_snd, m); 1406 if (error) { 1407 URTW_UNLOCK(sc); 1408 return (error); 1409 } 1410 urtw_start(sc); 1411 URTW_UNLOCK(sc); 1412 1413 return (0); 1414 } 1415 1416 static void 1417 urtw_start(struct urtw_softc *sc) 1418 { 1419 struct urtw_data *bf; 1420 struct ieee80211_node *ni; 1421 struct mbuf *m; 1422 1423 URTW_ASSERT_LOCKED(sc); 1424 1425 if ((sc->sc_flags & URTW_RUNNING) == 0) 1426 return; 1427 1428 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1429 bf = urtw_getbuf(sc); 1430 if (bf == NULL) { 1431 mbufq_prepend(&sc->sc_snd, m); 1432 break; 1433 } 1434 1435 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1436 m->m_pkthdr.rcvif = NULL; 1437 1438 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1439 if_inc_counter(ni->ni_vap->iv_ifp, 1440 IFCOUNTER_OERRORS, 1); 1441 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1442 ieee80211_free_node(ni); 1443 break; 1444 } 1445 1446 sc->sc_txtimer = 5; 1447 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1448 } 1449 } 1450 1451 static int 1452 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1453 int ndata, int maxsz, void *dma_buf) 1454 { 1455 int i, error; 1456 1457 for (i = 0; i < ndata; i++) { 1458 struct urtw_data *dp = &data[i]; 1459 1460 dp->sc = sc; 1461 if (dma_buf == NULL) { 1462 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1463 if (dp->m == NULL) { 1464 device_printf(sc->sc_dev, 1465 "could not allocate rx mbuf\n"); 1466 error = ENOMEM; 1467 goto fail; 1468 } 1469 dp->buf = mtod(dp->m, uint8_t *); 1470 } else { 1471 dp->m = NULL; 1472 dp->buf = ((uint8_t *)dma_buf) + 1473 (i * maxsz); 1474 } 1475 dp->ni = NULL; 1476 } 1477 return (0); 1478 1479 fail: urtw_free_data_list(sc, data, ndata, 1); 1480 return (error); 1481 } 1482 1483 static int 1484 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1485 { 1486 int error, i; 1487 1488 error = urtw_alloc_data_list(sc, 1489 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1490 MCLBYTES, NULL /* mbufs */); 1491 if (error != 0) 1492 return (error); 1493 1494 STAILQ_INIT(&sc->sc_rx_active); 1495 STAILQ_INIT(&sc->sc_rx_inactive); 1496 1497 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1498 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1499 1500 return (0); 1501 } 1502 1503 static int 1504 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1505 { 1506 int error, i; 1507 1508 error = urtw_alloc_data_list(sc, 1509 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1510 sc->sc_tx_dma_buf /* no mbufs */); 1511 if (error != 0) 1512 return (error); 1513 1514 STAILQ_INIT(&sc->sc_tx_active); 1515 STAILQ_INIT(&sc->sc_tx_inactive); 1516 STAILQ_INIT(&sc->sc_tx_pending); 1517 1518 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1519 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1520 next); 1521 1522 return (0); 1523 } 1524 1525 static int 1526 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1527 const struct ieee80211_bpf_params *params) 1528 { 1529 struct ieee80211com *ic = ni->ni_ic; 1530 struct urtw_softc *sc = ic->ic_softc; 1531 struct urtw_data *bf; 1532 1533 /* prevent management frames from being sent if we're not ready */ 1534 if (!(sc->sc_flags & URTW_RUNNING)) { 1535 m_freem(m); 1536 return ENETDOWN; 1537 } 1538 URTW_LOCK(sc); 1539 bf = urtw_getbuf(sc); 1540 if (bf == NULL) { 1541 m_freem(m); 1542 URTW_UNLOCK(sc); 1543 return (ENOBUFS); /* XXX */ 1544 } 1545 1546 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1547 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1548 URTW_UNLOCK(sc); 1549 return (EIO); 1550 } 1551 URTW_UNLOCK(sc); 1552 1553 sc->sc_txtimer = 5; 1554 return (0); 1555 } 1556 1557 static void 1558 urtw_scan_start(struct ieee80211com *ic) 1559 { 1560 1561 /* XXX do nothing? */ 1562 } 1563 1564 static void 1565 urtw_scan_end(struct ieee80211com *ic) 1566 { 1567 1568 /* XXX do nothing? */ 1569 } 1570 1571 static void 1572 urtw_getradiocaps(struct ieee80211com *ic, 1573 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1574 { 1575 uint8_t bands[IEEE80211_MODE_BYTES]; 1576 1577 memset(bands, 0, sizeof(bands)); 1578 setbit(bands, IEEE80211_MODE_11B); 1579 setbit(bands, IEEE80211_MODE_11G); 1580 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 1581 urtw_chan_2ghz, nitems(urtw_chan_2ghz), bands, 0); 1582 } 1583 1584 static void 1585 urtw_set_channel(struct ieee80211com *ic) 1586 { 1587 struct urtw_softc *sc = ic->ic_softc; 1588 uint32_t data, orig; 1589 usb_error_t error; 1590 1591 /* 1592 * if the user set a channel explicitly using ifconfig(8) this function 1593 * can be called earlier than we're expected that in some cases the 1594 * initialization would be failed if setting a channel is called before 1595 * the init have done. 1596 */ 1597 if (!(sc->sc_flags & URTW_RUNNING)) 1598 return; 1599 1600 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1601 return; 1602 1603 URTW_LOCK(sc); 1604 1605 /* 1606 * during changing th channel we need to temporarily be disable 1607 * TX. 1608 */ 1609 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1610 data = orig & ~URTW_TX_LOOPBACK_MASK; 1611 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1612 1613 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1614 if (error != 0) 1615 goto fail; 1616 usb_pause_mtx(&sc->sc_mtx, 10); 1617 urtw_write32_m(sc, URTW_TX_CONF, orig); 1618 1619 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1620 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1621 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1622 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1623 1624 fail: 1625 URTW_UNLOCK(sc); 1626 1627 sc->sc_curchan = ic->ic_curchan; 1628 1629 if (error != 0) 1630 device_printf(sc->sc_dev, "could not change the channel\n"); 1631 } 1632 1633 static void 1634 urtw_update_mcast(struct ieee80211com *ic) 1635 { 1636 1637 /* XXX do nothing? */ 1638 } 1639 1640 static int 1641 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1642 struct urtw_data *data, int prior) 1643 { 1644 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1645 struct ieee80211_key *k; 1646 const struct ieee80211_txparam *tp; 1647 struct ieee80211com *ic = &sc->sc_ic; 1648 struct ieee80211vap *vap = ni->ni_vap; 1649 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1650 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1651 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1652 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1653 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1654 }; 1655 struct usb_xfer *xfer; 1656 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, 1657 pkttime = 0, txdur = 0, isshort = 0, xferlen; 1658 uint16_t acktime, rtstime, ctstime; 1659 uint32_t flags; 1660 usb_error_t error; 1661 1662 URTW_ASSERT_LOCKED(sc); 1663 1664 /* 1665 * Software crypto. 1666 */ 1667 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1668 k = ieee80211_crypto_encap(ni, m0); 1669 if (k == NULL) { 1670 device_printf(sc->sc_dev, 1671 "ieee80211_crypto_encap returns NULL.\n"); 1672 /* XXX we don't expect the fragmented frames */ 1673 m_freem(m0); 1674 return (ENOBUFS); 1675 } 1676 1677 /* in case packet header moved, reset pointer */ 1678 wh = mtod(m0, struct ieee80211_frame *); 1679 } 1680 1681 if (ieee80211_radiotap_active_vap(vap)) { 1682 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1683 1684 /* XXX Are variables correct? */ 1685 tap->wt_flags = 0; 1686 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1687 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1688 1689 ieee80211_radiotap_tx(vap, m0); 1690 } 1691 1692 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT || 1693 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { 1694 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1695 rate = tp->mgmtrate; 1696 } else { 1697 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1698 /* for data frames */ 1699 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1700 rate = tp->mcastrate; 1701 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1702 rate = tp->ucastrate; 1703 else 1704 rate = urtw_rtl2rate(sc->sc_currate); 1705 } 1706 1707 sc->sc_stats.txrates[sc->sc_currate]++; 1708 1709 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1710 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1711 IEEE80211_CRC_LEN, rate, 0, 0); 1712 else { 1713 acktime = urtw_compute_txtime(14, 2,0, 0); 1714 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1715 rtsenable = 1; 1716 ctsenable = 0; 1717 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1718 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1719 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1720 IEEE80211_CRC_LEN, rate, 0, isshort); 1721 rtsdur = ctstime + pkttime + acktime + 1722 3 * URTW_ASIFS_TIME; 1723 txdur = rtstime + rtsdur; 1724 } else { 1725 rtsenable = ctsenable = rtsdur = 0; 1726 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1727 IEEE80211_CRC_LEN, rate, 0, isshort); 1728 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1729 } 1730 1731 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1732 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1733 IEEE80211_CRC_LEN, rate, 0, isshort) + 1734 3 * URTW_ASIFS_TIME + 1735 2 * acktime; 1736 else 1737 dur = URTW_ASIFS_TIME + acktime; 1738 } 1739 USETW(wh->i_dur, dur); 1740 1741 xferlen = m0->m_pkthdr.len; 1742 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1743 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1744 xferlen += 1; 1745 1746 memset(data->buf, 0, URTW_TX_MAXSIZE); 1747 flags = m0->m_pkthdr.len & 0xfff; 1748 flags |= URTW_TX_FLAG_NO_ENC; 1749 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1750 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1751 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1752 (sc->sc_currate != 0)) 1753 flags |= URTW_TX_FLAG_SPLCP; 1754 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1755 flags |= URTW_TX_FLAG_MOREFRAG; 1756 1757 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1758 1759 if (sc->sc_flags & URTW_RTL8187B) { 1760 struct urtw_8187b_txhdr *tx; 1761 1762 tx = (struct urtw_8187b_txhdr *)data->buf; 1763 if (ctsenable) 1764 flags |= URTW_TX_FLAG_CTS; 1765 if (rtsenable) { 1766 flags |= URTW_TX_FLAG_RTS; 1767 flags |= (urtw_rate2rtl(11) & 0xf) << 1768 URTW_TX_FLAG_RTSRATE_SHIFT; 1769 tx->rtsdur = rtsdur; 1770 } 1771 tx->flag = htole32(flags); 1772 tx->txdur = txdur; 1773 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1774 IEEE80211_FC0_TYPE_MGT && 1775 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1776 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1777 tx->retry = 1; 1778 else 1779 tx->retry = URTW_TX_MAXRETRY; 1780 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1781 } else { 1782 struct urtw_8187l_txhdr *tx; 1783 1784 tx = (struct urtw_8187l_txhdr *)data->buf; 1785 if (rtsenable) { 1786 flags |= URTW_TX_FLAG_RTS; 1787 tx->rtsdur = rtsdur; 1788 } 1789 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT; 1790 tx->flag = htole32(flags); 1791 tx->retry = 3; /* CW minimum */ 1792 tx->retry |= 7 << 4; /* CW maximum */ 1793 tx->retry |= URTW_TX_MAXRETRY << 8; /* retry limitation */ 1794 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1795 } 1796 1797 data->buflen = xferlen; 1798 data->ni = ni; 1799 data->m = m0; 1800 1801 if (sc->sc_flags & URTW_RTL8187B) { 1802 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1803 case IEEE80211_FC0_TYPE_CTL: 1804 case IEEE80211_FC0_TYPE_MGT: 1805 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1806 break; 1807 default: 1808 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1809 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1810 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1811 break; 1812 } 1813 } else 1814 xfer = (prior == URTW_PRIORITY_LOW) ? 1815 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1816 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1817 1818 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1819 usbd_transfer_start(xfer); 1820 1821 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1822 if (error != 0) 1823 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1824 error); 1825 return (0); 1826 } 1827 1828 static int 1829 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1830 { 1831 struct ieee80211com *ic = vap->iv_ic; 1832 struct urtw_softc *sc = ic->ic_softc; 1833 struct urtw_vap *uvp = URTW_VAP(vap); 1834 struct ieee80211_node *ni; 1835 usb_error_t error = 0; 1836 1837 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1838 ieee80211_state_name[vap->iv_state], 1839 ieee80211_state_name[nstate]); 1840 1841 sc->sc_state = nstate; 1842 1843 IEEE80211_UNLOCK(ic); 1844 URTW_LOCK(sc); 1845 usb_callout_stop(&sc->sc_led_ch); 1846 callout_stop(&sc->sc_watchdog_ch); 1847 1848 switch (nstate) { 1849 case IEEE80211_S_INIT: 1850 case IEEE80211_S_SCAN: 1851 case IEEE80211_S_AUTH: 1852 case IEEE80211_S_ASSOC: 1853 break; 1854 case IEEE80211_S_RUN: 1855 ni = ieee80211_ref_node(vap->iv_bss); 1856 /* setting bssid. */ 1857 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1858 urtw_write16_m(sc, URTW_BSSID + 4, 1859 ((uint16_t *)ni->ni_bssid)[2]); 1860 urtw_update_msr(sc); 1861 /* XXX maybe the below would be incorrect. */ 1862 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1863 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1864 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1865 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1866 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1867 if (error != 0) 1868 device_printf(sc->sc_dev, 1869 "could not control LED (%d)\n", error); 1870 ieee80211_free_node(ni); 1871 break; 1872 default: 1873 break; 1874 } 1875 fail: 1876 URTW_UNLOCK(sc); 1877 IEEE80211_LOCK(ic); 1878 return (uvp->newstate(vap, nstate, arg)); 1879 } 1880 1881 static void 1882 urtw_watchdog(void *arg) 1883 { 1884 struct urtw_softc *sc = arg; 1885 1886 if (sc->sc_txtimer > 0) { 1887 if (--sc->sc_txtimer == 0) { 1888 device_printf(sc->sc_dev, "device timeout\n"); 1889 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1890 return; 1891 } 1892 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1893 } 1894 } 1895 1896 static void 1897 urtw_set_multi(void *arg) 1898 { 1899 /* XXX don't know how to set a device. Lack of docs. */ 1900 } 1901 1902 static usb_error_t 1903 urtw_set_rate(struct urtw_softc *sc) 1904 { 1905 int i, basic_rate, min_rr_rate, max_rr_rate; 1906 uint16_t data; 1907 usb_error_t error; 1908 1909 basic_rate = urtw_rate2rtl(48); 1910 min_rr_rate = urtw_rate2rtl(12); 1911 max_rr_rate = urtw_rate2rtl(48); 1912 1913 urtw_write8_m(sc, URTW_RESP_RATE, 1914 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1915 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1916 1917 urtw_read16_m(sc, URTW_BRSR, &data); 1918 data &= ~URTW_BRSR_MBR_8185; 1919 1920 for (i = 0; i <= basic_rate; i++) 1921 data |= (1 << i); 1922 1923 urtw_write16_m(sc, URTW_BRSR, data); 1924 fail: 1925 return (error); 1926 } 1927 1928 static uint16_t 1929 urtw_rate2rtl(uint32_t rate) 1930 { 1931 unsigned int i; 1932 1933 for (i = 0; i < nitems(urtw_ratetable); i++) { 1934 if (rate == urtw_ratetable[i].reg) 1935 return urtw_ratetable[i].val; 1936 } 1937 1938 return (3); 1939 } 1940 1941 static uint16_t 1942 urtw_rtl2rate(uint32_t rate) 1943 { 1944 unsigned int i; 1945 1946 for (i = 0; i < nitems(urtw_ratetable); i++) { 1947 if (rate == urtw_ratetable[i].val) 1948 return urtw_ratetable[i].reg; 1949 } 1950 1951 return (0); 1952 } 1953 1954 static usb_error_t 1955 urtw_update_msr(struct urtw_softc *sc) 1956 { 1957 struct ieee80211com *ic = &sc->sc_ic; 1958 uint8_t data; 1959 usb_error_t error; 1960 1961 urtw_read8_m(sc, URTW_MSR, &data); 1962 data &= ~URTW_MSR_LINK_MASK; 1963 1964 if (sc->sc_state == IEEE80211_S_RUN) { 1965 switch (ic->ic_opmode) { 1966 case IEEE80211_M_STA: 1967 case IEEE80211_M_MONITOR: 1968 data |= URTW_MSR_LINK_STA; 1969 if (sc->sc_flags & URTW_RTL8187B) 1970 data |= URTW_MSR_LINK_ENEDCA; 1971 break; 1972 case IEEE80211_M_IBSS: 1973 data |= URTW_MSR_LINK_ADHOC; 1974 break; 1975 case IEEE80211_M_HOSTAP: 1976 data |= URTW_MSR_LINK_HOSTAP; 1977 break; 1978 default: 1979 DPRINTF(sc, URTW_DEBUG_STATE, 1980 "unsupported operation mode 0x%x\n", 1981 ic->ic_opmode); 1982 error = USB_ERR_INVAL; 1983 goto fail; 1984 } 1985 } else 1986 data |= URTW_MSR_LINK_NONE; 1987 1988 urtw_write8_m(sc, URTW_MSR, data); 1989 fail: 1990 return (error); 1991 } 1992 1993 static usb_error_t 1994 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1995 { 1996 struct usb_device_request req; 1997 usb_error_t error; 1998 1999 URTW_ASSERT_LOCKED(sc); 2000 2001 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2002 req.bRequest = URTW_8187_GETREGS_REQ; 2003 USETW(req.wValue, (val & 0xff) | 0xff00); 2004 USETW(req.wIndex, (val >> 8) & 0x3); 2005 USETW(req.wLength, sizeof(uint8_t)); 2006 2007 error = urtw_do_request(sc, &req, data); 2008 return (error); 2009 } 2010 2011 static usb_error_t 2012 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 2013 { 2014 struct usb_device_request req; 2015 usb_error_t error; 2016 2017 URTW_ASSERT_LOCKED(sc); 2018 2019 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2020 req.bRequest = URTW_8187_GETREGS_REQ; 2021 USETW(req.wValue, (val & 0xff) | 0xff00); 2022 USETW(req.wIndex, (val >> 8) & 0x3); 2023 USETW(req.wLength, sizeof(uint16_t)); 2024 2025 error = urtw_do_request(sc, &req, data); 2026 return (error); 2027 } 2028 2029 static usb_error_t 2030 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2031 { 2032 struct usb_device_request req; 2033 usb_error_t error; 2034 2035 URTW_ASSERT_LOCKED(sc); 2036 2037 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2038 req.bRequest = URTW_8187_GETREGS_REQ; 2039 USETW(req.wValue, (val & 0xff) | 0xff00); 2040 USETW(req.wIndex, (val >> 8) & 0x3); 2041 USETW(req.wLength, sizeof(uint32_t)); 2042 2043 error = urtw_do_request(sc, &req, data); 2044 return (error); 2045 } 2046 2047 static usb_error_t 2048 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2049 { 2050 struct usb_device_request req; 2051 2052 URTW_ASSERT_LOCKED(sc); 2053 2054 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2055 req.bRequest = URTW_8187_SETREGS_REQ; 2056 USETW(req.wValue, (val & 0xff) | 0xff00); 2057 USETW(req.wIndex, (val >> 8) & 0x3); 2058 USETW(req.wLength, sizeof(uint8_t)); 2059 2060 return (urtw_do_request(sc, &req, &data)); 2061 } 2062 2063 static usb_error_t 2064 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2065 { 2066 struct usb_device_request req; 2067 2068 URTW_ASSERT_LOCKED(sc); 2069 2070 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2071 req.bRequest = URTW_8187_SETREGS_REQ; 2072 USETW(req.wValue, (val & 0xff) | 0xff00); 2073 USETW(req.wIndex, (val >> 8) & 0x3); 2074 USETW(req.wLength, sizeof(uint16_t)); 2075 2076 return (urtw_do_request(sc, &req, &data)); 2077 } 2078 2079 static usb_error_t 2080 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2081 { 2082 struct usb_device_request req; 2083 2084 URTW_ASSERT_LOCKED(sc); 2085 2086 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2087 req.bRequest = URTW_8187_SETREGS_REQ; 2088 USETW(req.wValue, (val & 0xff) | 0xff00); 2089 USETW(req.wIndex, (val >> 8) & 0x3); 2090 USETW(req.wLength, sizeof(uint32_t)); 2091 2092 return (urtw_do_request(sc, &req, &data)); 2093 } 2094 2095 static usb_error_t 2096 urtw_get_macaddr(struct urtw_softc *sc) 2097 { 2098 struct ieee80211com *ic = &sc->sc_ic; 2099 uint32_t data; 2100 usb_error_t error; 2101 2102 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2103 if (error != 0) 2104 goto fail; 2105 ic->ic_macaddr[0] = data & 0xff; 2106 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2107 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2108 if (error != 0) 2109 goto fail; 2110 ic->ic_macaddr[2] = data & 0xff; 2111 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2112 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2113 if (error != 0) 2114 goto fail; 2115 ic->ic_macaddr[4] = data & 0xff; 2116 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2117 fail: 2118 return (error); 2119 } 2120 2121 static usb_error_t 2122 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2123 { 2124 #define URTW_READCMD_LEN 3 2125 int addrlen, i; 2126 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2127 usb_error_t error; 2128 2129 /* NB: make sure the buffer is initialized */ 2130 *data = 0; 2131 2132 /* enable EPROM programming */ 2133 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2134 DELAY(URTW_EPROM_DELAY); 2135 2136 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2137 if (error != 0) 2138 goto fail; 2139 error = urtw_eprom_ck(sc); 2140 if (error != 0) 2141 goto fail; 2142 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2143 if (error != 0) 2144 goto fail; 2145 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2146 addrlen = 8; 2147 addrstr[0] = addr & (1 << 7); 2148 addrstr[1] = addr & (1 << 6); 2149 addrstr[2] = addr & (1 << 5); 2150 addrstr[3] = addr & (1 << 4); 2151 addrstr[4] = addr & (1 << 3); 2152 addrstr[5] = addr & (1 << 2); 2153 addrstr[6] = addr & (1 << 1); 2154 addrstr[7] = addr & (1 << 0); 2155 } else { 2156 addrlen=6; 2157 addrstr[0] = addr & (1 << 5); 2158 addrstr[1] = addr & (1 << 4); 2159 addrstr[2] = addr & (1 << 3); 2160 addrstr[3] = addr & (1 << 2); 2161 addrstr[4] = addr & (1 << 1); 2162 addrstr[5] = addr & (1 << 0); 2163 } 2164 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2165 if (error != 0) 2166 goto fail; 2167 2168 error = urtw_eprom_writebit(sc, 0); 2169 if (error != 0) 2170 goto fail; 2171 2172 for (i = 0; i < 16; i++) { 2173 error = urtw_eprom_ck(sc); 2174 if (error != 0) 2175 goto fail; 2176 error = urtw_eprom_readbit(sc, &data16); 2177 if (error != 0) 2178 goto fail; 2179 2180 (*data) |= (data16 << (15 - i)); 2181 } 2182 2183 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2184 if (error != 0) 2185 goto fail; 2186 error = urtw_eprom_ck(sc); 2187 if (error != 0) 2188 goto fail; 2189 2190 /* now disable EPROM programming */ 2191 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2192 fail: 2193 return (error); 2194 #undef URTW_READCMD_LEN 2195 } 2196 2197 static usb_error_t 2198 urtw_eprom_cs(struct urtw_softc *sc, int able) 2199 { 2200 uint8_t data; 2201 usb_error_t error; 2202 2203 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2204 if (able == URTW_EPROM_ENABLE) 2205 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2206 else 2207 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2208 DELAY(URTW_EPROM_DELAY); 2209 fail: 2210 return (error); 2211 } 2212 2213 static usb_error_t 2214 urtw_eprom_ck(struct urtw_softc *sc) 2215 { 2216 uint8_t data; 2217 usb_error_t error; 2218 2219 /* masking */ 2220 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2221 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2222 DELAY(URTW_EPROM_DELAY); 2223 /* unmasking */ 2224 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2225 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2226 DELAY(URTW_EPROM_DELAY); 2227 fail: 2228 return (error); 2229 } 2230 2231 static usb_error_t 2232 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2233 { 2234 uint8_t data8; 2235 usb_error_t error; 2236 2237 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2238 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2239 DELAY(URTW_EPROM_DELAY); 2240 2241 fail: 2242 return (error); 2243 } 2244 2245 static usb_error_t 2246 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2247 { 2248 uint8_t data; 2249 usb_error_t error; 2250 2251 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2252 if (bit != 0) 2253 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2254 else 2255 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2256 DELAY(URTW_EPROM_DELAY); 2257 fail: 2258 return (error); 2259 } 2260 2261 static usb_error_t 2262 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2263 { 2264 int i = 0; 2265 usb_error_t error = 0; 2266 2267 for (i = 0; i < buflen; i++) { 2268 error = urtw_eprom_writebit(sc, buf[i]); 2269 if (error != 0) 2270 goto fail; 2271 error = urtw_eprom_ck(sc); 2272 if (error != 0) 2273 goto fail; 2274 } 2275 fail: 2276 return (error); 2277 } 2278 2279 2280 static usb_error_t 2281 urtw_get_txpwr(struct urtw_softc *sc) 2282 { 2283 int i, j; 2284 uint32_t data; 2285 usb_error_t error; 2286 2287 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2288 if (error != 0) 2289 goto fail; 2290 sc->sc_txpwr_cck_base = data & 0xf; 2291 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2292 2293 for (i = 1, j = 0; i < 6; i += 2, j++) { 2294 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2295 if (error != 0) 2296 goto fail; 2297 sc->sc_txpwr_cck[i] = data & 0xf; 2298 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2299 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2300 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2301 } 2302 for (i = 1, j = 0; i < 4; i += 2, j++) { 2303 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2304 if (error != 0) 2305 goto fail; 2306 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2307 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2308 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2309 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2310 } 2311 if (sc->sc_flags & URTW_RTL8187B) { 2312 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2313 if (error != 0) 2314 goto fail; 2315 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2316 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2317 error = urtw_eprom_read32(sc, 0x0a, &data); 2318 if (error != 0) 2319 goto fail; 2320 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2321 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2322 error = urtw_eprom_read32(sc, 0x1c, &data); 2323 if (error != 0) 2324 goto fail; 2325 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2326 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2327 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2328 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2329 } else { 2330 for (i = 1, j = 0; i < 4; i += 2, j++) { 2331 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2332 &data); 2333 if (error != 0) 2334 goto fail; 2335 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2336 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2337 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2338 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2339 } 2340 } 2341 fail: 2342 return (error); 2343 } 2344 2345 2346 static usb_error_t 2347 urtw_get_rfchip(struct urtw_softc *sc) 2348 { 2349 int ret; 2350 uint8_t data8; 2351 uint32_t data; 2352 usb_error_t error; 2353 2354 if (sc->sc_flags & URTW_RTL8187B) { 2355 urtw_read8_m(sc, 0xe1, &data8); 2356 switch (data8) { 2357 case 0: 2358 sc->sc_flags |= URTW_RTL8187B_REV_B; 2359 break; 2360 case 1: 2361 sc->sc_flags |= URTW_RTL8187B_REV_D; 2362 break; 2363 case 2: 2364 sc->sc_flags |= URTW_RTL8187B_REV_E; 2365 break; 2366 default: 2367 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2368 sc->sc_flags |= URTW_RTL8187B_REV_B; 2369 break; 2370 } 2371 } else { 2372 urtw_read32_m(sc, URTW_TX_CONF, &data); 2373 switch (data & URTW_TX_HWMASK) { 2374 case URTW_TX_R8187vD_B: 2375 sc->sc_flags |= URTW_RTL8187B; 2376 break; 2377 case URTW_TX_R8187vD: 2378 break; 2379 default: 2380 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2381 data & URTW_TX_HWMASK); 2382 break; 2383 } 2384 } 2385 2386 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2387 if (error != 0) 2388 goto fail; 2389 switch (data & 0xff) { 2390 case URTW_EPROM_RFCHIPID_RTL8225U: 2391 error = urtw_8225_isv2(sc, &ret); 2392 if (error != 0) 2393 goto fail; 2394 if (ret == 0) { 2395 sc->sc_rf_init = urtw_8225_rf_init; 2396 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2397 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2398 sc->sc_rf_stop = urtw_8225_rf_stop; 2399 } else { 2400 sc->sc_rf_init = urtw_8225v2_rf_init; 2401 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2402 sc->sc_rf_stop = urtw_8225_rf_stop; 2403 } 2404 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2405 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2406 break; 2407 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2408 sc->sc_rf_init = urtw_8225v2b_rf_init; 2409 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2410 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2411 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2412 sc->sc_rf_stop = urtw_8225_rf_stop; 2413 break; 2414 default: 2415 DPRINTF(sc, URTW_DEBUG_STATE, 2416 "unsupported RF chip %d\n", data & 0xff); 2417 error = USB_ERR_INVAL; 2418 goto fail; 2419 } 2420 2421 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2422 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2423 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2424 "rtl8225z2", 2425 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2426 (data8 == 1) ? "d" : "e") : "none"); 2427 2428 fail: 2429 return (error); 2430 } 2431 2432 2433 static usb_error_t 2434 urtw_led_init(struct urtw_softc *sc) 2435 { 2436 uint32_t rev; 2437 usb_error_t error; 2438 2439 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2440 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2441 if (error != 0) 2442 goto fail; 2443 2444 switch (rev & URTW_EPROM_CID_MASK) { 2445 case URTW_EPROM_CID_ALPHA0: 2446 sc->sc_strategy = URTW_SW_LED_MODE1; 2447 break; 2448 case URTW_EPROM_CID_SERCOMM_PS: 2449 sc->sc_strategy = URTW_SW_LED_MODE3; 2450 break; 2451 case URTW_EPROM_CID_HW_LED: 2452 sc->sc_strategy = URTW_HW_LED; 2453 break; 2454 case URTW_EPROM_CID_RSVD0: 2455 case URTW_EPROM_CID_RSVD1: 2456 default: 2457 sc->sc_strategy = URTW_SW_LED_MODE0; 2458 break; 2459 } 2460 2461 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2462 2463 fail: 2464 return (error); 2465 } 2466 2467 2468 static usb_error_t 2469 urtw_8225_rf_init(struct urtw_softc *sc) 2470 { 2471 unsigned int i; 2472 uint16_t data; 2473 usb_error_t error; 2474 2475 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2476 if (error) 2477 goto fail; 2478 2479 error = urtw_8225_usb_init(sc); 2480 if (error) 2481 goto fail; 2482 2483 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2484 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2485 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2486 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2487 2488 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2489 if (error) 2490 goto fail; 2491 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2492 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2493 if (error) 2494 goto fail; 2495 2496 error = urtw_8185_rf_pins_enable(sc); 2497 if (error) 2498 goto fail; 2499 usb_pause_mtx(&sc->sc_mtx, 1000); 2500 2501 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2502 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2503 urtw_8225_rf_part1[i].val); 2504 usb_pause_mtx(&sc->sc_mtx, 1); 2505 } 2506 usb_pause_mtx(&sc->sc_mtx, 100); 2507 urtw_8225_write(sc, 2508 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2509 usb_pause_mtx(&sc->sc_mtx, 200); 2510 urtw_8225_write(sc, 2511 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2512 usb_pause_mtx(&sc->sc_mtx, 200); 2513 urtw_8225_write(sc, 2514 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2515 2516 for (i = 0; i < 95; i++) { 2517 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2518 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2519 } 2520 2521 urtw_8225_write(sc, 2522 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2523 urtw_8225_write(sc, 2524 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2525 2526 for (i = 0; i < 128; i++) { 2527 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2528 usb_pause_mtx(&sc->sc_mtx, 1); 2529 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2530 usb_pause_mtx(&sc->sc_mtx, 1); 2531 } 2532 2533 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2534 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2535 urtw_8225_rf_part2[i].val); 2536 usb_pause_mtx(&sc->sc_mtx, 1); 2537 } 2538 2539 error = urtw_8225_setgain(sc, 4); 2540 if (error) 2541 goto fail; 2542 2543 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2544 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2545 urtw_8225_rf_part3[i].val); 2546 usb_pause_mtx(&sc->sc_mtx, 1); 2547 } 2548 2549 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2550 2551 error = urtw_8225_set_txpwrlvl(sc, 1); 2552 if (error) 2553 goto fail; 2554 2555 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2556 usb_pause_mtx(&sc->sc_mtx, 1); 2557 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2558 usb_pause_mtx(&sc->sc_mtx, 1); 2559 2560 /* TX ant A, 0x0 for B */ 2561 error = urtw_8185_tx_antenna(sc, 0x3); 2562 if (error) 2563 goto fail; 2564 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2565 2566 error = urtw_8225_rf_set_chan(sc, 1); 2567 fail: 2568 return (error); 2569 } 2570 2571 static usb_error_t 2572 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2573 { 2574 usb_error_t error = 0; 2575 2576 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2577 fail: 2578 return (error); 2579 } 2580 2581 static usb_error_t 2582 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2583 { 2584 usb_error_t error; 2585 2586 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2587 usb_pause_mtx(&sc->sc_mtx, 1); 2588 fail: 2589 return (error); 2590 } 2591 2592 static usb_error_t 2593 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2594 { 2595 2596 data = data & 0xff; 2597 return urtw_8187_write_phy(sc, addr, data); 2598 } 2599 2600 static usb_error_t 2601 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2602 { 2603 2604 data = data & 0xff; 2605 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2606 } 2607 2608 static usb_error_t 2609 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2610 { 2611 uint32_t phyw; 2612 usb_error_t error; 2613 2614 phyw = ((data << 8) | (addr | 0x80)); 2615 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2616 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2617 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2618 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2619 usb_pause_mtx(&sc->sc_mtx, 1); 2620 fail: 2621 return (error); 2622 } 2623 2624 static usb_error_t 2625 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2626 { 2627 usb_error_t error; 2628 2629 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2630 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2631 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2632 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2633 fail: 2634 return (error); 2635 } 2636 2637 static usb_error_t 2638 urtw_8225_usb_init(struct urtw_softc *sc) 2639 { 2640 uint8_t data; 2641 usb_error_t error; 2642 2643 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2644 urtw_write8_m(sc, URTW_GPIO, 0); 2645 error = urtw_read8e(sc, 0x53, &data); 2646 if (error) 2647 goto fail; 2648 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2649 if (error) 2650 goto fail; 2651 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2652 urtw_write8_m(sc, URTW_GPIO, 0x20); 2653 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2654 2655 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2656 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2657 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2658 2659 usb_pause_mtx(&sc->sc_mtx, 500); 2660 fail: 2661 return (error); 2662 } 2663 2664 static usb_error_t 2665 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2666 { 2667 uint16_t d80, d82, d84; 2668 usb_error_t error; 2669 2670 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2671 d80 &= URTW_RF_PINS_MAGIC1; 2672 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2673 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2674 d84 &= URTW_RF_PINS_MAGIC2; 2675 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2676 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2677 DELAY(10); 2678 2679 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2680 DELAY(2); 2681 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2682 DELAY(10); 2683 2684 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2685 if (error != 0) 2686 goto fail; 2687 2688 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2689 DELAY(10); 2690 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2691 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2692 usb_pause_mtx(&sc->sc_mtx, 2); 2693 fail: 2694 return (error); 2695 } 2696 2697 static usb_error_t 2698 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2699 uint16_t *data) 2700 { 2701 uint8_t buf[2]; 2702 uint16_t data16; 2703 struct usb_device_request req; 2704 usb_error_t error = 0; 2705 2706 data16 = *data; 2707 2708 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2709 req.bRequest = URTW_8187_SETREGS_REQ; 2710 USETW(req.wValue, addr); 2711 USETW(req.wIndex, index); 2712 USETW(req.wLength, sizeof(uint16_t)); 2713 buf[0] = (data16 & 0x00ff); 2714 buf[1] = (data16 & 0xff00) >> 8; 2715 2716 error = urtw_do_request(sc, &req, buf); 2717 2718 return (error); 2719 } 2720 2721 static usb_error_t 2722 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2723 { 2724 usb_error_t error; 2725 2726 error = urtw_8225_set_txpwrlvl(sc, chan); 2727 if (error) 2728 goto fail; 2729 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2730 usb_pause_mtx(&sc->sc_mtx, 10); 2731 fail: 2732 return (error); 2733 } 2734 2735 static usb_error_t 2736 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2737 { 2738 usb_error_t error; 2739 2740 if (sens < 0 || sens > 6) 2741 return -1; 2742 2743 if (sens > 4) 2744 urtw_8225_write(sc, 2745 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2746 else 2747 urtw_8225_write(sc, 2748 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2749 2750 sens = 6 - sens; 2751 error = urtw_8225_setgain(sc, sens); 2752 if (error) 2753 goto fail; 2754 2755 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2756 2757 fail: 2758 return (error); 2759 } 2760 2761 static usb_error_t 2762 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2763 { 2764 int i, idx, set; 2765 uint8_t *cck_pwltable; 2766 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2767 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2768 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2769 usb_error_t error; 2770 2771 cck_pwrlvl_max = 11; 2772 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2773 ofdm_pwrlvl_min = 10; 2774 2775 /* CCK power setting */ 2776 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2777 idx = cck_pwrlvl % 6; 2778 set = cck_pwrlvl / 6; 2779 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2780 urtw_8225_txpwr_cck; 2781 2782 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2783 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2784 for (i = 0; i < 8; i++) { 2785 urtw_8187_write_phy_cck(sc, 0x44 + i, 2786 cck_pwltable[idx * 8 + i]); 2787 } 2788 usb_pause_mtx(&sc->sc_mtx, 1); 2789 2790 /* OFDM power setting */ 2791 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2792 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2793 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2794 2795 idx = ofdm_pwrlvl % 6; 2796 set = ofdm_pwrlvl / 6; 2797 2798 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2799 if (error) 2800 goto fail; 2801 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2802 urtw_8187_write_phy_ofdm(sc, 6, 0); 2803 urtw_8187_write_phy_ofdm(sc, 8, 0); 2804 2805 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2806 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2807 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2808 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2809 usb_pause_mtx(&sc->sc_mtx, 1); 2810 fail: 2811 return (error); 2812 } 2813 2814 2815 static usb_error_t 2816 urtw_8225_rf_stop(struct urtw_softc *sc) 2817 { 2818 uint8_t data; 2819 usb_error_t error; 2820 2821 urtw_8225_write(sc, 0x4, 0x1f); 2822 2823 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2824 if (error) 2825 goto fail; 2826 2827 urtw_read8_m(sc, URTW_CONFIG3, &data); 2828 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2829 if (sc->sc_flags & URTW_RTL8187B) { 2830 urtw_write32_m(sc, URTW_ANAPARAM2, 2831 URTW_8187B_8225_ANAPARAM2_OFF); 2832 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2833 urtw_write32_m(sc, URTW_ANAPARAM3, 2834 URTW_8187B_8225_ANAPARAM3_OFF); 2835 } else { 2836 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2837 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2838 } 2839 2840 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2841 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2842 if (error) 2843 goto fail; 2844 2845 fail: 2846 return (error); 2847 } 2848 2849 static usb_error_t 2850 urtw_8225v2_rf_init(struct urtw_softc *sc) 2851 { 2852 unsigned int i; 2853 uint16_t data; 2854 uint32_t data32; 2855 usb_error_t error; 2856 2857 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2858 if (error) 2859 goto fail; 2860 2861 error = urtw_8225_usb_init(sc); 2862 if (error) 2863 goto fail; 2864 2865 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2866 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2867 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2868 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2869 2870 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2871 if (error) 2872 goto fail; 2873 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2874 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2875 if (error) 2876 goto fail; 2877 2878 error = urtw_8185_rf_pins_enable(sc); 2879 if (error) 2880 goto fail; 2881 2882 usb_pause_mtx(&sc->sc_mtx, 500); 2883 2884 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2885 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2886 urtw_8225v2_rf_part1[i].val); 2887 } 2888 usb_pause_mtx(&sc->sc_mtx, 50); 2889 2890 urtw_8225_write(sc, 2891 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2892 2893 for (i = 0; i < 95; i++) { 2894 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2895 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2896 urtw_8225v2_rxgain[i]); 2897 } 2898 2899 urtw_8225_write(sc, 2900 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2901 urtw_8225_write(sc, 2902 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2903 urtw_8225_write(sc, 2904 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2905 urtw_8225_write(sc, 2906 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2907 usb_pause_mtx(&sc->sc_mtx, 100); 2908 urtw_8225_write(sc, 2909 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2910 usb_pause_mtx(&sc->sc_mtx, 100); 2911 2912 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2913 if (error != 0) 2914 goto fail; 2915 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2916 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2917 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2918 urtw_8225_write(sc, 2919 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2920 usb_pause_mtx(&sc->sc_mtx, 100); 2921 urtw_8225_write(sc, 2922 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2923 usb_pause_mtx(&sc->sc_mtx, 50); 2924 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2925 if (error != 0) 2926 goto fail; 2927 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2928 device_printf(sc->sc_dev, "RF calibration failed\n"); 2929 } 2930 usb_pause_mtx(&sc->sc_mtx, 100); 2931 2932 urtw_8225_write(sc, 2933 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2934 for (i = 0; i < 128; i++) { 2935 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2936 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2937 } 2938 2939 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2940 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2941 urtw_8225v2_rf_part2[i].val); 2942 } 2943 2944 error = urtw_8225v2_setgain(sc, 4); 2945 if (error) 2946 goto fail; 2947 2948 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2949 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2950 urtw_8225v2_rf_part3[i].val); 2951 } 2952 2953 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2954 2955 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2956 if (error) 2957 goto fail; 2958 2959 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2960 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2961 2962 /* TX ant A, 0x0 for B */ 2963 error = urtw_8185_tx_antenna(sc, 0x3); 2964 if (error) 2965 goto fail; 2966 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2967 2968 error = urtw_8225_rf_set_chan(sc, 1); 2969 fail: 2970 return (error); 2971 } 2972 2973 static usb_error_t 2974 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2975 { 2976 usb_error_t error; 2977 2978 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2979 if (error) 2980 goto fail; 2981 2982 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2983 usb_pause_mtx(&sc->sc_mtx, 10); 2984 fail: 2985 return (error); 2986 } 2987 2988 static usb_error_t 2989 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2990 { 2991 int i; 2992 int16_t bit; 2993 uint8_t rlen = 12, wlen = 6; 2994 uint16_t o1, o2, o3, tmp; 2995 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2996 uint32_t mask = 0x80000000, value = 0; 2997 usb_error_t error; 2998 2999 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 3000 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 3001 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 3002 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 3003 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 3004 o1 &= ~URTW_RF_PINS_MAGIC4; 3005 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 3006 DELAY(5); 3007 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 3008 DELAY(5); 3009 3010 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 3011 bit = ((d2w & mask) != 0) ? 1 : 0; 3012 3013 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3014 DELAY(2); 3015 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3016 URTW_BB_HOST_BANG_CLK); 3017 DELAY(2); 3018 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3019 URTW_BB_HOST_BANG_CLK); 3020 DELAY(2); 3021 mask = mask >> 1; 3022 if (i == 2) 3023 break; 3024 bit = ((d2w & mask) != 0) ? 1 : 0; 3025 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3026 URTW_BB_HOST_BANG_CLK); 3027 DELAY(2); 3028 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3029 URTW_BB_HOST_BANG_CLK); 3030 DELAY(2); 3031 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3032 DELAY(1); 3033 } 3034 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3035 URTW_BB_HOST_BANG_CLK); 3036 DELAY(2); 3037 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3038 DELAY(2); 3039 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3040 DELAY(2); 3041 3042 mask = 0x800; 3043 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3044 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3045 o1 | URTW_BB_HOST_BANG_RW); 3046 DELAY(2); 3047 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3048 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3049 DELAY(2); 3050 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3051 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3052 DELAY(2); 3053 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3054 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3055 DELAY(2); 3056 3057 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3058 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3059 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3060 o1 | URTW_BB_HOST_BANG_RW); 3061 DELAY(2); 3062 } 3063 3064 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3065 URTW_BB_HOST_BANG_RW); 3066 DELAY(2); 3067 3068 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3069 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3070 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3071 3072 if (data != NULL) 3073 *data = value; 3074 fail: 3075 return (error); 3076 } 3077 3078 3079 static usb_error_t 3080 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3081 { 3082 int i; 3083 uint8_t *cck_pwrtable; 3084 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3085 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3086 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3087 usb_error_t error; 3088 3089 /* CCK power setting */ 3090 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3091 cck_pwrlvl += sc->sc_txpwr_cck_base; 3092 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3093 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3094 urtw_8225v2_txpwr_cck; 3095 3096 for (i = 0; i < 8; i++) 3097 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3098 3099 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3100 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3101 usb_pause_mtx(&sc->sc_mtx, 1); 3102 3103 /* OFDM power setting */ 3104 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3105 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3106 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3107 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3108 3109 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3110 if (error) 3111 goto fail; 3112 3113 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3114 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3115 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3116 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3117 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3118 3119 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3120 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3121 usb_pause_mtx(&sc->sc_mtx, 1); 3122 fail: 3123 return (error); 3124 } 3125 3126 static usb_error_t 3127 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3128 { 3129 uint8_t *gainp; 3130 usb_error_t error; 3131 3132 /* XXX for A? */ 3133 gainp = urtw_8225v2_gain_bg; 3134 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3135 usb_pause_mtx(&sc->sc_mtx, 1); 3136 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3137 usb_pause_mtx(&sc->sc_mtx, 1); 3138 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3139 usb_pause_mtx(&sc->sc_mtx, 1); 3140 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3141 usb_pause_mtx(&sc->sc_mtx, 1); 3142 fail: 3143 return (error); 3144 } 3145 3146 static usb_error_t 3147 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3148 { 3149 uint32_t data; 3150 usb_error_t error; 3151 3152 *ret = 1; 3153 3154 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3155 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3156 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3157 usb_pause_mtx(&sc->sc_mtx, 500); 3158 3159 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3160 URTW_8225_ADDR_0_DATA_MAGIC1); 3161 3162 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3163 if (error != 0) 3164 goto fail; 3165 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3166 *ret = 0; 3167 else { 3168 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3169 if (error != 0) 3170 goto fail; 3171 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3172 *ret = 0; 3173 } 3174 3175 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3176 URTW_8225_ADDR_0_DATA_MAGIC2); 3177 fail: 3178 return (error); 3179 } 3180 3181 static usb_error_t 3182 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3183 { 3184 struct ieee80211com *ic = &sc->sc_ic; 3185 unsigned int i; 3186 uint8_t data8; 3187 usb_error_t error; 3188 3189 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3190 if (error) 3191 goto fail; 3192 3193 /* 3194 * initialize extra registers on 8187 3195 */ 3196 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3197 3198 /* retry limit */ 3199 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3200 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3201 urtw_write8_m(sc, URTW_CW_CONF, data8); 3202 3203 /* TX AGC */ 3204 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3205 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3206 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3207 3208 /* Auto Rate Fallback Control */ 3209 #define URTW_ARFR 0x1e0 3210 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3211 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3212 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3213 data8 | URTW_RATE_FALLBACK_ENABLE); 3214 3215 urtw_read8_m(sc, URTW_MSR, &data8); 3216 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3217 urtw_read8_m(sc, URTW_MSR, &data8); 3218 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3219 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3220 3221 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3222 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3223 #define URTW_FEMR_FOR_8187B 0x1d4 3224 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3225 3226 /* led type */ 3227 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3228 data8 = (data8 & 0x3f) | 0x80; 3229 urtw_write8_m(sc, URTW_CONFIG1, data8); 3230 3231 /* applying MAC address again. */ 3232 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3233 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3234 3235 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3236 if (error) 3237 goto fail; 3238 3239 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3240 3241 /* 3242 * MAC configuration 3243 */ 3244 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3245 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3246 urtw_8225v2b_rf_part1[i].val); 3247 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3248 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3249 urtw_write32_m(sc, 0x1f0, 0); 3250 urtw_write32_m(sc, 0x1f4, 0); 3251 urtw_write8_m(sc, 0x1f8, 0); 3252 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3253 3254 #define URTW_RFSW_CTRL 0x272 3255 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3256 3257 /* 3258 * initialize PHY 3259 */ 3260 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3261 if (error) 3262 goto fail; 3263 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3264 urtw_write8_m(sc, URTW_CONFIG3, 3265 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3266 3267 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3268 if (error) 3269 goto fail; 3270 3271 /* setup RFE initial timing */ 3272 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3273 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3274 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3275 usb_pause_mtx(&sc->sc_mtx, 1100); 3276 3277 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3278 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3279 urtw_8225v2b_rf_part0[i].val); 3280 usb_pause_mtx(&sc->sc_mtx, 1); 3281 } 3282 urtw_8225_write(sc, 0x00, 0x01b7); 3283 3284 for (i = 0; i < 95; i++) { 3285 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3286 usb_pause_mtx(&sc->sc_mtx, 1); 3287 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3288 urtw_8225v2b_rxgain[i]); 3289 usb_pause_mtx(&sc->sc_mtx, 1); 3290 } 3291 3292 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3293 usb_pause_mtx(&sc->sc_mtx, 1); 3294 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3295 usb_pause_mtx(&sc->sc_mtx, 1); 3296 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3297 usb_pause_mtx(&sc->sc_mtx, 1); 3298 usb_pause_mtx(&sc->sc_mtx, 3000); 3299 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3300 usb_pause_mtx(&sc->sc_mtx, 2000); 3301 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3302 usb_pause_mtx(&sc->sc_mtx, 1); 3303 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3304 usb_pause_mtx(&sc->sc_mtx, 1); 3305 3306 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3307 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3308 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3309 3310 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3311 for (i = 0; i < 128; i++) { 3312 uint32_t addr, data; 3313 3314 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3315 addr = ((i + 0x80) << 8) | 0x0000008e; 3316 3317 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3318 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3319 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3320 } 3321 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3322 3323 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3324 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3325 3326 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3327 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3328 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3329 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3330 3331 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3332 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3333 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3334 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3335 3336 fail: 3337 return (error); 3338 } 3339 3340 static usb_error_t 3341 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3342 { 3343 usb_error_t error; 3344 3345 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3346 if (error) 3347 goto fail; 3348 3349 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3350 usb_pause_mtx(&sc->sc_mtx, 10); 3351 fail: 3352 return (error); 3353 } 3354 3355 static usb_error_t 3356 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3357 { 3358 int i; 3359 uint8_t *cck_pwrtable; 3360 uint8_t cck_pwrlvl_max = 15; 3361 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3362 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3363 usb_error_t error; 3364 3365 /* CCK power setting */ 3366 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3367 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3368 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3369 cck_pwrlvl += sc->sc_txpwr_cck_base; 3370 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3371 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3372 urtw_8225v2b_txpwr_cck; 3373 3374 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3375 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3376 ((cck_pwrlvl <= 11) ? 8 : 16); 3377 else 3378 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3379 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3380 3381 for (i = 0; i < 8; i++) 3382 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3383 3384 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3385 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3386 usb_pause_mtx(&sc->sc_mtx, 1); 3387 3388 /* OFDM power setting */ 3389 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3390 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3391 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3392 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3393 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3394 3395 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3396 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3397 3398 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3399 if (ofdm_pwrlvl <= 11) { 3400 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3401 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3402 } else { 3403 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3404 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3405 } 3406 } else { 3407 if (ofdm_pwrlvl <= 11) { 3408 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3409 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3410 } else if (ofdm_pwrlvl <= 17) { 3411 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3412 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3413 } else { 3414 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3415 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3416 } 3417 } 3418 usb_pause_mtx(&sc->sc_mtx, 1); 3419 fail: 3420 return (error); 3421 } 3422 3423 static usb_error_t 3424 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3425 { 3426 struct usb_device_request req; 3427 usb_error_t error; 3428 3429 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3430 req.bRequest = URTW_8187_GETREGS_REQ; 3431 USETW(req.wValue, val | 0xfe00); 3432 USETW(req.wIndex, 0); 3433 USETW(req.wLength, sizeof(uint8_t)); 3434 3435 error = urtw_do_request(sc, &req, data); 3436 return (error); 3437 } 3438 3439 static usb_error_t 3440 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3441 { 3442 struct usb_device_request req; 3443 3444 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3445 req.bRequest = URTW_8187_SETREGS_REQ; 3446 USETW(req.wValue, val | 0xfe00); 3447 USETW(req.wIndex, 0); 3448 USETW(req.wLength, sizeof(uint8_t)); 3449 3450 return (urtw_do_request(sc, &req, &data)); 3451 } 3452 3453 static usb_error_t 3454 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3455 { 3456 uint8_t data; 3457 usb_error_t error; 3458 3459 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3460 if (error) 3461 goto fail; 3462 3463 urtw_read8_m(sc, URTW_CONFIG3, &data); 3464 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3465 urtw_write32_m(sc, URTW_ANAPARAM, val); 3466 urtw_read8_m(sc, URTW_CONFIG3, &data); 3467 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3468 3469 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3470 if (error) 3471 goto fail; 3472 fail: 3473 return (error); 3474 } 3475 3476 static usb_error_t 3477 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3478 { 3479 uint8_t data; 3480 usb_error_t error; 3481 3482 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3483 if (error) 3484 goto fail; 3485 3486 urtw_read8_m(sc, URTW_CONFIG3, &data); 3487 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3488 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3489 urtw_read8_m(sc, URTW_CONFIG3, &data); 3490 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3491 3492 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3493 if (error) 3494 goto fail; 3495 fail: 3496 return (error); 3497 } 3498 3499 static usb_error_t 3500 urtw_intr_enable(struct urtw_softc *sc) 3501 { 3502 usb_error_t error; 3503 3504 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3505 fail: 3506 return (error); 3507 } 3508 3509 static usb_error_t 3510 urtw_intr_disable(struct urtw_softc *sc) 3511 { 3512 usb_error_t error; 3513 3514 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3515 fail: 3516 return (error); 3517 } 3518 3519 static usb_error_t 3520 urtw_reset(struct urtw_softc *sc) 3521 { 3522 uint8_t data; 3523 usb_error_t error; 3524 3525 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3526 if (error) 3527 goto fail; 3528 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3529 if (error) 3530 goto fail; 3531 3532 error = urtw_intr_disable(sc); 3533 if (error) 3534 goto fail; 3535 usb_pause_mtx(&sc->sc_mtx, 100); 3536 3537 error = urtw_write8e(sc, 0x18, 0x10); 3538 if (error != 0) 3539 goto fail; 3540 error = urtw_write8e(sc, 0x18, 0x11); 3541 if (error != 0) 3542 goto fail; 3543 error = urtw_write8e(sc, 0x18, 0x00); 3544 if (error != 0) 3545 goto fail; 3546 usb_pause_mtx(&sc->sc_mtx, 100); 3547 3548 urtw_read8_m(sc, URTW_CMD, &data); 3549 data = (data & 0x2) | URTW_CMD_RST; 3550 urtw_write8_m(sc, URTW_CMD, data); 3551 usb_pause_mtx(&sc->sc_mtx, 100); 3552 3553 urtw_read8_m(sc, URTW_CMD, &data); 3554 if (data & URTW_CMD_RST) { 3555 device_printf(sc->sc_dev, "reset timeout\n"); 3556 goto fail; 3557 } 3558 3559 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3560 if (error) 3561 goto fail; 3562 usb_pause_mtx(&sc->sc_mtx, 100); 3563 3564 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3565 if (error) 3566 goto fail; 3567 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3568 if (error) 3569 goto fail; 3570 fail: 3571 return (error); 3572 } 3573 3574 static usb_error_t 3575 urtw_led_ctl(struct urtw_softc *sc, int mode) 3576 { 3577 usb_error_t error = 0; 3578 3579 switch (sc->sc_strategy) { 3580 case URTW_SW_LED_MODE0: 3581 error = urtw_led_mode0(sc, mode); 3582 break; 3583 case URTW_SW_LED_MODE1: 3584 error = urtw_led_mode1(sc, mode); 3585 break; 3586 case URTW_SW_LED_MODE2: 3587 error = urtw_led_mode2(sc, mode); 3588 break; 3589 case URTW_SW_LED_MODE3: 3590 error = urtw_led_mode3(sc, mode); 3591 break; 3592 default: 3593 DPRINTF(sc, URTW_DEBUG_STATE, 3594 "unsupported LED mode %d\n", sc->sc_strategy); 3595 error = USB_ERR_INVAL; 3596 break; 3597 } 3598 3599 return (error); 3600 } 3601 3602 static usb_error_t 3603 urtw_led_mode0(struct urtw_softc *sc, int mode) 3604 { 3605 3606 switch (mode) { 3607 case URTW_LED_CTL_POWER_ON: 3608 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3609 break; 3610 case URTW_LED_CTL_TX: 3611 if (sc->sc_gpio_ledinprogress == 1) 3612 return (0); 3613 3614 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3615 sc->sc_gpio_blinktime = 2; 3616 break; 3617 case URTW_LED_CTL_LINK: 3618 sc->sc_gpio_ledstate = URTW_LED_ON; 3619 break; 3620 default: 3621 DPRINTF(sc, URTW_DEBUG_STATE, 3622 "unsupported LED mode 0x%x", mode); 3623 return (USB_ERR_INVAL); 3624 } 3625 3626 switch (sc->sc_gpio_ledstate) { 3627 case URTW_LED_ON: 3628 if (sc->sc_gpio_ledinprogress != 0) 3629 break; 3630 urtw_led_on(sc, URTW_LED_GPIO); 3631 break; 3632 case URTW_LED_BLINK_NORMAL: 3633 if (sc->sc_gpio_ledinprogress != 0) 3634 break; 3635 sc->sc_gpio_ledinprogress = 1; 3636 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3637 URTW_LED_OFF : URTW_LED_ON; 3638 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3639 break; 3640 case URTW_LED_POWER_ON_BLINK: 3641 urtw_led_on(sc, URTW_LED_GPIO); 3642 usb_pause_mtx(&sc->sc_mtx, 100); 3643 urtw_led_off(sc, URTW_LED_GPIO); 3644 break; 3645 default: 3646 DPRINTF(sc, URTW_DEBUG_STATE, 3647 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3648 return (USB_ERR_INVAL); 3649 } 3650 return (0); 3651 } 3652 3653 static usb_error_t 3654 urtw_led_mode1(struct urtw_softc *sc, int mode) 3655 { 3656 return (USB_ERR_INVAL); 3657 } 3658 3659 static usb_error_t 3660 urtw_led_mode2(struct urtw_softc *sc, int mode) 3661 { 3662 return (USB_ERR_INVAL); 3663 } 3664 3665 static usb_error_t 3666 urtw_led_mode3(struct urtw_softc *sc, int mode) 3667 { 3668 return (USB_ERR_INVAL); 3669 } 3670 3671 static usb_error_t 3672 urtw_led_on(struct urtw_softc *sc, int type) 3673 { 3674 usb_error_t error; 3675 3676 if (type == URTW_LED_GPIO) { 3677 switch (sc->sc_gpio_ledpin) { 3678 case URTW_LED_PIN_GPIO0: 3679 urtw_write8_m(sc, URTW_GPIO, 0x01); 3680 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3681 break; 3682 default: 3683 DPRINTF(sc, URTW_DEBUG_STATE, 3684 "unsupported LED PIN type 0x%x", 3685 sc->sc_gpio_ledpin); 3686 error = USB_ERR_INVAL; 3687 goto fail; 3688 } 3689 } else { 3690 DPRINTF(sc, URTW_DEBUG_STATE, 3691 "unsupported LED type 0x%x", type); 3692 error = USB_ERR_INVAL; 3693 goto fail; 3694 } 3695 3696 sc->sc_gpio_ledon = 1; 3697 fail: 3698 return (error); 3699 } 3700 3701 static usb_error_t 3702 urtw_led_off(struct urtw_softc *sc, int type) 3703 { 3704 usb_error_t error; 3705 3706 if (type == URTW_LED_GPIO) { 3707 switch (sc->sc_gpio_ledpin) { 3708 case URTW_LED_PIN_GPIO0: 3709 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3710 urtw_write8_m(sc, 3711 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3712 break; 3713 default: 3714 DPRINTF(sc, URTW_DEBUG_STATE, 3715 "unsupported LED PIN type 0x%x", 3716 sc->sc_gpio_ledpin); 3717 error = USB_ERR_INVAL; 3718 goto fail; 3719 } 3720 } else { 3721 DPRINTF(sc, URTW_DEBUG_STATE, 3722 "unsupported LED type 0x%x", type); 3723 error = USB_ERR_INVAL; 3724 goto fail; 3725 } 3726 3727 sc->sc_gpio_ledon = 0; 3728 3729 fail: 3730 return (error); 3731 } 3732 3733 static void 3734 urtw_led_ch(void *arg) 3735 { 3736 struct urtw_softc *sc = arg; 3737 struct ieee80211com *ic = &sc->sc_ic; 3738 3739 ieee80211_runtask(ic, &sc->sc_led_task); 3740 } 3741 3742 static void 3743 urtw_ledtask(void *arg, int pending) 3744 { 3745 struct urtw_softc *sc = arg; 3746 3747 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3748 DPRINTF(sc, URTW_DEBUG_STATE, 3749 "could not process a LED strategy 0x%x", 3750 sc->sc_strategy); 3751 return; 3752 } 3753 3754 URTW_LOCK(sc); 3755 urtw_led_blink(sc); 3756 URTW_UNLOCK(sc); 3757 } 3758 3759 static usb_error_t 3760 urtw_led_blink(struct urtw_softc *sc) 3761 { 3762 uint8_t ing = 0; 3763 usb_error_t error; 3764 3765 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3766 error = urtw_led_on(sc, URTW_LED_GPIO); 3767 else 3768 error = urtw_led_off(sc, URTW_LED_GPIO); 3769 sc->sc_gpio_blinktime--; 3770 if (sc->sc_gpio_blinktime == 0) 3771 ing = 1; 3772 else { 3773 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3774 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3775 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3776 ing = 1; 3777 } 3778 if (ing == 1) { 3779 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3780 sc->sc_gpio_ledon == 0) 3781 error = urtw_led_on(sc, URTW_LED_GPIO); 3782 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3783 sc->sc_gpio_ledon == 1) 3784 error = urtw_led_off(sc, URTW_LED_GPIO); 3785 3786 sc->sc_gpio_blinktime = 0; 3787 sc->sc_gpio_ledinprogress = 0; 3788 return (0); 3789 } 3790 3791 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3792 URTW_LED_ON : URTW_LED_OFF; 3793 3794 switch (sc->sc_gpio_ledstate) { 3795 case URTW_LED_BLINK_NORMAL: 3796 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3797 break; 3798 default: 3799 DPRINTF(sc, URTW_DEBUG_STATE, 3800 "unknown LED status 0x%x", 3801 sc->sc_gpio_ledstate); 3802 return (USB_ERR_INVAL); 3803 } 3804 return (0); 3805 } 3806 3807 static usb_error_t 3808 urtw_rx_enable(struct urtw_softc *sc) 3809 { 3810 uint8_t data; 3811 usb_error_t error; 3812 3813 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3814 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3815 3816 error = urtw_rx_setconf(sc); 3817 if (error != 0) 3818 goto fail; 3819 3820 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3821 urtw_read8_m(sc, URTW_CMD, &data); 3822 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3823 } 3824 fail: 3825 return (error); 3826 } 3827 3828 static usb_error_t 3829 urtw_tx_enable(struct urtw_softc *sc) 3830 { 3831 uint8_t data8; 3832 uint32_t data; 3833 usb_error_t error; 3834 3835 if (sc->sc_flags & URTW_RTL8187B) { 3836 urtw_read32_m(sc, URTW_TX_CONF, &data); 3837 data &= ~URTW_TX_LOOPBACK_MASK; 3838 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3839 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3840 data &= ~URTW_TX_SWPLCPLEN; 3841 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3842 (7 << 8) | /* short retry limit */ 3843 (7 << 0) | /* long retry limit */ 3844 (7 << 21); /* MAX TX DMA */ 3845 urtw_write32_m(sc, URTW_TX_CONF, data); 3846 3847 urtw_read8_m(sc, URTW_MSR, &data8); 3848 data8 |= URTW_MSR_LINK_ENEDCA; 3849 urtw_write8_m(sc, URTW_MSR, data8); 3850 return (error); 3851 } 3852 3853 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3854 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3855 urtw_write8_m(sc, URTW_CW_CONF, data8); 3856 3857 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3858 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3859 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3860 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3861 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3862 3863 urtw_read32_m(sc, URTW_TX_CONF, &data); 3864 data &= ~URTW_TX_LOOPBACK_MASK; 3865 data |= URTW_TX_LOOPBACK_NONE; 3866 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3867 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3868 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3869 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3870 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3871 data &= ~URTW_TX_SWPLCPLEN; 3872 data |= URTW_TX_NOICV; 3873 urtw_write32_m(sc, URTW_TX_CONF, data); 3874 3875 urtw_read8_m(sc, URTW_CMD, &data8); 3876 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3877 fail: 3878 return (error); 3879 } 3880 3881 static usb_error_t 3882 urtw_rx_setconf(struct urtw_softc *sc) 3883 { 3884 struct ieee80211com *ic = &sc->sc_ic; 3885 uint32_t data; 3886 usb_error_t error; 3887 3888 urtw_read32_m(sc, URTW_RX, &data); 3889 data = data &~ URTW_RX_FILTER_MASK; 3890 if (sc->sc_flags & URTW_RTL8187B) { 3891 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3892 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3893 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID | 3894 URTW_RX_FIFO_THRESHOLD_NONE | 3895 URTW_MAX_RX_DMA_2048 | 3896 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3897 } else { 3898 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3899 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3900 3901 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3902 data = data | URTW_RX_FILTER_ICVERR; 3903 data = data | URTW_RX_FILTER_PWR; 3904 } 3905 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3906 data = data | URTW_RX_FILTER_CRCERR; 3907 3908 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3909 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3910 data = data | URTW_RX_FILTER_ALLMAC; 3911 } else { 3912 data = data | URTW_RX_FILTER_NICMAC; 3913 data = data | URTW_RX_CHECK_BSSID; 3914 } 3915 3916 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3917 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3918 URTW_RX_AUTORESETPHY; 3919 data = data &~ URTW_MAX_RX_DMA_MASK; 3920 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3921 } 3922 3923 urtw_write32_m(sc, URTW_RX, data); 3924 fail: 3925 return (error); 3926 } 3927 3928 static struct mbuf * 3929 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3930 int8_t *nf_p) 3931 { 3932 int actlen, flen, rssi; 3933 struct ieee80211_frame *wh; 3934 struct mbuf *m, *mnew; 3935 struct urtw_softc *sc = data->sc; 3936 struct ieee80211com *ic = &sc->sc_ic; 3937 uint8_t noise = 0, rate; 3938 3939 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3940 3941 if (actlen < (int)URTW_MIN_RXBUFSZ) { 3942 counter_u64_add(ic->ic_ierrors, 1); 3943 return (NULL); 3944 } 3945 3946 if (sc->sc_flags & URTW_RTL8187B) { 3947 struct urtw_8187b_rxhdr *rx; 3948 3949 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3950 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3951 flen = le32toh(rx->flag) & 0xfff; 3952 if (flen > actlen) { 3953 counter_u64_add(ic->ic_ierrors, 1); 3954 return (NULL); 3955 } 3956 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3957 /* XXX correct? */ 3958 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3959 noise = rx->noise; 3960 } else { 3961 struct urtw_8187l_rxhdr *rx; 3962 3963 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3964 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3965 flen = le32toh(rx->flag) & 0xfff; 3966 if (flen > actlen) { 3967 counter_u64_add(ic->ic_ierrors, 1); 3968 return (NULL); 3969 } 3970 3971 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3972 /* XXX correct? */ 3973 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3974 noise = rx->noise; 3975 } 3976 3977 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3978 if (mnew == NULL) { 3979 counter_u64_add(ic->ic_ierrors, 1); 3980 return (NULL); 3981 } 3982 3983 m = data->m; 3984 data->m = mnew; 3985 data->buf = mtod(mnew, uint8_t *); 3986 3987 /* finalize mbuf */ 3988 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3989 3990 if (ieee80211_radiotap_active(ic)) { 3991 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3992 3993 /* XXX Are variables correct? */ 3994 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 3995 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3996 tap->wr_dbm_antsignal = (int8_t)rssi; 3997 } 3998 3999 wh = mtod(m, struct ieee80211_frame *); 4000 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 4001 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 4002 4003 *rssi_p = rssi; 4004 *nf_p = noise; /* XXX correct? */ 4005 4006 return (m); 4007 } 4008 4009 static void 4010 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 4011 { 4012 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4013 struct ieee80211com *ic = &sc->sc_ic; 4014 struct ieee80211_frame *wh; 4015 struct ieee80211_node *ni; 4016 struct mbuf *m = NULL; 4017 struct urtw_data *data; 4018 int8_t nf = -95; 4019 int rssi = 1; 4020 4021 URTW_ASSERT_LOCKED(sc); 4022 4023 switch (USB_GET_STATE(xfer)) { 4024 case USB_ST_TRANSFERRED: 4025 data = STAILQ_FIRST(&sc->sc_rx_active); 4026 if (data == NULL) 4027 goto setup; 4028 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4029 m = urtw_rxeof(xfer, data, &rssi, &nf); 4030 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4031 /* FALLTHROUGH */ 4032 case USB_ST_SETUP: 4033 setup: 4034 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4035 if (data == NULL) { 4036 KASSERT(m == NULL, ("mbuf isn't NULL")); 4037 return; 4038 } 4039 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4040 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4041 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4042 usbd_xfer_max_len(xfer)); 4043 usbd_transfer_submit(xfer); 4044 4045 /* 4046 * To avoid LOR we should unlock our private mutex here to call 4047 * ieee80211_input() because here is at the end of a USB 4048 * callback and safe to unlock. 4049 */ 4050 URTW_UNLOCK(sc); 4051 if (m != NULL) { 4052 wh = mtod(m, struct ieee80211_frame *); 4053 ni = ieee80211_find_rxnode(ic, 4054 (struct ieee80211_frame_min *)wh); 4055 if (ni != NULL) { 4056 (void) ieee80211_input(ni, m, rssi, nf); 4057 /* node is no longer needed */ 4058 ieee80211_free_node(ni); 4059 } else 4060 (void) ieee80211_input_all(ic, m, rssi, nf); 4061 m = NULL; 4062 } 4063 URTW_LOCK(sc); 4064 break; 4065 default: 4066 /* needs it to the inactive queue due to a error. */ 4067 data = STAILQ_FIRST(&sc->sc_rx_active); 4068 if (data != NULL) { 4069 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4070 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4071 } 4072 if (error != USB_ERR_CANCELLED) { 4073 usbd_xfer_set_stall(xfer); 4074 counter_u64_add(ic->ic_ierrors, 1); 4075 goto setup; 4076 } 4077 break; 4078 } 4079 } 4080 4081 #define URTW_STATUS_TYPE_TXCLOSE 1 4082 #define URTW_STATUS_TYPE_BEACON_INTR 0 4083 4084 static void 4085 urtw_txstatus_eof(struct usb_xfer *xfer) 4086 { 4087 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4088 struct ieee80211com *ic = &sc->sc_ic; 4089 int actlen, type, pktretry, seq; 4090 uint64_t val; 4091 4092 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4093 4094 if (actlen != sizeof(uint64_t)) 4095 return; 4096 4097 val = le64toh(sc->sc_txstatus); 4098 type = (val >> 30) & 0x3; 4099 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4100 pktretry = val & 0xff; 4101 seq = (val >> 16) & 0xff; 4102 if (pktretry == URTW_TX_MAXRETRY) 4103 counter_u64_add(ic->ic_oerrors, 1); 4104 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4105 pktretry, seq); 4106 } 4107 } 4108 4109 static void 4110 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4111 { 4112 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4113 struct ieee80211com *ic = &sc->sc_ic; 4114 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4115 4116 URTW_ASSERT_LOCKED(sc); 4117 4118 switch (USB_GET_STATE(xfer)) { 4119 case USB_ST_TRANSFERRED: 4120 urtw_txstatus_eof(xfer); 4121 /* FALLTHROUGH */ 4122 case USB_ST_SETUP: 4123 setup: 4124 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4125 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4126 usbd_transfer_submit(xfer); 4127 break; 4128 default: 4129 if (error != USB_ERR_CANCELLED) { 4130 usbd_xfer_set_stall(xfer); 4131 counter_u64_add(ic->ic_ierrors, 1); 4132 goto setup; 4133 } 4134 break; 4135 } 4136 } 4137 4138 static void 4139 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4140 { 4141 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4142 4143 URTW_ASSERT_LOCKED(sc); 4144 4145 if (data->m) { 4146 /* XXX status? */ 4147 ieee80211_tx_complete(data->ni, data->m, 0); 4148 data->m = NULL; 4149 data->ni = NULL; 4150 } 4151 sc->sc_txtimer = 0; 4152 } 4153 4154 static void 4155 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4156 { 4157 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4158 struct urtw_data *data; 4159 4160 URTW_ASSERT_LOCKED(sc); 4161 4162 switch (USB_GET_STATE(xfer)) { 4163 case USB_ST_TRANSFERRED: 4164 data = STAILQ_FIRST(&sc->sc_tx_active); 4165 if (data == NULL) 4166 goto setup; 4167 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4168 urtw_txeof(xfer, data); 4169 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4170 /* FALLTHROUGH */ 4171 case USB_ST_SETUP: 4172 setup: 4173 data = STAILQ_FIRST(&sc->sc_tx_pending); 4174 if (data == NULL) { 4175 DPRINTF(sc, URTW_DEBUG_XMIT, 4176 "%s: empty pending queue\n", __func__); 4177 return; 4178 } 4179 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4180 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4181 4182 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4183 usbd_transfer_submit(xfer); 4184 4185 urtw_start(sc); 4186 break; 4187 default: 4188 data = STAILQ_FIRST(&sc->sc_tx_active); 4189 if (data == NULL) 4190 goto setup; 4191 if (data->ni != NULL) { 4192 if_inc_counter(data->ni->ni_vap->iv_ifp, 4193 IFCOUNTER_OERRORS, 1); 4194 ieee80211_free_node(data->ni); 4195 data->ni = NULL; 4196 } 4197 if (error != USB_ERR_CANCELLED) { 4198 usbd_xfer_set_stall(xfer); 4199 goto setup; 4200 } 4201 break; 4202 } 4203 } 4204 4205 static struct urtw_data * 4206 _urtw_getbuf(struct urtw_softc *sc) 4207 { 4208 struct urtw_data *bf; 4209 4210 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4211 if (bf != NULL) 4212 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4213 else 4214 bf = NULL; 4215 if (bf == NULL) 4216 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4217 "out of xmit buffers"); 4218 return (bf); 4219 } 4220 4221 static struct urtw_data * 4222 urtw_getbuf(struct urtw_softc *sc) 4223 { 4224 struct urtw_data *bf; 4225 4226 URTW_ASSERT_LOCKED(sc); 4227 4228 bf = _urtw_getbuf(sc); 4229 if (bf == NULL) 4230 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4231 return (bf); 4232 } 4233 4234 static int 4235 urtw_isbmode(uint16_t rate) 4236 { 4237 4238 return ((rate <= 22 && rate != 12 && rate != 18) || 4239 rate == 44) ? (1) : (0); 4240 } 4241 4242 static uint16_t 4243 urtw_rate2dbps(uint16_t rate) 4244 { 4245 4246 switch(rate) { 4247 case 12: 4248 case 18: 4249 case 24: 4250 case 36: 4251 case 48: 4252 case 72: 4253 case 96: 4254 case 108: 4255 return (rate * 2); 4256 default: 4257 break; 4258 } 4259 return (24); 4260 } 4261 4262 static int 4263 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4264 uint8_t ismgt, uint8_t isshort) 4265 { 4266 uint16_t ceiling, frametime, n_dbps; 4267 4268 if (urtw_isbmode(rate)) { 4269 if (ismgt || !isshort || rate == 2) 4270 frametime = (uint16_t)(144 + 48 + 4271 (framelen * 8 / (rate / 2))); 4272 else 4273 frametime = (uint16_t)(72 + 24 + 4274 (framelen * 8 / (rate / 2))); 4275 if ((framelen * 8 % (rate / 2)) != 0) 4276 frametime++; 4277 } else { 4278 n_dbps = urtw_rate2dbps(rate); 4279 ceiling = (16 + 8 * framelen + 6) / n_dbps 4280 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4281 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4282 } 4283 return (frametime); 4284 } 4285 4286 /* 4287 * Callback from the 802.11 layer to update the 4288 * slot time based on the current setting. 4289 */ 4290 static void 4291 urtw_updateslot(struct ieee80211com *ic) 4292 { 4293 struct urtw_softc *sc = ic->ic_softc; 4294 4295 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4296 } 4297 4298 static void 4299 urtw_updateslottask(void *arg, int pending) 4300 { 4301 struct urtw_softc *sc = arg; 4302 struct ieee80211com *ic = &sc->sc_ic; 4303 int error; 4304 4305 URTW_LOCK(sc); 4306 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4307 URTW_UNLOCK(sc); 4308 return; 4309 } 4310 if (sc->sc_flags & URTW_RTL8187B) { 4311 urtw_write8_m(sc, URTW_SIFS, 0x22); 4312 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4313 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4314 else 4315 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4316 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4317 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4318 } else { 4319 urtw_write8_m(sc, URTW_SIFS, 0x22); 4320 if (sc->sc_state == IEEE80211_S_ASSOC && 4321 ic->ic_flags & IEEE80211_F_SHSLOT) 4322 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4323 else 4324 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4325 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4326 urtw_write8_m(sc, URTW_DIFS, 0x14); 4327 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4328 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4329 } else { 4330 urtw_write8_m(sc, URTW_DIFS, 0x24); 4331 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4332 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4333 } 4334 } 4335 fail: 4336 URTW_UNLOCK(sc); 4337 } 4338 4339 static void 4340 urtw_sysctl_node(struct urtw_softc *sc) 4341 { 4342 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4343 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4344 struct sysctl_ctx_list *ctx; 4345 struct sysctl_oid_list *child, *parent; 4346 struct sysctl_oid *tree; 4347 struct urtw_stats *stats = &sc->sc_stats; 4348 4349 ctx = device_get_sysctl_ctx(sc->sc_dev); 4350 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4351 4352 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4353 NULL, "URTW statistics"); 4354 parent = SYSCTL_CHILDREN(tree); 4355 4356 /* Tx statistics. */ 4357 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4358 NULL, "Tx MAC statistics"); 4359 child = SYSCTL_CHILDREN(tree); 4360 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4361 "1 Mbit/s"); 4362 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4363 "2 Mbit/s"); 4364 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4365 "5.5 Mbit/s"); 4366 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4367 "6 Mbit/s"); 4368 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4369 "9 Mbit/s"); 4370 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4371 "11 Mbit/s"); 4372 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4373 "12 Mbit/s"); 4374 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4375 "18 Mbit/s"); 4376 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4377 "24 Mbit/s"); 4378 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4379 "36 Mbit/s"); 4380 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4381 "48 Mbit/s"); 4382 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4383 "54 Mbit/s"); 4384 #undef URTW_SYSCTL_STAT_ADD32 4385 } 4386 4387 static device_method_t urtw_methods[] = { 4388 DEVMETHOD(device_probe, urtw_match), 4389 DEVMETHOD(device_attach, urtw_attach), 4390 DEVMETHOD(device_detach, urtw_detach), 4391 DEVMETHOD_END 4392 }; 4393 static driver_t urtw_driver = { 4394 .name = "urtw", 4395 .methods = urtw_methods, 4396 .size = sizeof(struct urtw_softc) 4397 }; 4398 static devclass_t urtw_devclass; 4399 4400 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4401 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4402 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4403 MODULE_VERSION(urtw, 1); 4404 USB_PNP_HOST_INFO(urtw_devs); 4405