1 /*- 2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include <sys/cdefs.h> 18 __FBSDID("$FreeBSD$"); 19 #include <sys/param.h> 20 #include <sys/sockio.h> 21 #include <sys/sysctl.h> 22 #include <sys/lock.h> 23 #include <sys/mutex.h> 24 #include <sys/mbuf.h> 25 #include <sys/kernel.h> 26 #include <sys/socket.h> 27 #include <sys/systm.h> 28 #include <sys/malloc.h> 29 #include <sys/module.h> 30 #include <sys/bus.h> 31 #include <sys/endian.h> 32 #include <sys/kdb.h> 33 34 #include <machine/bus.h> 35 #include <machine/resource.h> 36 #include <sys/rman.h> 37 38 #include <net/if.h> 39 #include <net/if_var.h> 40 #include <net/if_arp.h> 41 #include <net/ethernet.h> 42 #include <net/if_dl.h> 43 #include <net/if_media.h> 44 #include <net/if_types.h> 45 46 #ifdef INET 47 #include <netinet/in.h> 48 #include <netinet/in_systm.h> 49 #include <netinet/in_var.h> 50 #include <netinet/if_ether.h> 51 #include <netinet/ip.h> 52 #endif 53 54 #include <net80211/ieee80211_var.h> 55 #include <net80211/ieee80211_regdomain.h> 56 #include <net80211/ieee80211_radiotap.h> 57 58 #include <dev/usb/usb.h> 59 #include <dev/usb/usbdi.h> 60 #include "usbdevs.h" 61 62 #include <dev/usb/wlan/if_urtwreg.h> 63 #include <dev/usb/wlan/if_urtwvar.h> 64 65 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L"); 66 #ifdef URTW_DEBUG 67 int urtw_debug = 0; 68 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0, 69 "control debugging printfs"); 70 enum { 71 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 72 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */ 73 URTW_DEBUG_RESET = 0x00000004, /* reset processing */ 74 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 75 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 76 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */ 77 URTW_DEBUG_STAT = 0x00000040, /* statistic */ 78 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */ 79 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */ 80 URTW_DEBUG_ANY = 0xffffffff 81 }; 82 #define DPRINTF(sc, m, fmt, ...) do { \ 83 if (sc->sc_debug & (m)) \ 84 printf(fmt, __VA_ARGS__); \ 85 } while (0) 86 #else 87 #define DPRINTF(sc, m, fmt, ...) do { \ 88 (void) sc; \ 89 } while (0) 90 #endif 91 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG; 92 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RWTUN, 93 &urtw_preamble_mode, 0, "set the preable mode (long or short)"); 94 95 /* recognized device vendors/products */ 96 #define urtw_lookup(v, p) \ 97 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p)) 98 #define URTW_DEV_B(v,p) \ 99 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) } 100 #define URTW_DEV_L(v,p) \ 101 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) } 102 #define URTW_REV_RTL8187B 0 103 #define URTW_REV_RTL8187L 1 104 static const STRUCT_USB_HOST_ID urtw_devs[] = { 105 URTW_DEV_B(NETGEAR, WG111V3), 106 URTW_DEV_B(REALTEK, RTL8187B_0), 107 URTW_DEV_B(REALTEK, RTL8187B_1), 108 URTW_DEV_B(REALTEK, RTL8187B_2), 109 URTW_DEV_B(SITECOMEU, WL168V4), 110 URTW_DEV_L(ASUS, P5B_WIFI), 111 URTW_DEV_L(BELKIN, F5D7050E), 112 URTW_DEV_L(LINKSYS4, WUSB54GCV2), 113 URTW_DEV_L(NETGEAR, WG111V2), 114 URTW_DEV_L(REALTEK, RTL8187), 115 URTW_DEV_L(SITECOMEU, WL168V1), 116 URTW_DEV_L(SURECOM, EP9001G2A), 117 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) }, 118 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) }, 119 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) }, 120 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) }, 121 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) }, 122 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) }, 123 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) }, 124 #undef URTW_DEV_L 125 #undef URTW_DEV_B 126 }; 127 128 #define urtw_read8_m(sc, val, data) do { \ 129 error = urtw_read8_c(sc, val, data); \ 130 if (error != 0) \ 131 goto fail; \ 132 } while (0) 133 #define urtw_write8_m(sc, val, data) do { \ 134 error = urtw_write8_c(sc, val, data); \ 135 if (error != 0) \ 136 goto fail; \ 137 } while (0) 138 #define urtw_read16_m(sc, val, data) do { \ 139 error = urtw_read16_c(sc, val, data); \ 140 if (error != 0) \ 141 goto fail; \ 142 } while (0) 143 #define urtw_write16_m(sc, val, data) do { \ 144 error = urtw_write16_c(sc, val, data); \ 145 if (error != 0) \ 146 goto fail; \ 147 } while (0) 148 #define urtw_read32_m(sc, val, data) do { \ 149 error = urtw_read32_c(sc, val, data); \ 150 if (error != 0) \ 151 goto fail; \ 152 } while (0) 153 #define urtw_write32_m(sc, val, data) do { \ 154 error = urtw_write32_c(sc, val, data); \ 155 if (error != 0) \ 156 goto fail; \ 157 } while (0) 158 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \ 159 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \ 160 if (error != 0) \ 161 goto fail; \ 162 } while (0) 163 #define urtw_8187_write_phy_cck(sc, val, data) do { \ 164 error = urtw_8187_write_phy_cck_c(sc, val, data); \ 165 if (error != 0) \ 166 goto fail; \ 167 } while (0) 168 #define urtw_8225_write(sc, val, data) do { \ 169 error = urtw_8225_write_c(sc, val, data); \ 170 if (error != 0) \ 171 goto fail; \ 172 } while (0) 173 174 struct urtw_pair { 175 uint32_t reg; 176 uint32_t val; 177 }; 178 179 static uint8_t urtw_8225_agc[] = { 180 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b, 181 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 182 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85, 183 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a, 184 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 185 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 186 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19, 187 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 188 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03, 189 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 190 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 191 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 192 }; 193 194 static uint8_t urtw_8225z2_agc[] = { 195 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51, 196 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b, 197 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25, 198 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f, 199 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 200 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19, 201 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23, 202 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a, 203 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d, 204 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31, 205 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 206 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31 207 }; 208 209 static uint32_t urtw_8225_channel[] = { 210 0x0000, /* dummy channel 0 */ 211 0x085c, /* 1 */ 212 0x08dc, /* 2 */ 213 0x095c, /* 3 */ 214 0x09dc, /* 4 */ 215 0x0a5c, /* 5 */ 216 0x0adc, /* 6 */ 217 0x0b5c, /* 7 */ 218 0x0bdc, /* 8 */ 219 0x0c5c, /* 9 */ 220 0x0cdc, /* 10 */ 221 0x0d5c, /* 11 */ 222 0x0ddc, /* 12 */ 223 0x0e5c, /* 13 */ 224 0x0f72, /* 14 */ 225 }; 226 227 static uint8_t urtw_8225_gain[] = { 228 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */ 229 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */ 230 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */ 231 0x33, 0x80, 0x79, 0xc5, /* -78dbm */ 232 0x43, 0x78, 0x76, 0xc5, /* -74dbm */ 233 0x53, 0x60, 0x73, 0xc5, /* -70dbm */ 234 0x63, 0x58, 0x70, 0xc5, /* -66dbm */ 235 }; 236 237 static struct urtw_pair urtw_8225_rf_part1[] = { 238 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 239 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a }, 240 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 }, 241 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 }, 242 }; 243 244 static struct urtw_pair urtw_8225_rf_part2[] = { 245 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 246 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 247 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 }, 248 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 }, 249 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 }, 250 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef }, 251 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 }, 252 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 }, 253 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 }, 254 { 0x27, 0x88 } 255 }; 256 257 static struct urtw_pair urtw_8225_rf_part3[] = { 258 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 259 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b }, 260 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, 261 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d }, 262 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e }, 263 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a }, 264 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 } 265 }; 266 267 static uint16_t urtw_8225_rxgain[] = { 268 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 269 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 270 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 271 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 272 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 273 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 274 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 275 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 276 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 277 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 278 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3, 279 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb 280 }; 281 282 static uint8_t urtw_8225_threshold[] = { 283 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd, 284 }; 285 286 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = { 287 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e 288 }; 289 290 static uint8_t urtw_8225_txpwr_cck[] = { 291 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02, 292 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02, 293 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02, 294 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02, 295 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03, 296 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03 297 }; 298 299 static uint8_t urtw_8225_txpwr_cck_ch14[] = { 300 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00, 301 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00, 302 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00, 303 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00, 304 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00, 305 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00 306 }; 307 308 static uint8_t urtw_8225_txpwr_ofdm[]={ 309 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4 310 }; 311 312 static uint8_t urtw_8225v2_gain_bg[]={ 313 0x23, 0x15, 0xa5, /* -82-1dbm */ 314 0x23, 0x15, 0xb5, /* -82-2dbm */ 315 0x23, 0x15, 0xc5, /* -82-3dbm */ 316 0x33, 0x15, 0xc5, /* -78dbm */ 317 0x43, 0x15, 0xc5, /* -74dbm */ 318 0x53, 0x15, 0xc5, /* -70dbm */ 319 0x63, 0x15, 0xc5, /* -66dbm */ 320 }; 321 322 static struct urtw_pair urtw_8225v2_rf_part1[] = { 323 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 324 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 325 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 326 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 327 }; 328 329 static struct urtw_pair urtw_8225v2b_rf_part0[] = { 330 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 }, 331 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a }, 332 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb }, 333 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 } 334 }; 335 336 static struct urtw_pair urtw_8225v2b_rf_part1[] = { 337 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00}, 338 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43}, 339 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46}, 340 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00}, 341 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00}, 342 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00}, 343 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b}, 344 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09}, 345 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff}, 346 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e}, 347 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03}, 348 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06}, 349 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00}, 350 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68}, 351 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d}, 352 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08}, 353 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04}, 354 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23}, 355 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08}, 356 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08}, 357 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08}, 358 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56}, 359 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f}, 360 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24}, 361 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07}, 362 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12}, 363 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a}, 364 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80}, 365 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03}, 366 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01}, 367 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00} 368 }; 369 370 static struct urtw_pair urtw_8225v2_rf_part2[] = { 371 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 }, 372 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 }, 373 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 }, 374 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, 375 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 }, 376 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, 377 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 }, 378 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 }, 379 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 }, 380 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 } 381 }; 382 383 static struct urtw_pair urtw_8225v2b_rf_part2[] = { 384 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 }, 385 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 }, 386 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 }, 387 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 }, 388 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 }, 389 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 }, 390 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 }, 391 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 }, 392 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a }, 393 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f }, 394 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 }, 395 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 }, 396 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 }, 397 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e }, 398 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 } 399 }; 400 401 static struct urtw_pair urtw_8225v2_rf_part3[] = { 402 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 }, 403 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 }, 404 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 }, 405 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 }, 406 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d }, 407 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 }, 408 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 }, 409 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 } 410 }; 411 412 static uint16_t urtw_8225v2_rxgain[] = { 413 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009, 414 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141, 415 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183, 416 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244, 417 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288, 418 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345, 419 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389, 420 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393, 421 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d, 422 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9, 423 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 424 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 425 }; 426 427 static uint16_t urtw_8225v2b_rxgain[] = { 428 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409, 429 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541, 430 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583, 431 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644, 432 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688, 433 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745, 434 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789, 435 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793, 436 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d, 437 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9, 438 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3, 439 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb 440 }; 441 442 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = { 443 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 444 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 445 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11, 446 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 447 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 448 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23, 449 }; 450 451 static uint8_t urtw_8225v2_txpwr_cck[] = { 452 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04 453 }; 454 455 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = { 456 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00 457 }; 458 459 static uint8_t urtw_8225v2b_txpwr_cck[] = { 460 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04, 461 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03, 462 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03, 463 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03 464 }; 465 466 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = { 467 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00, 468 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 469 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00, 470 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00 471 }; 472 473 static struct urtw_pair urtw_ratetable[] = { 474 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 }, 475 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 }, 476 { 96, 10 }, { 108, 11 } 477 }; 478 479 #if 0 480 static const uint8_t urtw_8187b_reg_table[][3] = { 481 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 }, 482 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 }, 483 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 }, 484 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 }, 485 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 }, 486 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 }, 487 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 }, 488 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 }, 489 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 }, 490 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 }, 491 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 }, 492 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 }, 493 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 }, 494 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 }, 495 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 }, 496 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 }, 497 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 }, 498 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 }, 499 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 }, 500 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 }, 501 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 }, 502 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 }, 503 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 }, 504 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 }, 505 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 }, 506 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 }, 507 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 }, 508 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 }, 509 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 }, 510 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 }, 511 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 } 512 }; 513 #endif 514 515 static usb_callback_t urtw_bulk_rx_callback; 516 static usb_callback_t urtw_bulk_tx_callback; 517 static usb_callback_t urtw_bulk_tx_status_callback; 518 519 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = { 520 [URTW_8187B_BULK_RX] = { 521 .type = UE_BULK, 522 .endpoint = 0x83, 523 .direction = UE_DIR_IN, 524 .bufsize = MCLBYTES, 525 .flags = { 526 .ext_buffer = 1, 527 .pipe_bof = 1, 528 .short_xfer_ok = 1 529 }, 530 .callback = urtw_bulk_rx_callback 531 }, 532 [URTW_8187B_BULK_TX_STATUS] = { 533 .type = UE_BULK, 534 .endpoint = 0x89, 535 .direction = UE_DIR_IN, 536 .bufsize = sizeof(uint64_t), 537 .flags = { 538 .pipe_bof = 1, 539 .short_xfer_ok = 1 540 }, 541 .callback = urtw_bulk_tx_status_callback 542 }, 543 [URTW_8187B_BULK_TX_BE] = { 544 .type = UE_BULK, 545 .endpoint = URTW_8187B_TXPIPE_BE, 546 .direction = UE_DIR_OUT, 547 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 548 .flags = { 549 .force_short_xfer = 1, 550 .pipe_bof = 1, 551 }, 552 .callback = urtw_bulk_tx_callback, 553 .timeout = URTW_DATA_TIMEOUT 554 }, 555 [URTW_8187B_BULK_TX_BK] = { 556 .type = UE_BULK, 557 .endpoint = URTW_8187B_TXPIPE_BK, 558 .direction = UE_DIR_OUT, 559 .bufsize = URTW_TX_MAXSIZE, 560 .flags = { 561 .ext_buffer = 1, 562 .force_short_xfer = 1, 563 .pipe_bof = 1, 564 }, 565 .callback = urtw_bulk_tx_callback, 566 .timeout = URTW_DATA_TIMEOUT 567 }, 568 [URTW_8187B_BULK_TX_VI] = { 569 .type = UE_BULK, 570 .endpoint = URTW_8187B_TXPIPE_VI, 571 .direction = UE_DIR_OUT, 572 .bufsize = URTW_TX_MAXSIZE, 573 .flags = { 574 .ext_buffer = 1, 575 .force_short_xfer = 1, 576 .pipe_bof = 1, 577 }, 578 .callback = urtw_bulk_tx_callback, 579 .timeout = URTW_DATA_TIMEOUT 580 }, 581 [URTW_8187B_BULK_TX_VO] = { 582 .type = UE_BULK, 583 .endpoint = URTW_8187B_TXPIPE_VO, 584 .direction = UE_DIR_OUT, 585 .bufsize = URTW_TX_MAXSIZE, 586 .flags = { 587 .ext_buffer = 1, 588 .force_short_xfer = 1, 589 .pipe_bof = 1, 590 }, 591 .callback = urtw_bulk_tx_callback, 592 .timeout = URTW_DATA_TIMEOUT 593 }, 594 [URTW_8187B_BULK_TX_EP12] = { 595 .type = UE_BULK, 596 .endpoint = 0xc, 597 .direction = UE_DIR_OUT, 598 .bufsize = URTW_TX_MAXSIZE, 599 .flags = { 600 .ext_buffer = 1, 601 .force_short_xfer = 1, 602 .pipe_bof = 1, 603 }, 604 .callback = urtw_bulk_tx_callback, 605 .timeout = URTW_DATA_TIMEOUT 606 } 607 }; 608 609 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = { 610 [URTW_8187L_BULK_RX] = { 611 .type = UE_BULK, 612 .endpoint = 0x81, 613 .direction = UE_DIR_IN, 614 .bufsize = MCLBYTES, 615 .flags = { 616 .ext_buffer = 1, 617 .pipe_bof = 1, 618 .short_xfer_ok = 1 619 }, 620 .callback = urtw_bulk_rx_callback 621 }, 622 [URTW_8187L_BULK_TX_LOW] = { 623 .type = UE_BULK, 624 .endpoint = 0x2, 625 .direction = UE_DIR_OUT, 626 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT, 627 .flags = { 628 .force_short_xfer = 1, 629 .pipe_bof = 1, 630 }, 631 .callback = urtw_bulk_tx_callback, 632 .timeout = URTW_DATA_TIMEOUT 633 }, 634 [URTW_8187L_BULK_TX_NORMAL] = { 635 .type = UE_BULK, 636 .endpoint = 0x3, 637 .direction = UE_DIR_OUT, 638 .bufsize = URTW_TX_MAXSIZE, 639 .flags = { 640 .ext_buffer = 1, 641 .force_short_xfer = 1, 642 .pipe_bof = 1, 643 }, 644 .callback = urtw_bulk_tx_callback, 645 .timeout = URTW_DATA_TIMEOUT 646 }, 647 }; 648 649 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *, 650 const char [IFNAMSIZ], int, enum ieee80211_opmode, 651 int, const uint8_t [IEEE80211_ADDR_LEN], 652 const uint8_t [IEEE80211_ADDR_LEN]); 653 static void urtw_vap_delete(struct ieee80211vap *); 654 static void urtw_init(struct urtw_softc *); 655 static void urtw_stop(struct urtw_softc *); 656 static void urtw_parent(struct ieee80211com *); 657 static int urtw_transmit(struct ieee80211com *, struct mbuf *); 658 static void urtw_start(struct urtw_softc *); 659 static int urtw_alloc_rx_data_list(struct urtw_softc *); 660 static int urtw_alloc_tx_data_list(struct urtw_softc *); 661 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *, 662 const struct ieee80211_bpf_params *); 663 static void urtw_scan_start(struct ieee80211com *); 664 static void urtw_scan_end(struct ieee80211com *); 665 static void urtw_set_channel(struct ieee80211com *); 666 static void urtw_update_mcast(struct ieee80211com *); 667 static int urtw_tx_start(struct urtw_softc *, 668 struct ieee80211_node *, struct mbuf *, 669 struct urtw_data *, int); 670 static int urtw_newstate(struct ieee80211vap *, 671 enum ieee80211_state, int); 672 static void urtw_led_ch(void *); 673 static void urtw_ledtask(void *, int); 674 static void urtw_watchdog(void *); 675 static void urtw_set_multi(void *); 676 static int urtw_isbmode(uint16_t); 677 static uint16_t urtw_rate2rtl(uint32_t); 678 static uint16_t urtw_rtl2rate(uint32_t); 679 static usb_error_t urtw_set_rate(struct urtw_softc *); 680 static usb_error_t urtw_update_msr(struct urtw_softc *); 681 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *); 682 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *); 683 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *); 684 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t); 685 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t); 686 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t); 687 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int); 688 static usb_error_t urtw_eprom_ck(struct urtw_softc *); 689 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *, 690 int); 691 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t, 692 uint32_t *); 693 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *); 694 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t); 695 static usb_error_t urtw_get_macaddr(struct urtw_softc *); 696 static usb_error_t urtw_get_txpwr(struct urtw_softc *); 697 static usb_error_t urtw_get_rfchip(struct urtw_softc *); 698 static usb_error_t urtw_led_init(struct urtw_softc *); 699 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *); 700 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t); 701 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t, 702 uint32_t); 703 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *, 704 uint8_t, uint32_t); 705 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t, 706 uint32_t); 707 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t); 708 static usb_error_t urtw_8225_usb_init(struct urtw_softc *); 709 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t, 710 uint16_t); 711 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int, 712 uint16_t *); 713 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t, 714 uint32_t *); 715 static usb_error_t urtw_8225_rf_init(struct urtw_softc *); 716 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int); 717 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int); 718 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int); 719 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *); 720 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *); 721 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int); 722 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int); 723 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t); 724 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *); 725 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *); 726 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int); 727 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *); 728 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t); 729 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t); 730 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t); 731 static usb_error_t urtw_intr_enable(struct urtw_softc *); 732 static usb_error_t urtw_intr_disable(struct urtw_softc *); 733 static usb_error_t urtw_reset(struct urtw_softc *); 734 static usb_error_t urtw_led_on(struct urtw_softc *, int); 735 static usb_error_t urtw_led_ctl(struct urtw_softc *, int); 736 static usb_error_t urtw_led_blink(struct urtw_softc *); 737 static usb_error_t urtw_led_mode0(struct urtw_softc *, int); 738 static usb_error_t urtw_led_mode1(struct urtw_softc *, int); 739 static usb_error_t urtw_led_mode2(struct urtw_softc *, int); 740 static usb_error_t urtw_led_mode3(struct urtw_softc *, int); 741 static usb_error_t urtw_rx_setconf(struct urtw_softc *); 742 static usb_error_t urtw_rx_enable(struct urtw_softc *); 743 static usb_error_t urtw_tx_enable(struct urtw_softc *sc); 744 static void urtw_free_tx_data_list(struct urtw_softc *); 745 static void urtw_free_rx_data_list(struct urtw_softc *); 746 static void urtw_free_data_list(struct urtw_softc *, 747 struct urtw_data data[], int, int); 748 static usb_error_t urtw_adapter_start(struct urtw_softc *); 749 static usb_error_t urtw_adapter_start_b(struct urtw_softc *); 750 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t); 751 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *); 752 static usb_error_t urtw_do_request(struct urtw_softc *, 753 struct usb_device_request *, void *); 754 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int); 755 static usb_error_t urtw_led_off(struct urtw_softc *, int); 756 static void urtw_abort_xfers(struct urtw_softc *); 757 static struct urtw_data * 758 urtw_getbuf(struct urtw_softc *sc); 759 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t, 760 uint8_t); 761 static void urtw_updateslot(struct ieee80211com *); 762 static void urtw_updateslottask(void *, int); 763 static void urtw_sysctl_node(struct urtw_softc *); 764 765 static int 766 urtw_match(device_t dev) 767 { 768 struct usb_attach_arg *uaa = device_get_ivars(dev); 769 770 if (uaa->usb_mode != USB_MODE_HOST) 771 return (ENXIO); 772 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX) 773 return (ENXIO); 774 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX) 775 return (ENXIO); 776 777 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa)); 778 } 779 780 static int 781 urtw_attach(device_t dev) 782 { 783 const struct usb_config *setup_start; 784 int ret = ENXIO; 785 struct urtw_softc *sc = device_get_softc(dev); 786 struct usb_attach_arg *uaa = device_get_ivars(dev); 787 struct ieee80211com *ic = &sc->sc_ic; 788 uint8_t bands[howmany(IEEE80211_MODE_MAX, 8)]; 789 uint8_t iface_index = URTW_IFACE_INDEX; /* XXX */ 790 uint16_t n_setup; 791 uint32_t data; 792 usb_error_t error; 793 794 device_set_usb_desc(dev); 795 796 sc->sc_dev = dev; 797 sc->sc_udev = uaa->device; 798 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B) 799 sc->sc_flags |= URTW_RTL8187B; 800 #ifdef URTW_DEBUG 801 sc->sc_debug = urtw_debug; 802 #endif 803 804 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 805 MTX_DEF); 806 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0); 807 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc); 808 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc); 809 callout_init(&sc->sc_watchdog_ch, 0); 810 mbufq_init(&sc->sc_snd, ifqmaxlen); 811 812 if (sc->sc_flags & URTW_RTL8187B) { 813 setup_start = urtw_8187b_usbconfig; 814 n_setup = URTW_8187B_N_XFERS; 815 } else { 816 setup_start = urtw_8187l_usbconfig; 817 n_setup = URTW_8187L_N_XFERS; 818 } 819 820 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 821 setup_start, n_setup, sc, &sc->sc_mtx); 822 if (error) { 823 device_printf(dev, "could not allocate USB transfers, " 824 "err=%s\n", usbd_errstr(error)); 825 ret = ENXIO; 826 goto fail0; 827 } 828 829 if (sc->sc_flags & URTW_RTL8187B) { 830 sc->sc_tx_dma_buf = 831 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 832 URTW_8187B_BULK_TX_BE], 0); 833 } else { 834 sc->sc_tx_dma_buf = 835 usbd_xfer_get_frame_buffer(sc->sc_xfer[ 836 URTW_8187L_BULK_TX_LOW], 0); 837 } 838 839 URTW_LOCK(sc); 840 841 urtw_read32_m(sc, URTW_RX, &data); 842 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 : 843 URTW_EEPROM_93C46; 844 845 error = urtw_get_rfchip(sc); 846 if (error != 0) 847 goto fail; 848 error = urtw_get_macaddr(sc); 849 if (error != 0) 850 goto fail; 851 error = urtw_get_txpwr(sc); 852 if (error != 0) 853 goto fail; 854 error = urtw_led_init(sc); 855 if (error != 0) 856 goto fail; 857 858 URTW_UNLOCK(sc); 859 860 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY; 861 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY; 862 sc->sc_currate = 3; 863 sc->sc_preamble_mode = urtw_preamble_mode; 864 865 ic->ic_softc = sc; 866 ic->ic_name = device_get_nameunit(dev); 867 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 868 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 869 870 /* set device capabilities */ 871 ic->ic_caps = 872 IEEE80211_C_STA | /* station mode */ 873 IEEE80211_C_MONITOR | /* monitor mode supported */ 874 IEEE80211_C_TXPMGT | /* tx power management */ 875 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 876 IEEE80211_C_SHSLOT | /* short slot time supported */ 877 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 878 IEEE80211_C_WPA; /* 802.11i */ 879 880 memset(bands, 0, sizeof(bands)); 881 setbit(bands, IEEE80211_MODE_11B); 882 setbit(bands, IEEE80211_MODE_11G); 883 ieee80211_init_channels(ic, NULL, bands); 884 885 ieee80211_ifattach(ic); 886 ic->ic_raw_xmit = urtw_raw_xmit; 887 ic->ic_scan_start = urtw_scan_start; 888 ic->ic_scan_end = urtw_scan_end; 889 ic->ic_set_channel = urtw_set_channel; 890 ic->ic_updateslot = urtw_updateslot; 891 ic->ic_vap_create = urtw_vap_create; 892 ic->ic_vap_delete = urtw_vap_delete; 893 ic->ic_update_mcast = urtw_update_mcast; 894 ic->ic_parent = urtw_parent; 895 ic->ic_transmit = urtw_transmit; 896 897 ieee80211_radiotap_attach(ic, 898 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 899 URTW_TX_RADIOTAP_PRESENT, 900 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 901 URTW_RX_RADIOTAP_PRESENT); 902 903 urtw_sysctl_node(sc); 904 905 if (bootverbose) 906 ieee80211_announce(ic); 907 return (0); 908 909 fail: 910 URTW_UNLOCK(sc); 911 usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ? 912 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS); 913 fail0: 914 return (ret); 915 } 916 917 static int 918 urtw_detach(device_t dev) 919 { 920 struct urtw_softc *sc = device_get_softc(dev); 921 struct ieee80211com *ic = &sc->sc_ic; 922 unsigned int x; 923 unsigned int n_xfers; 924 925 /* Prevent further ioctls */ 926 URTW_LOCK(sc); 927 sc->sc_flags |= URTW_DETACHED; 928 urtw_stop(sc); 929 URTW_UNLOCK(sc); 930 931 ieee80211_draintask(ic, &sc->sc_updateslot_task); 932 ieee80211_draintask(ic, &sc->sc_led_task); 933 934 usb_callout_drain(&sc->sc_led_ch); 935 callout_drain(&sc->sc_watchdog_ch); 936 937 n_xfers = (sc->sc_flags & URTW_RTL8187B) ? 938 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS; 939 940 /* prevent further allocations from RX/TX data lists */ 941 URTW_LOCK(sc); 942 STAILQ_INIT(&sc->sc_tx_active); 943 STAILQ_INIT(&sc->sc_tx_inactive); 944 STAILQ_INIT(&sc->sc_tx_pending); 945 946 STAILQ_INIT(&sc->sc_rx_active); 947 STAILQ_INIT(&sc->sc_rx_inactive); 948 URTW_UNLOCK(sc); 949 950 /* drain USB transfers */ 951 for (x = 0; x != n_xfers; x++) 952 usbd_transfer_drain(sc->sc_xfer[x]); 953 954 /* free data buffers */ 955 URTW_LOCK(sc); 956 urtw_free_tx_data_list(sc); 957 urtw_free_rx_data_list(sc); 958 URTW_UNLOCK(sc); 959 960 /* free USB transfers and some data buffers */ 961 usbd_transfer_unsetup(sc->sc_xfer, n_xfers); 962 963 ieee80211_ifdetach(ic); 964 mbufq_drain(&sc->sc_snd); 965 mtx_destroy(&sc->sc_mtx); 966 return (0); 967 } 968 969 static void 970 urtw_free_tx_data_list(struct urtw_softc *sc) 971 { 972 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0); 973 } 974 975 static void 976 urtw_free_rx_data_list(struct urtw_softc *sc) 977 { 978 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1); 979 } 980 981 static void 982 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata, 983 int fillmbuf) 984 { 985 int i; 986 987 for (i = 0; i < ndata; i++) { 988 struct urtw_data *dp = &data[i]; 989 990 if (fillmbuf == 1) { 991 if (dp->m != NULL) { 992 m_freem(dp->m); 993 dp->m = NULL; 994 dp->buf = NULL; 995 } 996 } else { 997 dp->buf = NULL; 998 } 999 if (dp->ni != NULL) { 1000 ieee80211_free_node(dp->ni); 1001 dp->ni = NULL; 1002 } 1003 } 1004 } 1005 1006 static struct ieee80211vap * 1007 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1008 enum ieee80211_opmode opmode, int flags, 1009 const uint8_t bssid[IEEE80211_ADDR_LEN], 1010 const uint8_t mac[IEEE80211_ADDR_LEN]) 1011 { 1012 struct urtw_vap *uvp; 1013 struct ieee80211vap *vap; 1014 1015 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1016 return (NULL); 1017 uvp = malloc(sizeof(struct urtw_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1018 vap = &uvp->vap; 1019 /* enable s/w bmiss handling for sta mode */ 1020 1021 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 1022 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 1023 /* out of memory */ 1024 free(uvp, M_80211_VAP); 1025 return (NULL); 1026 } 1027 1028 /* override state transition machine */ 1029 uvp->newstate = vap->iv_newstate; 1030 vap->iv_newstate = urtw_newstate; 1031 1032 /* complete setup */ 1033 ieee80211_vap_attach(vap, ieee80211_media_change, 1034 ieee80211_media_status, mac); 1035 ic->ic_opmode = opmode; 1036 return (vap); 1037 } 1038 1039 static void 1040 urtw_vap_delete(struct ieee80211vap *vap) 1041 { 1042 struct urtw_vap *uvp = URTW_VAP(vap); 1043 1044 ieee80211_vap_detach(vap); 1045 free(uvp, M_80211_VAP); 1046 } 1047 1048 static void 1049 urtw_init(struct urtw_softc *sc) 1050 { 1051 usb_error_t error; 1052 int ret; 1053 1054 URTW_ASSERT_LOCKED(sc); 1055 1056 if (sc->sc_flags & URTW_RUNNING) 1057 urtw_stop(sc); 1058 1059 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) : 1060 urtw_adapter_start(sc); 1061 if (error != 0) 1062 goto fail; 1063 1064 /* reset softc variables */ 1065 sc->sc_txtimer = 0; 1066 1067 if (!(sc->sc_flags & URTW_INIT_ONCE)) { 1068 ret = urtw_alloc_rx_data_list(sc); 1069 if (ret != 0) 1070 goto fail; 1071 ret = urtw_alloc_tx_data_list(sc); 1072 if (ret != 0) 1073 goto fail; 1074 sc->sc_flags |= URTW_INIT_ONCE; 1075 } 1076 1077 error = urtw_rx_enable(sc); 1078 if (error != 0) 1079 goto fail; 1080 error = urtw_tx_enable(sc); 1081 if (error != 0) 1082 goto fail; 1083 1084 if (sc->sc_flags & URTW_RTL8187B) 1085 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]); 1086 1087 sc->sc_flags |= URTW_RUNNING; 1088 1089 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1090 fail: 1091 return; 1092 } 1093 1094 static usb_error_t 1095 urtw_adapter_start_b(struct urtw_softc *sc) 1096 { 1097 uint8_t data8; 1098 usb_error_t error; 1099 1100 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1101 if (error) 1102 goto fail; 1103 1104 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1105 urtw_write8_m(sc, URTW_CONFIG3, 1106 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT); 1107 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON); 1108 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON); 1109 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON); 1110 1111 urtw_write8_m(sc, 0x61, 0x10); 1112 urtw_read8_m(sc, 0x62, &data8); 1113 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5)); 1114 urtw_write8_m(sc, 0x62, data8 | (1 << 5)); 1115 1116 urtw_read8_m(sc, URTW_CONFIG3, &data8); 1117 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE; 1118 urtw_write8_m(sc, URTW_CONFIG3, data8); 1119 1120 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1121 if (error) 1122 goto fail; 1123 1124 error = urtw_8187b_cmd_reset(sc); 1125 if (error) 1126 goto fail; 1127 1128 error = sc->sc_rf_init(sc); 1129 if (error != 0) 1130 goto fail; 1131 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1132 1133 /* fix RTL8187B RX stall */ 1134 error = urtw_intr_enable(sc); 1135 if (error) 1136 goto fail; 1137 1138 error = urtw_write8e(sc, 0x41, 0xf4); 1139 if (error) 1140 goto fail; 1141 error = urtw_write8e(sc, 0x40, 0x00); 1142 if (error) 1143 goto fail; 1144 error = urtw_write8e(sc, 0x42, 0x00); 1145 if (error) 1146 goto fail; 1147 error = urtw_write8e(sc, 0x42, 0x01); 1148 if (error) 1149 goto fail; 1150 error = urtw_write8e(sc, 0x40, 0x0f); 1151 if (error) 1152 goto fail; 1153 error = urtw_write8e(sc, 0x42, 0x00); 1154 if (error) 1155 goto fail; 1156 error = urtw_write8e(sc, 0x42, 0x01); 1157 if (error) 1158 goto fail; 1159 1160 urtw_read8_m(sc, 0xdb, &data8); 1161 urtw_write8_m(sc, 0xdb, data8 | (1 << 2)); 1162 urtw_write16_m(sc, 0x372, 0x59fa); 1163 urtw_write16_m(sc, 0x374, 0x59d2); 1164 urtw_write16_m(sc, 0x376, 0x59d2); 1165 urtw_write16_m(sc, 0x378, 0x19fa); 1166 urtw_write16_m(sc, 0x37a, 0x19fa); 1167 urtw_write16_m(sc, 0x37c, 0x00d0); 1168 urtw_write8_m(sc, 0x61, 0); 1169 1170 urtw_write8_m(sc, 0x180, 0x0f); 1171 urtw_write8_m(sc, 0x183, 0x03); 1172 urtw_write8_m(sc, 0xda, 0x10); 1173 urtw_write8_m(sc, 0x24d, 0x08); 1174 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b); 1175 1176 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */ 1177 fail: 1178 return (error); 1179 } 1180 1181 static usb_error_t 1182 urtw_adapter_start(struct urtw_softc *sc) 1183 { 1184 struct ieee80211com *ic = &sc->sc_ic; 1185 usb_error_t error; 1186 1187 error = urtw_reset(sc); 1188 if (error) 1189 goto fail; 1190 1191 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0); 1192 urtw_write8_m(sc, URTW_GPIO, 0); 1193 1194 /* for led */ 1195 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1196 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON); 1197 if (error != 0) 1198 goto fail; 1199 1200 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1201 if (error) 1202 goto fail; 1203 /* applying MAC address again. */ 1204 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 1205 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 1206 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1207 if (error) 1208 goto fail; 1209 1210 error = urtw_update_msr(sc); 1211 if (error) 1212 goto fail; 1213 1214 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0); 1215 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 1216 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1); 1217 error = urtw_set_rate(sc); 1218 if (error != 0) 1219 goto fail; 1220 1221 error = sc->sc_rf_init(sc); 1222 if (error != 0) 1223 goto fail; 1224 if (sc->sc_rf_set_sens != NULL) 1225 sc->sc_rf_set_sens(sc, sc->sc_sens); 1226 1227 /* XXX correct? to call write16 */ 1228 urtw_write16_m(sc, URTW_PSR, 1); 1229 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10); 1230 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80); 1231 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60); 1232 /* XXX correct? to call write16 */ 1233 urtw_write16_m(sc, URTW_PSR, 0); 1234 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4); 1235 1236 error = urtw_intr_enable(sc); 1237 if (error != 0) 1238 goto fail; 1239 1240 fail: 1241 return (error); 1242 } 1243 1244 static usb_error_t 1245 urtw_set_mode(struct urtw_softc *sc, uint32_t mode) 1246 { 1247 uint8_t data; 1248 usb_error_t error; 1249 1250 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 1251 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT); 1252 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK); 1253 urtw_write8_m(sc, URTW_EPROM_CMD, data); 1254 fail: 1255 return (error); 1256 } 1257 1258 static usb_error_t 1259 urtw_8187b_cmd_reset(struct urtw_softc *sc) 1260 { 1261 int i; 1262 uint8_t data8; 1263 usb_error_t error; 1264 1265 /* XXX the code can be duplicate with urtw_reset(). */ 1266 urtw_read8_m(sc, URTW_CMD, &data8); 1267 data8 = (data8 & 0x2) | URTW_CMD_RST; 1268 urtw_write8_m(sc, URTW_CMD, data8); 1269 1270 for (i = 0; i < 20; i++) { 1271 usb_pause_mtx(&sc->sc_mtx, 2); 1272 urtw_read8_m(sc, URTW_CMD, &data8); 1273 if (!(data8 & URTW_CMD_RST)) 1274 break; 1275 } 1276 if (i >= 20) { 1277 device_printf(sc->sc_dev, "reset timeout\n"); 1278 goto fail; 1279 } 1280 fail: 1281 return (error); 1282 } 1283 1284 static usb_error_t 1285 urtw_do_request(struct urtw_softc *sc, 1286 struct usb_device_request *req, void *data) 1287 { 1288 usb_error_t err; 1289 int ntries = 10; 1290 1291 URTW_ASSERT_LOCKED(sc); 1292 1293 while (ntries--) { 1294 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 1295 req, data, 0, NULL, 250 /* ms */); 1296 if (err == 0) 1297 break; 1298 1299 DPRINTF(sc, URTW_DEBUG_INIT, 1300 "Control request failed, %s (retrying)\n", 1301 usbd_errstr(err)); 1302 usb_pause_mtx(&sc->sc_mtx, hz / 100); 1303 } 1304 return (err); 1305 } 1306 1307 static void 1308 urtw_stop(struct urtw_softc *sc) 1309 { 1310 uint8_t data8; 1311 usb_error_t error; 1312 1313 URTW_ASSERT_LOCKED(sc); 1314 1315 sc->sc_flags &= ~URTW_RUNNING; 1316 1317 error = urtw_intr_disable(sc); 1318 if (error) 1319 goto fail; 1320 urtw_read8_m(sc, URTW_CMD, &data8); 1321 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE); 1322 urtw_write8_m(sc, URTW_CMD, data8); 1323 1324 error = sc->sc_rf_stop(sc); 1325 if (error != 0) 1326 goto fail; 1327 1328 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 1329 if (error) 1330 goto fail; 1331 urtw_read8_m(sc, URTW_CONFIG4, &data8); 1332 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF); 1333 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 1334 if (error) 1335 goto fail; 1336 fail: 1337 if (error) 1338 device_printf(sc->sc_dev, "failed to stop (%s)\n", 1339 usbd_errstr(error)); 1340 1341 usb_callout_stop(&sc->sc_led_ch); 1342 callout_stop(&sc->sc_watchdog_ch); 1343 1344 urtw_abort_xfers(sc); 1345 } 1346 1347 static void 1348 urtw_abort_xfers(struct urtw_softc *sc) 1349 { 1350 int i, max; 1351 1352 URTW_ASSERT_LOCKED(sc); 1353 1354 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS : 1355 URTW_8187L_N_XFERS; 1356 1357 /* abort any pending transfers */ 1358 for (i = 0; i < max; i++) 1359 usbd_transfer_stop(sc->sc_xfer[i]); 1360 } 1361 1362 static void 1363 urtw_parent(struct ieee80211com *ic) 1364 { 1365 struct urtw_softc *sc = ic->ic_softc; 1366 int startall = 0; 1367 1368 URTW_LOCK(sc); 1369 if (sc->sc_flags & URTW_DETACHED) { 1370 URTW_UNLOCK(sc); 1371 return; 1372 } 1373 1374 if (ic->ic_nrunning > 0) { 1375 if (sc->sc_flags & URTW_RUNNING) { 1376 if (ic->ic_promisc > 0 || ic->ic_allmulti > 0) 1377 urtw_set_multi(sc); 1378 } else { 1379 urtw_init(sc); 1380 startall = 1; 1381 } 1382 } else if (sc->sc_flags & URTW_RUNNING) 1383 urtw_stop(sc); 1384 URTW_UNLOCK(sc); 1385 if (startall) 1386 ieee80211_start_all(ic); 1387 } 1388 1389 static int 1390 urtw_transmit(struct ieee80211com *ic, struct mbuf *m) 1391 { 1392 struct urtw_softc *sc = ic->ic_softc; 1393 int error; 1394 1395 URTW_LOCK(sc); 1396 if ((sc->sc_flags & URTW_RUNNING) == 0) { 1397 URTW_UNLOCK(sc); 1398 return (ENXIO); 1399 } 1400 error = mbufq_enqueue(&sc->sc_snd, m); 1401 if (error) { 1402 URTW_UNLOCK(sc); 1403 return (error); 1404 } 1405 urtw_start(sc); 1406 URTW_UNLOCK(sc); 1407 1408 return (0); 1409 } 1410 1411 static void 1412 urtw_start(struct urtw_softc *sc) 1413 { 1414 struct urtw_data *bf; 1415 struct ieee80211_node *ni; 1416 struct mbuf *m; 1417 1418 URTW_ASSERT_LOCKED(sc); 1419 1420 if ((sc->sc_flags & URTW_RUNNING) == 0) 1421 return; 1422 1423 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1424 bf = urtw_getbuf(sc); 1425 if (bf == NULL) { 1426 mbufq_prepend(&sc->sc_snd, m); 1427 break; 1428 } 1429 1430 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1431 m->m_pkthdr.rcvif = NULL; 1432 1433 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) { 1434 if_inc_counter(ni->ni_vap->iv_ifp, 1435 IFCOUNTER_OERRORS, 1); 1436 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1437 ieee80211_free_node(ni); 1438 break; 1439 } 1440 1441 sc->sc_txtimer = 5; 1442 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1443 } 1444 } 1445 1446 static int 1447 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[], 1448 int ndata, int maxsz, void *dma_buf) 1449 { 1450 int i, error; 1451 1452 for (i = 0; i < ndata; i++) { 1453 struct urtw_data *dp = &data[i]; 1454 1455 dp->sc = sc; 1456 if (dma_buf == NULL) { 1457 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1458 if (dp->m == NULL) { 1459 device_printf(sc->sc_dev, 1460 "could not allocate rx mbuf\n"); 1461 error = ENOMEM; 1462 goto fail; 1463 } 1464 dp->buf = mtod(dp->m, uint8_t *); 1465 } else { 1466 dp->m = NULL; 1467 dp->buf = ((uint8_t *)dma_buf) + 1468 (i * maxsz); 1469 } 1470 dp->ni = NULL; 1471 } 1472 return (0); 1473 1474 fail: urtw_free_data_list(sc, data, ndata, 1); 1475 return (error); 1476 } 1477 1478 static int 1479 urtw_alloc_rx_data_list(struct urtw_softc *sc) 1480 { 1481 int error, i; 1482 1483 error = urtw_alloc_data_list(sc, 1484 sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1485 MCLBYTES, NULL /* mbufs */); 1486 if (error != 0) 1487 return (error); 1488 1489 STAILQ_INIT(&sc->sc_rx_active); 1490 STAILQ_INIT(&sc->sc_rx_inactive); 1491 1492 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++) 1493 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next); 1494 1495 return (0); 1496 } 1497 1498 static int 1499 urtw_alloc_tx_data_list(struct urtw_softc *sc) 1500 { 1501 int error, i; 1502 1503 error = urtw_alloc_data_list(sc, 1504 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE, 1505 sc->sc_tx_dma_buf /* no mbufs */); 1506 if (error != 0) 1507 return (error); 1508 1509 STAILQ_INIT(&sc->sc_tx_active); 1510 STAILQ_INIT(&sc->sc_tx_inactive); 1511 STAILQ_INIT(&sc->sc_tx_pending); 1512 1513 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++) 1514 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1515 next); 1516 1517 return (0); 1518 } 1519 1520 static int 1521 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1522 const struct ieee80211_bpf_params *params) 1523 { 1524 struct ieee80211com *ic = ni->ni_ic; 1525 struct urtw_softc *sc = ic->ic_softc; 1526 struct urtw_data *bf; 1527 1528 /* prevent management frames from being sent if we're not ready */ 1529 if (!(sc->sc_flags & URTW_RUNNING)) { 1530 m_freem(m); 1531 return ENETDOWN; 1532 } 1533 URTW_LOCK(sc); 1534 bf = urtw_getbuf(sc); 1535 if (bf == NULL) { 1536 m_freem(m); 1537 URTW_UNLOCK(sc); 1538 return (ENOBUFS); /* XXX */ 1539 } 1540 1541 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) { 1542 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1543 URTW_UNLOCK(sc); 1544 return (EIO); 1545 } 1546 URTW_UNLOCK(sc); 1547 1548 sc->sc_txtimer = 5; 1549 return (0); 1550 } 1551 1552 static void 1553 urtw_scan_start(struct ieee80211com *ic) 1554 { 1555 1556 /* XXX do nothing? */ 1557 } 1558 1559 static void 1560 urtw_scan_end(struct ieee80211com *ic) 1561 { 1562 1563 /* XXX do nothing? */ 1564 } 1565 1566 static void 1567 urtw_set_channel(struct ieee80211com *ic) 1568 { 1569 struct urtw_softc *sc = ic->ic_softc; 1570 uint32_t data, orig; 1571 usb_error_t error; 1572 1573 /* 1574 * if the user set a channel explicitly using ifconfig(8) this function 1575 * can be called earlier than we're expected that in some cases the 1576 * initialization would be failed if setting a channel is called before 1577 * the init have done. 1578 */ 1579 if (!(sc->sc_flags & URTW_RUNNING)) 1580 return; 1581 1582 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan) 1583 return; 1584 1585 URTW_LOCK(sc); 1586 1587 /* 1588 * during changing th channel we need to temporarily be disable 1589 * TX. 1590 */ 1591 urtw_read32_m(sc, URTW_TX_CONF, &orig); 1592 data = orig & ~URTW_TX_LOOPBACK_MASK; 1593 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC); 1594 1595 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan)); 1596 if (error != 0) 1597 goto fail; 1598 usb_pause_mtx(&sc->sc_mtx, 10); 1599 urtw_write32_m(sc, URTW_TX_CONF, orig); 1600 1601 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1602 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1603 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 1604 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1605 1606 fail: 1607 URTW_UNLOCK(sc); 1608 1609 sc->sc_curchan = ic->ic_curchan; 1610 1611 if (error != 0) 1612 device_printf(sc->sc_dev, "could not change the channel\n"); 1613 } 1614 1615 static void 1616 urtw_update_mcast(struct ieee80211com *ic) 1617 { 1618 1619 /* XXX do nothing? */ 1620 } 1621 1622 static int 1623 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0, 1624 struct urtw_data *data, int prior) 1625 { 1626 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *); 1627 struct ieee80211_key *k; 1628 const struct ieee80211_txparam *tp; 1629 struct ieee80211com *ic = &sc->sc_ic; 1630 struct ieee80211vap *vap = ni->ni_vap; 1631 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = { 1632 sc->sc_xfer[URTW_8187B_BULK_TX_BE], 1633 sc->sc_xfer[URTW_8187B_BULK_TX_BK], 1634 sc->sc_xfer[URTW_8187B_BULK_TX_VI], 1635 sc->sc_xfer[URTW_8187B_BULK_TX_VO] 1636 }; 1637 struct usb_xfer *xfer; 1638 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate, 1639 pkttime = 0, txdur = 0, isshort = 0, xferlen; 1640 uint16_t acktime, rtstime, ctstime; 1641 uint32_t flags; 1642 usb_error_t error; 1643 1644 URTW_ASSERT_LOCKED(sc); 1645 1646 /* 1647 * Software crypto. 1648 */ 1649 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1650 k = ieee80211_crypto_encap(ni, m0); 1651 if (k == NULL) { 1652 device_printf(sc->sc_dev, 1653 "ieee80211_crypto_encap returns NULL.\n"); 1654 /* XXX we don't expect the fragmented frames */ 1655 m_freem(m0); 1656 return (ENOBUFS); 1657 } 1658 1659 /* in case packet header moved, reset pointer */ 1660 wh = mtod(m0, struct ieee80211_frame *); 1661 } 1662 1663 if (ieee80211_radiotap_active_vap(vap)) { 1664 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap; 1665 1666 /* XXX Are variables correct? */ 1667 tap->wt_flags = 0; 1668 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq); 1669 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags); 1670 1671 ieee80211_radiotap_tx(vap, m0); 1672 } 1673 1674 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT || 1675 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) { 1676 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1677 rate = tp->mgmtrate; 1678 } else { 1679 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1680 /* for data frames */ 1681 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1682 rate = tp->mcastrate; 1683 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1684 rate = tp->ucastrate; 1685 else 1686 rate = urtw_rtl2rate(sc->sc_currate); 1687 } 1688 1689 sc->sc_stats.txrates[sc->sc_currate]++; 1690 1691 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1692 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1693 IEEE80211_CRC_LEN, rate, 0, 0); 1694 else { 1695 acktime = urtw_compute_txtime(14, 2,0, 0); 1696 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) { 1697 rtsenable = 1; 1698 ctsenable = 0; 1699 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0); 1700 ctstime = urtw_compute_txtime(14, 2, 0, 0); 1701 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1702 IEEE80211_CRC_LEN, rate, 0, isshort); 1703 rtsdur = ctstime + pkttime + acktime + 1704 3 * URTW_ASIFS_TIME; 1705 txdur = rtstime + rtsdur; 1706 } else { 1707 rtsenable = ctsenable = rtsdur = 0; 1708 pkttime = urtw_compute_txtime(m0->m_pkthdr.len + 1709 IEEE80211_CRC_LEN, rate, 0, isshort); 1710 txdur = pkttime + URTW_ASIFS_TIME + acktime; 1711 } 1712 1713 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1714 dur = urtw_compute_txtime(m0->m_pkthdr.len + 1715 IEEE80211_CRC_LEN, rate, 0, isshort) + 1716 3 * URTW_ASIFS_TIME + 1717 2 * acktime; 1718 else 1719 dur = URTW_ASIFS_TIME + acktime; 1720 } 1721 USETW(wh->i_dur, dur); 1722 1723 xferlen = m0->m_pkthdr.len; 1724 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3); 1725 if ((0 == xferlen % 64) || (0 == xferlen % 512)) 1726 xferlen += 1; 1727 1728 memset(data->buf, 0, URTW_TX_MAXSIZE); 1729 flags = m0->m_pkthdr.len & 0xfff; 1730 flags |= URTW_TX_FLAG_NO_ENC; 1731 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 1732 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) && 1733 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) && 1734 (sc->sc_currate != 0)) 1735 flags |= URTW_TX_FLAG_SPLCP; 1736 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) 1737 flags |= URTW_TX_FLAG_MOREFRAG; 1738 1739 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT; 1740 1741 if (sc->sc_flags & URTW_RTL8187B) { 1742 struct urtw_8187b_txhdr *tx; 1743 1744 tx = (struct urtw_8187b_txhdr *)data->buf; 1745 if (ctsenable) 1746 flags |= URTW_TX_FLAG_CTS; 1747 if (rtsenable) { 1748 flags |= URTW_TX_FLAG_RTS; 1749 flags |= (urtw_rate2rtl(11) & 0xf) << 1750 URTW_TX_FLAG_RTSRATE_SHIFT; 1751 tx->rtsdur = rtsdur; 1752 } 1753 tx->flag = htole32(flags); 1754 tx->txdur = txdur; 1755 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1756 IEEE80211_FC0_TYPE_MGT && 1757 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1758 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1759 tx->retry = 1; 1760 else 1761 tx->retry = URTW_TX_MAXRETRY; 1762 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1763 } else { 1764 struct urtw_8187l_txhdr *tx; 1765 1766 tx = (struct urtw_8187l_txhdr *)data->buf; 1767 if (rtsenable) { 1768 flags |= URTW_TX_FLAG_RTS; 1769 tx->rtsdur = rtsdur; 1770 } 1771 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT; 1772 tx->flag = htole32(flags); 1773 tx->retry = 3; /* CW minimum */ 1774 tx->retry = 7 << 4; /* CW maximum */ 1775 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */ 1776 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1)); 1777 } 1778 1779 data->buflen = xferlen; 1780 data->ni = ni; 1781 data->m = m0; 1782 1783 if (sc->sc_flags & URTW_RTL8187B) { 1784 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1785 case IEEE80211_FC0_TYPE_CTL: 1786 case IEEE80211_FC0_TYPE_MGT: 1787 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12]; 1788 break; 1789 default: 1790 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX, 1791 ("unsupported WME pipe %d", M_WME_GETAC(m0))); 1792 xfer = rtl8187b_pipes[M_WME_GETAC(m0)]; 1793 break; 1794 } 1795 } else 1796 xfer = (prior == URTW_PRIORITY_LOW) ? 1797 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] : 1798 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL]; 1799 1800 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1801 usbd_transfer_start(xfer); 1802 1803 error = urtw_led_ctl(sc, URTW_LED_CTL_TX); 1804 if (error != 0) 1805 device_printf(sc->sc_dev, "could not control LED (%d)\n", 1806 error); 1807 return (0); 1808 } 1809 1810 static int 1811 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1812 { 1813 struct ieee80211com *ic = vap->iv_ic; 1814 struct urtw_softc *sc = ic->ic_softc; 1815 struct urtw_vap *uvp = URTW_VAP(vap); 1816 struct ieee80211_node *ni; 1817 usb_error_t error = 0; 1818 1819 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__, 1820 ieee80211_state_name[vap->iv_state], 1821 ieee80211_state_name[nstate]); 1822 1823 sc->sc_state = nstate; 1824 1825 IEEE80211_UNLOCK(ic); 1826 URTW_LOCK(sc); 1827 usb_callout_stop(&sc->sc_led_ch); 1828 callout_stop(&sc->sc_watchdog_ch); 1829 1830 switch (nstate) { 1831 case IEEE80211_S_INIT: 1832 case IEEE80211_S_SCAN: 1833 case IEEE80211_S_AUTH: 1834 case IEEE80211_S_ASSOC: 1835 break; 1836 case IEEE80211_S_RUN: 1837 ni = ieee80211_ref_node(vap->iv_bss); 1838 /* setting bssid. */ 1839 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]); 1840 urtw_write16_m(sc, URTW_BSSID + 4, 1841 ((uint16_t *)ni->ni_bssid)[2]); 1842 urtw_update_msr(sc); 1843 /* XXX maybe the below would be incorrect. */ 1844 urtw_write16_m(sc, URTW_ATIM_WND, 2); 1845 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100); 1846 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64); 1847 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100); 1848 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK); 1849 if (error != 0) 1850 device_printf(sc->sc_dev, 1851 "could not control LED (%d)\n", error); 1852 ieee80211_free_node(ni); 1853 break; 1854 default: 1855 break; 1856 } 1857 fail: 1858 URTW_UNLOCK(sc); 1859 IEEE80211_LOCK(ic); 1860 return (uvp->newstate(vap, nstate, arg)); 1861 } 1862 1863 static void 1864 urtw_watchdog(void *arg) 1865 { 1866 struct urtw_softc *sc = arg; 1867 1868 if (sc->sc_txtimer > 0) { 1869 if (--sc->sc_txtimer == 0) { 1870 device_printf(sc->sc_dev, "device timeout\n"); 1871 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1872 return; 1873 } 1874 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc); 1875 } 1876 } 1877 1878 static void 1879 urtw_set_multi(void *arg) 1880 { 1881 /* XXX don't know how to set a device. Lack of docs. */ 1882 } 1883 1884 static usb_error_t 1885 urtw_set_rate(struct urtw_softc *sc) 1886 { 1887 int i, basic_rate, min_rr_rate, max_rr_rate; 1888 uint16_t data; 1889 usb_error_t error; 1890 1891 basic_rate = urtw_rate2rtl(48); 1892 min_rr_rate = urtw_rate2rtl(12); 1893 max_rr_rate = urtw_rate2rtl(48); 1894 1895 urtw_write8_m(sc, URTW_RESP_RATE, 1896 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT | 1897 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT); 1898 1899 urtw_read16_m(sc, URTW_BRSR, &data); 1900 data &= ~URTW_BRSR_MBR_8185; 1901 1902 for (i = 0; i <= basic_rate; i++) 1903 data |= (1 << i); 1904 1905 urtw_write16_m(sc, URTW_BRSR, data); 1906 fail: 1907 return (error); 1908 } 1909 1910 static uint16_t 1911 urtw_rate2rtl(uint32_t rate) 1912 { 1913 int i; 1914 1915 for (i = 0; i < nitems(urtw_ratetable); i++) { 1916 if (rate == urtw_ratetable[i].reg) 1917 return urtw_ratetable[i].val; 1918 } 1919 1920 return (3); 1921 } 1922 1923 static uint16_t 1924 urtw_rtl2rate(uint32_t rate) 1925 { 1926 int i; 1927 1928 for (i = 0; i < nitems(urtw_ratetable); i++) { 1929 if (rate == urtw_ratetable[i].val) 1930 return urtw_ratetable[i].reg; 1931 } 1932 1933 return (0); 1934 } 1935 1936 static usb_error_t 1937 urtw_update_msr(struct urtw_softc *sc) 1938 { 1939 struct ieee80211com *ic = &sc->sc_ic; 1940 uint8_t data; 1941 usb_error_t error; 1942 1943 urtw_read8_m(sc, URTW_MSR, &data); 1944 data &= ~URTW_MSR_LINK_MASK; 1945 1946 if (sc->sc_state == IEEE80211_S_RUN) { 1947 switch (ic->ic_opmode) { 1948 case IEEE80211_M_STA: 1949 case IEEE80211_M_MONITOR: 1950 data |= URTW_MSR_LINK_STA; 1951 if (sc->sc_flags & URTW_RTL8187B) 1952 data |= URTW_MSR_LINK_ENEDCA; 1953 break; 1954 case IEEE80211_M_IBSS: 1955 data |= URTW_MSR_LINK_ADHOC; 1956 break; 1957 case IEEE80211_M_HOSTAP: 1958 data |= URTW_MSR_LINK_HOSTAP; 1959 break; 1960 default: 1961 DPRINTF(sc, URTW_DEBUG_STATE, 1962 "unsupported operation mode 0x%x\n", 1963 ic->ic_opmode); 1964 error = USB_ERR_INVAL; 1965 goto fail; 1966 } 1967 } else 1968 data |= URTW_MSR_LINK_NONE; 1969 1970 urtw_write8_m(sc, URTW_MSR, data); 1971 fail: 1972 return (error); 1973 } 1974 1975 static usb_error_t 1976 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data) 1977 { 1978 struct usb_device_request req; 1979 usb_error_t error; 1980 1981 URTW_ASSERT_LOCKED(sc); 1982 1983 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1984 req.bRequest = URTW_8187_GETREGS_REQ; 1985 USETW(req.wValue, (val & 0xff) | 0xff00); 1986 USETW(req.wIndex, (val >> 8) & 0x3); 1987 USETW(req.wLength, sizeof(uint8_t)); 1988 1989 error = urtw_do_request(sc, &req, data); 1990 return (error); 1991 } 1992 1993 static usb_error_t 1994 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data) 1995 { 1996 struct usb_device_request req; 1997 usb_error_t error; 1998 1999 URTW_ASSERT_LOCKED(sc); 2000 2001 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2002 req.bRequest = URTW_8187_GETREGS_REQ; 2003 USETW(req.wValue, (val & 0xff) | 0xff00); 2004 USETW(req.wIndex, (val >> 8) & 0x3); 2005 USETW(req.wLength, sizeof(uint16_t)); 2006 2007 error = urtw_do_request(sc, &req, data); 2008 return (error); 2009 } 2010 2011 static usb_error_t 2012 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data) 2013 { 2014 struct usb_device_request req; 2015 usb_error_t error; 2016 2017 URTW_ASSERT_LOCKED(sc); 2018 2019 req.bmRequestType = UT_READ_VENDOR_DEVICE; 2020 req.bRequest = URTW_8187_GETREGS_REQ; 2021 USETW(req.wValue, (val & 0xff) | 0xff00); 2022 USETW(req.wIndex, (val >> 8) & 0x3); 2023 USETW(req.wLength, sizeof(uint32_t)); 2024 2025 error = urtw_do_request(sc, &req, data); 2026 return (error); 2027 } 2028 2029 static usb_error_t 2030 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data) 2031 { 2032 struct usb_device_request req; 2033 2034 URTW_ASSERT_LOCKED(sc); 2035 2036 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2037 req.bRequest = URTW_8187_SETREGS_REQ; 2038 USETW(req.wValue, (val & 0xff) | 0xff00); 2039 USETW(req.wIndex, (val >> 8) & 0x3); 2040 USETW(req.wLength, sizeof(uint8_t)); 2041 2042 return (urtw_do_request(sc, &req, &data)); 2043 } 2044 2045 static usb_error_t 2046 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data) 2047 { 2048 struct usb_device_request req; 2049 2050 URTW_ASSERT_LOCKED(sc); 2051 2052 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2053 req.bRequest = URTW_8187_SETREGS_REQ; 2054 USETW(req.wValue, (val & 0xff) | 0xff00); 2055 USETW(req.wIndex, (val >> 8) & 0x3); 2056 USETW(req.wLength, sizeof(uint16_t)); 2057 2058 return (urtw_do_request(sc, &req, &data)); 2059 } 2060 2061 static usb_error_t 2062 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data) 2063 { 2064 struct usb_device_request req; 2065 2066 URTW_ASSERT_LOCKED(sc); 2067 2068 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2069 req.bRequest = URTW_8187_SETREGS_REQ; 2070 USETW(req.wValue, (val & 0xff) | 0xff00); 2071 USETW(req.wIndex, (val >> 8) & 0x3); 2072 USETW(req.wLength, sizeof(uint32_t)); 2073 2074 return (urtw_do_request(sc, &req, &data)); 2075 } 2076 2077 static usb_error_t 2078 urtw_get_macaddr(struct urtw_softc *sc) 2079 { 2080 struct ieee80211com *ic = &sc->sc_ic; 2081 uint32_t data; 2082 usb_error_t error; 2083 2084 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data); 2085 if (error != 0) 2086 goto fail; 2087 ic->ic_macaddr[0] = data & 0xff; 2088 ic->ic_macaddr[1] = (data & 0xff00) >> 8; 2089 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data); 2090 if (error != 0) 2091 goto fail; 2092 ic->ic_macaddr[2] = data & 0xff; 2093 ic->ic_macaddr[3] = (data & 0xff00) >> 8; 2094 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data); 2095 if (error != 0) 2096 goto fail; 2097 ic->ic_macaddr[4] = data & 0xff; 2098 ic->ic_macaddr[5] = (data & 0xff00) >> 8; 2099 fail: 2100 return (error); 2101 } 2102 2103 static usb_error_t 2104 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data) 2105 { 2106 #define URTW_READCMD_LEN 3 2107 int addrlen, i; 2108 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 }; 2109 usb_error_t error; 2110 2111 /* NB: make sure the buffer is initialized */ 2112 *data = 0; 2113 2114 /* enable EPROM programming */ 2115 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE); 2116 DELAY(URTW_EPROM_DELAY); 2117 2118 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE); 2119 if (error != 0) 2120 goto fail; 2121 error = urtw_eprom_ck(sc); 2122 if (error != 0) 2123 goto fail; 2124 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN); 2125 if (error != 0) 2126 goto fail; 2127 if (sc->sc_epromtype == URTW_EEPROM_93C56) { 2128 addrlen = 8; 2129 addrstr[0] = addr & (1 << 7); 2130 addrstr[1] = addr & (1 << 6); 2131 addrstr[2] = addr & (1 << 5); 2132 addrstr[3] = addr & (1 << 4); 2133 addrstr[4] = addr & (1 << 3); 2134 addrstr[5] = addr & (1 << 2); 2135 addrstr[6] = addr & (1 << 1); 2136 addrstr[7] = addr & (1 << 0); 2137 } else { 2138 addrlen=6; 2139 addrstr[0] = addr & (1 << 5); 2140 addrstr[1] = addr & (1 << 4); 2141 addrstr[2] = addr & (1 << 3); 2142 addrstr[3] = addr & (1 << 2); 2143 addrstr[4] = addr & (1 << 1); 2144 addrstr[5] = addr & (1 << 0); 2145 } 2146 error = urtw_eprom_sendbits(sc, addrstr, addrlen); 2147 if (error != 0) 2148 goto fail; 2149 2150 error = urtw_eprom_writebit(sc, 0); 2151 if (error != 0) 2152 goto fail; 2153 2154 for (i = 0; i < 16; i++) { 2155 error = urtw_eprom_ck(sc); 2156 if (error != 0) 2157 goto fail; 2158 error = urtw_eprom_readbit(sc, &data16); 2159 if (error != 0) 2160 goto fail; 2161 2162 (*data) |= (data16 << (15 - i)); 2163 } 2164 2165 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE); 2166 if (error != 0) 2167 goto fail; 2168 error = urtw_eprom_ck(sc); 2169 if (error != 0) 2170 goto fail; 2171 2172 /* now disable EPROM programming */ 2173 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE); 2174 fail: 2175 return (error); 2176 #undef URTW_READCMD_LEN 2177 } 2178 2179 static usb_error_t 2180 urtw_eprom_cs(struct urtw_softc *sc, int able) 2181 { 2182 uint8_t data; 2183 usb_error_t error; 2184 2185 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2186 if (able == URTW_EPROM_ENABLE) 2187 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS); 2188 else 2189 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS); 2190 DELAY(URTW_EPROM_DELAY); 2191 fail: 2192 return (error); 2193 } 2194 2195 static usb_error_t 2196 urtw_eprom_ck(struct urtw_softc *sc) 2197 { 2198 uint8_t data; 2199 usb_error_t error; 2200 2201 /* masking */ 2202 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2203 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK); 2204 DELAY(URTW_EPROM_DELAY); 2205 /* unmasking */ 2206 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2207 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK); 2208 DELAY(URTW_EPROM_DELAY); 2209 fail: 2210 return (error); 2211 } 2212 2213 static usb_error_t 2214 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data) 2215 { 2216 uint8_t data8; 2217 usb_error_t error; 2218 2219 urtw_read8_m(sc, URTW_EPROM_CMD, &data8); 2220 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0; 2221 DELAY(URTW_EPROM_DELAY); 2222 2223 fail: 2224 return (error); 2225 } 2226 2227 static usb_error_t 2228 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit) 2229 { 2230 uint8_t data; 2231 usb_error_t error; 2232 2233 urtw_read8_m(sc, URTW_EPROM_CMD, &data); 2234 if (bit != 0) 2235 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT); 2236 else 2237 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT); 2238 DELAY(URTW_EPROM_DELAY); 2239 fail: 2240 return (error); 2241 } 2242 2243 static usb_error_t 2244 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen) 2245 { 2246 int i = 0; 2247 usb_error_t error = 0; 2248 2249 for (i = 0; i < buflen; i++) { 2250 error = urtw_eprom_writebit(sc, buf[i]); 2251 if (error != 0) 2252 goto fail; 2253 error = urtw_eprom_ck(sc); 2254 if (error != 0) 2255 goto fail; 2256 } 2257 fail: 2258 return (error); 2259 } 2260 2261 2262 static usb_error_t 2263 urtw_get_txpwr(struct urtw_softc *sc) 2264 { 2265 int i, j; 2266 uint32_t data; 2267 usb_error_t error; 2268 2269 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data); 2270 if (error != 0) 2271 goto fail; 2272 sc->sc_txpwr_cck_base = data & 0xf; 2273 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf; 2274 2275 for (i = 1, j = 0; i < 6; i += 2, j++) { 2276 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data); 2277 if (error != 0) 2278 goto fail; 2279 sc->sc_txpwr_cck[i] = data & 0xf; 2280 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8; 2281 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4; 2282 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12; 2283 } 2284 for (i = 1, j = 0; i < 4; i += 2, j++) { 2285 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data); 2286 if (error != 0) 2287 goto fail; 2288 sc->sc_txpwr_cck[i + 6] = data & 0xf; 2289 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8; 2290 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4; 2291 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12; 2292 } 2293 if (sc->sc_flags & URTW_RTL8187B) { 2294 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data); 2295 if (error != 0) 2296 goto fail; 2297 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf; 2298 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4; 2299 error = urtw_eprom_read32(sc, 0x0a, &data); 2300 if (error != 0) 2301 goto fail; 2302 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf; 2303 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4; 2304 error = urtw_eprom_read32(sc, 0x1c, &data); 2305 if (error != 0) 2306 goto fail; 2307 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf; 2308 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8; 2309 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4; 2310 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12; 2311 } else { 2312 for (i = 1, j = 0; i < 4; i += 2, j++) { 2313 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j, 2314 &data); 2315 if (error != 0) 2316 goto fail; 2317 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf; 2318 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8; 2319 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4; 2320 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12; 2321 } 2322 } 2323 fail: 2324 return (error); 2325 } 2326 2327 2328 static usb_error_t 2329 urtw_get_rfchip(struct urtw_softc *sc) 2330 { 2331 int ret; 2332 uint8_t data8; 2333 uint32_t data; 2334 usb_error_t error; 2335 2336 if (sc->sc_flags & URTW_RTL8187B) { 2337 urtw_read8_m(sc, 0xe1, &data8); 2338 switch (data8) { 2339 case 0: 2340 sc->sc_flags |= URTW_RTL8187B_REV_B; 2341 break; 2342 case 1: 2343 sc->sc_flags |= URTW_RTL8187B_REV_D; 2344 break; 2345 case 2: 2346 sc->sc_flags |= URTW_RTL8187B_REV_E; 2347 break; 2348 default: 2349 device_printf(sc->sc_dev, "unknown type: %#x\n", data8); 2350 sc->sc_flags |= URTW_RTL8187B_REV_B; 2351 break; 2352 } 2353 } else { 2354 urtw_read32_m(sc, URTW_TX_CONF, &data); 2355 switch (data & URTW_TX_HWMASK) { 2356 case URTW_TX_R8187vD_B: 2357 sc->sc_flags |= URTW_RTL8187B; 2358 break; 2359 case URTW_TX_R8187vD: 2360 break; 2361 default: 2362 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n", 2363 data & URTW_TX_HWMASK); 2364 break; 2365 } 2366 } 2367 2368 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data); 2369 if (error != 0) 2370 goto fail; 2371 switch (data & 0xff) { 2372 case URTW_EPROM_RFCHIPID_RTL8225U: 2373 error = urtw_8225_isv2(sc, &ret); 2374 if (error != 0) 2375 goto fail; 2376 if (ret == 0) { 2377 sc->sc_rf_init = urtw_8225_rf_init; 2378 sc->sc_rf_set_sens = urtw_8225_rf_set_sens; 2379 sc->sc_rf_set_chan = urtw_8225_rf_set_chan; 2380 sc->sc_rf_stop = urtw_8225_rf_stop; 2381 } else { 2382 sc->sc_rf_init = urtw_8225v2_rf_init; 2383 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan; 2384 sc->sc_rf_stop = urtw_8225_rf_stop; 2385 } 2386 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2387 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2388 break; 2389 case URTW_EPROM_RFCHIPID_RTL8225Z2: 2390 sc->sc_rf_init = urtw_8225v2b_rf_init; 2391 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan; 2392 sc->sc_max_sens = URTW_8225_RF_MAX_SENS; 2393 sc->sc_sens = URTW_8225_RF_DEF_SENS; 2394 sc->sc_rf_stop = urtw_8225_rf_stop; 2395 break; 2396 default: 2397 DPRINTF(sc, URTW_DEBUG_STATE, 2398 "unsupported RF chip %d\n", data & 0xff); 2399 error = USB_ERR_INVAL; 2400 goto fail; 2401 } 2402 2403 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n", 2404 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l", 2405 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" : 2406 "rtl8225z2", 2407 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" : 2408 (data8 == 1) ? "d" : "e") : "none"); 2409 2410 fail: 2411 return (error); 2412 } 2413 2414 2415 static usb_error_t 2416 urtw_led_init(struct urtw_softc *sc) 2417 { 2418 uint32_t rev; 2419 usb_error_t error; 2420 2421 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr); 2422 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev); 2423 if (error != 0) 2424 goto fail; 2425 2426 switch (rev & URTW_EPROM_CID_MASK) { 2427 case URTW_EPROM_CID_ALPHA0: 2428 sc->sc_strategy = URTW_SW_LED_MODE1; 2429 break; 2430 case URTW_EPROM_CID_SERCOMM_PS: 2431 sc->sc_strategy = URTW_SW_LED_MODE3; 2432 break; 2433 case URTW_EPROM_CID_HW_LED: 2434 sc->sc_strategy = URTW_HW_LED; 2435 break; 2436 case URTW_EPROM_CID_RSVD0: 2437 case URTW_EPROM_CID_RSVD1: 2438 default: 2439 sc->sc_strategy = URTW_SW_LED_MODE0; 2440 break; 2441 } 2442 2443 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0; 2444 2445 fail: 2446 return (error); 2447 } 2448 2449 2450 static usb_error_t 2451 urtw_8225_rf_init(struct urtw_softc *sc) 2452 { 2453 int i; 2454 uint16_t data; 2455 usb_error_t error; 2456 2457 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2458 if (error) 2459 goto fail; 2460 2461 error = urtw_8225_usb_init(sc); 2462 if (error) 2463 goto fail; 2464 2465 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2466 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2467 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2468 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2469 2470 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2471 if (error) 2472 goto fail; 2473 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2474 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2475 if (error) 2476 goto fail; 2477 2478 error = urtw_8185_rf_pins_enable(sc); 2479 if (error) 2480 goto fail; 2481 usb_pause_mtx(&sc->sc_mtx, 1000); 2482 2483 for (i = 0; i < nitems(urtw_8225_rf_part1); i++) { 2484 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg, 2485 urtw_8225_rf_part1[i].val); 2486 usb_pause_mtx(&sc->sc_mtx, 1); 2487 } 2488 usb_pause_mtx(&sc->sc_mtx, 100); 2489 urtw_8225_write(sc, 2490 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2491 usb_pause_mtx(&sc->sc_mtx, 200); 2492 urtw_8225_write(sc, 2493 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2494 usb_pause_mtx(&sc->sc_mtx, 200); 2495 urtw_8225_write(sc, 2496 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3); 2497 2498 for (i = 0; i < 95; i++) { 2499 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2500 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]); 2501 } 2502 2503 urtw_8225_write(sc, 2504 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4); 2505 urtw_8225_write(sc, 2506 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5); 2507 2508 for (i = 0; i < 128; i++) { 2509 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2510 usb_pause_mtx(&sc->sc_mtx, 1); 2511 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2512 usb_pause_mtx(&sc->sc_mtx, 1); 2513 } 2514 2515 for (i = 0; i < nitems(urtw_8225_rf_part2); i++) { 2516 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg, 2517 urtw_8225_rf_part2[i].val); 2518 usb_pause_mtx(&sc->sc_mtx, 1); 2519 } 2520 2521 error = urtw_8225_setgain(sc, 4); 2522 if (error) 2523 goto fail; 2524 2525 for (i = 0; i < nitems(urtw_8225_rf_part3); i++) { 2526 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg, 2527 urtw_8225_rf_part3[i].val); 2528 usb_pause_mtx(&sc->sc_mtx, 1); 2529 } 2530 2531 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2532 2533 error = urtw_8225_set_txpwrlvl(sc, 1); 2534 if (error) 2535 goto fail; 2536 2537 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2538 usb_pause_mtx(&sc->sc_mtx, 1); 2539 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2540 usb_pause_mtx(&sc->sc_mtx, 1); 2541 2542 /* TX ant A, 0x0 for B */ 2543 error = urtw_8185_tx_antenna(sc, 0x3); 2544 if (error) 2545 goto fail; 2546 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2547 2548 error = urtw_8225_rf_set_chan(sc, 1); 2549 fail: 2550 return (error); 2551 } 2552 2553 static usb_error_t 2554 urtw_8185_rf_pins_enable(struct urtw_softc *sc) 2555 { 2556 usb_error_t error = 0; 2557 2558 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7); 2559 fail: 2560 return (error); 2561 } 2562 2563 static usb_error_t 2564 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant) 2565 { 2566 usb_error_t error; 2567 2568 urtw_write8_m(sc, URTW_TX_ANTENNA, ant); 2569 usb_pause_mtx(&sc->sc_mtx, 1); 2570 fail: 2571 return (error); 2572 } 2573 2574 static usb_error_t 2575 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2576 { 2577 2578 data = data & 0xff; 2579 return urtw_8187_write_phy(sc, addr, data); 2580 } 2581 2582 static usb_error_t 2583 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2584 { 2585 2586 data = data & 0xff; 2587 return urtw_8187_write_phy(sc, addr, data | 0x10000); 2588 } 2589 2590 static usb_error_t 2591 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data) 2592 { 2593 uint32_t phyw; 2594 usb_error_t error; 2595 2596 phyw = ((data << 8) | (addr | 0x80)); 2597 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24)); 2598 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16)); 2599 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8)); 2600 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff))); 2601 usb_pause_mtx(&sc->sc_mtx, 1); 2602 fail: 2603 return (error); 2604 } 2605 2606 static usb_error_t 2607 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain) 2608 { 2609 usb_error_t error; 2610 2611 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]); 2612 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]); 2613 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]); 2614 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]); 2615 fail: 2616 return (error); 2617 } 2618 2619 static usb_error_t 2620 urtw_8225_usb_init(struct urtw_softc *sc) 2621 { 2622 uint8_t data; 2623 usb_error_t error; 2624 2625 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0); 2626 urtw_write8_m(sc, URTW_GPIO, 0); 2627 error = urtw_read8e(sc, 0x53, &data); 2628 if (error) 2629 goto fail; 2630 error = urtw_write8e(sc, 0x53, data | (1 << 7)); 2631 if (error) 2632 goto fail; 2633 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4); 2634 urtw_write8_m(sc, URTW_GPIO, 0x20); 2635 urtw_write8_m(sc, URTW_GP_ENABLE, 0); 2636 2637 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80); 2638 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80); 2639 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80); 2640 2641 usb_pause_mtx(&sc->sc_mtx, 500); 2642 fail: 2643 return (error); 2644 } 2645 2646 static usb_error_t 2647 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data) 2648 { 2649 uint16_t d80, d82, d84; 2650 usb_error_t error; 2651 2652 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80); 2653 d80 &= URTW_RF_PINS_MAGIC1; 2654 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82); 2655 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84); 2656 d84 &= URTW_RF_PINS_MAGIC2; 2657 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3); 2658 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3); 2659 DELAY(10); 2660 2661 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2662 DELAY(2); 2663 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80); 2664 DELAY(10); 2665 2666 error = urtw_8225_write_s16(sc, addr, 0x8225, &data); 2667 if (error != 0) 2668 goto fail; 2669 2670 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2671 DELAY(10); 2672 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN); 2673 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84); 2674 usb_pause_mtx(&sc->sc_mtx, 2); 2675 fail: 2676 return (error); 2677 } 2678 2679 static usb_error_t 2680 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index, 2681 uint16_t *data) 2682 { 2683 uint8_t buf[2]; 2684 uint16_t data16; 2685 struct usb_device_request req; 2686 usb_error_t error = 0; 2687 2688 data16 = *data; 2689 2690 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 2691 req.bRequest = URTW_8187_SETREGS_REQ; 2692 USETW(req.wValue, addr); 2693 USETW(req.wIndex, index); 2694 USETW(req.wLength, sizeof(uint16_t)); 2695 buf[0] = (data16 & 0x00ff); 2696 buf[1] = (data16 & 0xff00) >> 8; 2697 2698 error = urtw_do_request(sc, &req, buf); 2699 2700 return (error); 2701 } 2702 2703 static usb_error_t 2704 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan) 2705 { 2706 usb_error_t error; 2707 2708 error = urtw_8225_set_txpwrlvl(sc, chan); 2709 if (error) 2710 goto fail; 2711 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2712 usb_pause_mtx(&sc->sc_mtx, 10); 2713 fail: 2714 return (error); 2715 } 2716 2717 static usb_error_t 2718 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens) 2719 { 2720 usb_error_t error; 2721 2722 if (sens < 0 || sens > 6) 2723 return -1; 2724 2725 if (sens > 4) 2726 urtw_8225_write(sc, 2727 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1); 2728 else 2729 urtw_8225_write(sc, 2730 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2); 2731 2732 sens = 6 - sens; 2733 error = urtw_8225_setgain(sc, sens); 2734 if (error) 2735 goto fail; 2736 2737 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]); 2738 2739 fail: 2740 return (error); 2741 } 2742 2743 static usb_error_t 2744 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan) 2745 { 2746 int i, idx, set; 2747 uint8_t *cck_pwltable; 2748 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max; 2749 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 2750 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 2751 usb_error_t error; 2752 2753 cck_pwrlvl_max = 11; 2754 ofdm_pwrlvl_max = 25; /* 12 -> 25 */ 2755 ofdm_pwrlvl_min = 10; 2756 2757 /* CCK power setting */ 2758 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 2759 idx = cck_pwrlvl % 6; 2760 set = cck_pwrlvl / 6; 2761 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 : 2762 urtw_8225_txpwr_cck; 2763 2764 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 2765 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2766 for (i = 0; i < 8; i++) { 2767 urtw_8187_write_phy_cck(sc, 0x44 + i, 2768 cck_pwltable[idx * 8 + i]); 2769 } 2770 usb_pause_mtx(&sc->sc_mtx, 1); 2771 2772 /* OFDM power setting */ 2773 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 2774 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 2775 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 2776 2777 idx = ofdm_pwrlvl % 6; 2778 set = ofdm_pwrlvl / 6; 2779 2780 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 2781 if (error) 2782 goto fail; 2783 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 2784 urtw_8187_write_phy_ofdm(sc, 6, 0); 2785 urtw_8187_write_phy_ofdm(sc, 8, 0); 2786 2787 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 2788 urtw_8225_tx_gain_cck_ofdm[set] >> 1); 2789 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]); 2790 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]); 2791 usb_pause_mtx(&sc->sc_mtx, 1); 2792 fail: 2793 return (error); 2794 } 2795 2796 2797 static usb_error_t 2798 urtw_8225_rf_stop(struct urtw_softc *sc) 2799 { 2800 uint8_t data; 2801 usb_error_t error; 2802 2803 urtw_8225_write(sc, 0x4, 0x1f); 2804 2805 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2806 if (error) 2807 goto fail; 2808 2809 urtw_read8_m(sc, URTW_CONFIG3, &data); 2810 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 2811 if (sc->sc_flags & URTW_RTL8187B) { 2812 urtw_write32_m(sc, URTW_ANAPARAM2, 2813 URTW_8187B_8225_ANAPARAM2_OFF); 2814 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF); 2815 urtw_write32_m(sc, URTW_ANAPARAM3, 2816 URTW_8187B_8225_ANAPARAM3_OFF); 2817 } else { 2818 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF); 2819 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF); 2820 } 2821 2822 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 2823 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2824 if (error) 2825 goto fail; 2826 2827 fail: 2828 return (error); 2829 } 2830 2831 static usb_error_t 2832 urtw_8225v2_rf_init(struct urtw_softc *sc) 2833 { 2834 int i; 2835 uint16_t data; 2836 uint32_t data32; 2837 usb_error_t error; 2838 2839 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 2840 if (error) 2841 goto fail; 2842 2843 error = urtw_8225_usb_init(sc); 2844 if (error) 2845 goto fail; 2846 2847 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008); 2848 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */ 2849 urtw_write16_m(sc, URTW_BRSR, 0xffff); 2850 urtw_write32_m(sc, URTW_RF_PARA, 0x100044); 2851 2852 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 2853 if (error) 2854 goto fail; 2855 urtw_write8_m(sc, URTW_CONFIG3, 0x44); 2856 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 2857 if (error) 2858 goto fail; 2859 2860 error = urtw_8185_rf_pins_enable(sc); 2861 if (error) 2862 goto fail; 2863 2864 usb_pause_mtx(&sc->sc_mtx, 500); 2865 2866 for (i = 0; i < nitems(urtw_8225v2_rf_part1); i++) { 2867 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg, 2868 urtw_8225v2_rf_part1[i].val); 2869 } 2870 usb_pause_mtx(&sc->sc_mtx, 50); 2871 2872 urtw_8225_write(sc, 2873 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1); 2874 2875 for (i = 0; i < 95; i++) { 2876 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 2877 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 2878 urtw_8225v2_rxgain[i]); 2879 } 2880 2881 urtw_8225_write(sc, 2882 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1); 2883 urtw_8225_write(sc, 2884 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1); 2885 urtw_8225_write(sc, 2886 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2); 2887 urtw_8225_write(sc, 2888 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2889 usb_pause_mtx(&sc->sc_mtx, 100); 2890 urtw_8225_write(sc, 2891 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2892 usb_pause_mtx(&sc->sc_mtx, 100); 2893 2894 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2895 if (error != 0) 2896 goto fail; 2897 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1) 2898 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32); 2899 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) { 2900 urtw_8225_write(sc, 2901 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1); 2902 usb_pause_mtx(&sc->sc_mtx, 100); 2903 urtw_8225_write(sc, 2904 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2); 2905 usb_pause_mtx(&sc->sc_mtx, 50); 2906 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32); 2907 if (error != 0) 2908 goto fail; 2909 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) 2910 device_printf(sc->sc_dev, "RF calibration failed\n"); 2911 } 2912 usb_pause_mtx(&sc->sc_mtx, 100); 2913 2914 urtw_8225_write(sc, 2915 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6); 2916 for (i = 0; i < 128; i++) { 2917 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]); 2918 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80); 2919 } 2920 2921 for (i = 0; i < nitems(urtw_8225v2_rf_part2); i++) { 2922 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg, 2923 urtw_8225v2_rf_part2[i].val); 2924 } 2925 2926 error = urtw_8225v2_setgain(sc, 4); 2927 if (error) 2928 goto fail; 2929 2930 for (i = 0; i < nitems(urtw_8225v2_rf_part3); i++) { 2931 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg, 2932 urtw_8225v2_rf_part3[i].val); 2933 } 2934 2935 urtw_write8_m(sc, URTW_TESTR, 0x0d); 2936 2937 error = urtw_8225v2_set_txpwrlvl(sc, 1); 2938 if (error) 2939 goto fail; 2940 2941 urtw_8187_write_phy_cck(sc, 0x10, 0x9b); 2942 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90); 2943 2944 /* TX ant A, 0x0 for B */ 2945 error = urtw_8185_tx_antenna(sc, 0x3); 2946 if (error) 2947 goto fail; 2948 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002); 2949 2950 error = urtw_8225_rf_set_chan(sc, 1); 2951 fail: 2952 return (error); 2953 } 2954 2955 static usb_error_t 2956 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan) 2957 { 2958 usb_error_t error; 2959 2960 error = urtw_8225v2_set_txpwrlvl(sc, chan); 2961 if (error) 2962 goto fail; 2963 2964 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 2965 usb_pause_mtx(&sc->sc_mtx, 10); 2966 fail: 2967 return (error); 2968 } 2969 2970 static usb_error_t 2971 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data) 2972 { 2973 int i; 2974 int16_t bit; 2975 uint8_t rlen = 12, wlen = 6; 2976 uint16_t o1, o2, o3, tmp; 2977 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27; 2978 uint32_t mask = 0x80000000, value = 0; 2979 usb_error_t error; 2980 2981 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1); 2982 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2); 2983 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3); 2984 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4); 2985 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4); 2986 o1 &= ~URTW_RF_PINS_MAGIC4; 2987 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN); 2988 DELAY(5); 2989 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1); 2990 DELAY(5); 2991 2992 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) { 2993 bit = ((d2w & mask) != 0) ? 1 : 0; 2994 2995 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 2996 DELAY(2); 2997 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 2998 URTW_BB_HOST_BANG_CLK); 2999 DELAY(2); 3000 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3001 URTW_BB_HOST_BANG_CLK); 3002 DELAY(2); 3003 mask = mask >> 1; 3004 if (i == 2) 3005 break; 3006 bit = ((d2w & mask) != 0) ? 1 : 0; 3007 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3008 URTW_BB_HOST_BANG_CLK); 3009 DELAY(2); 3010 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | 3011 URTW_BB_HOST_BANG_CLK); 3012 DELAY(2); 3013 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1); 3014 DELAY(1); 3015 } 3016 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW | 3017 URTW_BB_HOST_BANG_CLK); 3018 DELAY(2); 3019 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW); 3020 DELAY(2); 3021 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW); 3022 DELAY(2); 3023 3024 mask = 0x800; 3025 for (i = 0; i < rlen; i++, mask = mask >> 1) { 3026 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3027 o1 | URTW_BB_HOST_BANG_RW); 3028 DELAY(2); 3029 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3030 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3031 DELAY(2); 3032 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3033 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3034 DELAY(2); 3035 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3036 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK); 3037 DELAY(2); 3038 3039 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp); 3040 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0); 3041 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 3042 o1 | URTW_BB_HOST_BANG_RW); 3043 DELAY(2); 3044 } 3045 3046 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN | 3047 URTW_BB_HOST_BANG_RW); 3048 DELAY(2); 3049 3050 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2); 3051 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3); 3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1); 3053 3054 if (data != NULL) 3055 *data = value; 3056 fail: 3057 return (error); 3058 } 3059 3060 3061 static usb_error_t 3062 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan) 3063 { 3064 int i; 3065 uint8_t *cck_pwrtable; 3066 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10; 3067 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3068 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3069 usb_error_t error; 3070 3071 /* CCK power setting */ 3072 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl; 3073 cck_pwrlvl += sc->sc_txpwr_cck_base; 3074 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3075 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 : 3076 urtw_8225v2_txpwr_cck; 3077 3078 for (i = 0; i < 8; i++) 3079 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3080 3081 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3082 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]); 3083 usb_pause_mtx(&sc->sc_mtx, 1); 3084 3085 /* OFDM power setting */ 3086 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ? 3087 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min; 3088 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3089 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3090 3091 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3092 if (error) 3093 goto fail; 3094 3095 urtw_8187_write_phy_ofdm(sc, 2, 0x42); 3096 urtw_8187_write_phy_ofdm(sc, 5, 0x0); 3097 urtw_8187_write_phy_ofdm(sc, 6, 0x40); 3098 urtw_8187_write_phy_ofdm(sc, 7, 0x0); 3099 urtw_8187_write_phy_ofdm(sc, 8, 0x40); 3100 3101 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3102 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]); 3103 usb_pause_mtx(&sc->sc_mtx, 1); 3104 fail: 3105 return (error); 3106 } 3107 3108 static usb_error_t 3109 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain) 3110 { 3111 uint8_t *gainp; 3112 usb_error_t error; 3113 3114 /* XXX for A? */ 3115 gainp = urtw_8225v2_gain_bg; 3116 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]); 3117 usb_pause_mtx(&sc->sc_mtx, 1); 3118 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]); 3119 usb_pause_mtx(&sc->sc_mtx, 1); 3120 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]); 3121 usb_pause_mtx(&sc->sc_mtx, 1); 3122 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17); 3123 usb_pause_mtx(&sc->sc_mtx, 1); 3124 fail: 3125 return (error); 3126 } 3127 3128 static usb_error_t 3129 urtw_8225_isv2(struct urtw_softc *sc, int *ret) 3130 { 3131 uint32_t data; 3132 usb_error_t error; 3133 3134 *ret = 1; 3135 3136 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5); 3137 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5); 3138 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5); 3139 usb_pause_mtx(&sc->sc_mtx, 500); 3140 3141 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3142 URTW_8225_ADDR_0_DATA_MAGIC1); 3143 3144 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data); 3145 if (error != 0) 3146 goto fail; 3147 if (data != URTW_8225_ADDR_8_DATA_MAGIC1) 3148 *ret = 0; 3149 else { 3150 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data); 3151 if (error != 0) 3152 goto fail; 3153 if (data != URTW_8225_ADDR_9_DATA_MAGIC1) 3154 *ret = 0; 3155 } 3156 3157 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 3158 URTW_8225_ADDR_0_DATA_MAGIC2); 3159 fail: 3160 return (error); 3161 } 3162 3163 static usb_error_t 3164 urtw_8225v2b_rf_init(struct urtw_softc *sc) 3165 { 3166 struct ieee80211com *ic = &sc->sc_ic; 3167 int i; 3168 uint8_t data8; 3169 usb_error_t error; 3170 3171 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3172 if (error) 3173 goto fail; 3174 3175 /* 3176 * initialize extra registers on 8187 3177 */ 3178 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff); 3179 3180 /* retry limit */ 3181 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3182 data8 |= URTW_CW_CONF_PERPACKET_RETRY; 3183 urtw_write8_m(sc, URTW_CW_CONF, data8); 3184 3185 /* TX AGC */ 3186 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3187 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN; 3188 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3189 3190 /* Auto Rate Fallback Control */ 3191 #define URTW_ARFR 0x1e0 3192 urtw_write16_m(sc, URTW_ARFR, 0xfff); 3193 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8); 3194 urtw_write8_m(sc, URTW_RATE_FALLBACK, 3195 data8 | URTW_RATE_FALLBACK_ENABLE); 3196 3197 urtw_read8_m(sc, URTW_MSR, &data8); 3198 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3); 3199 urtw_read8_m(sc, URTW_MSR, &data8); 3200 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA); 3201 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl); 3202 3203 urtw_write16_m(sc, URTW_ATIM_WND, 2); 3204 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100); 3205 #define URTW_FEMR_FOR_8187B 0x1d4 3206 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff); 3207 3208 /* led type */ 3209 urtw_read8_m(sc, URTW_CONFIG1, &data8); 3210 data8 = (data8 & 0x3f) | 0x80; 3211 urtw_write8_m(sc, URTW_CONFIG1, data8); 3212 3213 /* applying MAC address again. */ 3214 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)ic->ic_macaddr)[0]); 3215 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)ic->ic_macaddr)[1] & 0xffff); 3216 3217 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3218 if (error) 3219 goto fail; 3220 3221 urtw_write8_m(sc, URTW_WPA_CONFIG, 0); 3222 3223 /* 3224 * MAC configuration 3225 */ 3226 for (i = 0; i < nitems(urtw_8225v2b_rf_part1); i++) 3227 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg, 3228 urtw_8225v2b_rf_part1[i].val); 3229 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50); 3230 urtw_write16_m(sc, URTW_INT_MIG, 0x0000); 3231 urtw_write32_m(sc, 0x1f0, 0); 3232 urtw_write32_m(sc, 0x1f4, 0); 3233 urtw_write8_m(sc, 0x1f8, 0); 3234 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001); 3235 3236 #define URTW_RFSW_CTRL 0x272 3237 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a); 3238 3239 /* 3240 * initialize PHY 3241 */ 3242 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3243 if (error) 3244 goto fail; 3245 urtw_read8_m(sc, URTW_CONFIG3, &data8); 3246 urtw_write8_m(sc, URTW_CONFIG3, 3247 data8 | URTW_CONFIG3_ANAPARAM_WRITE); 3248 3249 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3250 if (error) 3251 goto fail; 3252 3253 /* setup RFE initial timing */ 3254 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480); 3255 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488); 3256 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff); 3257 usb_pause_mtx(&sc->sc_mtx, 1100); 3258 3259 for (i = 0; i < nitems(urtw_8225v2b_rf_part0); i++) { 3260 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg, 3261 urtw_8225v2b_rf_part0[i].val); 3262 usb_pause_mtx(&sc->sc_mtx, 1); 3263 } 3264 urtw_8225_write(sc, 0x00, 0x01b7); 3265 3266 for (i = 0; i < 95; i++) { 3267 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1)); 3268 usb_pause_mtx(&sc->sc_mtx, 1); 3269 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 3270 urtw_8225v2b_rxgain[i]); 3271 usb_pause_mtx(&sc->sc_mtx, 1); 3272 } 3273 3274 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080); 3275 usb_pause_mtx(&sc->sc_mtx, 1); 3276 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004); 3277 usb_pause_mtx(&sc->sc_mtx, 1); 3278 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7); 3279 usb_pause_mtx(&sc->sc_mtx, 1); 3280 usb_pause_mtx(&sc->sc_mtx, 3000); 3281 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d); 3282 usb_pause_mtx(&sc->sc_mtx, 2000); 3283 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d); 3284 usb_pause_mtx(&sc->sc_mtx, 1); 3285 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf); 3286 usb_pause_mtx(&sc->sc_mtx, 1); 3287 3288 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03); 3289 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07); 3290 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03); 3291 3292 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12); 3293 for (i = 0; i < 128; i++) { 3294 uint32_t addr, data; 3295 3296 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f; 3297 addr = ((i + 0x80) << 8) | 0x0000008e; 3298 3299 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff); 3300 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff); 3301 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00); 3302 } 3303 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10); 3304 3305 for (i = 0; i < nitems(urtw_8225v2b_rf_part2); i++) 3306 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val); 3307 3308 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c); 3309 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c); 3310 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c); 3311 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c); 3312 3313 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46); 3314 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6); 3315 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc); 3316 urtw_8187_write_phy_cck(sc, 0xc1, 0x88); 3317 3318 fail: 3319 return (error); 3320 } 3321 3322 static usb_error_t 3323 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan) 3324 { 3325 usb_error_t error; 3326 3327 error = urtw_8225v2b_set_txpwrlvl(sc, chan); 3328 if (error) 3329 goto fail; 3330 3331 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]); 3332 usb_pause_mtx(&sc->sc_mtx, 10); 3333 fail: 3334 return (error); 3335 } 3336 3337 static usb_error_t 3338 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan) 3339 { 3340 int i; 3341 uint8_t *cck_pwrtable; 3342 uint8_t cck_pwrlvl_max = 15; 3343 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff; 3344 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff; 3345 usb_error_t error; 3346 3347 /* CCK power setting */ 3348 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? 3349 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) : 3350 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7)); 3351 cck_pwrlvl += sc->sc_txpwr_cck_base; 3352 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl; 3353 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 : 3354 urtw_8225v2b_txpwr_cck; 3355 3356 if (sc->sc_flags & URTW_RTL8187B_REV_B) 3357 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 : 3358 ((cck_pwrlvl <= 11) ? 8 : 16); 3359 else 3360 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 : 3361 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24)); 3362 3363 for (i = 0; i < 8; i++) 3364 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]); 3365 3366 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 3367 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1); 3368 usb_pause_mtx(&sc->sc_mtx, 1); 3369 3370 /* OFDM power setting */ 3371 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ? 3372 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) : 3373 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10)); 3374 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base; 3375 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl; 3376 3377 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 3378 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1); 3379 3380 if (sc->sc_flags & URTW_RTL8187B_REV_B) { 3381 if (ofdm_pwrlvl <= 11) { 3382 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60); 3383 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60); 3384 } else { 3385 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3386 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3387 } 3388 } else { 3389 if (ofdm_pwrlvl <= 11) { 3390 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c); 3391 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c); 3392 } else if (ofdm_pwrlvl <= 17) { 3393 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54); 3394 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54); 3395 } else { 3396 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50); 3397 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50); 3398 } 3399 } 3400 usb_pause_mtx(&sc->sc_mtx, 1); 3401 fail: 3402 return (error); 3403 } 3404 3405 static usb_error_t 3406 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data) 3407 { 3408 struct usb_device_request req; 3409 usb_error_t error; 3410 3411 req.bmRequestType = UT_READ_VENDOR_DEVICE; 3412 req.bRequest = URTW_8187_GETREGS_REQ; 3413 USETW(req.wValue, val | 0xfe00); 3414 USETW(req.wIndex, 0); 3415 USETW(req.wLength, sizeof(uint8_t)); 3416 3417 error = urtw_do_request(sc, &req, data); 3418 return (error); 3419 } 3420 3421 static usb_error_t 3422 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data) 3423 { 3424 struct usb_device_request req; 3425 3426 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 3427 req.bRequest = URTW_8187_SETREGS_REQ; 3428 USETW(req.wValue, val | 0xfe00); 3429 USETW(req.wIndex, 0); 3430 USETW(req.wLength, sizeof(uint8_t)); 3431 3432 return (urtw_do_request(sc, &req, &data)); 3433 } 3434 3435 static usb_error_t 3436 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val) 3437 { 3438 uint8_t data; 3439 usb_error_t error; 3440 3441 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3442 if (error) 3443 goto fail; 3444 3445 urtw_read8_m(sc, URTW_CONFIG3, &data); 3446 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3447 urtw_write32_m(sc, URTW_ANAPARAM, val); 3448 urtw_read8_m(sc, URTW_CONFIG3, &data); 3449 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3450 3451 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3452 if (error) 3453 goto fail; 3454 fail: 3455 return (error); 3456 } 3457 3458 static usb_error_t 3459 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val) 3460 { 3461 uint8_t data; 3462 usb_error_t error; 3463 3464 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG); 3465 if (error) 3466 goto fail; 3467 3468 urtw_read8_m(sc, URTW_CONFIG3, &data); 3469 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE); 3470 urtw_write32_m(sc, URTW_ANAPARAM2, val); 3471 urtw_read8_m(sc, URTW_CONFIG3, &data); 3472 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE); 3473 3474 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL); 3475 if (error) 3476 goto fail; 3477 fail: 3478 return (error); 3479 } 3480 3481 static usb_error_t 3482 urtw_intr_enable(struct urtw_softc *sc) 3483 { 3484 usb_error_t error; 3485 3486 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff); 3487 fail: 3488 return (error); 3489 } 3490 3491 static usb_error_t 3492 urtw_intr_disable(struct urtw_softc *sc) 3493 { 3494 usb_error_t error; 3495 3496 urtw_write16_m(sc, URTW_INTR_MASK, 0); 3497 fail: 3498 return (error); 3499 } 3500 3501 static usb_error_t 3502 urtw_reset(struct urtw_softc *sc) 3503 { 3504 uint8_t data; 3505 usb_error_t error; 3506 3507 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3508 if (error) 3509 goto fail; 3510 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3511 if (error) 3512 goto fail; 3513 3514 error = urtw_intr_disable(sc); 3515 if (error) 3516 goto fail; 3517 usb_pause_mtx(&sc->sc_mtx, 100); 3518 3519 error = urtw_write8e(sc, 0x18, 0x10); 3520 if (error != 0) 3521 goto fail; 3522 error = urtw_write8e(sc, 0x18, 0x11); 3523 if (error != 0) 3524 goto fail; 3525 error = urtw_write8e(sc, 0x18, 0x00); 3526 if (error != 0) 3527 goto fail; 3528 usb_pause_mtx(&sc->sc_mtx, 100); 3529 3530 urtw_read8_m(sc, URTW_CMD, &data); 3531 data = (data & 0x2) | URTW_CMD_RST; 3532 urtw_write8_m(sc, URTW_CMD, data); 3533 usb_pause_mtx(&sc->sc_mtx, 100); 3534 3535 urtw_read8_m(sc, URTW_CMD, &data); 3536 if (data & URTW_CMD_RST) { 3537 device_printf(sc->sc_dev, "reset timeout\n"); 3538 goto fail; 3539 } 3540 3541 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD); 3542 if (error) 3543 goto fail; 3544 usb_pause_mtx(&sc->sc_mtx, 100); 3545 3546 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON); 3547 if (error) 3548 goto fail; 3549 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON); 3550 if (error) 3551 goto fail; 3552 fail: 3553 return (error); 3554 } 3555 3556 static usb_error_t 3557 urtw_led_ctl(struct urtw_softc *sc, int mode) 3558 { 3559 usb_error_t error = 0; 3560 3561 switch (sc->sc_strategy) { 3562 case URTW_SW_LED_MODE0: 3563 error = urtw_led_mode0(sc, mode); 3564 break; 3565 case URTW_SW_LED_MODE1: 3566 error = urtw_led_mode1(sc, mode); 3567 break; 3568 case URTW_SW_LED_MODE2: 3569 error = urtw_led_mode2(sc, mode); 3570 break; 3571 case URTW_SW_LED_MODE3: 3572 error = urtw_led_mode3(sc, mode); 3573 break; 3574 default: 3575 DPRINTF(sc, URTW_DEBUG_STATE, 3576 "unsupported LED mode %d\n", sc->sc_strategy); 3577 error = USB_ERR_INVAL; 3578 break; 3579 } 3580 3581 return (error); 3582 } 3583 3584 static usb_error_t 3585 urtw_led_mode0(struct urtw_softc *sc, int mode) 3586 { 3587 3588 switch (mode) { 3589 case URTW_LED_CTL_POWER_ON: 3590 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK; 3591 break; 3592 case URTW_LED_CTL_TX: 3593 if (sc->sc_gpio_ledinprogress == 1) 3594 return (0); 3595 3596 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL; 3597 sc->sc_gpio_blinktime = 2; 3598 break; 3599 case URTW_LED_CTL_LINK: 3600 sc->sc_gpio_ledstate = URTW_LED_ON; 3601 break; 3602 default: 3603 DPRINTF(sc, URTW_DEBUG_STATE, 3604 "unsupported LED mode 0x%x", mode); 3605 return (USB_ERR_INVAL); 3606 } 3607 3608 switch (sc->sc_gpio_ledstate) { 3609 case URTW_LED_ON: 3610 if (sc->sc_gpio_ledinprogress != 0) 3611 break; 3612 urtw_led_on(sc, URTW_LED_GPIO); 3613 break; 3614 case URTW_LED_BLINK_NORMAL: 3615 if (sc->sc_gpio_ledinprogress != 0) 3616 break; 3617 sc->sc_gpio_ledinprogress = 1; 3618 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ? 3619 URTW_LED_OFF : URTW_LED_ON; 3620 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3621 break; 3622 case URTW_LED_POWER_ON_BLINK: 3623 urtw_led_on(sc, URTW_LED_GPIO); 3624 usb_pause_mtx(&sc->sc_mtx, 100); 3625 urtw_led_off(sc, URTW_LED_GPIO); 3626 break; 3627 default: 3628 DPRINTF(sc, URTW_DEBUG_STATE, 3629 "unknown LED status 0x%x", sc->sc_gpio_ledstate); 3630 return (USB_ERR_INVAL); 3631 } 3632 return (0); 3633 } 3634 3635 static usb_error_t 3636 urtw_led_mode1(struct urtw_softc *sc, int mode) 3637 { 3638 return (USB_ERR_INVAL); 3639 } 3640 3641 static usb_error_t 3642 urtw_led_mode2(struct urtw_softc *sc, int mode) 3643 { 3644 return (USB_ERR_INVAL); 3645 } 3646 3647 static usb_error_t 3648 urtw_led_mode3(struct urtw_softc *sc, int mode) 3649 { 3650 return (USB_ERR_INVAL); 3651 } 3652 3653 static usb_error_t 3654 urtw_led_on(struct urtw_softc *sc, int type) 3655 { 3656 usb_error_t error; 3657 3658 if (type == URTW_LED_GPIO) { 3659 switch (sc->sc_gpio_ledpin) { 3660 case URTW_LED_PIN_GPIO0: 3661 urtw_write8_m(sc, URTW_GPIO, 0x01); 3662 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00); 3663 break; 3664 default: 3665 DPRINTF(sc, URTW_DEBUG_STATE, 3666 "unsupported LED PIN type 0x%x", 3667 sc->sc_gpio_ledpin); 3668 error = USB_ERR_INVAL; 3669 goto fail; 3670 } 3671 } else { 3672 DPRINTF(sc, URTW_DEBUG_STATE, 3673 "unsupported LED type 0x%x", type); 3674 error = USB_ERR_INVAL; 3675 goto fail; 3676 } 3677 3678 sc->sc_gpio_ledon = 1; 3679 fail: 3680 return (error); 3681 } 3682 3683 static usb_error_t 3684 urtw_led_off(struct urtw_softc *sc, int type) 3685 { 3686 usb_error_t error; 3687 3688 if (type == URTW_LED_GPIO) { 3689 switch (sc->sc_gpio_ledpin) { 3690 case URTW_LED_PIN_GPIO0: 3691 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1); 3692 urtw_write8_m(sc, 3693 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1); 3694 break; 3695 default: 3696 DPRINTF(sc, URTW_DEBUG_STATE, 3697 "unsupported LED PIN type 0x%x", 3698 sc->sc_gpio_ledpin); 3699 error = USB_ERR_INVAL; 3700 goto fail; 3701 } 3702 } else { 3703 DPRINTF(sc, URTW_DEBUG_STATE, 3704 "unsupported LED type 0x%x", type); 3705 error = USB_ERR_INVAL; 3706 goto fail; 3707 } 3708 3709 sc->sc_gpio_ledon = 0; 3710 3711 fail: 3712 return (error); 3713 } 3714 3715 static void 3716 urtw_led_ch(void *arg) 3717 { 3718 struct urtw_softc *sc = arg; 3719 struct ieee80211com *ic = &sc->sc_ic; 3720 3721 ieee80211_runtask(ic, &sc->sc_led_task); 3722 } 3723 3724 static void 3725 urtw_ledtask(void *arg, int pending) 3726 { 3727 struct urtw_softc *sc = arg; 3728 3729 if (sc->sc_strategy != URTW_SW_LED_MODE0) { 3730 DPRINTF(sc, URTW_DEBUG_STATE, 3731 "could not process a LED strategy 0x%x", 3732 sc->sc_strategy); 3733 return; 3734 } 3735 3736 URTW_LOCK(sc); 3737 urtw_led_blink(sc); 3738 URTW_UNLOCK(sc); 3739 } 3740 3741 static usb_error_t 3742 urtw_led_blink(struct urtw_softc *sc) 3743 { 3744 uint8_t ing = 0; 3745 usb_error_t error; 3746 3747 if (sc->sc_gpio_blinkstate == URTW_LED_ON) 3748 error = urtw_led_on(sc, URTW_LED_GPIO); 3749 else 3750 error = urtw_led_off(sc, URTW_LED_GPIO); 3751 sc->sc_gpio_blinktime--; 3752 if (sc->sc_gpio_blinktime == 0) 3753 ing = 1; 3754 else { 3755 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL && 3756 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY && 3757 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3) 3758 ing = 1; 3759 } 3760 if (ing == 1) { 3761 if (sc->sc_gpio_ledstate == URTW_LED_ON && 3762 sc->sc_gpio_ledon == 0) 3763 error = urtw_led_on(sc, URTW_LED_GPIO); 3764 else if (sc->sc_gpio_ledstate == URTW_LED_OFF && 3765 sc->sc_gpio_ledon == 1) 3766 error = urtw_led_off(sc, URTW_LED_GPIO); 3767 3768 sc->sc_gpio_blinktime = 0; 3769 sc->sc_gpio_ledinprogress = 0; 3770 return (0); 3771 } 3772 3773 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ? 3774 URTW_LED_ON : URTW_LED_OFF; 3775 3776 switch (sc->sc_gpio_ledstate) { 3777 case URTW_LED_BLINK_NORMAL: 3778 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc); 3779 break; 3780 default: 3781 DPRINTF(sc, URTW_DEBUG_STATE, 3782 "unknown LED status 0x%x", 3783 sc->sc_gpio_ledstate); 3784 return (USB_ERR_INVAL); 3785 } 3786 return (0); 3787 } 3788 3789 static usb_error_t 3790 urtw_rx_enable(struct urtw_softc *sc) 3791 { 3792 uint8_t data; 3793 usb_error_t error; 3794 3795 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ? 3796 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]); 3797 3798 error = urtw_rx_setconf(sc); 3799 if (error != 0) 3800 goto fail; 3801 3802 if ((sc->sc_flags & URTW_RTL8187B) == 0) { 3803 urtw_read8_m(sc, URTW_CMD, &data); 3804 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE); 3805 } 3806 fail: 3807 return (error); 3808 } 3809 3810 static usb_error_t 3811 urtw_tx_enable(struct urtw_softc *sc) 3812 { 3813 uint8_t data8; 3814 uint32_t data; 3815 usb_error_t error; 3816 3817 if (sc->sc_flags & URTW_RTL8187B) { 3818 urtw_read32_m(sc, URTW_TX_CONF, &data); 3819 data &= ~URTW_TX_LOOPBACK_MASK; 3820 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3821 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3822 data &= ~URTW_TX_SWPLCPLEN; 3823 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE | 3824 (7 << 8) | /* short retry limit */ 3825 (7 << 0) | /* long retry limit */ 3826 (7 << 21); /* MAX TX DMA */ 3827 urtw_write32_m(sc, URTW_TX_CONF, data); 3828 3829 urtw_read8_m(sc, URTW_MSR, &data8); 3830 data8 |= URTW_MSR_LINK_ENEDCA; 3831 urtw_write8_m(sc, URTW_MSR, data8); 3832 return (error); 3833 } 3834 3835 urtw_read8_m(sc, URTW_CW_CONF, &data8); 3836 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY); 3837 urtw_write8_m(sc, URTW_CW_CONF, data8); 3838 3839 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8); 3840 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN; 3841 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL; 3842 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT; 3843 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8); 3844 3845 urtw_read32_m(sc, URTW_TX_CONF, &data); 3846 data &= ~URTW_TX_LOOPBACK_MASK; 3847 data |= URTW_TX_LOOPBACK_NONE; 3848 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK); 3849 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT; 3850 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT; 3851 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK); 3852 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW; 3853 data &= ~URTW_TX_SWPLCPLEN; 3854 data |= URTW_TX_NOICV; 3855 urtw_write32_m(sc, URTW_TX_CONF, data); 3856 3857 urtw_read8_m(sc, URTW_CMD, &data8); 3858 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE); 3859 fail: 3860 return (error); 3861 } 3862 3863 static usb_error_t 3864 urtw_rx_setconf(struct urtw_softc *sc) 3865 { 3866 struct ieee80211com *ic = &sc->sc_ic; 3867 uint32_t data; 3868 usb_error_t error; 3869 3870 urtw_read32_m(sc, URTW_RX, &data); 3871 data = data &~ URTW_RX_FILTER_MASK; 3872 if (sc->sc_flags & URTW_RTL8187B) { 3873 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA | 3874 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST | 3875 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID | 3876 URTW_RX_FIFO_THRESHOLD_NONE | 3877 URTW_MAX_RX_DMA_2048 | 3878 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT; 3879 } else { 3880 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA; 3881 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST; 3882 3883 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 3884 data = data | URTW_RX_FILTER_ICVERR; 3885 data = data | URTW_RX_FILTER_PWR; 3886 } 3887 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR) 3888 data = data | URTW_RX_FILTER_CRCERR; 3889 3890 if (ic->ic_opmode == IEEE80211_M_MONITOR || 3891 ic->ic_promisc > 0 || ic->ic_allmulti > 0) { 3892 data = data | URTW_RX_FILTER_ALLMAC; 3893 } else { 3894 data = data | URTW_RX_FILTER_NICMAC; 3895 data = data | URTW_RX_CHECK_BSSID; 3896 } 3897 3898 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK; 3899 data = data | URTW_RX_FIFO_THRESHOLD_NONE | 3900 URTW_RX_AUTORESETPHY; 3901 data = data &~ URTW_MAX_RX_DMA_MASK; 3902 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT; 3903 } 3904 3905 urtw_write32_m(sc, URTW_RX, data); 3906 fail: 3907 return (error); 3908 } 3909 3910 static struct mbuf * 3911 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p, 3912 int8_t *nf_p) 3913 { 3914 int actlen, flen, rssi; 3915 struct ieee80211_frame *wh; 3916 struct mbuf *m, *mnew; 3917 struct urtw_softc *sc = data->sc; 3918 struct ieee80211com *ic = &sc->sc_ic; 3919 uint8_t noise = 0, rate; 3920 3921 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 3922 3923 if (actlen < (int)URTW_MIN_RXBUFSZ) { 3924 counter_u64_add(ic->ic_ierrors, 1); 3925 return (NULL); 3926 } 3927 3928 if (sc->sc_flags & URTW_RTL8187B) { 3929 struct urtw_8187b_rxhdr *rx; 3930 3931 rx = (struct urtw_8187b_rxhdr *)(data->buf + 3932 (actlen - (sizeof(struct urtw_8187b_rxhdr)))); 3933 flen = le32toh(rx->flag) & 0xfff; 3934 if (flen > actlen) { 3935 counter_u64_add(ic->ic_ierrors, 1); 3936 return (NULL); 3937 } 3938 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3939 /* XXX correct? */ 3940 rssi = rx->rssi & URTW_RX_RSSI_MASK; 3941 noise = rx->noise; 3942 } else { 3943 struct urtw_8187l_rxhdr *rx; 3944 3945 rx = (struct urtw_8187l_rxhdr *)(data->buf + 3946 (actlen - (sizeof(struct urtw_8187l_rxhdr)))); 3947 flen = le32toh(rx->flag) & 0xfff; 3948 if (flen > actlen) { 3949 counter_u64_add(ic->ic_ierrors, 1); 3950 return (NULL); 3951 } 3952 3953 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf; 3954 /* XXX correct? */ 3955 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK; 3956 noise = rx->noise; 3957 } 3958 3959 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3960 if (mnew == NULL) { 3961 counter_u64_add(ic->ic_ierrors, 1); 3962 return (NULL); 3963 } 3964 3965 m = data->m; 3966 data->m = mnew; 3967 data->buf = mtod(mnew, uint8_t *); 3968 3969 /* finalize mbuf */ 3970 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN; 3971 3972 if (ieee80211_radiotap_active(ic)) { 3973 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap; 3974 3975 /* XXX Are variables correct? */ 3976 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq); 3977 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags); 3978 tap->wr_dbm_antsignal = (int8_t)rssi; 3979 } 3980 3981 wh = mtod(m, struct ieee80211_frame *); 3982 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA) 3983 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate; 3984 3985 *rssi_p = rssi; 3986 *nf_p = noise; /* XXX correct? */ 3987 3988 return (m); 3989 } 3990 3991 static void 3992 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 3993 { 3994 struct urtw_softc *sc = usbd_xfer_softc(xfer); 3995 struct ieee80211com *ic = &sc->sc_ic; 3996 struct ieee80211_frame *wh; 3997 struct ieee80211_node *ni; 3998 struct mbuf *m = NULL; 3999 struct urtw_data *data; 4000 int8_t nf = -95; 4001 int rssi = 1; 4002 4003 URTW_ASSERT_LOCKED(sc); 4004 4005 switch (USB_GET_STATE(xfer)) { 4006 case USB_ST_TRANSFERRED: 4007 data = STAILQ_FIRST(&sc->sc_rx_active); 4008 if (data == NULL) 4009 goto setup; 4010 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4011 m = urtw_rxeof(xfer, data, &rssi, &nf); 4012 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4013 /* FALLTHROUGH */ 4014 case USB_ST_SETUP: 4015 setup: 4016 data = STAILQ_FIRST(&sc->sc_rx_inactive); 4017 if (data == NULL) { 4018 KASSERT(m == NULL, ("mbuf isn't NULL")); 4019 return; 4020 } 4021 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 4022 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 4023 usbd_xfer_set_frame_data(xfer, 0, data->buf, 4024 usbd_xfer_max_len(xfer)); 4025 usbd_transfer_submit(xfer); 4026 4027 /* 4028 * To avoid LOR we should unlock our private mutex here to call 4029 * ieee80211_input() because here is at the end of a USB 4030 * callback and safe to unlock. 4031 */ 4032 URTW_UNLOCK(sc); 4033 if (m != NULL) { 4034 wh = mtod(m, struct ieee80211_frame *); 4035 ni = ieee80211_find_rxnode(ic, 4036 (struct ieee80211_frame_min *)wh); 4037 if (ni != NULL) { 4038 (void) ieee80211_input(ni, m, rssi, nf); 4039 /* node is no longer needed */ 4040 ieee80211_free_node(ni); 4041 } else 4042 (void) ieee80211_input_all(ic, m, rssi, nf); 4043 m = NULL; 4044 } 4045 URTW_LOCK(sc); 4046 break; 4047 default: 4048 /* needs it to the inactive queue due to a error. */ 4049 data = STAILQ_FIRST(&sc->sc_rx_active); 4050 if (data != NULL) { 4051 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 4052 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 4053 } 4054 if (error != USB_ERR_CANCELLED) { 4055 usbd_xfer_set_stall(xfer); 4056 counter_u64_add(ic->ic_ierrors, 1); 4057 goto setup; 4058 } 4059 break; 4060 } 4061 } 4062 4063 #define URTW_STATUS_TYPE_TXCLOSE 1 4064 #define URTW_STATUS_TYPE_BEACON_INTR 0 4065 4066 static void 4067 urtw_txstatus_eof(struct usb_xfer *xfer) 4068 { 4069 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4070 struct ieee80211com *ic = &sc->sc_ic; 4071 int actlen, type, pktretry, seq; 4072 uint64_t val; 4073 4074 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 4075 4076 if (actlen != sizeof(uint64_t)) 4077 return; 4078 4079 val = le64toh(sc->sc_txstatus); 4080 type = (val >> 30) & 0x3; 4081 if (type == URTW_STATUS_TYPE_TXCLOSE) { 4082 pktretry = val & 0xff; 4083 seq = (val >> 16) & 0xff; 4084 if (pktretry == URTW_TX_MAXRETRY) 4085 counter_u64_add(ic->ic_oerrors, 1); 4086 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n", 4087 pktretry, seq); 4088 } 4089 } 4090 4091 static void 4092 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error) 4093 { 4094 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4095 struct ieee80211com *ic = &sc->sc_ic; 4096 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0); 4097 4098 URTW_ASSERT_LOCKED(sc); 4099 4100 switch (USB_GET_STATE(xfer)) { 4101 case USB_ST_TRANSFERRED: 4102 urtw_txstatus_eof(xfer); 4103 /* FALLTHROUGH */ 4104 case USB_ST_SETUP: 4105 setup: 4106 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t)); 4107 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t)); 4108 usbd_transfer_submit(xfer); 4109 break; 4110 default: 4111 if (error != USB_ERR_CANCELLED) { 4112 usbd_xfer_set_stall(xfer); 4113 counter_u64_add(ic->ic_ierrors, 1); 4114 goto setup; 4115 } 4116 break; 4117 } 4118 } 4119 4120 static void 4121 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data) 4122 { 4123 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4124 4125 URTW_ASSERT_LOCKED(sc); 4126 4127 if (data->m) { 4128 /* XXX status? */ 4129 ieee80211_tx_complete(data->ni, data->m, 0); 4130 data->m = NULL; 4131 data->ni = NULL; 4132 } 4133 sc->sc_txtimer = 0; 4134 } 4135 4136 static void 4137 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 4138 { 4139 struct urtw_softc *sc = usbd_xfer_softc(xfer); 4140 struct urtw_data *data; 4141 4142 URTW_ASSERT_LOCKED(sc); 4143 4144 switch (USB_GET_STATE(xfer)) { 4145 case USB_ST_TRANSFERRED: 4146 data = STAILQ_FIRST(&sc->sc_tx_active); 4147 if (data == NULL) 4148 goto setup; 4149 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 4150 urtw_txeof(xfer, data); 4151 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 4152 /* FALLTHROUGH */ 4153 case USB_ST_SETUP: 4154 setup: 4155 data = STAILQ_FIRST(&sc->sc_tx_pending); 4156 if (data == NULL) { 4157 DPRINTF(sc, URTW_DEBUG_XMIT, 4158 "%s: empty pending queue\n", __func__); 4159 return; 4160 } 4161 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 4162 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 4163 4164 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 4165 usbd_transfer_submit(xfer); 4166 4167 urtw_start(sc); 4168 break; 4169 default: 4170 data = STAILQ_FIRST(&sc->sc_tx_active); 4171 if (data == NULL) 4172 goto setup; 4173 if (data->ni != NULL) { 4174 if_inc_counter(data->ni->ni_vap->iv_ifp, 4175 IFCOUNTER_OERRORS, 1); 4176 ieee80211_free_node(data->ni); 4177 data->ni = NULL; 4178 } 4179 if (error != USB_ERR_CANCELLED) { 4180 usbd_xfer_set_stall(xfer); 4181 goto setup; 4182 } 4183 break; 4184 } 4185 } 4186 4187 static struct urtw_data * 4188 _urtw_getbuf(struct urtw_softc *sc) 4189 { 4190 struct urtw_data *bf; 4191 4192 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 4193 if (bf != NULL) 4194 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 4195 else 4196 bf = NULL; 4197 if (bf == NULL) 4198 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__, 4199 "out of xmit buffers"); 4200 return (bf); 4201 } 4202 4203 static struct urtw_data * 4204 urtw_getbuf(struct urtw_softc *sc) 4205 { 4206 struct urtw_data *bf; 4207 4208 URTW_ASSERT_LOCKED(sc); 4209 4210 bf = _urtw_getbuf(sc); 4211 if (bf == NULL) 4212 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__); 4213 return (bf); 4214 } 4215 4216 static int 4217 urtw_isbmode(uint16_t rate) 4218 { 4219 4220 return ((rate <= 22 && rate != 12 && rate != 18) || 4221 rate == 44) ? (1) : (0); 4222 } 4223 4224 static uint16_t 4225 urtw_rate2dbps(uint16_t rate) 4226 { 4227 4228 switch(rate) { 4229 case 12: 4230 case 18: 4231 case 24: 4232 case 36: 4233 case 48: 4234 case 72: 4235 case 96: 4236 case 108: 4237 return (rate * 2); 4238 default: 4239 break; 4240 } 4241 return (24); 4242 } 4243 4244 static int 4245 urtw_compute_txtime(uint16_t framelen, uint16_t rate, 4246 uint8_t ismgt, uint8_t isshort) 4247 { 4248 uint16_t ceiling, frametime, n_dbps; 4249 4250 if (urtw_isbmode(rate)) { 4251 if (ismgt || !isshort || rate == 2) 4252 frametime = (uint16_t)(144 + 48 + 4253 (framelen * 8 / (rate / 2))); 4254 else 4255 frametime = (uint16_t)(72 + 24 + 4256 (framelen * 8 / (rate / 2))); 4257 if ((framelen * 8 % (rate / 2)) != 0) 4258 frametime++; 4259 } else { 4260 n_dbps = urtw_rate2dbps(rate); 4261 ceiling = (16 + 8 * framelen + 6) / n_dbps 4262 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0); 4263 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6); 4264 } 4265 return (frametime); 4266 } 4267 4268 /* 4269 * Callback from the 802.11 layer to update the 4270 * slot time based on the current setting. 4271 */ 4272 static void 4273 urtw_updateslot(struct ieee80211com *ic) 4274 { 4275 struct urtw_softc *sc = ic->ic_softc; 4276 4277 ieee80211_runtask(ic, &sc->sc_updateslot_task); 4278 } 4279 4280 static void 4281 urtw_updateslottask(void *arg, int pending) 4282 { 4283 struct urtw_softc *sc = arg; 4284 struct ieee80211com *ic = &sc->sc_ic; 4285 int error; 4286 4287 URTW_LOCK(sc); 4288 if ((sc->sc_flags & URTW_RUNNING) == 0) { 4289 URTW_UNLOCK(sc); 4290 return; 4291 } 4292 if (sc->sc_flags & URTW_RTL8187B) { 4293 urtw_write8_m(sc, URTW_SIFS, 0x22); 4294 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 4295 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4296 else 4297 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4298 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b); 4299 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b); 4300 } else { 4301 urtw_write8_m(sc, URTW_SIFS, 0x22); 4302 if (sc->sc_state == IEEE80211_S_ASSOC && 4303 ic->ic_flags & IEEE80211_F_SHSLOT) 4304 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SHSLOT); 4305 else 4306 urtw_write8_m(sc, URTW_SLOT, IEEE80211_DUR_SLOT); 4307 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) { 4308 urtw_write8_m(sc, URTW_DIFS, 0x14); 4309 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14); 4310 urtw_write8_m(sc, URTW_CW_VAL, 0x73); 4311 } else { 4312 urtw_write8_m(sc, URTW_DIFS, 0x24); 4313 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24); 4314 urtw_write8_m(sc, URTW_CW_VAL, 0xa5); 4315 } 4316 } 4317 fail: 4318 URTW_UNLOCK(sc); 4319 } 4320 4321 static void 4322 urtw_sysctl_node(struct urtw_softc *sc) 4323 { 4324 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 4325 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 4326 struct sysctl_ctx_list *ctx; 4327 struct sysctl_oid_list *child, *parent; 4328 struct sysctl_oid *tree; 4329 struct urtw_stats *stats = &sc->sc_stats; 4330 4331 ctx = device_get_sysctl_ctx(sc->sc_dev); 4332 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 4333 4334 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4335 NULL, "URTW statistics"); 4336 parent = SYSCTL_CHILDREN(tree); 4337 4338 /* Tx statistics. */ 4339 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 4340 NULL, "Tx MAC statistics"); 4341 child = SYSCTL_CHILDREN(tree); 4342 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0], 4343 "1 Mbit/s"); 4344 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1], 4345 "2 Mbit/s"); 4346 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2], 4347 "5.5 Mbit/s"); 4348 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4], 4349 "6 Mbit/s"); 4350 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5], 4351 "9 Mbit/s"); 4352 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3], 4353 "11 Mbit/s"); 4354 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6], 4355 "12 Mbit/s"); 4356 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7], 4357 "18 Mbit/s"); 4358 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8], 4359 "24 Mbit/s"); 4360 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9], 4361 "36 Mbit/s"); 4362 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10], 4363 "48 Mbit/s"); 4364 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11], 4365 "54 Mbit/s"); 4366 #undef URTW_SYSCTL_STAT_ADD32 4367 } 4368 4369 static device_method_t urtw_methods[] = { 4370 DEVMETHOD(device_probe, urtw_match), 4371 DEVMETHOD(device_attach, urtw_attach), 4372 DEVMETHOD(device_detach, urtw_detach), 4373 DEVMETHOD_END 4374 }; 4375 static driver_t urtw_driver = { 4376 .name = "urtw", 4377 .methods = urtw_methods, 4378 .size = sizeof(struct urtw_softc) 4379 }; 4380 static devclass_t urtw_devclass; 4381 4382 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0); 4383 MODULE_DEPEND(urtw, wlan, 1, 1, 1); 4384 MODULE_DEPEND(urtw, usb, 1, 1, 1); 4385 MODULE_VERSION(urtw, 1); 4386 USB_PNP_HOST_INFO(urtw_devs); 4387