1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 /*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kdb.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/rman.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/if_ether.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include "usbdevs.h" 75 76 #define USB_DEBUG_VAR ural_debug 77 #include <dev/usb/usb_debug.h> 78 79 #include <dev/usb/wlan/if_uralreg.h> 80 #include <dev/usb/wlan/if_uralvar.h> 81 82 #ifdef USB_DEBUG 83 static int ural_debug = 0; 84 85 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 86 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 87 "Debug level"); 88 #endif 89 90 #define URAL_RSSI(rssi) \ 91 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 92 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 93 94 /* various supported device vendors/products */ 95 static const STRUCT_USB_HOST_ID ural_devs[] = { 96 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 97 URAL_DEV(ASUS, WL167G), 98 URAL_DEV(ASUS, RT2570), 99 URAL_DEV(BELKIN, F5D7050), 100 URAL_DEV(BELKIN, F5D7051), 101 URAL_DEV(CISCOLINKSYS, HU200TS), 102 URAL_DEV(CISCOLINKSYS, WUSB54G), 103 URAL_DEV(CISCOLINKSYS, WUSB54GP), 104 URAL_DEV(CONCEPTRONIC2, C54RU), 105 URAL_DEV(DLINK, DWLG122), 106 URAL_DEV(GIGABYTE, GN54G), 107 URAL_DEV(GIGABYTE, GNWBKG), 108 URAL_DEV(GUILLEMOT, HWGUSB254), 109 URAL_DEV(MELCO, KG54), 110 URAL_DEV(MELCO, KG54AI), 111 URAL_DEV(MELCO, KG54YB), 112 URAL_DEV(MELCO, NINWIFI), 113 URAL_DEV(MSI, RT2570), 114 URAL_DEV(MSI, RT2570_2), 115 URAL_DEV(MSI, RT2570_3), 116 URAL_DEV(NOVATECH, NV902), 117 URAL_DEV(RALINK, RT2570), 118 URAL_DEV(RALINK, RT2570_2), 119 URAL_DEV(RALINK, RT2570_3), 120 URAL_DEV(SIEMENS2, WL54G), 121 URAL_DEV(SMC, 2862WG), 122 URAL_DEV(SPHAIRON, UB801R), 123 URAL_DEV(SURECOM, RT2570), 124 URAL_DEV(VTECH, RT2570), 125 URAL_DEV(ZINWELL, RT2570), 126 #undef URAL_DEV 127 }; 128 129 static usb_callback_t ural_bulk_read_callback; 130 static usb_callback_t ural_bulk_write_callback; 131 132 static usb_error_t ural_do_request(struct ural_softc *sc, 133 struct usb_device_request *req, void *data); 134 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 135 const char [IFNAMSIZ], int, enum ieee80211_opmode, 136 int, const uint8_t [IEEE80211_ADDR_LEN], 137 const uint8_t [IEEE80211_ADDR_LEN]); 138 static void ural_vap_delete(struct ieee80211vap *); 139 static void ural_tx_free(struct ural_tx_data *, int); 140 static void ural_setup_tx_list(struct ural_softc *); 141 static void ural_unsetup_tx_list(struct ural_softc *); 142 static int ural_newstate(struct ieee80211vap *, 143 enum ieee80211_state, int); 144 static void ural_setup_tx_desc(struct ural_softc *, 145 struct ural_tx_desc *, uint32_t, int, int); 146 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 147 struct ieee80211_node *); 148 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 149 struct ieee80211_node *); 150 static int ural_tx_data(struct ural_softc *, struct mbuf *, 151 struct ieee80211_node *); 152 static void ural_start(struct ifnet *); 153 static int ural_ioctl(struct ifnet *, u_long, caddr_t); 154 static void ural_set_testmode(struct ural_softc *); 155 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 156 int); 157 static uint16_t ural_read(struct ural_softc *, uint16_t); 158 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 159 int); 160 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 161 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 162 int) __unused; 163 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 164 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 165 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 166 static void ural_scan_start(struct ieee80211com *); 167 static void ural_scan_end(struct ieee80211com *); 168 static void ural_set_channel(struct ieee80211com *); 169 static void ural_set_chan(struct ural_softc *, 170 struct ieee80211_channel *); 171 static void ural_disable_rf_tune(struct ural_softc *); 172 static void ural_enable_tsf_sync(struct ural_softc *); 173 static void ural_enable_tsf(struct ural_softc *); 174 static void ural_update_slot(struct ifnet *); 175 static void ural_set_txpreamble(struct ural_softc *); 176 static void ural_set_basicrates(struct ural_softc *, 177 const struct ieee80211_channel *); 178 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 179 static void ural_set_macaddr(struct ural_softc *, uint8_t *); 180 static void ural_update_promisc(struct ieee80211com *); 181 static void ural_setpromisc(struct ural_softc *); 182 static const char *ural_get_rf(int); 183 static void ural_read_eeprom(struct ural_softc *); 184 static int ural_bbp_init(struct ural_softc *); 185 static void ural_set_txantenna(struct ural_softc *, int); 186 static void ural_set_rxantenna(struct ural_softc *, int); 187 static void ural_init_locked(struct ural_softc *); 188 static void ural_init(void *); 189 static void ural_stop(struct ural_softc *); 190 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 191 const struct ieee80211_bpf_params *); 192 static void ural_ratectl_start(struct ural_softc *, 193 struct ieee80211_node *); 194 static void ural_ratectl_timeout(void *); 195 static void ural_ratectl_task(void *, int); 196 static int ural_pause(struct ural_softc *sc, int timeout); 197 198 /* 199 * Default values for MAC registers; values taken from the reference driver. 200 */ 201 static const struct { 202 uint16_t reg; 203 uint16_t val; 204 } ural_def_mac[] = { 205 { RAL_TXRX_CSR5, 0x8c8d }, 206 { RAL_TXRX_CSR6, 0x8b8a }, 207 { RAL_TXRX_CSR7, 0x8687 }, 208 { RAL_TXRX_CSR8, 0x0085 }, 209 { RAL_MAC_CSR13, 0x1111 }, 210 { RAL_MAC_CSR14, 0x1e11 }, 211 { RAL_TXRX_CSR21, 0xe78f }, 212 { RAL_MAC_CSR9, 0xff1d }, 213 { RAL_MAC_CSR11, 0x0002 }, 214 { RAL_MAC_CSR22, 0x0053 }, 215 { RAL_MAC_CSR15, 0x0000 }, 216 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 217 { RAL_TXRX_CSR19, 0x0000 }, 218 { RAL_TXRX_CSR18, 0x005a }, 219 { RAL_PHY_CSR2, 0x0000 }, 220 { RAL_TXRX_CSR0, 0x1ec0 }, 221 { RAL_PHY_CSR4, 0x000f } 222 }; 223 224 /* 225 * Default values for BBP registers; values taken from the reference driver. 226 */ 227 static const struct { 228 uint8_t reg; 229 uint8_t val; 230 } ural_def_bbp[] = { 231 { 3, 0x02 }, 232 { 4, 0x19 }, 233 { 14, 0x1c }, 234 { 15, 0x30 }, 235 { 16, 0xac }, 236 { 17, 0x48 }, 237 { 18, 0x18 }, 238 { 19, 0xff }, 239 { 20, 0x1e }, 240 { 21, 0x08 }, 241 { 22, 0x08 }, 242 { 23, 0x08 }, 243 { 24, 0x80 }, 244 { 25, 0x50 }, 245 { 26, 0x08 }, 246 { 27, 0x23 }, 247 { 30, 0x10 }, 248 { 31, 0x2b }, 249 { 32, 0xb9 }, 250 { 34, 0x12 }, 251 { 35, 0x50 }, 252 { 39, 0xc4 }, 253 { 40, 0x02 }, 254 { 41, 0x60 }, 255 { 53, 0x10 }, 256 { 54, 0x18 }, 257 { 56, 0x08 }, 258 { 57, 0x10 }, 259 { 58, 0x08 }, 260 { 61, 0x60 }, 261 { 62, 0x10 }, 262 { 75, 0xff } 263 }; 264 265 /* 266 * Default values for RF register R2 indexed by channel numbers. 267 */ 268 static const uint32_t ural_rf2522_r2[] = { 269 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 270 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 271 }; 272 273 static const uint32_t ural_rf2523_r2[] = { 274 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 275 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 276 }; 277 278 static const uint32_t ural_rf2524_r2[] = { 279 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 280 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 281 }; 282 283 static const uint32_t ural_rf2525_r2[] = { 284 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 285 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 286 }; 287 288 static const uint32_t ural_rf2525_hi_r2[] = { 289 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 290 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 291 }; 292 293 static const uint32_t ural_rf2525e_r2[] = { 294 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 295 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 296 }; 297 298 static const uint32_t ural_rf2526_hi_r2[] = { 299 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 300 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 301 }; 302 303 static const uint32_t ural_rf2526_r2[] = { 304 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 305 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 306 }; 307 308 /* 309 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 310 * values taken from the reference driver. 311 */ 312 static const struct { 313 uint8_t chan; 314 uint32_t r1; 315 uint32_t r2; 316 uint32_t r4; 317 } ural_rf5222[] = { 318 { 1, 0x08808, 0x0044d, 0x00282 }, 319 { 2, 0x08808, 0x0044e, 0x00282 }, 320 { 3, 0x08808, 0x0044f, 0x00282 }, 321 { 4, 0x08808, 0x00460, 0x00282 }, 322 { 5, 0x08808, 0x00461, 0x00282 }, 323 { 6, 0x08808, 0x00462, 0x00282 }, 324 { 7, 0x08808, 0x00463, 0x00282 }, 325 { 8, 0x08808, 0x00464, 0x00282 }, 326 { 9, 0x08808, 0x00465, 0x00282 }, 327 { 10, 0x08808, 0x00466, 0x00282 }, 328 { 11, 0x08808, 0x00467, 0x00282 }, 329 { 12, 0x08808, 0x00468, 0x00282 }, 330 { 13, 0x08808, 0x00469, 0x00282 }, 331 { 14, 0x08808, 0x0046b, 0x00286 }, 332 333 { 36, 0x08804, 0x06225, 0x00287 }, 334 { 40, 0x08804, 0x06226, 0x00287 }, 335 { 44, 0x08804, 0x06227, 0x00287 }, 336 { 48, 0x08804, 0x06228, 0x00287 }, 337 { 52, 0x08804, 0x06229, 0x00287 }, 338 { 56, 0x08804, 0x0622a, 0x00287 }, 339 { 60, 0x08804, 0x0622b, 0x00287 }, 340 { 64, 0x08804, 0x0622c, 0x00287 }, 341 342 { 100, 0x08804, 0x02200, 0x00283 }, 343 { 104, 0x08804, 0x02201, 0x00283 }, 344 { 108, 0x08804, 0x02202, 0x00283 }, 345 { 112, 0x08804, 0x02203, 0x00283 }, 346 { 116, 0x08804, 0x02204, 0x00283 }, 347 { 120, 0x08804, 0x02205, 0x00283 }, 348 { 124, 0x08804, 0x02206, 0x00283 }, 349 { 128, 0x08804, 0x02207, 0x00283 }, 350 { 132, 0x08804, 0x02208, 0x00283 }, 351 { 136, 0x08804, 0x02209, 0x00283 }, 352 { 140, 0x08804, 0x0220a, 0x00283 }, 353 354 { 149, 0x08808, 0x02429, 0x00281 }, 355 { 153, 0x08808, 0x0242b, 0x00281 }, 356 { 157, 0x08808, 0x0242d, 0x00281 }, 357 { 161, 0x08808, 0x0242f, 0x00281 } 358 }; 359 360 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 361 [URAL_BULK_WR] = { 362 .type = UE_BULK, 363 .endpoint = UE_ADDR_ANY, 364 .direction = UE_DIR_OUT, 365 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 366 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 367 .callback = ural_bulk_write_callback, 368 .timeout = 5000, /* ms */ 369 }, 370 [URAL_BULK_RD] = { 371 .type = UE_BULK, 372 .endpoint = UE_ADDR_ANY, 373 .direction = UE_DIR_IN, 374 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 375 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 376 .callback = ural_bulk_read_callback, 377 }, 378 }; 379 380 static device_probe_t ural_match; 381 static device_attach_t ural_attach; 382 static device_detach_t ural_detach; 383 384 static device_method_t ural_methods[] = { 385 /* Device interface */ 386 DEVMETHOD(device_probe, ural_match), 387 DEVMETHOD(device_attach, ural_attach), 388 DEVMETHOD(device_detach, ural_detach), 389 DEVMETHOD_END 390 }; 391 392 static driver_t ural_driver = { 393 .name = "ural", 394 .methods = ural_methods, 395 .size = sizeof(struct ural_softc), 396 }; 397 398 static devclass_t ural_devclass; 399 400 DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 401 MODULE_DEPEND(ural, usb, 1, 1, 1); 402 MODULE_DEPEND(ural, wlan, 1, 1, 1); 403 MODULE_VERSION(ural, 1); 404 405 static int 406 ural_match(device_t self) 407 { 408 struct usb_attach_arg *uaa = device_get_ivars(self); 409 410 if (uaa->usb_mode != USB_MODE_HOST) 411 return (ENXIO); 412 if (uaa->info.bConfigIndex != 0) 413 return (ENXIO); 414 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 415 return (ENXIO); 416 417 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 418 } 419 420 static int 421 ural_attach(device_t self) 422 { 423 struct usb_attach_arg *uaa = device_get_ivars(self); 424 struct ural_softc *sc = device_get_softc(self); 425 struct ifnet *ifp; 426 struct ieee80211com *ic; 427 uint8_t iface_index, bands; 428 int error; 429 430 device_set_usb_desc(self); 431 sc->sc_udev = uaa->device; 432 sc->sc_dev = self; 433 434 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 435 MTX_NETWORK_LOCK, MTX_DEF); 436 437 iface_index = RAL_IFACE_INDEX; 438 error = usbd_transfer_setup(uaa->device, 439 &iface_index, sc->sc_xfer, ural_config, 440 URAL_N_TRANSFER, sc, &sc->sc_mtx); 441 if (error) { 442 device_printf(self, "could not allocate USB transfers, " 443 "err=%s\n", usbd_errstr(error)); 444 goto detach; 445 } 446 447 RAL_LOCK(sc); 448 /* retrieve RT2570 rev. no */ 449 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 450 451 /* retrieve MAC address and various other things from EEPROM */ 452 ural_read_eeprom(sc); 453 RAL_UNLOCK(sc); 454 455 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 456 sc->asic_rev, ural_get_rf(sc->rf_rev)); 457 458 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 459 if (ifp == NULL) { 460 device_printf(sc->sc_dev, "can not if_alloc()\n"); 461 goto detach; 462 } 463 ic = ifp->if_l2com; 464 465 ifp->if_softc = sc; 466 if_initname(ifp, "ural", device_get_unit(sc->sc_dev)); 467 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 468 ifp->if_init = ural_init; 469 ifp->if_ioctl = ural_ioctl; 470 ifp->if_start = ural_start; 471 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 472 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 473 IFQ_SET_READY(&ifp->if_snd); 474 475 ic->ic_ifp = ifp; 476 ic->ic_softc = sc; 477 ic->ic_name = device_get_nameunit(self); 478 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 479 480 /* set device capabilities */ 481 ic->ic_caps = 482 IEEE80211_C_STA /* station mode supported */ 483 | IEEE80211_C_IBSS /* IBSS mode supported */ 484 | IEEE80211_C_MONITOR /* monitor mode supported */ 485 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 486 | IEEE80211_C_TXPMGT /* tx power management */ 487 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 488 | IEEE80211_C_SHSLOT /* short slot time supported */ 489 | IEEE80211_C_BGSCAN /* bg scanning supported */ 490 | IEEE80211_C_WPA /* 802.11i */ 491 ; 492 493 bands = 0; 494 setbit(&bands, IEEE80211_MODE_11B); 495 setbit(&bands, IEEE80211_MODE_11G); 496 if (sc->rf_rev == RAL_RF_5222) 497 setbit(&bands, IEEE80211_MODE_11A); 498 ieee80211_init_channels(ic, NULL, &bands); 499 500 ieee80211_ifattach(ic, sc->sc_bssid); 501 ic->ic_update_promisc = ural_update_promisc; 502 ic->ic_raw_xmit = ural_raw_xmit; 503 ic->ic_scan_start = ural_scan_start; 504 ic->ic_scan_end = ural_scan_end; 505 ic->ic_set_channel = ural_set_channel; 506 507 ic->ic_vap_create = ural_vap_create; 508 ic->ic_vap_delete = ural_vap_delete; 509 510 ieee80211_radiotap_attach(ic, 511 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 512 RAL_TX_RADIOTAP_PRESENT, 513 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 514 RAL_RX_RADIOTAP_PRESENT); 515 516 if (bootverbose) 517 ieee80211_announce(ic); 518 519 return (0); 520 521 detach: 522 ural_detach(self); 523 return (ENXIO); /* failure */ 524 } 525 526 static int 527 ural_detach(device_t self) 528 { 529 struct ural_softc *sc = device_get_softc(self); 530 struct ifnet *ifp = sc->sc_ifp; 531 struct ieee80211com *ic; 532 533 /* prevent further ioctls */ 534 RAL_LOCK(sc); 535 sc->sc_detached = 1; 536 RAL_UNLOCK(sc); 537 538 /* stop all USB transfers */ 539 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 540 541 /* free TX list, if any */ 542 RAL_LOCK(sc); 543 ural_unsetup_tx_list(sc); 544 RAL_UNLOCK(sc); 545 546 if (ifp) { 547 ic = ifp->if_l2com; 548 ieee80211_ifdetach(ic); 549 if_free(ifp); 550 } 551 mtx_destroy(&sc->sc_mtx); 552 553 return (0); 554 } 555 556 static usb_error_t 557 ural_do_request(struct ural_softc *sc, 558 struct usb_device_request *req, void *data) 559 { 560 usb_error_t err; 561 int ntries = 10; 562 563 while (ntries--) { 564 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 565 req, data, 0, NULL, 250 /* ms */); 566 if (err == 0) 567 break; 568 569 DPRINTFN(1, "Control request failed, %s (retrying)\n", 570 usbd_errstr(err)); 571 if (ural_pause(sc, hz / 100)) 572 break; 573 } 574 return (err); 575 } 576 577 static struct ieee80211vap * 578 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 579 enum ieee80211_opmode opmode, int flags, 580 const uint8_t bssid[IEEE80211_ADDR_LEN], 581 const uint8_t mac[IEEE80211_ADDR_LEN]) 582 { 583 struct ural_softc *sc = ic->ic_ifp->if_softc; 584 struct ural_vap *uvp; 585 struct ieee80211vap *vap; 586 587 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 588 return NULL; 589 uvp = (struct ural_vap *) malloc(sizeof(struct ural_vap), 590 M_80211_VAP, M_NOWAIT | M_ZERO); 591 if (uvp == NULL) 592 return NULL; 593 vap = &uvp->vap; 594 /* enable s/w bmiss handling for sta mode */ 595 596 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 597 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) { 598 /* out of memory */ 599 free(uvp, M_80211_VAP); 600 return (NULL); 601 } 602 603 /* override state transition machine */ 604 uvp->newstate = vap->iv_newstate; 605 vap->iv_newstate = ural_newstate; 606 607 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 608 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 609 ieee80211_ratectl_init(vap); 610 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 611 612 /* complete setup */ 613 ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); 614 ic->ic_opmode = opmode; 615 return vap; 616 } 617 618 static void 619 ural_vap_delete(struct ieee80211vap *vap) 620 { 621 struct ural_vap *uvp = URAL_VAP(vap); 622 struct ieee80211com *ic = vap->iv_ic; 623 624 usb_callout_drain(&uvp->ratectl_ch); 625 ieee80211_draintask(ic, &uvp->ratectl_task); 626 ieee80211_ratectl_deinit(vap); 627 ieee80211_vap_detach(vap); 628 free(uvp, M_80211_VAP); 629 } 630 631 static void 632 ural_tx_free(struct ural_tx_data *data, int txerr) 633 { 634 struct ural_softc *sc = data->sc; 635 636 if (data->m != NULL) { 637 if (data->m->m_flags & M_TXCB) 638 ieee80211_process_callback(data->ni, data->m, 639 txerr ? ETIMEDOUT : 0); 640 m_freem(data->m); 641 data->m = NULL; 642 643 ieee80211_free_node(data->ni); 644 data->ni = NULL; 645 } 646 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 647 sc->tx_nfree++; 648 } 649 650 static void 651 ural_setup_tx_list(struct ural_softc *sc) 652 { 653 struct ural_tx_data *data; 654 int i; 655 656 sc->tx_nfree = 0; 657 STAILQ_INIT(&sc->tx_q); 658 STAILQ_INIT(&sc->tx_free); 659 660 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 661 data = &sc->tx_data[i]; 662 663 data->sc = sc; 664 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 665 sc->tx_nfree++; 666 } 667 } 668 669 static void 670 ural_unsetup_tx_list(struct ural_softc *sc) 671 { 672 struct ural_tx_data *data; 673 int i; 674 675 /* make sure any subsequent use of the queues will fail */ 676 sc->tx_nfree = 0; 677 STAILQ_INIT(&sc->tx_q); 678 STAILQ_INIT(&sc->tx_free); 679 680 /* free up all node references and mbufs */ 681 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 682 data = &sc->tx_data[i]; 683 684 if (data->m != NULL) { 685 m_freem(data->m); 686 data->m = NULL; 687 } 688 if (data->ni != NULL) { 689 ieee80211_free_node(data->ni); 690 data->ni = NULL; 691 } 692 } 693 } 694 695 static int 696 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 697 { 698 struct ural_vap *uvp = URAL_VAP(vap); 699 struct ieee80211com *ic = vap->iv_ic; 700 struct ural_softc *sc = ic->ic_ifp->if_softc; 701 const struct ieee80211_txparam *tp; 702 struct ieee80211_node *ni; 703 struct mbuf *m; 704 705 DPRINTF("%s -> %s\n", 706 ieee80211_state_name[vap->iv_state], 707 ieee80211_state_name[nstate]); 708 709 IEEE80211_UNLOCK(ic); 710 RAL_LOCK(sc); 711 usb_callout_stop(&uvp->ratectl_ch); 712 713 switch (nstate) { 714 case IEEE80211_S_INIT: 715 if (vap->iv_state == IEEE80211_S_RUN) { 716 /* abort TSF synchronization */ 717 ural_write(sc, RAL_TXRX_CSR19, 0); 718 719 /* force tx led to stop blinking */ 720 ural_write(sc, RAL_MAC_CSR20, 0); 721 } 722 break; 723 724 case IEEE80211_S_RUN: 725 ni = ieee80211_ref_node(vap->iv_bss); 726 727 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 728 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 729 RAL_UNLOCK(sc); 730 IEEE80211_LOCK(ic); 731 ieee80211_free_node(ni); 732 return (-1); 733 } 734 ural_update_slot(ic->ic_ifp); 735 ural_set_txpreamble(sc); 736 ural_set_basicrates(sc, ic->ic_bsschan); 737 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 738 ural_set_bssid(sc, sc->sc_bssid); 739 } 740 741 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 742 vap->iv_opmode == IEEE80211_M_IBSS) { 743 m = ieee80211_beacon_alloc(ni, &uvp->bo); 744 if (m == NULL) { 745 device_printf(sc->sc_dev, 746 "could not allocate beacon\n"); 747 RAL_UNLOCK(sc); 748 IEEE80211_LOCK(ic); 749 ieee80211_free_node(ni); 750 return (-1); 751 } 752 ieee80211_ref_node(ni); 753 if (ural_tx_bcn(sc, m, ni) != 0) { 754 device_printf(sc->sc_dev, 755 "could not send beacon\n"); 756 RAL_UNLOCK(sc); 757 IEEE80211_LOCK(ic); 758 ieee80211_free_node(ni); 759 return (-1); 760 } 761 } 762 763 /* make tx led blink on tx (controlled by ASIC) */ 764 ural_write(sc, RAL_MAC_CSR20, 1); 765 766 if (vap->iv_opmode != IEEE80211_M_MONITOR) 767 ural_enable_tsf_sync(sc); 768 else 769 ural_enable_tsf(sc); 770 771 /* enable automatic rate adaptation */ 772 /* XXX should use ic_bsschan but not valid until after newstate call below */ 773 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 774 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 775 ural_ratectl_start(sc, ni); 776 ieee80211_free_node(ni); 777 break; 778 779 default: 780 break; 781 } 782 RAL_UNLOCK(sc); 783 IEEE80211_LOCK(ic); 784 return (uvp->newstate(vap, nstate, arg)); 785 } 786 787 788 static void 789 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 790 { 791 struct ural_softc *sc = usbd_xfer_softc(xfer); 792 struct ifnet *ifp = sc->sc_ifp; 793 struct ieee80211vap *vap; 794 struct ural_tx_data *data; 795 struct mbuf *m; 796 struct usb_page_cache *pc; 797 int len; 798 799 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 800 801 switch (USB_GET_STATE(xfer)) { 802 case USB_ST_TRANSFERRED: 803 DPRINTFN(11, "transfer complete, %d bytes\n", len); 804 805 /* free resources */ 806 data = usbd_xfer_get_priv(xfer); 807 ural_tx_free(data, 0); 808 usbd_xfer_set_priv(xfer, NULL); 809 810 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 811 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 812 813 /* FALLTHROUGH */ 814 case USB_ST_SETUP: 815 tr_setup: 816 data = STAILQ_FIRST(&sc->tx_q); 817 if (data) { 818 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 819 m = data->m; 820 821 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 822 DPRINTFN(0, "data overflow, %u bytes\n", 823 m->m_pkthdr.len); 824 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 825 } 826 pc = usbd_xfer_get_frame(xfer, 0); 827 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 828 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 829 m->m_pkthdr.len); 830 831 vap = data->ni->ni_vap; 832 if (ieee80211_radiotap_active_vap(vap)) { 833 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 834 835 tap->wt_flags = 0; 836 tap->wt_rate = data->rate; 837 tap->wt_antenna = sc->tx_ant; 838 839 ieee80211_radiotap_tx(vap, m); 840 } 841 842 /* xfer length needs to be a multiple of two! */ 843 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 844 if ((len % 64) == 0) 845 len += 2; 846 847 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 848 m->m_pkthdr.len, len); 849 850 usbd_xfer_set_frame_len(xfer, 0, len); 851 usbd_xfer_set_priv(xfer, data); 852 853 usbd_transfer_submit(xfer); 854 } 855 RAL_UNLOCK(sc); 856 ural_start(ifp); 857 RAL_LOCK(sc); 858 break; 859 860 default: /* Error */ 861 DPRINTFN(11, "transfer error, %s\n", 862 usbd_errstr(error)); 863 864 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 865 data = usbd_xfer_get_priv(xfer); 866 if (data != NULL) { 867 ural_tx_free(data, error); 868 usbd_xfer_set_priv(xfer, NULL); 869 } 870 871 if (error == USB_ERR_STALLED) { 872 /* try to clear stall first */ 873 usbd_xfer_set_stall(xfer); 874 goto tr_setup; 875 } 876 if (error == USB_ERR_TIMEOUT) 877 device_printf(sc->sc_dev, "device timeout\n"); 878 break; 879 } 880 } 881 882 static void 883 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 884 { 885 struct ural_softc *sc = usbd_xfer_softc(xfer); 886 struct ifnet *ifp = sc->sc_ifp; 887 struct ieee80211com *ic = ifp->if_l2com; 888 struct ieee80211_node *ni; 889 struct mbuf *m = NULL; 890 struct usb_page_cache *pc; 891 uint32_t flags; 892 int8_t rssi = 0, nf = 0; 893 int len; 894 895 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 896 897 switch (USB_GET_STATE(xfer)) { 898 case USB_ST_TRANSFERRED: 899 900 DPRINTFN(15, "rx done, actlen=%d\n", len); 901 902 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 903 DPRINTF("%s: xfer too short %d\n", 904 device_get_nameunit(sc->sc_dev), len); 905 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 906 goto tr_setup; 907 } 908 909 len -= RAL_RX_DESC_SIZE; 910 /* rx descriptor is located at the end */ 911 pc = usbd_xfer_get_frame(xfer, 0); 912 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 913 914 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 915 nf = RAL_NOISE_FLOOR; 916 flags = le32toh(sc->sc_rx_desc.flags); 917 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 918 /* 919 * This should not happen since we did not 920 * request to receive those frames when we 921 * filled RAL_TXRX_CSR2: 922 */ 923 DPRINTFN(5, "PHY or CRC error\n"); 924 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 925 goto tr_setup; 926 } 927 928 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 929 if (m == NULL) { 930 DPRINTF("could not allocate mbuf\n"); 931 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 932 goto tr_setup; 933 } 934 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 935 936 /* finalize mbuf */ 937 m->m_pkthdr.rcvif = ifp; 938 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 939 940 if (ieee80211_radiotap_active(ic)) { 941 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 942 943 /* XXX set once */ 944 tap->wr_flags = 0; 945 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 946 (flags & RAL_RX_OFDM) ? 947 IEEE80211_T_OFDM : IEEE80211_T_CCK); 948 tap->wr_antenna = sc->rx_ant; 949 tap->wr_antsignal = nf + rssi; 950 tap->wr_antnoise = nf; 951 } 952 /* Strip trailing 802.11 MAC FCS. */ 953 m_adj(m, -IEEE80211_CRC_LEN); 954 955 /* FALLTHROUGH */ 956 case USB_ST_SETUP: 957 tr_setup: 958 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 959 usbd_transfer_submit(xfer); 960 961 /* 962 * At the end of a USB callback it is always safe to unlock 963 * the private mutex of a device! That is why we do the 964 * "ieee80211_input" here, and not some lines up! 965 */ 966 RAL_UNLOCK(sc); 967 if (m) { 968 ni = ieee80211_find_rxnode(ic, 969 mtod(m, struct ieee80211_frame_min *)); 970 if (ni != NULL) { 971 (void) ieee80211_input(ni, m, rssi, nf); 972 ieee80211_free_node(ni); 973 } else 974 (void) ieee80211_input_all(ic, m, rssi, nf); 975 } 976 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 977 !IFQ_IS_EMPTY(&ifp->if_snd)) 978 ural_start(ifp); 979 RAL_LOCK(sc); 980 return; 981 982 default: /* Error */ 983 if (error != USB_ERR_CANCELLED) { 984 /* try to clear stall first */ 985 usbd_xfer_set_stall(xfer); 986 goto tr_setup; 987 } 988 return; 989 } 990 } 991 992 static uint8_t 993 ural_plcp_signal(int rate) 994 { 995 switch (rate) { 996 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 997 case 12: return 0xb; 998 case 18: return 0xf; 999 case 24: return 0xa; 1000 case 36: return 0xe; 1001 case 48: return 0x9; 1002 case 72: return 0xd; 1003 case 96: return 0x8; 1004 case 108: return 0xc; 1005 1006 /* CCK rates (NB: not IEEE std, device-specific) */ 1007 case 2: return 0x0; 1008 case 4: return 0x1; 1009 case 11: return 0x2; 1010 case 22: return 0x3; 1011 } 1012 return 0xff; /* XXX unsupported/unknown rate */ 1013 } 1014 1015 static void 1016 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 1017 uint32_t flags, int len, int rate) 1018 { 1019 struct ifnet *ifp = sc->sc_ifp; 1020 struct ieee80211com *ic = ifp->if_l2com; 1021 uint16_t plcp_length; 1022 int remainder; 1023 1024 desc->flags = htole32(flags); 1025 desc->flags |= htole32(RAL_TX_NEWSEQ); 1026 desc->flags |= htole32(len << 16); 1027 1028 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 1029 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 1030 1031 /* setup PLCP fields */ 1032 desc->plcp_signal = ural_plcp_signal(rate); 1033 desc->plcp_service = 4; 1034 1035 len += IEEE80211_CRC_LEN; 1036 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1037 desc->flags |= htole32(RAL_TX_OFDM); 1038 1039 plcp_length = len & 0xfff; 1040 desc->plcp_length_hi = plcp_length >> 6; 1041 desc->plcp_length_lo = plcp_length & 0x3f; 1042 } else { 1043 if (rate == 0) 1044 rate = 2; /* avoid division by zero */ 1045 plcp_length = (16 * len + rate - 1) / rate; 1046 if (rate == 22) { 1047 remainder = (16 * len) % 22; 1048 if (remainder != 0 && remainder < 7) 1049 desc->plcp_service |= RAL_PLCP_LENGEXT; 1050 } 1051 desc->plcp_length_hi = plcp_length >> 8; 1052 desc->plcp_length_lo = plcp_length & 0xff; 1053 1054 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1055 desc->plcp_signal |= 0x08; 1056 } 1057 1058 desc->iv = 0; 1059 desc->eiv = 0; 1060 } 1061 1062 #define RAL_TX_TIMEOUT 5000 1063 1064 static int 1065 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1066 { 1067 struct ieee80211vap *vap = ni->ni_vap; 1068 struct ieee80211com *ic = ni->ni_ic; 1069 struct ifnet *ifp = sc->sc_ifp; 1070 const struct ieee80211_txparam *tp; 1071 struct ural_tx_data *data; 1072 1073 if (sc->tx_nfree == 0) { 1074 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1075 m_freem(m0); 1076 ieee80211_free_node(ni); 1077 return (EIO); 1078 } 1079 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1080 m_freem(m0); 1081 ieee80211_free_node(ni); 1082 return (ENXIO); 1083 } 1084 data = STAILQ_FIRST(&sc->tx_free); 1085 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1086 sc->tx_nfree--; 1087 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1088 1089 data->m = m0; 1090 data->ni = ni; 1091 data->rate = tp->mgmtrate; 1092 1093 ural_setup_tx_desc(sc, &data->desc, 1094 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1095 tp->mgmtrate); 1096 1097 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1098 m0->m_pkthdr.len, tp->mgmtrate); 1099 1100 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1101 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1102 1103 return (0); 1104 } 1105 1106 static int 1107 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1108 { 1109 struct ieee80211vap *vap = ni->ni_vap; 1110 struct ieee80211com *ic = ni->ni_ic; 1111 const struct ieee80211_txparam *tp; 1112 struct ural_tx_data *data; 1113 struct ieee80211_frame *wh; 1114 struct ieee80211_key *k; 1115 uint32_t flags; 1116 uint16_t dur; 1117 1118 RAL_LOCK_ASSERT(sc, MA_OWNED); 1119 1120 data = STAILQ_FIRST(&sc->tx_free); 1121 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1122 sc->tx_nfree--; 1123 1124 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1125 1126 wh = mtod(m0, struct ieee80211_frame *); 1127 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1128 k = ieee80211_crypto_encap(ni, m0); 1129 if (k == NULL) { 1130 m_freem(m0); 1131 return ENOBUFS; 1132 } 1133 wh = mtod(m0, struct ieee80211_frame *); 1134 } 1135 1136 data->m = m0; 1137 data->ni = ni; 1138 data->rate = tp->mgmtrate; 1139 1140 flags = 0; 1141 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1142 flags |= RAL_TX_ACK; 1143 1144 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1145 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1146 USETW(wh->i_dur, dur); 1147 1148 /* tell hardware to add timestamp for probe responses */ 1149 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1150 IEEE80211_FC0_TYPE_MGT && 1151 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1152 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1153 flags |= RAL_TX_TIMESTAMP; 1154 } 1155 1156 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1157 1158 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1159 m0->m_pkthdr.len, tp->mgmtrate); 1160 1161 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1162 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1163 1164 return 0; 1165 } 1166 1167 static int 1168 ural_sendprot(struct ural_softc *sc, 1169 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1170 { 1171 struct ieee80211com *ic = ni->ni_ic; 1172 const struct ieee80211_frame *wh; 1173 struct ural_tx_data *data; 1174 struct mbuf *mprot; 1175 int protrate, ackrate, pktlen, flags, isshort; 1176 uint16_t dur; 1177 1178 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1179 ("protection %d", prot)); 1180 1181 wh = mtod(m, const struct ieee80211_frame *); 1182 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1183 1184 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1185 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1186 1187 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1188 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1189 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1190 flags = RAL_TX_RETRY(7); 1191 if (prot == IEEE80211_PROT_RTSCTS) { 1192 /* NB: CTS is the same size as an ACK */ 1193 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1194 flags |= RAL_TX_ACK; 1195 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1196 } else { 1197 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1198 } 1199 if (mprot == NULL) { 1200 /* XXX stat + msg */ 1201 return ENOBUFS; 1202 } 1203 data = STAILQ_FIRST(&sc->tx_free); 1204 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1205 sc->tx_nfree--; 1206 1207 data->m = mprot; 1208 data->ni = ieee80211_ref_node(ni); 1209 data->rate = protrate; 1210 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1211 1212 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1213 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1214 1215 return 0; 1216 } 1217 1218 static int 1219 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1220 const struct ieee80211_bpf_params *params) 1221 { 1222 struct ieee80211com *ic = ni->ni_ic; 1223 struct ural_tx_data *data; 1224 uint32_t flags; 1225 int error; 1226 int rate; 1227 1228 RAL_LOCK_ASSERT(sc, MA_OWNED); 1229 KASSERT(params != NULL, ("no raw xmit params")); 1230 1231 rate = params->ibp_rate0; 1232 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1233 m_freem(m0); 1234 return EINVAL; 1235 } 1236 flags = 0; 1237 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1238 flags |= RAL_TX_ACK; 1239 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1240 error = ural_sendprot(sc, m0, ni, 1241 params->ibp_flags & IEEE80211_BPF_RTS ? 1242 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1243 rate); 1244 if (error || sc->tx_nfree == 0) { 1245 m_freem(m0); 1246 return ENOBUFS; 1247 } 1248 flags |= RAL_TX_IFS_SIFS; 1249 } 1250 1251 data = STAILQ_FIRST(&sc->tx_free); 1252 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1253 sc->tx_nfree--; 1254 1255 data->m = m0; 1256 data->ni = ni; 1257 data->rate = rate; 1258 1259 /* XXX need to setup descriptor ourself */ 1260 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1261 1262 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1263 m0->m_pkthdr.len, rate); 1264 1265 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1266 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1267 1268 return 0; 1269 } 1270 1271 static int 1272 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1273 { 1274 struct ieee80211vap *vap = ni->ni_vap; 1275 struct ieee80211com *ic = ni->ni_ic; 1276 struct ural_tx_data *data; 1277 struct ieee80211_frame *wh; 1278 const struct ieee80211_txparam *tp; 1279 struct ieee80211_key *k; 1280 uint32_t flags = 0; 1281 uint16_t dur; 1282 int error, rate; 1283 1284 RAL_LOCK_ASSERT(sc, MA_OWNED); 1285 1286 wh = mtod(m0, struct ieee80211_frame *); 1287 1288 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1289 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1290 rate = tp->mcastrate; 1291 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1292 rate = tp->ucastrate; 1293 else 1294 rate = ni->ni_txrate; 1295 1296 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1297 k = ieee80211_crypto_encap(ni, m0); 1298 if (k == NULL) { 1299 m_freem(m0); 1300 return ENOBUFS; 1301 } 1302 /* packet header may have moved, reset our local pointer */ 1303 wh = mtod(m0, struct ieee80211_frame *); 1304 } 1305 1306 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1307 int prot = IEEE80211_PROT_NONE; 1308 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1309 prot = IEEE80211_PROT_RTSCTS; 1310 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1311 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1312 prot = ic->ic_protmode; 1313 if (prot != IEEE80211_PROT_NONE) { 1314 error = ural_sendprot(sc, m0, ni, prot, rate); 1315 if (error || sc->tx_nfree == 0) { 1316 m_freem(m0); 1317 return ENOBUFS; 1318 } 1319 flags |= RAL_TX_IFS_SIFS; 1320 } 1321 } 1322 1323 data = STAILQ_FIRST(&sc->tx_free); 1324 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1325 sc->tx_nfree--; 1326 1327 data->m = m0; 1328 data->ni = ni; 1329 data->rate = rate; 1330 1331 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1332 flags |= RAL_TX_ACK; 1333 flags |= RAL_TX_RETRY(7); 1334 1335 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1336 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1337 USETW(wh->i_dur, dur); 1338 } 1339 1340 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1341 1342 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1343 m0->m_pkthdr.len, rate); 1344 1345 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1346 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1347 1348 return 0; 1349 } 1350 1351 static void 1352 ural_start(struct ifnet *ifp) 1353 { 1354 struct ural_softc *sc = ifp->if_softc; 1355 struct ieee80211_node *ni; 1356 struct mbuf *m; 1357 1358 RAL_LOCK(sc); 1359 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1360 RAL_UNLOCK(sc); 1361 return; 1362 } 1363 for (;;) { 1364 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1365 if (m == NULL) 1366 break; 1367 if (sc->tx_nfree < RAL_TX_MINFREE) { 1368 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1369 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1370 break; 1371 } 1372 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1373 if (ural_tx_data(sc, m, ni) != 0) { 1374 ieee80211_free_node(ni); 1375 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1376 break; 1377 } 1378 } 1379 RAL_UNLOCK(sc); 1380 } 1381 1382 static int 1383 ural_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1384 { 1385 struct ural_softc *sc = ifp->if_softc; 1386 struct ieee80211com *ic = ifp->if_l2com; 1387 struct ifreq *ifr = (struct ifreq *) data; 1388 int error; 1389 int startall = 0; 1390 1391 RAL_LOCK(sc); 1392 error = sc->sc_detached ? ENXIO : 0; 1393 RAL_UNLOCK(sc); 1394 if (error) 1395 return (error); 1396 1397 switch (cmd) { 1398 case SIOCSIFFLAGS: 1399 RAL_LOCK(sc); 1400 if (ifp->if_flags & IFF_UP) { 1401 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1402 ural_init_locked(sc); 1403 startall = 1; 1404 } else 1405 ural_setpromisc(sc); 1406 } else { 1407 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1408 ural_stop(sc); 1409 } 1410 RAL_UNLOCK(sc); 1411 if (startall) 1412 ieee80211_start_all(ic); 1413 break; 1414 case SIOCGIFMEDIA: 1415 case SIOCSIFMEDIA: 1416 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1417 break; 1418 default: 1419 error = ether_ioctl(ifp, cmd, data); 1420 break; 1421 } 1422 return error; 1423 } 1424 1425 static void 1426 ural_set_testmode(struct ural_softc *sc) 1427 { 1428 struct usb_device_request req; 1429 usb_error_t error; 1430 1431 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1432 req.bRequest = RAL_VENDOR_REQUEST; 1433 USETW(req.wValue, 4); 1434 USETW(req.wIndex, 1); 1435 USETW(req.wLength, 0); 1436 1437 error = ural_do_request(sc, &req, NULL); 1438 if (error != 0) { 1439 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1440 usbd_errstr(error)); 1441 } 1442 } 1443 1444 static void 1445 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1446 { 1447 struct usb_device_request req; 1448 usb_error_t error; 1449 1450 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1451 req.bRequest = RAL_READ_EEPROM; 1452 USETW(req.wValue, 0); 1453 USETW(req.wIndex, addr); 1454 USETW(req.wLength, len); 1455 1456 error = ural_do_request(sc, &req, buf); 1457 if (error != 0) { 1458 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1459 usbd_errstr(error)); 1460 } 1461 } 1462 1463 static uint16_t 1464 ural_read(struct ural_softc *sc, uint16_t reg) 1465 { 1466 struct usb_device_request req; 1467 usb_error_t error; 1468 uint16_t val; 1469 1470 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1471 req.bRequest = RAL_READ_MAC; 1472 USETW(req.wValue, 0); 1473 USETW(req.wIndex, reg); 1474 USETW(req.wLength, sizeof (uint16_t)); 1475 1476 error = ural_do_request(sc, &req, &val); 1477 if (error != 0) { 1478 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1479 usbd_errstr(error)); 1480 return 0; 1481 } 1482 1483 return le16toh(val); 1484 } 1485 1486 static void 1487 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1488 { 1489 struct usb_device_request req; 1490 usb_error_t error; 1491 1492 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1493 req.bRequest = RAL_READ_MULTI_MAC; 1494 USETW(req.wValue, 0); 1495 USETW(req.wIndex, reg); 1496 USETW(req.wLength, len); 1497 1498 error = ural_do_request(sc, &req, buf); 1499 if (error != 0) { 1500 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1501 usbd_errstr(error)); 1502 } 1503 } 1504 1505 static void 1506 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1507 { 1508 struct usb_device_request req; 1509 usb_error_t error; 1510 1511 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1512 req.bRequest = RAL_WRITE_MAC; 1513 USETW(req.wValue, val); 1514 USETW(req.wIndex, reg); 1515 USETW(req.wLength, 0); 1516 1517 error = ural_do_request(sc, &req, NULL); 1518 if (error != 0) { 1519 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1520 usbd_errstr(error)); 1521 } 1522 } 1523 1524 static void 1525 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1526 { 1527 struct usb_device_request req; 1528 usb_error_t error; 1529 1530 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1531 req.bRequest = RAL_WRITE_MULTI_MAC; 1532 USETW(req.wValue, 0); 1533 USETW(req.wIndex, reg); 1534 USETW(req.wLength, len); 1535 1536 error = ural_do_request(sc, &req, buf); 1537 if (error != 0) { 1538 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1539 usbd_errstr(error)); 1540 } 1541 } 1542 1543 static void 1544 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1545 { 1546 uint16_t tmp; 1547 int ntries; 1548 1549 for (ntries = 0; ntries < 100; ntries++) { 1550 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1551 break; 1552 if (ural_pause(sc, hz / 100)) 1553 break; 1554 } 1555 if (ntries == 100) { 1556 device_printf(sc->sc_dev, "could not write to BBP\n"); 1557 return; 1558 } 1559 1560 tmp = reg << 8 | val; 1561 ural_write(sc, RAL_PHY_CSR7, tmp); 1562 } 1563 1564 static uint8_t 1565 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1566 { 1567 uint16_t val; 1568 int ntries; 1569 1570 val = RAL_BBP_WRITE | reg << 8; 1571 ural_write(sc, RAL_PHY_CSR7, val); 1572 1573 for (ntries = 0; ntries < 100; ntries++) { 1574 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1575 break; 1576 if (ural_pause(sc, hz / 100)) 1577 break; 1578 } 1579 if (ntries == 100) { 1580 device_printf(sc->sc_dev, "could not read BBP\n"); 1581 return 0; 1582 } 1583 1584 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1585 } 1586 1587 static void 1588 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1589 { 1590 uint32_t tmp; 1591 int ntries; 1592 1593 for (ntries = 0; ntries < 100; ntries++) { 1594 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1595 break; 1596 if (ural_pause(sc, hz / 100)) 1597 break; 1598 } 1599 if (ntries == 100) { 1600 device_printf(sc->sc_dev, "could not write to RF\n"); 1601 return; 1602 } 1603 1604 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1605 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1606 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1607 1608 /* remember last written value in sc */ 1609 sc->rf_regs[reg] = val; 1610 1611 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1612 } 1613 1614 static void 1615 ural_scan_start(struct ieee80211com *ic) 1616 { 1617 struct ifnet *ifp = ic->ic_ifp; 1618 struct ural_softc *sc = ifp->if_softc; 1619 1620 RAL_LOCK(sc); 1621 ural_write(sc, RAL_TXRX_CSR19, 0); 1622 ural_set_bssid(sc, ifp->if_broadcastaddr); 1623 RAL_UNLOCK(sc); 1624 } 1625 1626 static void 1627 ural_scan_end(struct ieee80211com *ic) 1628 { 1629 struct ural_softc *sc = ic->ic_ifp->if_softc; 1630 1631 RAL_LOCK(sc); 1632 ural_enable_tsf_sync(sc); 1633 ural_set_bssid(sc, sc->sc_bssid); 1634 RAL_UNLOCK(sc); 1635 1636 } 1637 1638 static void 1639 ural_set_channel(struct ieee80211com *ic) 1640 { 1641 struct ural_softc *sc = ic->ic_ifp->if_softc; 1642 1643 RAL_LOCK(sc); 1644 ural_set_chan(sc, ic->ic_curchan); 1645 RAL_UNLOCK(sc); 1646 } 1647 1648 static void 1649 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1650 { 1651 struct ifnet *ifp = sc->sc_ifp; 1652 struct ieee80211com *ic = ifp->if_l2com; 1653 uint8_t power, tmp; 1654 int i, chan; 1655 1656 chan = ieee80211_chan2ieee(ic, c); 1657 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1658 return; 1659 1660 if (IEEE80211_IS_CHAN_2GHZ(c)) 1661 power = min(sc->txpow[chan - 1], 31); 1662 else 1663 power = 31; 1664 1665 /* adjust txpower using ifconfig settings */ 1666 power -= (100 - ic->ic_txpowlimit) / 8; 1667 1668 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1669 1670 switch (sc->rf_rev) { 1671 case RAL_RF_2522: 1672 ural_rf_write(sc, RAL_RF1, 0x00814); 1673 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1674 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1675 break; 1676 1677 case RAL_RF_2523: 1678 ural_rf_write(sc, RAL_RF1, 0x08804); 1679 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1680 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1681 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1682 break; 1683 1684 case RAL_RF_2524: 1685 ural_rf_write(sc, RAL_RF1, 0x0c808); 1686 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1687 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1688 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1689 break; 1690 1691 case RAL_RF_2525: 1692 ural_rf_write(sc, RAL_RF1, 0x08808); 1693 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1694 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1695 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1696 1697 ural_rf_write(sc, RAL_RF1, 0x08808); 1698 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1699 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1700 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1701 break; 1702 1703 case RAL_RF_2525E: 1704 ural_rf_write(sc, RAL_RF1, 0x08808); 1705 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1706 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1707 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1708 break; 1709 1710 case RAL_RF_2526: 1711 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1712 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1713 ural_rf_write(sc, RAL_RF1, 0x08804); 1714 1715 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1716 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1717 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1718 break; 1719 1720 /* dual-band RF */ 1721 case RAL_RF_5222: 1722 for (i = 0; ural_rf5222[i].chan != chan; i++); 1723 1724 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1725 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1726 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1727 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1728 break; 1729 } 1730 1731 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1732 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1733 /* set Japan filter bit for channel 14 */ 1734 tmp = ural_bbp_read(sc, 70); 1735 1736 tmp &= ~RAL_JAPAN_FILTER; 1737 if (chan == 14) 1738 tmp |= RAL_JAPAN_FILTER; 1739 1740 ural_bbp_write(sc, 70, tmp); 1741 1742 /* clear CRC errors */ 1743 ural_read(sc, RAL_STA_CSR0); 1744 1745 ural_pause(sc, hz / 100); 1746 ural_disable_rf_tune(sc); 1747 } 1748 1749 /* XXX doesn't belong here */ 1750 /* update basic rate set */ 1751 ural_set_basicrates(sc, c); 1752 1753 /* give the hardware some time to do the switchover */ 1754 ural_pause(sc, hz / 100); 1755 } 1756 1757 /* 1758 * Disable RF auto-tuning. 1759 */ 1760 static void 1761 ural_disable_rf_tune(struct ural_softc *sc) 1762 { 1763 uint32_t tmp; 1764 1765 if (sc->rf_rev != RAL_RF_2523) { 1766 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1767 ural_rf_write(sc, RAL_RF1, tmp); 1768 } 1769 1770 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1771 ural_rf_write(sc, RAL_RF3, tmp); 1772 1773 DPRINTFN(2, "disabling RF autotune\n"); 1774 } 1775 1776 /* 1777 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1778 * synchronization. 1779 */ 1780 static void 1781 ural_enable_tsf_sync(struct ural_softc *sc) 1782 { 1783 struct ifnet *ifp = sc->sc_ifp; 1784 struct ieee80211com *ic = ifp->if_l2com; 1785 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1786 uint16_t logcwmin, preload, tmp; 1787 1788 /* first, disable TSF synchronization */ 1789 ural_write(sc, RAL_TXRX_CSR19, 0); 1790 1791 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1792 ural_write(sc, RAL_TXRX_CSR18, tmp); 1793 1794 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1795 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1796 tmp = logcwmin << 12 | preload; 1797 ural_write(sc, RAL_TXRX_CSR20, tmp); 1798 1799 /* finally, enable TSF synchronization */ 1800 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1801 if (ic->ic_opmode == IEEE80211_M_STA) 1802 tmp |= RAL_ENABLE_TSF_SYNC(1); 1803 else 1804 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1805 ural_write(sc, RAL_TXRX_CSR19, tmp); 1806 1807 DPRINTF("enabling TSF synchronization\n"); 1808 } 1809 1810 static void 1811 ural_enable_tsf(struct ural_softc *sc) 1812 { 1813 /* first, disable TSF synchronization */ 1814 ural_write(sc, RAL_TXRX_CSR19, 0); 1815 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1816 } 1817 1818 #define RAL_RXTX_TURNAROUND 5 /* us */ 1819 static void 1820 ural_update_slot(struct ifnet *ifp) 1821 { 1822 struct ural_softc *sc = ifp->if_softc; 1823 struct ieee80211com *ic = ifp->if_l2com; 1824 uint16_t slottime, sifs, eifs; 1825 1826 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1827 1828 /* 1829 * These settings may sound a bit inconsistent but this is what the 1830 * reference driver does. 1831 */ 1832 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1833 sifs = 16 - RAL_RXTX_TURNAROUND; 1834 eifs = 364; 1835 } else { 1836 sifs = 10 - RAL_RXTX_TURNAROUND; 1837 eifs = 64; 1838 } 1839 1840 ural_write(sc, RAL_MAC_CSR10, slottime); 1841 ural_write(sc, RAL_MAC_CSR11, sifs); 1842 ural_write(sc, RAL_MAC_CSR12, eifs); 1843 } 1844 1845 static void 1846 ural_set_txpreamble(struct ural_softc *sc) 1847 { 1848 struct ifnet *ifp = sc->sc_ifp; 1849 struct ieee80211com *ic = ifp->if_l2com; 1850 uint16_t tmp; 1851 1852 tmp = ural_read(sc, RAL_TXRX_CSR10); 1853 1854 tmp &= ~RAL_SHORT_PREAMBLE; 1855 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1856 tmp |= RAL_SHORT_PREAMBLE; 1857 1858 ural_write(sc, RAL_TXRX_CSR10, tmp); 1859 } 1860 1861 static void 1862 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1863 { 1864 /* XXX wrong, take from rate set */ 1865 /* update basic rate set */ 1866 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1867 /* 11a basic rates: 6, 12, 24Mbps */ 1868 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1869 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1870 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1871 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1872 } else { 1873 /* 11b basic rates: 1, 2Mbps */ 1874 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1875 } 1876 } 1877 1878 static void 1879 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1880 { 1881 uint16_t tmp; 1882 1883 tmp = bssid[0] | bssid[1] << 8; 1884 ural_write(sc, RAL_MAC_CSR5, tmp); 1885 1886 tmp = bssid[2] | bssid[3] << 8; 1887 ural_write(sc, RAL_MAC_CSR6, tmp); 1888 1889 tmp = bssid[4] | bssid[5] << 8; 1890 ural_write(sc, RAL_MAC_CSR7, tmp); 1891 1892 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1893 } 1894 1895 static void 1896 ural_set_macaddr(struct ural_softc *sc, uint8_t *addr) 1897 { 1898 uint16_t tmp; 1899 1900 tmp = addr[0] | addr[1] << 8; 1901 ural_write(sc, RAL_MAC_CSR2, tmp); 1902 1903 tmp = addr[2] | addr[3] << 8; 1904 ural_write(sc, RAL_MAC_CSR3, tmp); 1905 1906 tmp = addr[4] | addr[5] << 8; 1907 ural_write(sc, RAL_MAC_CSR4, tmp); 1908 1909 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1910 } 1911 1912 static void 1913 ural_setpromisc(struct ural_softc *sc) 1914 { 1915 struct ifnet *ifp = sc->sc_ifp; 1916 uint32_t tmp; 1917 1918 tmp = ural_read(sc, RAL_TXRX_CSR2); 1919 1920 tmp &= ~RAL_DROP_NOT_TO_ME; 1921 if (!(ifp->if_flags & IFF_PROMISC)) 1922 tmp |= RAL_DROP_NOT_TO_ME; 1923 1924 ural_write(sc, RAL_TXRX_CSR2, tmp); 1925 1926 DPRINTF("%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? 1927 "entering" : "leaving"); 1928 } 1929 1930 static void 1931 ural_update_promisc(struct ieee80211com *ic) 1932 { 1933 struct ural_softc *sc = ic->ic_softc; 1934 1935 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1936 return; 1937 1938 RAL_LOCK(sc); 1939 ural_setpromisc(sc); 1940 RAL_UNLOCK(sc); 1941 } 1942 1943 static const char * 1944 ural_get_rf(int rev) 1945 { 1946 switch (rev) { 1947 case RAL_RF_2522: return "RT2522"; 1948 case RAL_RF_2523: return "RT2523"; 1949 case RAL_RF_2524: return "RT2524"; 1950 case RAL_RF_2525: return "RT2525"; 1951 case RAL_RF_2525E: return "RT2525e"; 1952 case RAL_RF_2526: return "RT2526"; 1953 case RAL_RF_5222: return "RT5222"; 1954 default: return "unknown"; 1955 } 1956 } 1957 1958 static void 1959 ural_read_eeprom(struct ural_softc *sc) 1960 { 1961 uint16_t val; 1962 1963 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1964 val = le16toh(val); 1965 sc->rf_rev = (val >> 11) & 0x7; 1966 sc->hw_radio = (val >> 10) & 0x1; 1967 sc->led_mode = (val >> 6) & 0x7; 1968 sc->rx_ant = (val >> 4) & 0x3; 1969 sc->tx_ant = (val >> 2) & 0x3; 1970 sc->nb_ant = val & 0x3; 1971 1972 /* read MAC address */ 1973 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, sc->sc_bssid, 6); 1974 1975 /* read default values for BBP registers */ 1976 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1977 1978 /* read Tx power for all b/g channels */ 1979 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1980 } 1981 1982 static int 1983 ural_bbp_init(struct ural_softc *sc) 1984 { 1985 #define N(a) ((int)(sizeof (a) / sizeof ((a)[0]))) 1986 int i, ntries; 1987 1988 /* wait for BBP to be ready */ 1989 for (ntries = 0; ntries < 100; ntries++) { 1990 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1991 break; 1992 if (ural_pause(sc, hz / 100)) 1993 break; 1994 } 1995 if (ntries == 100) { 1996 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1997 return EIO; 1998 } 1999 2000 /* initialize BBP registers to default values */ 2001 for (i = 0; i < N(ural_def_bbp); i++) 2002 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 2003 2004 #if 0 2005 /* initialize BBP registers to values stored in EEPROM */ 2006 for (i = 0; i < 16; i++) { 2007 if (sc->bbp_prom[i].reg == 0xff) 2008 continue; 2009 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 2010 } 2011 #endif 2012 2013 return 0; 2014 #undef N 2015 } 2016 2017 static void 2018 ural_set_txantenna(struct ural_softc *sc, int antenna) 2019 { 2020 uint16_t tmp; 2021 uint8_t tx; 2022 2023 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 2024 if (antenna == 1) 2025 tx |= RAL_BBP_ANTA; 2026 else if (antenna == 2) 2027 tx |= RAL_BBP_ANTB; 2028 else 2029 tx |= RAL_BBP_DIVERSITY; 2030 2031 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 2032 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 2033 sc->rf_rev == RAL_RF_5222) 2034 tx |= RAL_BBP_FLIPIQ; 2035 2036 ural_bbp_write(sc, RAL_BBP_TX, tx); 2037 2038 /* update values in PHY_CSR5 and PHY_CSR6 */ 2039 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 2040 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 2041 2042 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2043 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2044 } 2045 2046 static void 2047 ural_set_rxantenna(struct ural_softc *sc, int antenna) 2048 { 2049 uint8_t rx; 2050 2051 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2052 if (antenna == 1) 2053 rx |= RAL_BBP_ANTA; 2054 else if (antenna == 2) 2055 rx |= RAL_BBP_ANTB; 2056 else 2057 rx |= RAL_BBP_DIVERSITY; 2058 2059 /* need to force no I/Q flip for RF 2525e and 2526 */ 2060 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2061 rx &= ~RAL_BBP_FLIPIQ; 2062 2063 ural_bbp_write(sc, RAL_BBP_RX, rx); 2064 } 2065 2066 static void 2067 ural_init_locked(struct ural_softc *sc) 2068 { 2069 #define N(a) ((int)(sizeof (a) / sizeof ((a)[0]))) 2070 struct ifnet *ifp = sc->sc_ifp; 2071 struct ieee80211com *ic = ifp->if_l2com; 2072 uint16_t tmp; 2073 int i, ntries; 2074 2075 RAL_LOCK_ASSERT(sc, MA_OWNED); 2076 2077 ural_set_testmode(sc); 2078 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2079 2080 ural_stop(sc); 2081 2082 /* initialize MAC registers to default values */ 2083 for (i = 0; i < N(ural_def_mac); i++) 2084 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2085 2086 /* wait for BBP and RF to wake up (this can take a long time!) */ 2087 for (ntries = 0; ntries < 100; ntries++) { 2088 tmp = ural_read(sc, RAL_MAC_CSR17); 2089 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2090 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2091 break; 2092 if (ural_pause(sc, hz / 100)) 2093 break; 2094 } 2095 if (ntries == 100) { 2096 device_printf(sc->sc_dev, 2097 "timeout waiting for BBP/RF to wakeup\n"); 2098 goto fail; 2099 } 2100 2101 /* we're ready! */ 2102 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2103 2104 /* set basic rate set (will be updated later) */ 2105 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2106 2107 if (ural_bbp_init(sc) != 0) 2108 goto fail; 2109 2110 ural_set_chan(sc, ic->ic_curchan); 2111 2112 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2113 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2114 2115 ural_set_txantenna(sc, sc->tx_ant); 2116 ural_set_rxantenna(sc, sc->rx_ant); 2117 2118 ural_set_macaddr(sc, IF_LLADDR(ifp)); 2119 2120 /* 2121 * Allocate Tx and Rx xfer queues. 2122 */ 2123 ural_setup_tx_list(sc); 2124 2125 /* kick Rx */ 2126 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2127 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2128 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2129 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2130 tmp |= RAL_DROP_TODS; 2131 if (!(ifp->if_flags & IFF_PROMISC)) 2132 tmp |= RAL_DROP_NOT_TO_ME; 2133 } 2134 ural_write(sc, RAL_TXRX_CSR2, tmp); 2135 2136 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2137 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2138 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2139 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2140 return; 2141 2142 fail: ural_stop(sc); 2143 #undef N 2144 } 2145 2146 static void 2147 ural_init(void *priv) 2148 { 2149 struct ural_softc *sc = priv; 2150 struct ifnet *ifp = sc->sc_ifp; 2151 struct ieee80211com *ic = ifp->if_l2com; 2152 2153 RAL_LOCK(sc); 2154 ural_init_locked(sc); 2155 RAL_UNLOCK(sc); 2156 2157 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2158 ieee80211_start_all(ic); /* start all vap's */ 2159 } 2160 2161 static void 2162 ural_stop(struct ural_softc *sc) 2163 { 2164 struct ifnet *ifp = sc->sc_ifp; 2165 2166 RAL_LOCK_ASSERT(sc, MA_OWNED); 2167 2168 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2169 2170 /* 2171 * Drain all the transfers, if not already drained: 2172 */ 2173 RAL_UNLOCK(sc); 2174 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2175 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2176 RAL_LOCK(sc); 2177 2178 ural_unsetup_tx_list(sc); 2179 2180 /* disable Rx */ 2181 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2182 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2183 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2184 /* wait a little */ 2185 ural_pause(sc, hz / 10); 2186 ural_write(sc, RAL_MAC_CSR1, 0); 2187 /* wait a little */ 2188 ural_pause(sc, hz / 10); 2189 } 2190 2191 static int 2192 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2193 const struct ieee80211_bpf_params *params) 2194 { 2195 struct ieee80211com *ic = ni->ni_ic; 2196 struct ifnet *ifp = ic->ic_ifp; 2197 struct ural_softc *sc = ifp->if_softc; 2198 2199 RAL_LOCK(sc); 2200 /* prevent management frames from being sent if we're not ready */ 2201 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 2202 RAL_UNLOCK(sc); 2203 m_freem(m); 2204 ieee80211_free_node(ni); 2205 return ENETDOWN; 2206 } 2207 if (sc->tx_nfree < RAL_TX_MINFREE) { 2208 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2209 RAL_UNLOCK(sc); 2210 m_freem(m); 2211 ieee80211_free_node(ni); 2212 return EIO; 2213 } 2214 2215 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2216 2217 if (params == NULL) { 2218 /* 2219 * Legacy path; interpret frame contents to decide 2220 * precisely how to send the frame. 2221 */ 2222 if (ural_tx_mgt(sc, m, ni) != 0) 2223 goto bad; 2224 } else { 2225 /* 2226 * Caller supplied explicit parameters to use in 2227 * sending the frame. 2228 */ 2229 if (ural_tx_raw(sc, m, ni, params) != 0) 2230 goto bad; 2231 } 2232 RAL_UNLOCK(sc); 2233 return 0; 2234 bad: 2235 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2236 RAL_UNLOCK(sc); 2237 ieee80211_free_node(ni); 2238 return EIO; /* XXX */ 2239 } 2240 2241 static void 2242 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2243 { 2244 struct ieee80211vap *vap = ni->ni_vap; 2245 struct ural_vap *uvp = URAL_VAP(vap); 2246 2247 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2248 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2249 2250 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2251 } 2252 2253 static void 2254 ural_ratectl_timeout(void *arg) 2255 { 2256 struct ural_vap *uvp = arg; 2257 struct ieee80211vap *vap = &uvp->vap; 2258 struct ieee80211com *ic = vap->iv_ic; 2259 2260 ieee80211_runtask(ic, &uvp->ratectl_task); 2261 } 2262 2263 static void 2264 ural_ratectl_task(void *arg, int pending) 2265 { 2266 struct ural_vap *uvp = arg; 2267 struct ieee80211vap *vap = &uvp->vap; 2268 struct ieee80211com *ic = vap->iv_ic; 2269 struct ifnet *ifp = ic->ic_ifp; 2270 struct ural_softc *sc = ifp->if_softc; 2271 struct ieee80211_node *ni; 2272 int ok, fail; 2273 int sum, retrycnt; 2274 2275 ni = ieee80211_ref_node(vap->iv_bss); 2276 RAL_LOCK(sc); 2277 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2278 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2279 2280 ok = sc->sta[7] + /* TX ok w/o retry */ 2281 sc->sta[8]; /* TX ok w/ retry */ 2282 fail = sc->sta[9]; /* TX retry-fail count */ 2283 sum = ok+fail; 2284 retrycnt = sc->sta[8] + fail; 2285 2286 ieee80211_ratectl_tx_update(vap, ni, &sum, &ok, &retrycnt); 2287 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2288 2289 if_inc_counter(ifp, IFCOUNTER_OERRORS, fail); /* count TX retry-fail as Tx errors */ 2290 2291 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2292 RAL_UNLOCK(sc); 2293 ieee80211_free_node(ni); 2294 } 2295 2296 static int 2297 ural_pause(struct ural_softc *sc, int timeout) 2298 { 2299 2300 usb_pause_mtx(&sc->sc_mtx, timeout); 2301 return (0); 2302 } 2303