1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 /*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31 #include <sys/param.h> 32 #include <sys/sockio.h> 33 #include <sys/sysctl.h> 34 #include <sys/lock.h> 35 #include <sys/mutex.h> 36 #include <sys/mbuf.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/systm.h> 40 #include <sys/malloc.h> 41 #include <sys/module.h> 42 #include <sys/bus.h> 43 #include <sys/endian.h> 44 #include <sys/kdb.h> 45 46 #include <machine/bus.h> 47 #include <machine/resource.h> 48 #include <sys/rman.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #ifdef INET 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/in_var.h> 63 #include <netinet/if_ether.h> 64 #include <netinet/ip.h> 65 #endif 66 67 #include <net80211/ieee80211_var.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <dev/usb/usb.h> 73 #include <dev/usb/usbdi.h> 74 #include "usbdevs.h" 75 76 #define USB_DEBUG_VAR ural_debug 77 #include <dev/usb/usb_debug.h> 78 79 #include <dev/usb/wlan/if_uralreg.h> 80 #include <dev/usb/wlan/if_uralvar.h> 81 82 #ifdef USB_DEBUG 83 static int ural_debug = 0; 84 85 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 86 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 87 "Debug level"); 88 #endif 89 90 #define URAL_RSSI(rssi) \ 91 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 92 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 93 94 /* various supported device vendors/products */ 95 static const STRUCT_USB_HOST_ID ural_devs[] = { 96 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 97 URAL_DEV(ASUS, WL167G), 98 URAL_DEV(ASUS, RT2570), 99 URAL_DEV(BELKIN, F5D7050), 100 URAL_DEV(BELKIN, F5D7051), 101 URAL_DEV(CISCOLINKSYS, HU200TS), 102 URAL_DEV(CISCOLINKSYS, WUSB54G), 103 URAL_DEV(CISCOLINKSYS, WUSB54GP), 104 URAL_DEV(CONCEPTRONIC2, C54RU), 105 URAL_DEV(DLINK, DWLG122), 106 URAL_DEV(GIGABYTE, GN54G), 107 URAL_DEV(GIGABYTE, GNWBKG), 108 URAL_DEV(GUILLEMOT, HWGUSB254), 109 URAL_DEV(MELCO, KG54), 110 URAL_DEV(MELCO, KG54AI), 111 URAL_DEV(MELCO, KG54YB), 112 URAL_DEV(MELCO, NINWIFI), 113 URAL_DEV(MSI, RT2570), 114 URAL_DEV(MSI, RT2570_2), 115 URAL_DEV(MSI, RT2570_3), 116 URAL_DEV(NOVATECH, NV902), 117 URAL_DEV(RALINK, RT2570), 118 URAL_DEV(RALINK, RT2570_2), 119 URAL_DEV(RALINK, RT2570_3), 120 URAL_DEV(SIEMENS2, WL54G), 121 URAL_DEV(SMC, 2862WG), 122 URAL_DEV(SPHAIRON, UB801R), 123 URAL_DEV(SURECOM, RT2570), 124 URAL_DEV(VTECH, RT2570), 125 URAL_DEV(ZINWELL, RT2570), 126 #undef URAL_DEV 127 }; 128 129 static usb_callback_t ural_bulk_read_callback; 130 static usb_callback_t ural_bulk_write_callback; 131 132 static usb_error_t ural_do_request(struct ural_softc *sc, 133 struct usb_device_request *req, void *data); 134 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 135 const char [IFNAMSIZ], int, enum ieee80211_opmode, 136 int, const uint8_t [IEEE80211_ADDR_LEN], 137 const uint8_t [IEEE80211_ADDR_LEN]); 138 static void ural_vap_delete(struct ieee80211vap *); 139 static void ural_tx_free(struct ural_tx_data *, int); 140 static void ural_setup_tx_list(struct ural_softc *); 141 static void ural_unsetup_tx_list(struct ural_softc *); 142 static int ural_newstate(struct ieee80211vap *, 143 enum ieee80211_state, int); 144 static void ural_setup_tx_desc(struct ural_softc *, 145 struct ural_tx_desc *, uint32_t, int, int); 146 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 147 struct ieee80211_node *); 148 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 149 struct ieee80211_node *); 150 static int ural_tx_data(struct ural_softc *, struct mbuf *, 151 struct ieee80211_node *); 152 static int ural_transmit(struct ieee80211com *, struct mbuf *); 153 static void ural_start(struct ural_softc *); 154 static void ural_parent(struct ieee80211com *); 155 static void ural_set_testmode(struct ural_softc *); 156 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 157 int); 158 static uint16_t ural_read(struct ural_softc *, uint16_t); 159 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 160 int); 161 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 162 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 163 int) __unused; 164 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 165 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 166 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 167 static void ural_scan_start(struct ieee80211com *); 168 static void ural_scan_end(struct ieee80211com *); 169 static void ural_set_channel(struct ieee80211com *); 170 static void ural_set_chan(struct ural_softc *, 171 struct ieee80211_channel *); 172 static void ural_disable_rf_tune(struct ural_softc *); 173 static void ural_enable_tsf_sync(struct ural_softc *); 174 static void ural_enable_tsf(struct ural_softc *); 175 static void ural_update_slot(struct ural_softc *); 176 static void ural_set_txpreamble(struct ural_softc *); 177 static void ural_set_basicrates(struct ural_softc *, 178 const struct ieee80211_channel *); 179 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 180 static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 181 static void ural_update_promisc(struct ieee80211com *); 182 static void ural_setpromisc(struct ural_softc *); 183 static const char *ural_get_rf(int); 184 static void ural_read_eeprom(struct ural_softc *); 185 static int ural_bbp_init(struct ural_softc *); 186 static void ural_set_txantenna(struct ural_softc *, int); 187 static void ural_set_rxantenna(struct ural_softc *, int); 188 static void ural_init(struct ural_softc *); 189 static void ural_stop(struct ural_softc *); 190 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 191 const struct ieee80211_bpf_params *); 192 static void ural_ratectl_start(struct ural_softc *, 193 struct ieee80211_node *); 194 static void ural_ratectl_timeout(void *); 195 static void ural_ratectl_task(void *, int); 196 static int ural_pause(struct ural_softc *sc, int timeout); 197 198 /* 199 * Default values for MAC registers; values taken from the reference driver. 200 */ 201 static const struct { 202 uint16_t reg; 203 uint16_t val; 204 } ural_def_mac[] = { 205 { RAL_TXRX_CSR5, 0x8c8d }, 206 { RAL_TXRX_CSR6, 0x8b8a }, 207 { RAL_TXRX_CSR7, 0x8687 }, 208 { RAL_TXRX_CSR8, 0x0085 }, 209 { RAL_MAC_CSR13, 0x1111 }, 210 { RAL_MAC_CSR14, 0x1e11 }, 211 { RAL_TXRX_CSR21, 0xe78f }, 212 { RAL_MAC_CSR9, 0xff1d }, 213 { RAL_MAC_CSR11, 0x0002 }, 214 { RAL_MAC_CSR22, 0x0053 }, 215 { RAL_MAC_CSR15, 0x0000 }, 216 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 217 { RAL_TXRX_CSR19, 0x0000 }, 218 { RAL_TXRX_CSR18, 0x005a }, 219 { RAL_PHY_CSR2, 0x0000 }, 220 { RAL_TXRX_CSR0, 0x1ec0 }, 221 { RAL_PHY_CSR4, 0x000f } 222 }; 223 224 /* 225 * Default values for BBP registers; values taken from the reference driver. 226 */ 227 static const struct { 228 uint8_t reg; 229 uint8_t val; 230 } ural_def_bbp[] = { 231 { 3, 0x02 }, 232 { 4, 0x19 }, 233 { 14, 0x1c }, 234 { 15, 0x30 }, 235 { 16, 0xac }, 236 { 17, 0x48 }, 237 { 18, 0x18 }, 238 { 19, 0xff }, 239 { 20, 0x1e }, 240 { 21, 0x08 }, 241 { 22, 0x08 }, 242 { 23, 0x08 }, 243 { 24, 0x80 }, 244 { 25, 0x50 }, 245 { 26, 0x08 }, 246 { 27, 0x23 }, 247 { 30, 0x10 }, 248 { 31, 0x2b }, 249 { 32, 0xb9 }, 250 { 34, 0x12 }, 251 { 35, 0x50 }, 252 { 39, 0xc4 }, 253 { 40, 0x02 }, 254 { 41, 0x60 }, 255 { 53, 0x10 }, 256 { 54, 0x18 }, 257 { 56, 0x08 }, 258 { 57, 0x10 }, 259 { 58, 0x08 }, 260 { 61, 0x60 }, 261 { 62, 0x10 }, 262 { 75, 0xff } 263 }; 264 265 /* 266 * Default values for RF register R2 indexed by channel numbers. 267 */ 268 static const uint32_t ural_rf2522_r2[] = { 269 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 270 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 271 }; 272 273 static const uint32_t ural_rf2523_r2[] = { 274 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 275 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 276 }; 277 278 static const uint32_t ural_rf2524_r2[] = { 279 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 280 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 281 }; 282 283 static const uint32_t ural_rf2525_r2[] = { 284 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 285 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 286 }; 287 288 static const uint32_t ural_rf2525_hi_r2[] = { 289 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 290 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 291 }; 292 293 static const uint32_t ural_rf2525e_r2[] = { 294 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 295 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 296 }; 297 298 static const uint32_t ural_rf2526_hi_r2[] = { 299 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 300 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 301 }; 302 303 static const uint32_t ural_rf2526_r2[] = { 304 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 305 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 306 }; 307 308 /* 309 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 310 * values taken from the reference driver. 311 */ 312 static const struct { 313 uint8_t chan; 314 uint32_t r1; 315 uint32_t r2; 316 uint32_t r4; 317 } ural_rf5222[] = { 318 { 1, 0x08808, 0x0044d, 0x00282 }, 319 { 2, 0x08808, 0x0044e, 0x00282 }, 320 { 3, 0x08808, 0x0044f, 0x00282 }, 321 { 4, 0x08808, 0x00460, 0x00282 }, 322 { 5, 0x08808, 0x00461, 0x00282 }, 323 { 6, 0x08808, 0x00462, 0x00282 }, 324 { 7, 0x08808, 0x00463, 0x00282 }, 325 { 8, 0x08808, 0x00464, 0x00282 }, 326 { 9, 0x08808, 0x00465, 0x00282 }, 327 { 10, 0x08808, 0x00466, 0x00282 }, 328 { 11, 0x08808, 0x00467, 0x00282 }, 329 { 12, 0x08808, 0x00468, 0x00282 }, 330 { 13, 0x08808, 0x00469, 0x00282 }, 331 { 14, 0x08808, 0x0046b, 0x00286 }, 332 333 { 36, 0x08804, 0x06225, 0x00287 }, 334 { 40, 0x08804, 0x06226, 0x00287 }, 335 { 44, 0x08804, 0x06227, 0x00287 }, 336 { 48, 0x08804, 0x06228, 0x00287 }, 337 { 52, 0x08804, 0x06229, 0x00287 }, 338 { 56, 0x08804, 0x0622a, 0x00287 }, 339 { 60, 0x08804, 0x0622b, 0x00287 }, 340 { 64, 0x08804, 0x0622c, 0x00287 }, 341 342 { 100, 0x08804, 0x02200, 0x00283 }, 343 { 104, 0x08804, 0x02201, 0x00283 }, 344 { 108, 0x08804, 0x02202, 0x00283 }, 345 { 112, 0x08804, 0x02203, 0x00283 }, 346 { 116, 0x08804, 0x02204, 0x00283 }, 347 { 120, 0x08804, 0x02205, 0x00283 }, 348 { 124, 0x08804, 0x02206, 0x00283 }, 349 { 128, 0x08804, 0x02207, 0x00283 }, 350 { 132, 0x08804, 0x02208, 0x00283 }, 351 { 136, 0x08804, 0x02209, 0x00283 }, 352 { 140, 0x08804, 0x0220a, 0x00283 }, 353 354 { 149, 0x08808, 0x02429, 0x00281 }, 355 { 153, 0x08808, 0x0242b, 0x00281 }, 356 { 157, 0x08808, 0x0242d, 0x00281 }, 357 { 161, 0x08808, 0x0242f, 0x00281 } 358 }; 359 360 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 361 [URAL_BULK_WR] = { 362 .type = UE_BULK, 363 .endpoint = UE_ADDR_ANY, 364 .direction = UE_DIR_OUT, 365 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 366 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 367 .callback = ural_bulk_write_callback, 368 .timeout = 5000, /* ms */ 369 }, 370 [URAL_BULK_RD] = { 371 .type = UE_BULK, 372 .endpoint = UE_ADDR_ANY, 373 .direction = UE_DIR_IN, 374 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 375 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 376 .callback = ural_bulk_read_callback, 377 }, 378 }; 379 380 static device_probe_t ural_match; 381 static device_attach_t ural_attach; 382 static device_detach_t ural_detach; 383 384 static device_method_t ural_methods[] = { 385 /* Device interface */ 386 DEVMETHOD(device_probe, ural_match), 387 DEVMETHOD(device_attach, ural_attach), 388 DEVMETHOD(device_detach, ural_detach), 389 DEVMETHOD_END 390 }; 391 392 static driver_t ural_driver = { 393 .name = "ural", 394 .methods = ural_methods, 395 .size = sizeof(struct ural_softc), 396 }; 397 398 static devclass_t ural_devclass; 399 400 DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 401 MODULE_DEPEND(ural, usb, 1, 1, 1); 402 MODULE_DEPEND(ural, wlan, 1, 1, 1); 403 MODULE_VERSION(ural, 1); 404 405 static int 406 ural_match(device_t self) 407 { 408 struct usb_attach_arg *uaa = device_get_ivars(self); 409 410 if (uaa->usb_mode != USB_MODE_HOST) 411 return (ENXIO); 412 if (uaa->info.bConfigIndex != 0) 413 return (ENXIO); 414 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 415 return (ENXIO); 416 417 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 418 } 419 420 static int 421 ural_attach(device_t self) 422 { 423 struct usb_attach_arg *uaa = device_get_ivars(self); 424 struct ural_softc *sc = device_get_softc(self); 425 struct ieee80211com *ic = &sc->sc_ic; 426 uint8_t iface_index, bands; 427 int error; 428 429 device_set_usb_desc(self); 430 sc->sc_udev = uaa->device; 431 sc->sc_dev = self; 432 433 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 434 MTX_NETWORK_LOCK, MTX_DEF); 435 mbufq_init(&sc->sc_snd, ifqmaxlen); 436 437 iface_index = RAL_IFACE_INDEX; 438 error = usbd_transfer_setup(uaa->device, 439 &iface_index, sc->sc_xfer, ural_config, 440 URAL_N_TRANSFER, sc, &sc->sc_mtx); 441 if (error) { 442 device_printf(self, "could not allocate USB transfers, " 443 "err=%s\n", usbd_errstr(error)); 444 goto detach; 445 } 446 447 RAL_LOCK(sc); 448 /* retrieve RT2570 rev. no */ 449 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 450 451 /* retrieve MAC address and various other things from EEPROM */ 452 ural_read_eeprom(sc); 453 RAL_UNLOCK(sc); 454 455 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 456 sc->asic_rev, ural_get_rf(sc->rf_rev)); 457 458 ic->ic_softc = sc; 459 ic->ic_name = device_get_nameunit(self); 460 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 461 462 /* set device capabilities */ 463 ic->ic_caps = 464 IEEE80211_C_STA /* station mode supported */ 465 | IEEE80211_C_IBSS /* IBSS mode supported */ 466 | IEEE80211_C_MONITOR /* monitor mode supported */ 467 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 468 | IEEE80211_C_TXPMGT /* tx power management */ 469 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 470 | IEEE80211_C_SHSLOT /* short slot time supported */ 471 | IEEE80211_C_BGSCAN /* bg scanning supported */ 472 | IEEE80211_C_WPA /* 802.11i */ 473 ; 474 475 bands = 0; 476 setbit(&bands, IEEE80211_MODE_11B); 477 setbit(&bands, IEEE80211_MODE_11G); 478 if (sc->rf_rev == RAL_RF_5222) 479 setbit(&bands, IEEE80211_MODE_11A); 480 ieee80211_init_channels(ic, NULL, &bands); 481 482 ieee80211_ifattach(ic); 483 ic->ic_update_promisc = ural_update_promisc; 484 ic->ic_raw_xmit = ural_raw_xmit; 485 ic->ic_scan_start = ural_scan_start; 486 ic->ic_scan_end = ural_scan_end; 487 ic->ic_set_channel = ural_set_channel; 488 ic->ic_parent = ural_parent; 489 ic->ic_transmit = ural_transmit; 490 ic->ic_vap_create = ural_vap_create; 491 ic->ic_vap_delete = ural_vap_delete; 492 493 ieee80211_radiotap_attach(ic, 494 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 495 RAL_TX_RADIOTAP_PRESENT, 496 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 497 RAL_RX_RADIOTAP_PRESENT); 498 499 if (bootverbose) 500 ieee80211_announce(ic); 501 502 return (0); 503 504 detach: 505 ural_detach(self); 506 return (ENXIO); /* failure */ 507 } 508 509 static int 510 ural_detach(device_t self) 511 { 512 struct ural_softc *sc = device_get_softc(self); 513 struct ieee80211com *ic = &sc->sc_ic; 514 515 /* prevent further ioctls */ 516 RAL_LOCK(sc); 517 sc->sc_detached = 1; 518 RAL_UNLOCK(sc); 519 520 /* stop all USB transfers */ 521 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 522 523 /* free TX list, if any */ 524 RAL_LOCK(sc); 525 ural_unsetup_tx_list(sc); 526 RAL_UNLOCK(sc); 527 528 if (ic->ic_softc == sc) 529 ieee80211_ifdetach(ic); 530 mbufq_drain(&sc->sc_snd); 531 mtx_destroy(&sc->sc_mtx); 532 533 return (0); 534 } 535 536 static usb_error_t 537 ural_do_request(struct ural_softc *sc, 538 struct usb_device_request *req, void *data) 539 { 540 usb_error_t err; 541 int ntries = 10; 542 543 while (ntries--) { 544 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 545 req, data, 0, NULL, 250 /* ms */); 546 if (err == 0) 547 break; 548 549 DPRINTFN(1, "Control request failed, %s (retrying)\n", 550 usbd_errstr(err)); 551 if (ural_pause(sc, hz / 100)) 552 break; 553 } 554 return (err); 555 } 556 557 static struct ieee80211vap * 558 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 559 enum ieee80211_opmode opmode, int flags, 560 const uint8_t bssid[IEEE80211_ADDR_LEN], 561 const uint8_t mac[IEEE80211_ADDR_LEN]) 562 { 563 struct ural_softc *sc = ic->ic_softc; 564 struct ural_vap *uvp; 565 struct ieee80211vap *vap; 566 567 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 568 return NULL; 569 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 570 vap = &uvp->vap; 571 /* enable s/w bmiss handling for sta mode */ 572 573 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 574 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 575 /* out of memory */ 576 free(uvp, M_80211_VAP); 577 return (NULL); 578 } 579 580 /* override state transition machine */ 581 uvp->newstate = vap->iv_newstate; 582 vap->iv_newstate = ural_newstate; 583 584 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 585 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 586 ieee80211_ratectl_init(vap); 587 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 588 589 /* complete setup */ 590 ieee80211_vap_attach(vap, ieee80211_media_change, 591 ieee80211_media_status, mac); 592 ic->ic_opmode = opmode; 593 return vap; 594 } 595 596 static void 597 ural_vap_delete(struct ieee80211vap *vap) 598 { 599 struct ural_vap *uvp = URAL_VAP(vap); 600 struct ieee80211com *ic = vap->iv_ic; 601 602 usb_callout_drain(&uvp->ratectl_ch); 603 ieee80211_draintask(ic, &uvp->ratectl_task); 604 ieee80211_ratectl_deinit(vap); 605 ieee80211_vap_detach(vap); 606 free(uvp, M_80211_VAP); 607 } 608 609 static void 610 ural_tx_free(struct ural_tx_data *data, int txerr) 611 { 612 struct ural_softc *sc = data->sc; 613 614 if (data->m != NULL) { 615 ieee80211_tx_complete(data->ni, data->m, txerr); 616 data->m = NULL; 617 data->ni = NULL; 618 } 619 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 620 sc->tx_nfree++; 621 } 622 623 static void 624 ural_setup_tx_list(struct ural_softc *sc) 625 { 626 struct ural_tx_data *data; 627 int i; 628 629 sc->tx_nfree = 0; 630 STAILQ_INIT(&sc->tx_q); 631 STAILQ_INIT(&sc->tx_free); 632 633 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 634 data = &sc->tx_data[i]; 635 636 data->sc = sc; 637 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 638 sc->tx_nfree++; 639 } 640 } 641 642 static void 643 ural_unsetup_tx_list(struct ural_softc *sc) 644 { 645 struct ural_tx_data *data; 646 int i; 647 648 /* make sure any subsequent use of the queues will fail */ 649 sc->tx_nfree = 0; 650 STAILQ_INIT(&sc->tx_q); 651 STAILQ_INIT(&sc->tx_free); 652 653 /* free up all node references and mbufs */ 654 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 655 data = &sc->tx_data[i]; 656 657 if (data->m != NULL) { 658 m_freem(data->m); 659 data->m = NULL; 660 } 661 if (data->ni != NULL) { 662 ieee80211_free_node(data->ni); 663 data->ni = NULL; 664 } 665 } 666 } 667 668 static int 669 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 670 { 671 struct ural_vap *uvp = URAL_VAP(vap); 672 struct ieee80211com *ic = vap->iv_ic; 673 struct ural_softc *sc = ic->ic_softc; 674 const struct ieee80211_txparam *tp; 675 struct ieee80211_node *ni; 676 struct mbuf *m; 677 678 DPRINTF("%s -> %s\n", 679 ieee80211_state_name[vap->iv_state], 680 ieee80211_state_name[nstate]); 681 682 IEEE80211_UNLOCK(ic); 683 RAL_LOCK(sc); 684 usb_callout_stop(&uvp->ratectl_ch); 685 686 switch (nstate) { 687 case IEEE80211_S_INIT: 688 if (vap->iv_state == IEEE80211_S_RUN) { 689 /* abort TSF synchronization */ 690 ural_write(sc, RAL_TXRX_CSR19, 0); 691 692 /* force tx led to stop blinking */ 693 ural_write(sc, RAL_MAC_CSR20, 0); 694 } 695 break; 696 697 case IEEE80211_S_RUN: 698 ni = ieee80211_ref_node(vap->iv_bss); 699 700 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 701 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 702 RAL_UNLOCK(sc); 703 IEEE80211_LOCK(ic); 704 ieee80211_free_node(ni); 705 return (-1); 706 } 707 ural_update_slot(sc); 708 ural_set_txpreamble(sc); 709 ural_set_basicrates(sc, ic->ic_bsschan); 710 IEEE80211_ADDR_COPY(ic->ic_macaddr, ni->ni_bssid); 711 ural_set_bssid(sc, ic->ic_macaddr); 712 } 713 714 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 715 vap->iv_opmode == IEEE80211_M_IBSS) { 716 m = ieee80211_beacon_alloc(ni, &uvp->bo); 717 if (m == NULL) { 718 device_printf(sc->sc_dev, 719 "could not allocate beacon\n"); 720 RAL_UNLOCK(sc); 721 IEEE80211_LOCK(ic); 722 ieee80211_free_node(ni); 723 return (-1); 724 } 725 ieee80211_ref_node(ni); 726 if (ural_tx_bcn(sc, m, ni) != 0) { 727 device_printf(sc->sc_dev, 728 "could not send beacon\n"); 729 RAL_UNLOCK(sc); 730 IEEE80211_LOCK(ic); 731 ieee80211_free_node(ni); 732 return (-1); 733 } 734 } 735 736 /* make tx led blink on tx (controlled by ASIC) */ 737 ural_write(sc, RAL_MAC_CSR20, 1); 738 739 if (vap->iv_opmode != IEEE80211_M_MONITOR) 740 ural_enable_tsf_sync(sc); 741 else 742 ural_enable_tsf(sc); 743 744 /* enable automatic rate adaptation */ 745 /* XXX should use ic_bsschan but not valid until after newstate call below */ 746 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 747 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 748 ural_ratectl_start(sc, ni); 749 ieee80211_free_node(ni); 750 break; 751 752 default: 753 break; 754 } 755 RAL_UNLOCK(sc); 756 IEEE80211_LOCK(ic); 757 return (uvp->newstate(vap, nstate, arg)); 758 } 759 760 761 static void 762 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 763 { 764 struct ural_softc *sc = usbd_xfer_softc(xfer); 765 struct ieee80211vap *vap; 766 struct ural_tx_data *data; 767 struct mbuf *m; 768 struct usb_page_cache *pc; 769 int len; 770 771 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 772 773 switch (USB_GET_STATE(xfer)) { 774 case USB_ST_TRANSFERRED: 775 DPRINTFN(11, "transfer complete, %d bytes\n", len); 776 777 /* free resources */ 778 data = usbd_xfer_get_priv(xfer); 779 ural_tx_free(data, 0); 780 usbd_xfer_set_priv(xfer, NULL); 781 782 /* FALLTHROUGH */ 783 case USB_ST_SETUP: 784 tr_setup: 785 data = STAILQ_FIRST(&sc->tx_q); 786 if (data) { 787 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 788 m = data->m; 789 790 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 791 DPRINTFN(0, "data overflow, %u bytes\n", 792 m->m_pkthdr.len); 793 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 794 } 795 pc = usbd_xfer_get_frame(xfer, 0); 796 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 797 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 798 m->m_pkthdr.len); 799 800 vap = data->ni->ni_vap; 801 if (ieee80211_radiotap_active_vap(vap)) { 802 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 803 804 tap->wt_flags = 0; 805 tap->wt_rate = data->rate; 806 tap->wt_antenna = sc->tx_ant; 807 808 ieee80211_radiotap_tx(vap, m); 809 } 810 811 /* xfer length needs to be a multiple of two! */ 812 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 813 if ((len % 64) == 0) 814 len += 2; 815 816 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 817 m->m_pkthdr.len, len); 818 819 usbd_xfer_set_frame_len(xfer, 0, len); 820 usbd_xfer_set_priv(xfer, data); 821 822 usbd_transfer_submit(xfer); 823 } 824 ural_start(sc); 825 break; 826 827 default: /* Error */ 828 DPRINTFN(11, "transfer error, %s\n", 829 usbd_errstr(error)); 830 831 data = usbd_xfer_get_priv(xfer); 832 if (data != NULL) { 833 ural_tx_free(data, error); 834 usbd_xfer_set_priv(xfer, NULL); 835 } 836 837 if (error == USB_ERR_STALLED) { 838 /* try to clear stall first */ 839 usbd_xfer_set_stall(xfer); 840 goto tr_setup; 841 } 842 if (error == USB_ERR_TIMEOUT) 843 device_printf(sc->sc_dev, "device timeout\n"); 844 break; 845 } 846 } 847 848 static void 849 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 850 { 851 struct ural_softc *sc = usbd_xfer_softc(xfer); 852 struct ieee80211com *ic = &sc->sc_ic; 853 struct ieee80211_node *ni; 854 struct mbuf *m = NULL; 855 struct usb_page_cache *pc; 856 uint32_t flags; 857 int8_t rssi = 0, nf = 0; 858 int len; 859 860 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 861 862 switch (USB_GET_STATE(xfer)) { 863 case USB_ST_TRANSFERRED: 864 865 DPRINTFN(15, "rx done, actlen=%d\n", len); 866 867 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 868 DPRINTF("%s: xfer too short %d\n", 869 device_get_nameunit(sc->sc_dev), len); 870 counter_u64_add(ic->ic_ierrors, 1); 871 goto tr_setup; 872 } 873 874 len -= RAL_RX_DESC_SIZE; 875 /* rx descriptor is located at the end */ 876 pc = usbd_xfer_get_frame(xfer, 0); 877 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 878 879 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 880 nf = RAL_NOISE_FLOOR; 881 flags = le32toh(sc->sc_rx_desc.flags); 882 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 883 /* 884 * This should not happen since we did not 885 * request to receive those frames when we 886 * filled RAL_TXRX_CSR2: 887 */ 888 DPRINTFN(5, "PHY or CRC error\n"); 889 counter_u64_add(ic->ic_ierrors, 1); 890 goto tr_setup; 891 } 892 893 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 894 if (m == NULL) { 895 DPRINTF("could not allocate mbuf\n"); 896 counter_u64_add(ic->ic_ierrors, 1); 897 goto tr_setup; 898 } 899 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 900 901 /* finalize mbuf */ 902 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 903 904 if (ieee80211_radiotap_active(ic)) { 905 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 906 907 /* XXX set once */ 908 tap->wr_flags = 0; 909 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 910 (flags & RAL_RX_OFDM) ? 911 IEEE80211_T_OFDM : IEEE80211_T_CCK); 912 tap->wr_antenna = sc->rx_ant; 913 tap->wr_antsignal = nf + rssi; 914 tap->wr_antnoise = nf; 915 } 916 /* Strip trailing 802.11 MAC FCS. */ 917 m_adj(m, -IEEE80211_CRC_LEN); 918 919 /* FALLTHROUGH */ 920 case USB_ST_SETUP: 921 tr_setup: 922 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 923 usbd_transfer_submit(xfer); 924 925 /* 926 * At the end of a USB callback it is always safe to unlock 927 * the private mutex of a device! That is why we do the 928 * "ieee80211_input" here, and not some lines up! 929 */ 930 RAL_UNLOCK(sc); 931 if (m) { 932 ni = ieee80211_find_rxnode(ic, 933 mtod(m, struct ieee80211_frame_min *)); 934 if (ni != NULL) { 935 (void) ieee80211_input(ni, m, rssi, nf); 936 ieee80211_free_node(ni); 937 } else 938 (void) ieee80211_input_all(ic, m, rssi, nf); 939 } 940 RAL_LOCK(sc); 941 ural_start(sc); 942 return; 943 944 default: /* Error */ 945 if (error != USB_ERR_CANCELLED) { 946 /* try to clear stall first */ 947 usbd_xfer_set_stall(xfer); 948 goto tr_setup; 949 } 950 return; 951 } 952 } 953 954 static uint8_t 955 ural_plcp_signal(int rate) 956 { 957 switch (rate) { 958 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 959 case 12: return 0xb; 960 case 18: return 0xf; 961 case 24: return 0xa; 962 case 36: return 0xe; 963 case 48: return 0x9; 964 case 72: return 0xd; 965 case 96: return 0x8; 966 case 108: return 0xc; 967 968 /* CCK rates (NB: not IEEE std, device-specific) */ 969 case 2: return 0x0; 970 case 4: return 0x1; 971 case 11: return 0x2; 972 case 22: return 0x3; 973 } 974 return 0xff; /* XXX unsupported/unknown rate */ 975 } 976 977 static void 978 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 979 uint32_t flags, int len, int rate) 980 { 981 struct ieee80211com *ic = &sc->sc_ic; 982 uint16_t plcp_length; 983 int remainder; 984 985 desc->flags = htole32(flags); 986 desc->flags |= htole32(RAL_TX_NEWSEQ); 987 desc->flags |= htole32(len << 16); 988 989 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 990 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 991 992 /* setup PLCP fields */ 993 desc->plcp_signal = ural_plcp_signal(rate); 994 desc->plcp_service = 4; 995 996 len += IEEE80211_CRC_LEN; 997 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 998 desc->flags |= htole32(RAL_TX_OFDM); 999 1000 plcp_length = len & 0xfff; 1001 desc->plcp_length_hi = plcp_length >> 6; 1002 desc->plcp_length_lo = plcp_length & 0x3f; 1003 } else { 1004 if (rate == 0) 1005 rate = 2; /* avoid division by zero */ 1006 plcp_length = (16 * len + rate - 1) / rate; 1007 if (rate == 22) { 1008 remainder = (16 * len) % 22; 1009 if (remainder != 0 && remainder < 7) 1010 desc->plcp_service |= RAL_PLCP_LENGEXT; 1011 } 1012 desc->plcp_length_hi = plcp_length >> 8; 1013 desc->plcp_length_lo = plcp_length & 0xff; 1014 1015 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1016 desc->plcp_signal |= 0x08; 1017 } 1018 1019 desc->iv = 0; 1020 desc->eiv = 0; 1021 } 1022 1023 #define RAL_TX_TIMEOUT 5000 1024 1025 static int 1026 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1027 { 1028 struct ieee80211vap *vap = ni->ni_vap; 1029 struct ieee80211com *ic = ni->ni_ic; 1030 const struct ieee80211_txparam *tp; 1031 struct ural_tx_data *data; 1032 1033 if (sc->tx_nfree == 0) { 1034 m_freem(m0); 1035 ieee80211_free_node(ni); 1036 return (EIO); 1037 } 1038 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1039 m_freem(m0); 1040 ieee80211_free_node(ni); 1041 return (ENXIO); 1042 } 1043 data = STAILQ_FIRST(&sc->tx_free); 1044 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1045 sc->tx_nfree--; 1046 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1047 1048 data->m = m0; 1049 data->ni = ni; 1050 data->rate = tp->mgmtrate; 1051 1052 ural_setup_tx_desc(sc, &data->desc, 1053 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1054 tp->mgmtrate); 1055 1056 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1057 m0->m_pkthdr.len, tp->mgmtrate); 1058 1059 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1060 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1061 1062 return (0); 1063 } 1064 1065 static int 1066 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1067 { 1068 struct ieee80211vap *vap = ni->ni_vap; 1069 struct ieee80211com *ic = ni->ni_ic; 1070 const struct ieee80211_txparam *tp; 1071 struct ural_tx_data *data; 1072 struct ieee80211_frame *wh; 1073 struct ieee80211_key *k; 1074 uint32_t flags; 1075 uint16_t dur; 1076 1077 RAL_LOCK_ASSERT(sc, MA_OWNED); 1078 1079 data = STAILQ_FIRST(&sc->tx_free); 1080 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1081 sc->tx_nfree--; 1082 1083 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 1084 1085 wh = mtod(m0, struct ieee80211_frame *); 1086 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1087 k = ieee80211_crypto_encap(ni, m0); 1088 if (k == NULL) { 1089 m_freem(m0); 1090 return ENOBUFS; 1091 } 1092 wh = mtod(m0, struct ieee80211_frame *); 1093 } 1094 1095 data->m = m0; 1096 data->ni = ni; 1097 data->rate = tp->mgmtrate; 1098 1099 flags = 0; 1100 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1101 flags |= RAL_TX_ACK; 1102 1103 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1104 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1105 USETW(wh->i_dur, dur); 1106 1107 /* tell hardware to add timestamp for probe responses */ 1108 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1109 IEEE80211_FC0_TYPE_MGT && 1110 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1111 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1112 flags |= RAL_TX_TIMESTAMP; 1113 } 1114 1115 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1116 1117 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1118 m0->m_pkthdr.len, tp->mgmtrate); 1119 1120 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1121 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1122 1123 return 0; 1124 } 1125 1126 static int 1127 ural_sendprot(struct ural_softc *sc, 1128 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1129 { 1130 struct ieee80211com *ic = ni->ni_ic; 1131 const struct ieee80211_frame *wh; 1132 struct ural_tx_data *data; 1133 struct mbuf *mprot; 1134 int protrate, ackrate, pktlen, flags, isshort; 1135 uint16_t dur; 1136 1137 KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, 1138 ("protection %d", prot)); 1139 1140 wh = mtod(m, const struct ieee80211_frame *); 1141 pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; 1142 1143 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1144 ackrate = ieee80211_ack_rate(ic->ic_rt, rate); 1145 1146 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 1147 dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) 1148 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1149 flags = RAL_TX_RETRY(7); 1150 if (prot == IEEE80211_PROT_RTSCTS) { 1151 /* NB: CTS is the same size as an ACK */ 1152 dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); 1153 flags |= RAL_TX_ACK; 1154 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); 1155 } else { 1156 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); 1157 } 1158 if (mprot == NULL) { 1159 /* XXX stat + msg */ 1160 return ENOBUFS; 1161 } 1162 data = STAILQ_FIRST(&sc->tx_free); 1163 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1164 sc->tx_nfree--; 1165 1166 data->m = mprot; 1167 data->ni = ieee80211_ref_node(ni); 1168 data->rate = protrate; 1169 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1170 1171 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1172 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1173 1174 return 0; 1175 } 1176 1177 static int 1178 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1179 const struct ieee80211_bpf_params *params) 1180 { 1181 struct ieee80211com *ic = ni->ni_ic; 1182 struct ural_tx_data *data; 1183 uint32_t flags; 1184 int error; 1185 int rate; 1186 1187 RAL_LOCK_ASSERT(sc, MA_OWNED); 1188 KASSERT(params != NULL, ("no raw xmit params")); 1189 1190 rate = params->ibp_rate0; 1191 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1192 m_freem(m0); 1193 return EINVAL; 1194 } 1195 flags = 0; 1196 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1197 flags |= RAL_TX_ACK; 1198 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1199 error = ural_sendprot(sc, m0, ni, 1200 params->ibp_flags & IEEE80211_BPF_RTS ? 1201 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1202 rate); 1203 if (error || sc->tx_nfree == 0) { 1204 m_freem(m0); 1205 return ENOBUFS; 1206 } 1207 flags |= RAL_TX_IFS_SIFS; 1208 } 1209 1210 data = STAILQ_FIRST(&sc->tx_free); 1211 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1212 sc->tx_nfree--; 1213 1214 data->m = m0; 1215 data->ni = ni; 1216 data->rate = rate; 1217 1218 /* XXX need to setup descriptor ourself */ 1219 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1220 1221 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1222 m0->m_pkthdr.len, rate); 1223 1224 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1225 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1226 1227 return 0; 1228 } 1229 1230 static int 1231 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1232 { 1233 struct ieee80211vap *vap = ni->ni_vap; 1234 struct ieee80211com *ic = ni->ni_ic; 1235 struct ural_tx_data *data; 1236 struct ieee80211_frame *wh; 1237 const struct ieee80211_txparam *tp; 1238 struct ieee80211_key *k; 1239 uint32_t flags = 0; 1240 uint16_t dur; 1241 int error, rate; 1242 1243 RAL_LOCK_ASSERT(sc, MA_OWNED); 1244 1245 wh = mtod(m0, struct ieee80211_frame *); 1246 1247 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; 1248 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1249 rate = tp->mcastrate; 1250 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1251 rate = tp->ucastrate; 1252 else 1253 rate = ni->ni_txrate; 1254 1255 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1256 k = ieee80211_crypto_encap(ni, m0); 1257 if (k == NULL) { 1258 m_freem(m0); 1259 return ENOBUFS; 1260 } 1261 /* packet header may have moved, reset our local pointer */ 1262 wh = mtod(m0, struct ieee80211_frame *); 1263 } 1264 1265 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1266 int prot = IEEE80211_PROT_NONE; 1267 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1268 prot = IEEE80211_PROT_RTSCTS; 1269 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1270 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1271 prot = ic->ic_protmode; 1272 if (prot != IEEE80211_PROT_NONE) { 1273 error = ural_sendprot(sc, m0, ni, prot, rate); 1274 if (error || sc->tx_nfree == 0) { 1275 m_freem(m0); 1276 return ENOBUFS; 1277 } 1278 flags |= RAL_TX_IFS_SIFS; 1279 } 1280 } 1281 1282 data = STAILQ_FIRST(&sc->tx_free); 1283 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1284 sc->tx_nfree--; 1285 1286 data->m = m0; 1287 data->ni = ni; 1288 data->rate = rate; 1289 1290 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1291 flags |= RAL_TX_ACK; 1292 flags |= RAL_TX_RETRY(7); 1293 1294 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1295 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1296 USETW(wh->i_dur, dur); 1297 } 1298 1299 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1300 1301 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1302 m0->m_pkthdr.len, rate); 1303 1304 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1305 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1306 1307 return 0; 1308 } 1309 1310 static int 1311 ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1312 { 1313 struct ural_softc *sc = ic->ic_softc; 1314 int error; 1315 1316 RAL_LOCK(sc); 1317 if (!sc->sc_running) { 1318 RAL_UNLOCK(sc); 1319 return (ENXIO); 1320 } 1321 error = mbufq_enqueue(&sc->sc_snd, m); 1322 if (error) { 1323 RAL_UNLOCK(sc); 1324 return (error); 1325 } 1326 ural_start(sc); 1327 RAL_UNLOCK(sc); 1328 1329 return (0); 1330 } 1331 1332 static void 1333 ural_start(struct ural_softc *sc) 1334 { 1335 struct ieee80211_node *ni; 1336 struct mbuf *m; 1337 1338 RAL_LOCK_ASSERT(sc, MA_OWNED); 1339 1340 if (sc->sc_running == 0) 1341 return; 1342 1343 while (sc->tx_nfree >= RAL_TX_MINFREE && 1344 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1345 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1346 if (ural_tx_data(sc, m, ni) != 0) { 1347 if_inc_counter(ni->ni_vap->iv_ifp, 1348 IFCOUNTER_OERRORS, 1); 1349 ieee80211_free_node(ni); 1350 break; 1351 } 1352 } 1353 } 1354 1355 static void 1356 ural_parent(struct ieee80211com *ic) 1357 { 1358 struct ural_softc *sc = ic->ic_softc; 1359 int startall = 0; 1360 1361 RAL_LOCK(sc); 1362 if (sc->sc_detached) { 1363 RAL_UNLOCK(sc); 1364 return; 1365 } 1366 if (ic->ic_nrunning > 0) { 1367 if (sc->sc_running == 0) { 1368 ural_init(sc); 1369 startall = 1; 1370 } else 1371 ural_setpromisc(sc); 1372 } else if (sc->sc_running) 1373 ural_stop(sc); 1374 RAL_UNLOCK(sc); 1375 if (startall) 1376 ieee80211_start_all(ic); 1377 } 1378 1379 static void 1380 ural_set_testmode(struct ural_softc *sc) 1381 { 1382 struct usb_device_request req; 1383 usb_error_t error; 1384 1385 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1386 req.bRequest = RAL_VENDOR_REQUEST; 1387 USETW(req.wValue, 4); 1388 USETW(req.wIndex, 1); 1389 USETW(req.wLength, 0); 1390 1391 error = ural_do_request(sc, &req, NULL); 1392 if (error != 0) { 1393 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1394 usbd_errstr(error)); 1395 } 1396 } 1397 1398 static void 1399 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1400 { 1401 struct usb_device_request req; 1402 usb_error_t error; 1403 1404 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1405 req.bRequest = RAL_READ_EEPROM; 1406 USETW(req.wValue, 0); 1407 USETW(req.wIndex, addr); 1408 USETW(req.wLength, len); 1409 1410 error = ural_do_request(sc, &req, buf); 1411 if (error != 0) { 1412 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1413 usbd_errstr(error)); 1414 } 1415 } 1416 1417 static uint16_t 1418 ural_read(struct ural_softc *sc, uint16_t reg) 1419 { 1420 struct usb_device_request req; 1421 usb_error_t error; 1422 uint16_t val; 1423 1424 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1425 req.bRequest = RAL_READ_MAC; 1426 USETW(req.wValue, 0); 1427 USETW(req.wIndex, reg); 1428 USETW(req.wLength, sizeof (uint16_t)); 1429 1430 error = ural_do_request(sc, &req, &val); 1431 if (error != 0) { 1432 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1433 usbd_errstr(error)); 1434 return 0; 1435 } 1436 1437 return le16toh(val); 1438 } 1439 1440 static void 1441 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1442 { 1443 struct usb_device_request req; 1444 usb_error_t error; 1445 1446 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1447 req.bRequest = RAL_READ_MULTI_MAC; 1448 USETW(req.wValue, 0); 1449 USETW(req.wIndex, reg); 1450 USETW(req.wLength, len); 1451 1452 error = ural_do_request(sc, &req, buf); 1453 if (error != 0) { 1454 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1455 usbd_errstr(error)); 1456 } 1457 } 1458 1459 static void 1460 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1461 { 1462 struct usb_device_request req; 1463 usb_error_t error; 1464 1465 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1466 req.bRequest = RAL_WRITE_MAC; 1467 USETW(req.wValue, val); 1468 USETW(req.wIndex, reg); 1469 USETW(req.wLength, 0); 1470 1471 error = ural_do_request(sc, &req, NULL); 1472 if (error != 0) { 1473 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1474 usbd_errstr(error)); 1475 } 1476 } 1477 1478 static void 1479 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1480 { 1481 struct usb_device_request req; 1482 usb_error_t error; 1483 1484 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1485 req.bRequest = RAL_WRITE_MULTI_MAC; 1486 USETW(req.wValue, 0); 1487 USETW(req.wIndex, reg); 1488 USETW(req.wLength, len); 1489 1490 error = ural_do_request(sc, &req, buf); 1491 if (error != 0) { 1492 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1493 usbd_errstr(error)); 1494 } 1495 } 1496 1497 static void 1498 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1499 { 1500 uint16_t tmp; 1501 int ntries; 1502 1503 for (ntries = 0; ntries < 100; ntries++) { 1504 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1505 break; 1506 if (ural_pause(sc, hz / 100)) 1507 break; 1508 } 1509 if (ntries == 100) { 1510 device_printf(sc->sc_dev, "could not write to BBP\n"); 1511 return; 1512 } 1513 1514 tmp = reg << 8 | val; 1515 ural_write(sc, RAL_PHY_CSR7, tmp); 1516 } 1517 1518 static uint8_t 1519 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1520 { 1521 uint16_t val; 1522 int ntries; 1523 1524 val = RAL_BBP_WRITE | reg << 8; 1525 ural_write(sc, RAL_PHY_CSR7, val); 1526 1527 for (ntries = 0; ntries < 100; ntries++) { 1528 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1529 break; 1530 if (ural_pause(sc, hz / 100)) 1531 break; 1532 } 1533 if (ntries == 100) { 1534 device_printf(sc->sc_dev, "could not read BBP\n"); 1535 return 0; 1536 } 1537 1538 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1539 } 1540 1541 static void 1542 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1543 { 1544 uint32_t tmp; 1545 int ntries; 1546 1547 for (ntries = 0; ntries < 100; ntries++) { 1548 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1549 break; 1550 if (ural_pause(sc, hz / 100)) 1551 break; 1552 } 1553 if (ntries == 100) { 1554 device_printf(sc->sc_dev, "could not write to RF\n"); 1555 return; 1556 } 1557 1558 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1559 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1560 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1561 1562 /* remember last written value in sc */ 1563 sc->rf_regs[reg] = val; 1564 1565 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1566 } 1567 1568 static void 1569 ural_scan_start(struct ieee80211com *ic) 1570 { 1571 struct ural_softc *sc = ic->ic_softc; 1572 1573 RAL_LOCK(sc); 1574 ural_write(sc, RAL_TXRX_CSR19, 0); 1575 ural_set_bssid(sc, ieee80211broadcastaddr); 1576 RAL_UNLOCK(sc); 1577 } 1578 1579 static void 1580 ural_scan_end(struct ieee80211com *ic) 1581 { 1582 struct ural_softc *sc = ic->ic_softc; 1583 1584 RAL_LOCK(sc); 1585 ural_enable_tsf_sync(sc); 1586 ural_set_bssid(sc, ic->ic_macaddr); 1587 RAL_UNLOCK(sc); 1588 1589 } 1590 1591 static void 1592 ural_set_channel(struct ieee80211com *ic) 1593 { 1594 struct ural_softc *sc = ic->ic_softc; 1595 1596 RAL_LOCK(sc); 1597 ural_set_chan(sc, ic->ic_curchan); 1598 RAL_UNLOCK(sc); 1599 } 1600 1601 static void 1602 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1603 { 1604 struct ieee80211com *ic = &sc->sc_ic; 1605 uint8_t power, tmp; 1606 int i, chan; 1607 1608 chan = ieee80211_chan2ieee(ic, c); 1609 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1610 return; 1611 1612 if (IEEE80211_IS_CHAN_2GHZ(c)) 1613 power = min(sc->txpow[chan - 1], 31); 1614 else 1615 power = 31; 1616 1617 /* adjust txpower using ifconfig settings */ 1618 power -= (100 - ic->ic_txpowlimit) / 8; 1619 1620 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1621 1622 switch (sc->rf_rev) { 1623 case RAL_RF_2522: 1624 ural_rf_write(sc, RAL_RF1, 0x00814); 1625 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1626 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1627 break; 1628 1629 case RAL_RF_2523: 1630 ural_rf_write(sc, RAL_RF1, 0x08804); 1631 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1632 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1633 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1634 break; 1635 1636 case RAL_RF_2524: 1637 ural_rf_write(sc, RAL_RF1, 0x0c808); 1638 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1639 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1640 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1641 break; 1642 1643 case RAL_RF_2525: 1644 ural_rf_write(sc, RAL_RF1, 0x08808); 1645 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1646 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1647 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1648 1649 ural_rf_write(sc, RAL_RF1, 0x08808); 1650 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1651 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1652 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1653 break; 1654 1655 case RAL_RF_2525E: 1656 ural_rf_write(sc, RAL_RF1, 0x08808); 1657 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1658 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1659 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1660 break; 1661 1662 case RAL_RF_2526: 1663 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1664 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1665 ural_rf_write(sc, RAL_RF1, 0x08804); 1666 1667 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1668 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1669 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1670 break; 1671 1672 /* dual-band RF */ 1673 case RAL_RF_5222: 1674 for (i = 0; ural_rf5222[i].chan != chan; i++); 1675 1676 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1677 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1678 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1679 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1680 break; 1681 } 1682 1683 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1684 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1685 /* set Japan filter bit for channel 14 */ 1686 tmp = ural_bbp_read(sc, 70); 1687 1688 tmp &= ~RAL_JAPAN_FILTER; 1689 if (chan == 14) 1690 tmp |= RAL_JAPAN_FILTER; 1691 1692 ural_bbp_write(sc, 70, tmp); 1693 1694 /* clear CRC errors */ 1695 ural_read(sc, RAL_STA_CSR0); 1696 1697 ural_pause(sc, hz / 100); 1698 ural_disable_rf_tune(sc); 1699 } 1700 1701 /* XXX doesn't belong here */ 1702 /* update basic rate set */ 1703 ural_set_basicrates(sc, c); 1704 1705 /* give the hardware some time to do the switchover */ 1706 ural_pause(sc, hz / 100); 1707 } 1708 1709 /* 1710 * Disable RF auto-tuning. 1711 */ 1712 static void 1713 ural_disable_rf_tune(struct ural_softc *sc) 1714 { 1715 uint32_t tmp; 1716 1717 if (sc->rf_rev != RAL_RF_2523) { 1718 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1719 ural_rf_write(sc, RAL_RF1, tmp); 1720 } 1721 1722 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1723 ural_rf_write(sc, RAL_RF3, tmp); 1724 1725 DPRINTFN(2, "disabling RF autotune\n"); 1726 } 1727 1728 /* 1729 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1730 * synchronization. 1731 */ 1732 static void 1733 ural_enable_tsf_sync(struct ural_softc *sc) 1734 { 1735 struct ieee80211com *ic = &sc->sc_ic; 1736 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1737 uint16_t logcwmin, preload, tmp; 1738 1739 /* first, disable TSF synchronization */ 1740 ural_write(sc, RAL_TXRX_CSR19, 0); 1741 1742 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1743 ural_write(sc, RAL_TXRX_CSR18, tmp); 1744 1745 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1746 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1747 tmp = logcwmin << 12 | preload; 1748 ural_write(sc, RAL_TXRX_CSR20, tmp); 1749 1750 /* finally, enable TSF synchronization */ 1751 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1752 if (ic->ic_opmode == IEEE80211_M_STA) 1753 tmp |= RAL_ENABLE_TSF_SYNC(1); 1754 else 1755 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1756 ural_write(sc, RAL_TXRX_CSR19, tmp); 1757 1758 DPRINTF("enabling TSF synchronization\n"); 1759 } 1760 1761 static void 1762 ural_enable_tsf(struct ural_softc *sc) 1763 { 1764 /* first, disable TSF synchronization */ 1765 ural_write(sc, RAL_TXRX_CSR19, 0); 1766 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1767 } 1768 1769 #define RAL_RXTX_TURNAROUND 5 /* us */ 1770 static void 1771 ural_update_slot(struct ural_softc *sc) 1772 { 1773 struct ieee80211com *ic = &sc->sc_ic; 1774 uint16_t slottime, sifs, eifs; 1775 1776 slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; 1777 1778 /* 1779 * These settings may sound a bit inconsistent but this is what the 1780 * reference driver does. 1781 */ 1782 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1783 sifs = 16 - RAL_RXTX_TURNAROUND; 1784 eifs = 364; 1785 } else { 1786 sifs = 10 - RAL_RXTX_TURNAROUND; 1787 eifs = 64; 1788 } 1789 1790 ural_write(sc, RAL_MAC_CSR10, slottime); 1791 ural_write(sc, RAL_MAC_CSR11, sifs); 1792 ural_write(sc, RAL_MAC_CSR12, eifs); 1793 } 1794 1795 static void 1796 ural_set_txpreamble(struct ural_softc *sc) 1797 { 1798 struct ieee80211com *ic = &sc->sc_ic; 1799 uint16_t tmp; 1800 1801 tmp = ural_read(sc, RAL_TXRX_CSR10); 1802 1803 tmp &= ~RAL_SHORT_PREAMBLE; 1804 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1805 tmp |= RAL_SHORT_PREAMBLE; 1806 1807 ural_write(sc, RAL_TXRX_CSR10, tmp); 1808 } 1809 1810 static void 1811 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1812 { 1813 /* XXX wrong, take from rate set */ 1814 /* update basic rate set */ 1815 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1816 /* 11a basic rates: 6, 12, 24Mbps */ 1817 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1818 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1819 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1820 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1821 } else { 1822 /* 11b basic rates: 1, 2Mbps */ 1823 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1824 } 1825 } 1826 1827 static void 1828 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1829 { 1830 uint16_t tmp; 1831 1832 tmp = bssid[0] | bssid[1] << 8; 1833 ural_write(sc, RAL_MAC_CSR5, tmp); 1834 1835 tmp = bssid[2] | bssid[3] << 8; 1836 ural_write(sc, RAL_MAC_CSR6, tmp); 1837 1838 tmp = bssid[4] | bssid[5] << 8; 1839 ural_write(sc, RAL_MAC_CSR7, tmp); 1840 1841 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1842 } 1843 1844 static void 1845 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1846 { 1847 uint16_t tmp; 1848 1849 tmp = addr[0] | addr[1] << 8; 1850 ural_write(sc, RAL_MAC_CSR2, tmp); 1851 1852 tmp = addr[2] | addr[3] << 8; 1853 ural_write(sc, RAL_MAC_CSR3, tmp); 1854 1855 tmp = addr[4] | addr[5] << 8; 1856 ural_write(sc, RAL_MAC_CSR4, tmp); 1857 1858 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1859 } 1860 1861 static void 1862 ural_setpromisc(struct ural_softc *sc) 1863 { 1864 uint32_t tmp; 1865 1866 tmp = ural_read(sc, RAL_TXRX_CSR2); 1867 1868 tmp &= ~RAL_DROP_NOT_TO_ME; 1869 if (sc->sc_ic.ic_promisc == 0) 1870 tmp |= RAL_DROP_NOT_TO_ME; 1871 1872 ural_write(sc, RAL_TXRX_CSR2, tmp); 1873 1874 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1875 "entering" : "leaving"); 1876 } 1877 1878 static void 1879 ural_update_promisc(struct ieee80211com *ic) 1880 { 1881 struct ural_softc *sc = ic->ic_softc; 1882 1883 RAL_LOCK(sc); 1884 if (sc->sc_running) 1885 ural_setpromisc(sc); 1886 RAL_UNLOCK(sc); 1887 } 1888 1889 static const char * 1890 ural_get_rf(int rev) 1891 { 1892 switch (rev) { 1893 case RAL_RF_2522: return "RT2522"; 1894 case RAL_RF_2523: return "RT2523"; 1895 case RAL_RF_2524: return "RT2524"; 1896 case RAL_RF_2525: return "RT2525"; 1897 case RAL_RF_2525E: return "RT2525e"; 1898 case RAL_RF_2526: return "RT2526"; 1899 case RAL_RF_5222: return "RT5222"; 1900 default: return "unknown"; 1901 } 1902 } 1903 1904 static void 1905 ural_read_eeprom(struct ural_softc *sc) 1906 { 1907 struct ieee80211com *ic = &sc->sc_ic; 1908 uint16_t val; 1909 1910 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1911 val = le16toh(val); 1912 sc->rf_rev = (val >> 11) & 0x7; 1913 sc->hw_radio = (val >> 10) & 0x1; 1914 sc->led_mode = (val >> 6) & 0x7; 1915 sc->rx_ant = (val >> 4) & 0x3; 1916 sc->tx_ant = (val >> 2) & 0x3; 1917 sc->nb_ant = val & 0x3; 1918 1919 /* read MAC address */ 1920 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1921 1922 /* read default values for BBP registers */ 1923 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1924 1925 /* read Tx power for all b/g channels */ 1926 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1927 } 1928 1929 static int 1930 ural_bbp_init(struct ural_softc *sc) 1931 { 1932 #define N(a) ((int)(sizeof (a) / sizeof ((a)[0]))) 1933 int i, ntries; 1934 1935 /* wait for BBP to be ready */ 1936 for (ntries = 0; ntries < 100; ntries++) { 1937 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1938 break; 1939 if (ural_pause(sc, hz / 100)) 1940 break; 1941 } 1942 if (ntries == 100) { 1943 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1944 return EIO; 1945 } 1946 1947 /* initialize BBP registers to default values */ 1948 for (i = 0; i < N(ural_def_bbp); i++) 1949 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1950 1951 #if 0 1952 /* initialize BBP registers to values stored in EEPROM */ 1953 for (i = 0; i < 16; i++) { 1954 if (sc->bbp_prom[i].reg == 0xff) 1955 continue; 1956 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1957 } 1958 #endif 1959 1960 return 0; 1961 #undef N 1962 } 1963 1964 static void 1965 ural_set_txantenna(struct ural_softc *sc, int antenna) 1966 { 1967 uint16_t tmp; 1968 uint8_t tx; 1969 1970 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1971 if (antenna == 1) 1972 tx |= RAL_BBP_ANTA; 1973 else if (antenna == 2) 1974 tx |= RAL_BBP_ANTB; 1975 else 1976 tx |= RAL_BBP_DIVERSITY; 1977 1978 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1979 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1980 sc->rf_rev == RAL_RF_5222) 1981 tx |= RAL_BBP_FLIPIQ; 1982 1983 ural_bbp_write(sc, RAL_BBP_TX, tx); 1984 1985 /* update values in PHY_CSR5 and PHY_CSR6 */ 1986 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1987 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1988 1989 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1990 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1991 } 1992 1993 static void 1994 ural_set_rxantenna(struct ural_softc *sc, int antenna) 1995 { 1996 uint8_t rx; 1997 1998 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 1999 if (antenna == 1) 2000 rx |= RAL_BBP_ANTA; 2001 else if (antenna == 2) 2002 rx |= RAL_BBP_ANTB; 2003 else 2004 rx |= RAL_BBP_DIVERSITY; 2005 2006 /* need to force no I/Q flip for RF 2525e and 2526 */ 2007 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2008 rx &= ~RAL_BBP_FLIPIQ; 2009 2010 ural_bbp_write(sc, RAL_BBP_RX, rx); 2011 } 2012 2013 static void 2014 ural_init(struct ural_softc *sc) 2015 { 2016 #define N(a) ((int)(sizeof (a) / sizeof ((a)[0]))) 2017 struct ieee80211com *ic = &sc->sc_ic; 2018 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2019 uint16_t tmp; 2020 int i, ntries; 2021 2022 RAL_LOCK_ASSERT(sc, MA_OWNED); 2023 2024 ural_set_testmode(sc); 2025 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2026 2027 ural_stop(sc); 2028 2029 /* initialize MAC registers to default values */ 2030 for (i = 0; i < N(ural_def_mac); i++) 2031 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2032 2033 /* wait for BBP and RF to wake up (this can take a long time!) */ 2034 for (ntries = 0; ntries < 100; ntries++) { 2035 tmp = ural_read(sc, RAL_MAC_CSR17); 2036 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2037 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2038 break; 2039 if (ural_pause(sc, hz / 100)) 2040 break; 2041 } 2042 if (ntries == 100) { 2043 device_printf(sc->sc_dev, 2044 "timeout waiting for BBP/RF to wakeup\n"); 2045 goto fail; 2046 } 2047 2048 /* we're ready! */ 2049 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2050 2051 /* set basic rate set (will be updated later) */ 2052 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2053 2054 if (ural_bbp_init(sc) != 0) 2055 goto fail; 2056 2057 ural_set_chan(sc, ic->ic_curchan); 2058 2059 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2060 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2061 2062 ural_set_txantenna(sc, sc->tx_ant); 2063 ural_set_rxantenna(sc, sc->rx_ant); 2064 2065 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2066 2067 /* 2068 * Allocate Tx and Rx xfer queues. 2069 */ 2070 ural_setup_tx_list(sc); 2071 2072 /* kick Rx */ 2073 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2074 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2075 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2076 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2077 tmp |= RAL_DROP_TODS; 2078 if (ic->ic_promisc == 0) 2079 tmp |= RAL_DROP_NOT_TO_ME; 2080 } 2081 ural_write(sc, RAL_TXRX_CSR2, tmp); 2082 2083 sc->sc_running = 1; 2084 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2085 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2086 return; 2087 2088 fail: ural_stop(sc); 2089 #undef N 2090 } 2091 2092 static void 2093 ural_stop(struct ural_softc *sc) 2094 { 2095 2096 RAL_LOCK_ASSERT(sc, MA_OWNED); 2097 2098 sc->sc_running = 0; 2099 2100 /* 2101 * Drain all the transfers, if not already drained: 2102 */ 2103 RAL_UNLOCK(sc); 2104 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2105 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2106 RAL_LOCK(sc); 2107 2108 ural_unsetup_tx_list(sc); 2109 2110 /* disable Rx */ 2111 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2112 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2113 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2114 /* wait a little */ 2115 ural_pause(sc, hz / 10); 2116 ural_write(sc, RAL_MAC_CSR1, 0); 2117 /* wait a little */ 2118 ural_pause(sc, hz / 10); 2119 } 2120 2121 static int 2122 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2123 const struct ieee80211_bpf_params *params) 2124 { 2125 struct ieee80211com *ic = ni->ni_ic; 2126 struct ural_softc *sc = ic->ic_softc; 2127 2128 RAL_LOCK(sc); 2129 /* prevent management frames from being sent if we're not ready */ 2130 if (!sc->sc_running) { 2131 RAL_UNLOCK(sc); 2132 m_freem(m); 2133 ieee80211_free_node(ni); 2134 return ENETDOWN; 2135 } 2136 if (sc->tx_nfree < RAL_TX_MINFREE) { 2137 RAL_UNLOCK(sc); 2138 m_freem(m); 2139 ieee80211_free_node(ni); 2140 return EIO; 2141 } 2142 2143 if (params == NULL) { 2144 /* 2145 * Legacy path; interpret frame contents to decide 2146 * precisely how to send the frame. 2147 */ 2148 if (ural_tx_mgt(sc, m, ni) != 0) 2149 goto bad; 2150 } else { 2151 /* 2152 * Caller supplied explicit parameters to use in 2153 * sending the frame. 2154 */ 2155 if (ural_tx_raw(sc, m, ni, params) != 0) 2156 goto bad; 2157 } 2158 RAL_UNLOCK(sc); 2159 return 0; 2160 bad: 2161 RAL_UNLOCK(sc); 2162 ieee80211_free_node(ni); 2163 return EIO; /* XXX */ 2164 } 2165 2166 static void 2167 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2168 { 2169 struct ieee80211vap *vap = ni->ni_vap; 2170 struct ural_vap *uvp = URAL_VAP(vap); 2171 2172 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2173 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2174 2175 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2176 } 2177 2178 static void 2179 ural_ratectl_timeout(void *arg) 2180 { 2181 struct ural_vap *uvp = arg; 2182 struct ieee80211vap *vap = &uvp->vap; 2183 struct ieee80211com *ic = vap->iv_ic; 2184 2185 ieee80211_runtask(ic, &uvp->ratectl_task); 2186 } 2187 2188 static void 2189 ural_ratectl_task(void *arg, int pending) 2190 { 2191 struct ural_vap *uvp = arg; 2192 struct ieee80211vap *vap = &uvp->vap; 2193 struct ieee80211com *ic = vap->iv_ic; 2194 struct ural_softc *sc = ic->ic_softc; 2195 struct ieee80211_node *ni; 2196 int ok, fail; 2197 int sum, retrycnt; 2198 2199 ni = ieee80211_ref_node(vap->iv_bss); 2200 RAL_LOCK(sc); 2201 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2202 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2203 2204 ok = sc->sta[7] + /* TX ok w/o retry */ 2205 sc->sta[8]; /* TX ok w/ retry */ 2206 fail = sc->sta[9]; /* TX retry-fail count */ 2207 sum = ok+fail; 2208 retrycnt = sc->sta[8] + fail; 2209 2210 ieee80211_ratectl_tx_update(vap, ni, &sum, &ok, &retrycnt); 2211 (void) ieee80211_ratectl_rate(ni, NULL, 0); 2212 2213 /* count TX retry-fail as Tx errors */ 2214 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2215 2216 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2217 RAL_UNLOCK(sc); 2218 ieee80211_free_node(ni); 2219 } 2220 2221 static int 2222 ural_pause(struct ural_softc *sc, int timeout) 2223 { 2224 2225 usb_pause_mtx(&sc->sc_mtx, timeout); 2226 return (0); 2227 } 2228